Method and device for ensuring UPF model file accuracy based on low-power-consumption simulation

Abstract

The invention relates to the technical field of chips, in particular to a method and device for ensuring UPF model file accuracy based on low-power-consumption simulation. The method comprises the steps of obtaining a power supply architecture file of a to-be-verified RTL model, and generating a first UPF model file according to the power supply architecture file; performing difference analysis on the first UPF model file and a manually written second UPF model file to obtain at least one risk point; compiling a logic test case based on the at least one risk point, and performing dynamic simulation on the RTL model to be verified according to the logic test case to obtain a simulation result corresponding to each risk point; and comparing the simulation result with the second UPF model file so as to selectively modify the second UPF model file. According to the method, possible problems of the UPF model file can be found in the initial stage of a project, and timely modification is performed to reduce manpower and time cost and shorten the chip development period.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method and apparatus for ensuring the accuracy of UPF model files based on low-power simulation. Background Technology

[0002] In early integrated circuit design, the primary considerations were performance and area. However, with the significant increase in chip integration, power consumption has become a crucial factor. More and more System-on-Chips (SoCs) are incorporating low-power technologies such as clock gating, multi-threshold voltage library cells, reduced supply voltage, and power switching. Power switching technology requires a Unified Power Format (UPF) model file to describe the chip's power supply intent. Currently, the method for determining whether a UPF model file accurately describes the power supply intent is typically done later in the project. After the front-end converts the RTL-level design code into executable code, back-end engineers generate a power ground (PG) netlist through power planning and verify it through simulation. If problems arise, the UPF model file needs to be modified, and the executable code, placement, and routing processes need to be rewritten, with a single iteration cycle lasting weeks or even months. Therefore, identifying potential problems with the UPF model file in the early stages of low-power verification is crucial for reducing manpower and time costs, minimizing tape-out failure rates, and shortening chip development cycles.

[0003] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0004] In response to the above-mentioned defects or improvement needs of existing technologies, this invention addresses how to identify potential problems in UPF model files at the early stages of a project and make timely modifications to reduce manpower and time costs and shorten the chip development cycle.

[0005] The embodiments of the present invention adopt the following technical solutions: In a first aspect, the present invention provides a method for ensuring the accuracy of UPF model files based on low-power simulation, specifically: obtaining the power architecture file of the RTL model to be verified, and generating a first UPF model file based on the power architecture file; By performing a difference analysis between the first UPF model file and the manually written second UPF model file, at least one risk point is identified. Logical test cases are written based on at least one of the risk points, and dynamic simulation is performed on the RTL model to be verified according to the logical test cases to obtain the simulation results corresponding to each risk point. The simulation results are compared with the second UPF model file to selectively modify the second UPF model file.

[0006] First, parse the power architecture file and extract the power topology information; Parse the power topology information to obtain keywords; Based on the keywords, a matching deployment rule is selected, and the power topology information is converted into a first UPF model file according to the selected deployment rule. The keywords include one or more of power domain, supply voltage, isolator, and voltage converter; the deployment rules include one or more of voltage converter deployment rules, isolation unit configuration rules, and power domain partitioning rules.

[0007] Prior to this, when the risk point is the risk of unknown state propagation that may occur when the power domain is powered down, the method further includes: obtaining the name of the powered-down power domain; Based on the name of the power-down domain, obtain the digital signal during the power outage from the simulation results; If the digital signal exhibits an unknown state, an isolator is added at the interface where the unknown state propagates in the second UPF model file.

[0008] Preferably, when the risk point is the risk of an incorrect definition of the power supply voltage in the power domain, the method further includes: Get all power domain names; Based on the power domain name, obtain the target voltage value of the power state transition node from the simulation results; Based on the power domain name, obtain the actual voltage value of the power state transition node from the second UPF model file; For each power state transition node, the target voltage value is compared with the actual voltage value. If at least one voltage value is different, the actual voltage value at the power state transition node in the second UPF model file is modified according to the corresponding power domain name.

[0009] Preferably, when the risk point is the risk that there may be no voltage converter or the voltage converter direction may be incorrectly defined between two connected power domains, the method further includes: obtaining all cross-power domain signal names, wherein the cross-power domain signal appears between two connected different power domains. Based on the cross-power domain signal name, obtain the corresponding voltage amplitude and the direction of change of the target voltage amplitude from the simulation results; Obtain the actual voltage conversion direction from the voltage converter conversion rules in the second UPF model file; If the voltage amplitude remains unchanged, a voltage converter is added to the second UPF model; Otherwise, compare the target voltage amplitude change direction with the actual voltage conversion direction. If at least one voltage conversion direction is different, modify the actual voltage conversion direction in the voltage converter conversion rule in the second UPF model file.

[0010] Prior to this, when the risk point is the risk of an illegal state occurring during power state switching, the method further includes: obtaining the target jump path during power state switching from the simulation results; Obtain the actual jump path during power state switching from the second UPF model file; If the target jump path and the actual jump path are not the same, the actual jump path during power state switching in the second UPF model file is modified.

[0011] Prior to this, when the risk point is the risk of incorrect data definition in the save register after the power domain is powered down and then powered on again, the method further includes: obtaining the name of the power domain configured with the save register; Analyze the simulation results and obtain the target backup data during the power-down to power-on process based on the power domain name; Parse the second UPF model file and obtain the actual backup data based on the power domain name; Compare the target backup data with the actual backup data. If they are different, modify the backup data in the second UPF model file according to the power domain name.

[0012] Secondly, the present invention provides an apparatus for ensuring the accuracy of UPF model files based on low-power simulation, specifically comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the processor to perform the method for ensuring the accuracy of UPF model files based on low-power simulation in the first aspect.

[0013] Thirdly, the present invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors to perform the method provided by the method described in the first aspect.

[0014] Compared with existing technologies, the advantages of this invention are as follows: The power topology information in the power architecture file is used to generate a first UPF model file through an algorithmic model. This first UPF model file is then cross-validated with a manually written second UPF model file to identify at least one risk point. Logical test cases are then written based on this risk point, and dynamic simulation is performed using these test cases. The second UPF model file is selectively modified based on the simulation results. Using this method, the UPF model file can be identified and modified in advance, ensuring its accuracy from the early stages of the project. This effectively avoids excessively long modification iteration cycles, shortens the chip development cycle, reduces manpower and time costs, and lowers the tape-out failure rate. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0016] Figure 1 This is a flowchart illustrating a method for ensuring the accuracy of UPF model files based on low-power simulation, provided by an embodiment of the present invention. Figure 2 This is a schematic diagram of an overall chip power supply architecture provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a power domain provided in an embodiment of the present invention; Figure 4 This is provided by the embodiments of the present invention. Figure 1 A schematic diagram of the first specific process for step 104 in the middle section; Figure 5 This is provided by the embodiments of the present invention. Figure 1 A schematic diagram of the second specific process for step 104; Figure 6 This is provided by the embodiments of the present invention. Figure 1 A schematic diagram of the third specific process in step 104; Figure 7 This is provided by the embodiments of the present invention. Figure 1 A schematic diagram of the fourth specific process in step 104; Figure 8 This is provided by the embodiments of the present invention. Figure 1 A schematic diagram of the fifth specific process in step 104; Figure 9 A schematic diagram of a device for ensuring the accuracy of UPF model files based on low-power simulation, provided in an embodiment of the present invention; The reference numerals in the attached figures are as follows: 21: Processor; 22: Memory. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0019] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0020] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.

[0021] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0022] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0023] With the significant increase in chip integration, chip power consumption has become a growing concern during chip design. Consequently, more and more SoC chips are incorporating low-power technologies such as clock gating, multi-threshold voltage library units, reduced supply voltage, and power switching. While power switching technology reduces leakage and switching power consumption, potentially leading to a substantial reduction in overall power consumption, it presents additional challenges at the implementation level. These include the need to integrate complex power controllers, design intricate power switching networks, and properly manage the coordination between isolation units and holding registers. UPF model files are power supply intent descriptions generated based on the overall chip power architecture, addressing these issues and encompassing the chip's overall power supply strategy, power domain partitioning, and control logic.

[0024] Existing UPF model files are all written and provided by R&D personnel, but errors can occur due to misunderstandings of the architecture or oversights in the rules (such as incorrect power domain partitioning or missing isolation units). Currently, the method for determining whether a UPF model file is incorrect is usually done after the executable code is generated in the later stages of the project. Backend engineers generate a PG netlist through power planning and verify it through simulation. If problems are found, the UPF model file needs to be modified and the executable code rewritten, and placement and routing processes need to be repeated. A single iteration cycle can take several weeks or even months, which is inefficient and costly.

[0025] In summary, how to identify errors in UPF model files early in a project and correct them in a timely manner to reduce manpower and time costs and shorten the chip development cycle is an urgent problem to be solved in this technical field.

[0026] To address the aforementioned issues, the foregoing embodiments of this invention provide a method for ensuring the accuracy of UPF model files based on low-power simulation. An algorithm automatically generates a first UPF model file, which is then compared with a manually written second UPF model file to identify at least one risk point. A verification platform is built, and corresponding logic test cases are written based on the risk points. Dynamic simulation is performed on the verification platform to check for the risk points. The simulation results determine whether to modify the second UPF model file. This allows errors in the second UPF model file to be identified early in the project, avoiding iterative corrections later in the project, reducing manpower and time costs, and shortening the chip development cycle.

[0027] The following section, with reference to accompanying figures and specific examples, details the implementation process of a method for ensuring the accuracy of UPF model files based on low-power simulation.

[0028] like Figure 1As shown, the method for ensuring the accuracy of UPF model files based on low-power simulation provided in this embodiment of the invention specifically includes the following steps: Step 101: Obtain the power architecture file of the RTL model to be verified, and generate the first UPF model file based on the power architecture file.

[0029] The register-transfer level (RTL) model describes the logical functions between registers, defining the functions of each register and the module division. The power architecture file describes the rules and specifications for power design, management, and allocation. It mainly includes power domain hierarchy relationships (e.g., top-level power domain, sub-power domains), voltage requirements for each module (e.g., 0.8V core voltage, 1.2V I / O voltage), and power topology information such as cross-power domain signal connection topology. Its core objective is to ensure efficient, stable, and safe power supply to the power system. The UPF model file describes the power supply rules for modules under low-power conditions.

[0030] In one embodiment, the power architecture file includes a top-level power domain, power domain 1, power domain 2, and power domain 3. The top-level power domain is normally open, power domain 1 uses a 1.1V supply voltage, power domain 2 uses a 1.1V supply voltage, and power domain 3 uses a 0.8V power domain. Power domain 1 is connected to power domain 2, and power domain 2 is connected to power domain 3.

[0031] In one embodiment, a power architecture file is parsed to extract power topology information; the power topology information is parsed to obtain keywords; a matching deployment rule is selected based on the keywords, and the power topology information is converted into a first UPF model file according to the selected deployment rule. The keywords include one or more of power domains, supply voltages, isolators, and voltage converters; the deployment rules include one or more of voltage converter deployment rules, isolation unit configuration rules, and power domain partitioning rules.

[0032] Step 102: Perform a difference analysis between the first UPF model file and the manually written second UPF model file to obtain at least one risk point.

[0033] Both the first UPF model file and the manually written second UPF model file use a standardized instruction format to describe the power supply rules. The UPF model file includes multiple power domains, each identified by a unique name (e.g., power domain 1, power domain 2). Each power domain contains several configuration items used to define the attributes and behaviors of that power domain. Each configuration item has corresponding parameters, including isolation unit configuration, voltage converter and its direction, power conversion status, and the data and voltage values ​​stored in the save register.

[0034] By identifying configuration items with the same power domain name in two UPF model files, each matching configuration item with the same name is checked to see if its corresponding parameters are completely identical. If the parameters corresponding to the same configuration item in the two UPF model files are inconsistent, it can be considered a risk point. Difference analysis may yield multiple risk points, which are then placed in a risk tag list and recorded in pseudocode form.

[0035] Step 103: Write logical test cases based on the at least one risk point, and perform dynamic simulation on the RTL model to be verified according to the logical test cases to obtain the simulation results corresponding to each risk point.

[0036] Before dynamically simulating the RTL model file, a global simulation of the RTL model file is required to verify whether the normal functions of the RTL can be achieved. At this time, logic test cases are written based on the power architecture file, and the RTL model is globally simulated using the Verification Compiler Simulator (VCS) software according to the logic test cases. After verifying that the normal functions of the RTL can be achieved, corresponding logic test cases are written for each risk point in the risk label list, and the RTL model is dynamically simulated according to the logic test cases to obtain the simulation results corresponding to each risk point.

[0037] Step 104: Compare the simulation results with the second UPF model file to selectively modify the second UPF model file.

[0038] The simulation results can be a waveform file containing the states of multiple power domains, with different states corresponding to different values. By obtaining values ​​from the waveform file and comparing them with the corresponding content in the second UPF model file, the accuracy of the second UPF model file can be determined, and then a decision can be made on whether to modify the second UPF model file.

[0039] After obtaining the simulation results, we can further determine whether the risk points are correct. Since there may be more than one risk point, there will be more than one judgment required. Each judgment will produce a result. If the judgment result indicates that the risk point is problematic, the second UPF model file needs to be modified accordingly; if the judgment result indicates that the risk point is not problematic, the second UPF model file does not need to be modified.

[0040] When the second UPF model file is modified, a difference analysis needs to be performed on the first and second UPF model files again to generate a new risk marker list and remove the aforementioned risk points. Then, new logic test cases are written based on the new risk points, and a new round of dynamic simulation is performed until the risk marker list is free of risk points. Furthermore, there is no specific order for further judgment of risk points; it is sufficient to judge all risk points.

[0041] Optionally, when checking for errors in risk points, the corresponding judgment results will also be displayed through error messages. The error messages will clearly indicate that a parameter in a certain configuration item of a certain power domain is incorrect, and the second UPF model file can be selectively modified by viewing the error messages.

[0042] In this embodiment, a first UPF model file is automatically generated by an algorithm and cross-validated with a manually written second UPF model file. This significantly reduces human error, ensures the accuracy of the second UPF model file, guarantees that the actual power supply structure of the chip is consistent with the expected power supply architecture, and reduces the chip's development cycle. Furthermore, potential risk points are directly located through difference analysis, making simulation verification more targeted and shortening the debugging cycle by 30% to 50%.

[0043] The following is in conjunction with the appendix Figure 2 and attached Figure 3 Steps 101 to 104 are explained in detail to facilitate a better understanding of them.

[0044] In one embodiment, such as Figure 2 The diagram illustrates the overall power supply architecture of the chip. Specifically, the chip includes a top-level normally-on power domain and three sub-power domains: Power Domain 1, Power Domain 2, and Power Domain 3. Power Domain 1 is controllable and has two selectable power supplies, using a 1.1V supply voltage. Power Domain 2 is a normally-on power domain using a 1.1V supply voltage. Power Domain 3 is a normally-on power domain using a 0.8V supply voltage. Power Domain 1 is connected to Power Domain 2, and Power Domain 2 is connected to Power Domain 3.

[0045] Power topology information can be extracted from the chip's power architecture. This power topology information describes in more detail the rules and specifications for power design, management, and allocation. Figure 2 This includes information such as power domains, supply voltages, and power domain interconnections. In one embodiment, power topology information is presented using power domain diagrams and pseudocode. For example... Figure 3The diagram illustrates the power domains. Specifically, the chip operates under two power supplies, including a top-level normally-on power domain (TOP). TOP contains three power supply ports: power supply port 1, power supply port 2, and a reference ground port. Power supply port 1 is 1.1V, power supply port 2 is 0.8V, and the reference ground port is ground. Besides TOP, there are three other power domains: power domain 1, power domain 2, and power domain 3. Power domains TOP, 2, and 3 are normally-on and operate under power supply ports 1 and 2. Power domain 1 is controllable and has two power supplies: a switchable power supply port 1d and a normally-on power supply port 1. When power supply port 1d is off, the normally-on power supply port 1 is used to maintain the holding register in power domain 1. This requires a power switch unit in the top layer to control the switching of power supply port 1d. It also interacts with the holding register to back up data during power-up and power-down cycles. Since power domain 1 is a power domain that can be turned off, there is an isolator between it and power domain 2 to clamp the unknown state of the interface when power domain 1 is powered down. Power domain 2 and power domain 3 supply voltages differently, so a voltage converter is needed for voltage conversion.

[0046] In one embodiment, the chip power supply architecture file is first parsed to obtain power supply topology information, which is then presented in the form of power domain diagrams and pseudocode. The pseudocode is then parsed to obtain keywords, and the corresponding deployment rules are selected based on the keywords. The first UPF model file is generated based on the power domain partitioning rules, isolation unit configuration rules, and voltage converter deployment rules through a preset algorithm model.

[0047] Parsing the pseudocode reveals the keywords "isolated unit" and "voltage converter". The algorithm model then uses isolation unit configuration rules and voltage converter deployment rules to generate a template file for the first UPF model file. Simultaneously, power topology information is filled into the template file through string replacement to generate the first UPF model file.

[0048] The first generated UPF model file is in code form and contains configuration items such as power supply ports, isolators, voltage converters, storage registers, and power switch units. It is presented in a standardized form by power domain names and corresponding configuration item parameters, as follows: create_power_domain PD1;connect_voltage_net PD1 1.1; create_iso_cell_output PD1 PD2;create_power_domain PD2; connect_voltage_net PD2 1.1;create_power_domain PD3; connect_voltage_net PD3 1.1; connect_level_shifter PD2 PD3.

[0049] Then, compare the first UPF model file with the second UPF model file written by the technicians to obtain at least one risk point, and write all risk points into the risk mark list.

[0050] In one embodiment, for power domain 1, the descriptions of power supply voltage, isolators, etc. in the first UPF model file and the second UPF model file can be compared to see if they are consistent; for power domain 2 and power domain 3, the descriptions of power supply voltage, isolators, voltage converters, etc. in the first UPF model file and the second UPF model file can be compared to see if they are consistent. If there is no voltage converter between power domain 2 and power domain 3 in the second UPF model file, this point is marked as a risk point. The two files are compared repeatedly, and all risk points are written into the risk mark list.

[0051] Simultaneously, a verification platform is built to perform global simulation to verify whether the RTL model can function normally. Specifically, when power domain 1 is powered down, power domains 2 and 3 should function normally; when power domain 1 is powered on again, power domains 1, 2, and 3 should all function normally. If the RTL model functions normally, check if the risk flag list is empty. If the risk flag list is not empty, further dynamic simulation is required. For example, if unknown state propagation occurs in the chip, corresponding control logic test cases need to be constructed to check whether the isolator between power domain 1 and the external power domain can clamp all outputs of the module and achieve the expected values. If the voltage converter in the power domain is abnormal, it is necessary to check whether the interaction between power domain 2 and power domain 3 has undergone voltage conversion. If the simulation results are inconsistent with expectations, the second UPF model file needs to be modified, and then the above steps should be repeated.

[0052] In one embodiment, when a risk point exists, logical test cases need to be written based on the risk point, and dynamic simulation is performed according to these logical test cases to obtain simulation results. The simulation results are then used to determine whether the risk point is erroneous. For example, when a risk point occurs due to the power-down of a certain power domain, an unknown state propagation occurs in that power domain. Figure 4 As shown, determining whether unknown state propagation occurs when a power domain is powered down includes the following steps: Step 201: Obtain the name of the power domain.

[0053] Specifically, the second UPF model file describes which power domain is allowed to be powered down and has a corresponding power domain name. The name of the power domain that is powered down can be obtained from the second UPF model file.

[0054] Step 202: Based on the name of the power-down domain, obtain the digital signal during the power outage from the simulation results.

[0055] Specifically, by using the name of the power domain mentioned above, the falling edge of the power domain is found in the simulation results. The falling edge refers to the power domain jumping from high level to 0V. The time point at this moment is marked. Starting from this time point, the digital signal of the power domain during the power-down period is observed. The digital signal is represented as 0, 1, high impedance state and unknown state.

[0056] Step 203: If the digital signal exhibits an unknown state, an isolator is added to the interface where the unknown state propagates in the second UPF model file.

[0057] Specifically, under normal circumstances, after a power domain loses power, all output signals should be preserved as fixed values, including 0, 1, and high-impedance states, or saved in a register. However, if digital signals exhibit an unknown state during power loss, it indicates that the power domain lacks an isolator. When a power domain lacks an isolator, powering down that power domain will also affect connected power domains. In this case, an isolator description needs to be added at the interface where unknown state propagation occurs in the second UPF model file to ensure that even if the power domain loses power, it will not affect the connected power domains.

[0058] In one embodiment, one risk point is that at the power state transition node, all power domains have defined corresponding supply voltages, but there may be situations where the supply voltage of some power domains is incorrect compared to the defined supply voltage. For example... Figure 5 As shown, determining the existence and correct direction of voltage converters in all power domains involves the following steps: Step 301: Obtain all power domain names.

[0059] Specifically, all power domain names can be obtained from the second UPF model file.

[0060] Step 302: Based on the power domain name, obtain the target voltage value of the power state transition node from the simulation results.

[0061] Specifically, power state transition nodes refer to power domain power-on nodes, power domain power-off nodes, and power state switching nodes. The real-time voltage values ​​of these nodes can be obtained using their power domain names and used as target voltage values. Each power domain name corresponds to a specific target voltage value.

[0062] Step 303: Obtain the actual voltage value of the power state transition node from the second UPF model file according to the power domain name.

[0063] Specifically, the second UPF model file not only defines the name of each power domain, but also the voltage value of each power domain, as well as the voltage values ​​that should be present at power-on, power-off, and state transition nodes. The voltage values ​​of the power state transition nodes are obtained through the power domain name and used as the actual voltage values.

[0064] Step 304: For each power state transition node, compare the target voltage value with the actual voltage value. If at least one voltage value is different, modify the actual voltage value at the power state transition node in the second UPF model file according to the corresponding power domain name.

[0065] Specifically, based on the power domain name, for each power state transition node of each power domain, the target voltage value and the actual voltage value are compared. If the target voltage value and the actual voltage value of a certain power domain are found to be different, the specific power state node is recorded, and the actual voltage value at the corresponding power state transition node in the second UPF model file is modified according to the power domain name mentioned above.

[0066] In this embodiment, one risk point is that when two power domains using different supply voltages are connected, there may be a situation where a voltage converter is absent or exists but its direction is incorrect. For example... Figure 6 As shown, determining whether the supply voltage of all power domains is correct includes the following steps: Step 401: Obtain all cross-power domain signal names, where cross-power domain signals occur between two connected different power domains.

[0067] Specifically, the two power domains use different supply voltages due to different requirements, but these two power domains need to be connected to work together. At this time, a voltage converter is added between the two power domains to avoid logic errors or device damage caused by voltage mismatch.

[0068] In the second UPF model file, the voltage converter will be configured. At this time, the specific power domain can be associated with the voltage converter configuration, thereby implicitly obtaining the cross-power domain signal name.

[0069] Step 402: Based on the cross-power domain signal name, obtain the corresponding voltage amplitude and the direction of change of the target voltage amplitude from the simulation results.

[0070] Specifically, by using the aforementioned cross-power domain signal names, the cross-power domain signals are located in the simulation results, and the corresponding voltage amplitude and the direction of change of the target voltage amplitude are obtained. For example, if the obtained voltage amplitude change direction is from low level to high level, it indicates that there is a voltage amplitude change.

[0071] Step 403: Obtain the target voltage conversion direction from the voltage converter conversion rules in the second UPF model file.

[0072] Specifically, the second UPF model file specifies the voltage values ​​of two power domains, and the voltage converter configuration includes the power domain names associated with the voltage converter and the voltage converter conversion rules. These conversion rules specify whether the two power domains are transitioning from high to low or from low to high; for example, the target conversion direction might be from high to low. The target conversion direction essentially involves either reducing the supply voltage of the high power domain to the supply voltage of the low power domain, or increasing the supply voltage of the low power domain to the supply voltage of the high power domain, thereby meeting the power requirements of either the high or low power domain.

[0073] Step 404: If the voltage amplitude does not change, add a voltage converter in the second UPF model; otherwise, compare the direction of change of the target voltage amplitude with the actual voltage conversion direction. If at least one voltage conversion direction is different, modify the actual voltage conversion direction in the voltage converter conversion rule in the second UPF model file.

[0074] Specifically, if the voltage amplitude change direction is from low to high, it indicates the existence of a voltage converter between the two power domains, requiring further determination of the correctness of the voltage converter's direction. If the voltage amplitude change direction in the simulation results is from low to high, while the target conversion direction is from high to low, it indicates the voltage conversion direction between the two power domains is incorrect. In this case, the voltage converter conversion rule in the second UPF model file needs to be modified, changing the voltage converter conversion rule to be from low to high.

[0075] In this embodiment, one risk point is that an illegal state may occur during the transition between different power states. For example... Figure 7 As shown, determining whether an illegal state occurs during power state switching includes the following steps: Step 501: Obtain the target jump path during power state switching from the simulation results.

[0076] Specifically, the simulation results include the switching paths of the power domain at various times. The target switching path of the power domain can be obtained by the power domain name, and the switching path of the power domain during power switching can be known by the time point. For example, the switching path of power domain 2 is from ON to OFF.

[0077] Step 502: Obtain the actual jump path during power state switching from the second UPF model file.

[0078] Specifically, the second UPF model file defines the legal jump paths for each power domain. For example, power domain 1 can only jump from ON, while the jump path for power domain 2 is ON to STANDBY and then to OFF.

[0079] Step 503: Compare the target jump path with the actual jump path. If they are different, modify the actual jump path when the power state changes in the second UPF model file.

[0080] In this embodiment, the jump path during power state switching in the second UPF model file can be modified according to the target jump path.

[0081] Specifically, in the simulation results, the jump path of power domain 2 is ON to OFF, while in the second UPF model file, the jump path of power domain 2 is ON to STANDBY and then to OFF. It can be seen that the jump paths of the two are not the same. Therefore, the actual jump path when the power state changes in the second UPF model file should be modified according to the name of the power domain.

[0082] In this embodiment, one risk is the risk that the data saved in the register may be incorrectly defined when a power domain is powered on again after a power outage. For example... Figure 8 As shown, determining whether the data stored in the save register is correct after a power-down domain is powered on again includes the following steps: Step 601: Obtain the name of the power domain configured with the stored registers.

[0083] Specifically, power-down of a power domain will cause data loss in the standard registers. This loss can lead to state machine malfunctions and configuration failures. Therefore, during power supply design, an independently powered save register is configured for each power domain, ensuring that the save register retains the data in the standard registers even during power-down. Correspondingly, the second UPF model file configures the save register for this power domain and obtains the name of the power domain with the save register configured.

[0084] Step 602: Analyze the simulation results and obtain the target backup data during the power-down to power-on process based on the power domain name.

[0085] Specifically, from the perspective of voltage values, the power-down to power-on process refers to the process in which the voltage value of the power domain gradually increases from 0V to a specified voltage value. Based on the power domain name, the data stored in the save register of the power domain during the power-down to power-on process is obtained from the simulation results and used as the target backup data.

[0086] Step 603: Parse the second UPF model file and obtain the actual backup data based on the power domain name.

[0087] Specifically, based on the power domain name, the data stored in the save register is obtained from the second UPF model file as the actual backup data.

[0088] Step 604: Compare the target backup data with the actual backup data. If they are different, modify the backup data in the second UPF model file according to the power domain name.

[0089] Specifically, the target backup data and the actual backup data of the power domain are compared. If they are different, it means that the data in the standard register was not correctly restored after the power domain was restored. In this case, the backup data in the second UPF model file needs to be modified according to the power domain name.

[0090] In this embodiment, a first UPF model file is generated using an algorithmic model and cross-validated with a manually written second UPF model file to identify one or more risk points. Logical test cases are then written based on these risk points for dynamic simulation. The second UPF model file is selectively modified based on the simulation results. Using this method, the accuracy of the second UPF model file can be ensured at the beginning of the project, reducing the simulation cycle by more than half.

[0091] Based on the method for ensuring the accuracy of UPF model files through low-power simulation provided in the foregoing embodiments, the present invention also provides an apparatus for ensuring the accuracy of UPF model files through low-power simulation, which can be used to implement the above method, such as... Figure 9 The diagram shown is a schematic representation of the device architecture according to an embodiment of the present invention. The device for ensuring the accuracy of UPF model files based on low-power simulation in this embodiment includes one or more processors 21 and a memory 22. Figure 9 Take a processor 21 as an example.

[0092] Processor 21 and memory 22 can be connected via a bus or other means. Figure 9 Taking the example of a connection between China and Israel via a bus.

[0093] The memory 22, as a non-volatile computer-readable storage medium for ensuring the accuracy of UPF model files based on low-power simulation, can be used to store non-volatile software programs and non-volatile computer-executable programs, such as the method for ensuring the accuracy of UPF model files based on low-power simulation in the aforementioned embodiments. The processor 21 executes various functional applications and data processing of the device for ensuring the accuracy of UPF model files based on low-power simulation by running the non-volatile software programs, instructions, and modules stored in the memory 22, thereby implementing the method for ensuring the accuracy of UPF model files based on low-power simulation in the aforementioned embodiments.

[0094] Memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory remotely located relative to processor 21, which can be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0095] The program instructions / modules are stored in memory 22. When executed by one or more processors 21, they perform the method for ensuring the accuracy of UPF model files based on low-power simulation in the aforementioned embodiments. For example, they perform the above-described... Figure 1 , Figures 4 to 8 The steps shown.

[0096] This invention also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, for example... Figure 9 One of the processors 21 can enable the above-described one or more processors to execute the method for ensuring the accuracy of UPF model files based on low-power simulation in the foregoing embodiments, for example, to perform the above-described... Figure 1 , Figures 4 to 8 The steps shown.

[0097] It is worth noting that the information interaction and execution process between the modules and units in the above-mentioned device and system are based on the same concept as the processing method embodiment of the present invention. For details, please refer to the description in the method embodiment of the present invention, and will not be repeated here.

[0098] Those skilled in the art will understand that all or part of the steps in the various methods of the embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for ensuring the accuracy of UPF model files based on low-power simulation, characterized in that, include: Obtain the power architecture file of the RTL model to be verified, and generate a first UPF model file based on the power architecture file; By performing a difference analysis between the first UPF model file and the manually written second UPF model file, at least one risk point is identified. Logical test cases are written based on at least one of the risk points, and dynamic simulation is performed on the RTL model to be verified according to the logical test cases to obtain the simulation results corresponding to each risk point. The simulation results are compared with the second UPF model file to selectively modify the second UPF model file.

2. The method for ensuring the accuracy of UPF model files based on low-power simulation according to claim 1, characterized in that, Also includes: Parse the power architecture file and extract the power topology information; Parse the power topology information to obtain keywords; Based on the keywords, a matching deployment rule is selected, and the power topology information is converted into a first UPF model file according to the selected deployment rule.

3. The method for ensuring the accuracy of UPF model files based on low-power simulation according to claim 2, characterized in that, The keywords include one or more of power domain, supply voltage, isolator, and voltage converter; the deployment rules include one or more of voltage converter deployment rules, isolation unit configuration rules, and power domain partitioning rules.

4. The method for ensuring the accuracy of UPF model files based on low-power simulation according to claim 1, characterized in that, When the risk point is the risk of unknown state propagation when the power domain is powered down, the method further includes: Get the name of the next power domain; Based on the name of the power-down domain, obtain the digital signal during the power outage from the simulation results; If the digital signal exhibits an unknown state, an isolator is added at the interface where the unknown state propagates in the second UPF model file.

5. The method for ensuring the accuracy of UPF model files based on low-power simulation according to claim 1, characterized in that, When the risk point is the risk of an incorrect definition of the power supply voltage in the power domain, the method further includes: Get all power domain names; Based on the power domain name, obtain the target voltage value of the power state transition node from the simulation results; Based on the power domain name, obtain the actual voltage value of the power state transition node from the second UPF model file; For each power state transition node, the target voltage value is compared with the actual voltage value. If at least one voltage value is different, the actual voltage value at the power state transition node in the second UPF model file is modified according to the corresponding power domain name.

6. The method for ensuring the accuracy of UPF model files based on low-power simulation according to claim 1, characterized in that, When the risk point is the possibility that there may be no voltage converter or that the voltage converter direction is incorrectly defined between two connected power domains, the method further includes: Retrieve all cross-power domain signal names, where cross-power domain signals occur between two connected different power domains; Based on the cross-power domain signal name, obtain the corresponding voltage amplitude and the direction of change of the target voltage amplitude from the simulation results; Obtain the actual voltage conversion direction from the voltage converter conversion rules in the second UPF model file; If the voltage amplitude remains unchanged, a voltage converter is added to the second UPF model; Otherwise, compare the target voltage amplitude change direction with the actual voltage conversion direction. If at least one voltage conversion direction is different, modify the actual voltage conversion direction in the voltage converter conversion rule in the second UPF model file.

7. The method for ensuring the accuracy of UPF model files based on low-power simulation according to claim 1, characterized in that, When the risk point is the risk of an illegal state occurring during power state switching, the method further includes: Obtain the target jump path during power state switching from the simulation results; Obtain the actual jump path during power state switching from the second UPF model file; If the target jump path and the actual jump path are not the same, the actual jump path during power state switching in the second UPF model file is modified.

8. The method for ensuring the accuracy of UPF model files based on low-power simulation according to claim 1, characterized in that, When the risk point is the risk of incorrect data definition in the save register after the power domain is powered on again, the method further includes: Retrieve the name of the power domain configured with stored registers; Analyze the simulation results and obtain the target backup data during the power-down to power-on process based on the power domain name; Parse the second UPF model file and obtain the actual backup data based on the power domain name; Compare the target backup data with the actual backup data. If they are different, modify the backup data in the second UPF model file according to the power domain name.

9. A device for ensuring the accuracy of UPF model files based on low-power simulation, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the processor for performing the method for ensuring the accuracy of UPF model files based on low-power simulation as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it causes the computer to perform the method for ensuring the accuracy of UPF model files based on low-power simulation as described in any one of claims 1 to 8.

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