Systems, methods, and apparatus for interference avoidance in memory systems

Abstract

A method may include allocating a first memory page from a first portion of an address space based on a first access pattern to the first memory page; and allocating a second memory page from a second portion of the address space based on a second access pattern to the second memory page. The first portion of the address space may be configured for an interleaving operation. The second portion of the address space may be configured for a partitioning operation. The first memory page may be allocated based on an access mode indication. The first memory page may be allocated based on a request received from a user, and the access mode indication may be received from the user. The first portion of the address space may be mapped to a first dummy channel, and the second portion of the address space may be mapped to a second dummy channel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 63 / 515,086, filed on July 21, 2023, which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to memory systems, and more particularly, to systems, methods, and apparatus for disturb avoidance in memory systems. Background Art

[0004] The virtual memory system may use a memory mapping scheme to map virtual memory addresses to physical memory addresses in a physical memory system. The physical memory system may include one or more memory channel controllers to provide access to memory devices that may be arranged in banks, channels, ranks, etc. In some physical memory systems, a channel may be implemented with two or more pseudo-channels that may share resources such as command and / or address buses.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background of the principles of the present invention and therefore it may contain information that does not constitute the prior art. Summary of the invention

[0006] A method may include: allocating the first memory page from a first portion of an address space based on a first access mode to the first memory page; and allocating the second memory page from a second portion of the address space based on a second access mode to the second memory page. The first portion of the address space may be configured for an interleaved operation. The second portion of the address space may be configured for a partitioned operation. The first memory page may be allocated based on an access mode indication. The first memory page may be allocated based on a request received from a user, and the access mode indication may be received from the user. The first portion of the address space may be mapped to a first pseudo channel, and the second portion of the address space may be mapped to a second pseudo channel. The first pseudo channel may use a command bus, and the second pseudo channel may use a command bus. The first portion of the address space may be mapped to a third pseudo channel, and the first pseudo channel and the third pseudo channel may be configured for an interleaved operation. The interleaved operation may include channel interleaving. The interleaved operation may include bank interleaving. The method may also include: monitoring access to the first memory page; based on the monitoring, detecting a disturbance associated with the first memory page; and based on the detection, allocating a third memory page. The third memory page may be allocated from a portion of the address space configured for interleaved operation. The first memory page may be allocated from a first block of memory associated with a first channel, and the third memory page may be allocated from a second block of memory associated with a second channel. The interference may include command bus contention.

[0007] A method may include: allocating a first memory page using a first memory mapping scheme; detecting interference associated with the first memory page; and allocating a second memory page using a second memory mapping scheme based on the interference. The first memory mapping scheme may include a partitioned memory mapping scheme, and the second memory mapping scheme may include an interleaved memory mapping scheme. The first memory page may be allocated from a first portion of an address space mapped to a first pseudo channel, and the interference may include bus contention between the first pseudo channel and a second pseudo channel.

[0008] A memory system may include at least one processing circuit configured to allocate a first memory page from a first portion of an address space based on a first access pattern to the first memory page, and to allocate a second memory page from a second portion of the address space based on a second access pattern to the second memory page. The at least one processing circuit may be configured to: receive an access pattern indication; and allocate the first memory page based on the access pattern indication. The at least one processing circuit may be configured to allocate the first memory page using a first memory mapping scheme, the memory system may further include a monitoring circuit configured to detect a disturbance associated with the first memory page, and the at least one processing circuit may be configured to: allocate a third memory page using a second memory mapping scheme based on the disturbance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The drawings are not necessarily drawn to scale, and throughout the drawings, for illustrative purposes, elements of similar structure or function may generally be represented by the same reference numerals or portions thereof. The drawings are intended only to facilitate the description of the various embodiments described herein. The drawings do not describe every aspect of the teachings disclosed herein and do not limit the scope of the claims. In order to prevent the drawings from becoming obscure, not all components, connections, etc. may be shown, and not all components may have reference numerals. However, the pattern of the component configuration can be easily apparent from the drawings. The drawings, together with the specification, illustrate example embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0010] Figure 1 An embodiment of an interleaved memory address mapping scheme is shown.

[0011] Figure 2 An embodiment with a memory address mapping scheme that combines partitioning and interleaving is shown.

[0012] Figure 3 An embodiment of a memory system with combined partitioning and interleaving is shown.

[0013] Figure 4 An embodiment of a memory addressing scheme with address subspaces according to the present disclosure is shown.

[0014] Figure 5 An embodiment of a memory system with address subspaces according to the present disclosure is shown.

[0015] Figure 6 An embodiment of a memory system with disturb tracking according to the present disclosure is shown.

[0016] Figure 7 An embodiment of a memory system with address subspaces and disturb tracking according to the present disclosure is shown.

[0017] Figure 8 An example embodiment of a method for allocating memory according to the present disclosure is shown.

[0018] Fig. 9 An example embodiment of a method for allocating memory using address subspaces and disturbance tracking according to the present disclosure is shown.

[0019] Fig.10 An embodiment of a memory configuration according to the present disclosure is shown.

[0020] Fig.11 An embodiment of a partitioned memory allocation sequence according to the present disclosure is shown.

[0021] Fig.12 An embodiment of a memory allocation sequence according to the present disclosure is shown, wherein memory banks are interleaved within a memory subspace.

[0022] Fig.13 An embodiment of a memory allocation sequence according to the present disclosure is shown, wherein memory banks and channels are interleaved within a memory subspace.

[0023] Fig.14 An embodiment of a memory allocation sequence according to the present disclosure is shown in which memory banks, channels, and pseudo channels are interleaved. DETAILED DESCRIPTION

[0024] Some memory systems implement an interleaving scheme that interleaves memory accesses across memory resources (e.g., channels, rows, banks, and / or the like). Depending on implementation details, interleaving can improve performance, for example, by increasing utilization of memory resources, particularly for highly sequential traffic flows (e.g., performing sequential accesses to local memory resources such as row buffers). However, some memory traffic flows may be less sequential or even random. Depending on implementation details, less sequential traffic flows may cause interference in the interleaved access scheme. For example, using interleaved access with multi-programmed and / or multi-threaded workloads may result in interference that may reduce performance by reducing row buffer hit rates.

[0025] Some memory systems may implement partitioning schemes that can reduce interference by isolating less sequential traffic flows to non-interleaved memory partitions. However, in situations where interleaving may be beneficial, the partitioning scheme may not allow interleaving. Some memory systems may implement access schemes that can combine partitioning and interleaved access schemes, for example, using mapping aliases. However, these combined access schemes may not be applied to some memory interfaces where memory resources may have shared data paths and / or other features (e.g., pseudo channels that may have separate data buses but share command and / or address (C / A) buses).

[0026] Some memory systems according to the present disclosure may implement a partitioning scheme in which a first portion of an address space (e.g., a first subspace including a first group of first pseudo channels) may be used for a business flow having a first access mode, and a second portion of the address space (e.g., a second subspace including a second group of second pseudo channels) may be used for a business flow having a second access mode.

[0027] The first access mode may refer to a sequential access mode, a non-sequential access mode (e.g., a random access mode), etc. The second access mode may refer to a sequential access mode, a non-sequential access mode (e.g., a random access mode), etc. The second access mode may generally be, but not necessarily, different from the first access mode. For example, in an exemplary embodiment of a memory system, the first portion of the address space may initially be configured for sequential business flows, and the second portion of the address space may initially be configured for non-sequential business flows. However, the memory system may only receive business flows with sequential access modes until the first portion of the address space can be fully allocated to capacity. Therefore, the memory system may reconfigure at least some of the second portion of the memory space for sequential business flows. Nevertheless, the system is still able to allocate at least some of the second portion of the memory space or the third portion of the memory space for non-sequential business flows.

[0028] In some implementations of the above exemplary embodiments, a first portion of the address space may be implemented with a first address subspace that may include even pseudo channels, where interleaving is enabled across some or all of the even pseudo channels, and a second portion of the address space may be implemented with a second address subspace that may include odd pseudo channels, where interleaving may be disabled at least initially. In some implementations, one or more (e.g., each) of the first pseudo channels may share a C / A bus with corresponding one or more (e.g., each) of the second pseudo channels.

[0029] In some embodiments, an indication of the access pattern of memory pages to be allocated from the address space may be provided to the memory system. For example, a user such as an application, service, process, operating system, compiler, runtime environment, interpreter, etc. may provide an indication (e.g., by setting or clearing a flag) that memory pages may be accessed more sequentially or less sequentially. The memory system may use the indication to allocate pages that may be accessed more sequentially from a first portion of the address space (e.g., a first set of pseudo channels with interleaving enabled). Additionally or alternatively, the memory system may use the indication to allocate pages that may be accessed less sequentially from a second portion of the address space (e.g., a second set of pseudo channels with interleaving initially disabled).

[0030] Additionally or alternatively, some memory systems according to the present invention may implement a monitoring and / or adjustment scheme that can determine interference in the memory system and / or adjust allocation schemes, interleaving schemes, and / or the like based on the interference. For example, a memory system may track pseudo-channel contention in a portion of an address space (e.g., a set of pseudo-channels that initially disable interleaving) from which pages may be allocated for less sequential traffic flows. If pseudo-channel contention exceeds a threshold, the memory system may enable interleaving in the set of pseudo-channels. Additionally or alternatively, if pseudo-channel contention exceeds a threshold, the memory system may allocate pages for less sequential traffic flows from different channels.

[0031] The present invention covers many aspects related to memory systems. The aspects disclosed herein may have independent utility and may be embodied individually, and not every embodiment may utilize every aspect. In addition, these aspects may also be embodied in various combinations, some of which may amplify some benefits of the various aspects in a synergistic manner.

[0032] For purposes of illustration, some embodiments may be described in the context of certain specific implementation details, such as a memory device implemented using a dynamic random access memory (DRAM) having a certain number of ranks, channels, pseudo-channels, banks, etc. However, aspects of the present disclosure are not limited to these or any other implementation details.

[0033] In some embodiments, a memory page may refer to any unit of memory allocation, such as a page, cache line, block, region, etc.

[0034] Figure 1 An embodiment of an interleaved memory address mapping scheme is shown. Figure 1 The pattern of bits 102 at the top represents a physical address that a user of the memory system may send to the memory controller to access a physical memory location. Figure 1The pattern of bit indicators 104 at the bottom represents a mapping that a memory controller may use to map the physical address 102 to one or more rows, ranks, banks, groups of banks, channels, offsets, etc. of a physical memory device.

[0035] In pattern 104, Ro indicates row address bits, Ra indicates rank address bits, Ba indicates bank address bits, BG indicates bank group address bits, Ch indicates channel address bits, and X indicates an offset, e.g., within a burst. The relative positions of the bit indicators may determine the order, type, etc. of the interleaving. For example, if the bank bit Ba is closer to the least significant bit (LSB) side of the address than the channel bit Ch, the mapping may alternate more frequently between banks than between channels.

[0036] When used for a traffic flow (e.g., a sequence of memory accesses) having a relatively sequential access pattern (which may also be referred to as an access pattern having a relatively high level of sequentiality, regularity, locality, and / or localization), such as Figure 1 The interleaved memory address mapping scheme shown can provide a relatively high level of performance. Depending on the implementation details, the sequential access mode can improve performance (e.g., bandwidth, average read latency, etc.) by, for example, increasing the utilization of memory resources (e.g., channels, memory banks, etc.) and / or row buffer hit rate.

[0037] In some embodiments, a sequential access mode may refer to an access mode in which consecutive memory access requests may access consecutive or nearly consecutive physical memory addresses. Additionally or alternatively, in some embodiments, a sequential access mode may refer to an access mode in which consecutive memory access requests may access memory addresses in an order that may provide performance benefits to the underlying memory configuration. For example, in some embodiments, an access mode in which multiple columns within a row may be accessed consecutively (and therefore only involves a single row command, precharge, etc.) regardless of the exact order of column accesses may be referred to as a sequential access mode (or an access mode with a high level of locality).

[0038] However, some memory workloads may access physical memory using traffic flows that may be less sequential or non-sequential (e.g., may have less locality or may even be random). Depending on implementation details, the less sequential traffic flows may result in interference, which may degrade performance in an interleaved access scheme. For example, diverse workloads such as multi-process and / or multi-threaded workloads may contend for memory resources (e.g., may result in contention), which may exacerbate the irregularity of memory access requests received by a memory controller. Thus, the use of interleaving for multi-process and / or multi-threaded workloads may result in interference, which may degrade performance, for example, by reducing row buffer hit rates.

[0039] In some embodiments, interference caused by the use of interleaving can be reduced or eliminated by isolating less sequential traffic flows to non-interleaved memory partitions. For example, traffic flows from different processes, threads, etc. can be isolated to address subspaces that can be partitioned at the bank level or channel level using techniques such as bank-level partitioning mechanisms or application-aware memory channel partitioning. However, these partitioning schemes may not allow interleaving in situations where interleaving may be beneficial.

[0040] Some memory systems may combine partitioning and interleaving access schemes to reduce the interference caused by using interleaving for traffic flows that have less sequential behavior, while still enabling interleaving for traffic flows that can benefit from interleaving. Such memory systems may overlay multiple virtual regions on the physical address space, where each virtual region may be configured for partitioning or interleaving.

[0041] Figure 2 An embodiment with a combined partitioning and interleaving memory address mapping scheme is shown. Figure 2 The illustrated embodiment includes a memory device address space (e.g., a DRAM address space) 206, which may include a memory device arranged to be accessed using two channels Ch0 and Ch1, each channel accessing four memory banks Ba0, Ba1, Ba2, and Ba3 of the memory device, but any number of channels, memory banks, etc. may be used. In some embodiments, some or all of the memory address space 206 may be implemented with memory modules, which may include one or more rows of memory devices. For purposes of illustration, each memory bank may have memory cells arranged in 1K columns and 64K rows, as shown in a representative memory bank 210, but the memory banks may be arranged in any number of columns, rows, etc.

[0042] Multiple virtual memory regions, which may be referred to as memory device mapping aliases 212-1, 212-2, and 212-3, may be implemented by configuring a target address decoder (TAD) to overlay virtual regions on the physical address space 207. Each virtual memory region may be configured to allocate pages when: (1) both channel and bank interleaving are enabled, (2) bank interleaving is enabled but the channel is partitioned, or (3) interleaving is disabled (banks and channels are partitioned). The partitioning or interleaving scheme may be selected at runtime (e.g., by an operating system), and the memory system may ensure that only one alias is allowed to use each block of physical memory.

[0043] Map alias 212-1 shows four page frames 214-0, 214-1, 214-2, and 214-3 with both channel and bank interleaving enabled. Channel and bank identifiers in each of four rows within each page frame indicate interleaving between two channels Ch0 and Ch1 and four banks Ba0, Ba1, Ba2, and Ba3.

[0044] Map alias 212-2 shows four page frames 214-4, 214-5, 214-6, and 214-7 with bank interleaving enabled but channel interleaving disabled (e.g., channels are partitioned). The channel and bank identifiers in each of the four rows within each page frame indicate the interleaving between the four banks Ba0, Ba1, Ba2, and Ba3.

[0045] The mapping alias 212-3 shows four page frames 214-8, 214-9, 214-10, and 214-11 with both channel and bank interleaving disabled (e.g., the banks and channels are partitioned). The channel and bank identifiers in each of the two sets of rows within each page frame indicate the corresponding channels Ch0 and Ch1 and banks Ba0, Ba1, Ba2, and Ba3.

[0046] Figure 3 An embodiment of a memory system with combined partitioning and interleaving is shown. Figure 3 The illustrated embodiment can be used, for example, to implement Figure 2 The scheme shown.

[0047] refer to Figure 3, a central processing unit (CPU) 316 may implement a virtual memory system 318 that may allocate memory pages from a physical memory system 320. The virtual memory system 318 may include a translation lookaside buffer (TLB) 322 that may map a virtual address 324 to a physical address 326 using an alias identifier (ID) 328 to implement an alias 312-1 that enables both channel and bank interleaving, an alias 312-2 that enables bank interleaving but the channel is partitioned, and an alias 312-3 that disables interleaving (e.g., the bank and channel are partitioned). To ensure that only one alias is allowed to use each block of physical memory, the virtual memory system 318 may maintain mappings 330-1, 330-2, and 330-3 of blocks corresponding to the aliases 312-1, 312-2, and 312-3, and only bring blocks of memory (indicated by shading) online with only one alias. CPU 316 may run operating system 319, which may send allocation request 321 including alias selection to virtual memory system 318, which may allocate one or more pages of memory from physical memory system 320 using TLB in response to allocation request 321. In some embodiments, operating system 319 may select partitioning or interleaving aliasing at runtime.

[0048] The physical memory system 320 may include one or more channel controllers (e.g., "C" channel controllers) 332-0, ..., 332-(C-1). Each channel controller 332-0, ..., 332-(C-1) may interface with a corresponding portion of a physical memory device 341 (such as any generation of double data rate (DDR) DRAM devices (e.g., DDR3, DDR4, DDR5, etc.)) using a corresponding data bus 338-0, ..., 338-(C-1) and a C / A bus 346-0, ..., 346-(C-1).

[0049] The virtual memory system 318 and the physical memory system 320 can be connected using one or more connections 317, which can implement any type of memory interface, protocol, etc., such as one or more parallel buses that can be used with dual in-line memory modules (DIMMs) for DDR devices, graphics DDR (GDDR) devices, fully buffered DIMMs (FBDIMMs), open coherent accelerator processor interface (OpenCAPI), open memory interface (OMI), peripheral component interconnect express (PCIe), compute express link (CXL), remote direct memory access (RDMA), RDMA over converged Ethernet (RoCE), etc.

[0050] although Figure 2 and Figure 3 The memory address mapping schemes shown in can enable an operating system to select between different partitioning or interleaving schemes for each allocation request, but they may not operate with memory interfaces having certain features, such as shared signal paths, different operating modes, and / or other features that may be included in more advanced memory systems. For example, some memory systems, such as high bandwidth memory (HBM) systems, may operate in one or more modes that implement pseudo-channel pairs that may have separate data buses but share a C / A bus. Figure 2 and Figure 3 The memory address mapping scheme shown in may not be able to avoid interference in the traffic flow caused by the shared C / A bus used by the HBM pseudo channel.

[0051] Figure 4 An embodiment of a memory addressing scheme with address subspaces according to the present disclosure is shown. Figure 4 The embodiment shown in may include a physical address space 407 that can be mapped to a memory device address space (e.g., a DRAM address space) 406. For illustrative purposes, the physical address space 407 may include a first subspace 407-0 (which may also be referred to as subspace 0) and a second subspace 407-1 (which may also be referred to as subspace 1), but any number of subspaces may be used. In some embodiments, the address subspaces may be used for memory traffic flows with different access patterns. For example, the first subspace 407-0 may be used for a more sequential traffic flow, while the second subspace 407-1 may be used for a less sequential traffic flow.

[0052] The memory device address space 406 may include any arrangement of memory devices that may be configured to be mapped into the first subspace 407-0 and the second subspace 407-1. For purposes of illustration, the memory device address space 406 is shown as having memory devices that are configured to be accessed as two channels Ch0 and Ch1. The first channel Ch0 may have a first pseudo channel Pc0.0 and a second pseudo channel Pc0.1. The second channel Ch1 may have a first pseudo channel Pc1.0 and a second pseudo channel Pc1.1. Each pseudo channel may have four memory banks Ba0, Ba1, Ba2, and Ba3, but any number of banks, channels, memory banks, etc. may be used.

[0053] The first pseudo channel in each channel (e.g., Pc0.0 and / or Pc1.0) may be individually and / or collectively referred to as the first pseudo channel Pc0, and the second pseudo channel in each channel (e.g., Pc0.1 and / or Pc1.1) may be individually and / or collectively referred to as the second pseudo channel Pc1. Additionally or alternatively, the first pseudo channel in each channel (e.g., Pc0.0 and / or Pc1.0) may be individually and / or collectively referred to as the even pseudo channel, and the second pseudo channel in each channel (e.g., Pc0.1 and / or Pc1.1) may be individually and / or collectively referred to as the odd pseudo channel.

[0054] In some embodiments, the two pseudo channels of each channel can be configured as a pseudo channel pair, where each of the two pseudo channels uses a separate data bus, but the pseudo channel pair shares a common address and / or command bus. For example, pseudo channel Pc0.0 can use a first data bus, pseudo channel Pc0.1 can use a second data bus, and both pseudo channels Pc0.0 and Pc0.1 can share a command and / or address bus.

[0055] One or more memory devices used to implement the memory device address space 406 can operate in one or more modes. For example, in some embodiments, the HBM device can operate in a pseudo-channel mode, where each pseudo-channel can use a separate 16-bit wide data bus. The HBM device can also operate in a traditional mode, where two 16-bit wide data buses can be configured to operate as a single 32-bit wide data bus.

[0056] In some embodiments, the first subspace 407-0 and the second subspace 407-1 can be implemented with different subsets of pseudo channels. For example, pseudo channel Pc0.0 can be mapped to the first subspace 407-0, and pseudo channel Pc0.1 can be mapped to the second subspace 407-1. Additionally or alternatively, pseudo channel Pc1.0 can be mapped to the first subspace 407-0, and pseudo channel Pc1.1 can be mapped to the second subspace 407-1. Therefore, the pseudo channels can be partitioned into different address subspaces. For example, in some embodiments, even pseudo channels can be mapped to the first subspace, and odd pseudo channels can be mapped to the second subspace.

[0057] Additionally or alternatively, the first subspace 407-0 may be configured to enable interleaving (e.g., across memory banks), while the second subspace 407-1 may be configured to disable interleaving. Although such embodiments are not limited to any particular use, in some implementations, the first subspace 407-0 with interleaving enabled may be used for more sequential traffic flows, while the second subspace 407-1 with interleaving disabled may be used for less sequential traffic flows.

[0058] Depending on the implementation details, such a configuration can reduce pseudo-channel interference. For example, when two different types of memory traffic flows (e.g., a more sequential flow and a less sequential flow) utilize overlapping (overlapping) memory access requests (e.g., simultaneously) to attempt to access a pseudo-channel pair, a type of pseudo-channel interference may be caused. A more sequential traffic flow (e.g., a flow with relatively high locality) can send a row command (e.g., a row activation command) to open (open) row buffers, and then send multiple column commands to effectively read multiple columns in the open row. Therefore, a more sequential flow (which can advantageously use a shared C / A bus relatively freely) can use a shared C / A bus to send relatively fewer row commands.

[0059] However, due to the relative randomness of less sequential traffic flows, less sequential traffic flows (e.g., flows with relatively less locality) may send a relatively large number of row commands compared to column commands. That is, any particular access request may be less likely to access an already opened row, and therefore a row command may be sent to open a new row that may involve precharging. Therefore, if a less sequential traffic flow is mapped to the same pseudo-channel pair as a more sequential flow, a relatively large amount of C / A bus contention may result because the less sequential traffic flow may send a relatively large number of row commands using the shared C / A bus.

[0060] However, the pseudo-channel partitioning scheme according to the present disclosure can reduce this type of pseudo-channel interference (e.g., C / A bus contention). Specifically, mapping a more sequential traffic flow to a subspace interleaved across multiple pseudo-channels (e.g., interleaved across multiple even pseudo-channels) can reduce interference, where a less sequential traffic flow can be mapped to a different subspace (e.g., an odd pseudo-channel with no interleaving). Depending on implementation details, mapping a more sequential traffic flow to a subspace interleaved across multiple pseudo-channels can enable a more sequential traffic flow to send multiple column commands for each row command with little or no interference (e.g., little or no C / A bus contention with a less sequential traffic flow, which can be mapped to one or more pseudo-channels that can share one or more C / A buses with the pseudo-channels to which the more sequential traffic flow can be mapped).

[0061] Another type of interference may occur when two different traffic flows contend for different rows in the same bank of memory (e.g., attempting to activate two different rows in the same bank). For example, a less sequential memory traffic flow may be mapped not only to the same pseudo-channel pair, but also to the same pseudo-channel as a more sequential traffic flow or another less sequential traffic flow. Depending on implementation details, a pseudo-channel partitioning scheme according to the present disclosure may reduce this type of interference (e.g., bank contention), for example, by reducing or preventing overlapping attempts to access different rows in the same bank.

[0062] Figure 5 An embodiment of a memory system with address subspaces according to the present disclosure is shown. Figure 5 The system shown in can be used to implement, for example Figure 4 The memory addressing scheme shown in . Figure 5 The illustrated system may include one or more elements that may be similar to those shown in other figures, where similar elements may be indicated by reference numerals ending with and / or containing the same numbers, letters, etc.

[0063] refer to Figure 5 , the system may include a CPU 516, which may implement a virtual memory system 518 to allocate memory pages from a physical memory system 540. The virtual memory system 518 may include a translation lookaside buffer (TLB) 522, which may map a virtual address 524 to a physical address 526. The physical memory system 540 may include a memory device 542, a first pseudo channel controller 544-0, and a second pseudo channel controller 544-1 (which may also be referred to as PC controller 0 and PC controller 1, respectively). The memory device 542 and the pseudo channel controllers 544-0 and 544-1 are configured to implement one or more operating modes, at least one of which may be a pseudo channel mode, wherein the first pseudo channel may use a first data bus 546-0, the second pseudo channel may use a second data bus 546-1, and the two pseudo channels may share a command and / or address bus 5480 / 1. Some embodiments may include one or more additional pseudo channel controllers, which may implement one or more additional pseudo channels using the memory device 542, as indicated by the ellipsis.

[0064] Virtual memory system 518 and physical memory system 540 may be connected using one or more connections 517, which may implement any type of memory interface, protocol, etc., as described above with respect to Figure 3 as described.

[0065] exist Figure 5 The system shown is used to implement Figure 4In the illustrated embodiment of the memory addressing scheme, physical address 526 may refer to a physical address in physical address space 407 , and physical memory system 528 may be used to implement memory device address space 406 .

[0066] although Figure 5 The memory devices 542 shown in are not limited to any particular type of device, but in some embodiments, the memory devices 542 may be implemented with HBM devices, which may have at least one operation mode that may implement at least two pseudo channels, wherein a first pseudo channel may use a first data bus 546-0, a second pseudo channel may use a second data bus 546-1, and the two pseudo channels may share a command and / or address bus 548. Additionally or alternatively, one or more of the memory devices 542 may be implemented with two groups of memory devices (e.g., DDR devices), which may be arranged with interface circuits that may implement a pseudo channel interface, wherein one group of memory devices 542 may use a first data bus 546-0, a second group of memory devices 542 may use a second data bus 546-1, and the two groups of memory devices 542 may share a command and / or address bus 548.

[0067] Although pseudo channel controllers 544-0 and 544-1 (which may be collectively and / or individually referred to as 544) may be illustrated as separate components, in some embodiments, pseudo channel controller 544 may be implemented as part of a single channel controller, for example, as part of a memory controller that may be integrated with CPU 516.

[0068] The virtual memory system 518 may include allocation logic 550, which may be configured to allocate memory (e.g., one or more memory pages) to one or more users using a memory addressing scheme having one or more address subspaces according to the present disclosure. For example, the allocation logic 550 may allocate memory in a manner that may implement a first subspace and a second subspace, which may be similar to Figure 4 4. The first subspace 407-0 and the second subspace 407-1 are shown. The first subspace can be mapped to a pseudo channel implemented using a first pseudo channel controller 544-0, and the second subspace can be mapped to a pseudo channel implemented using a second pseudo channel controller 544-1. In some embodiments, either or both of the first subspace or the second subspace can be mapped to one or more additional pseudo channels, which can be implemented, for example, using one or more additional pseudo channel controllers 544 as indicated by the ellipsis. For example, the first subspace can be mapped to one or more even subspaces, and the second subspace can be mapped to one or more odd subspaces.

[0069] In some embodiments, the amount of memory allocated in response to a memory allocation request may be referred to as a memory allocation.Although memory allocations according to the present disclosure are not limited to any particular amount of memory, in some embodiments, memory allocations may be allocated in units of one or more pages of memory.

[0070] In some embodiments, memory allocated from an address subspace implemented by the allocation logic 550 and / or the virtual memory system 518 may be selected based on one or more memory traffic access patterns. For example, the allocation logic 550 may allocate memory for traffic flows having relatively more sequential access patterns from a first subspace including memory devices 542 controlled by a first pseudo channel controller 544-0 (and / or one or more additional even pseudo channel controllers). Additionally or alternatively, the allocation logic 550 may allocate memory for traffic flows having relatively less sequential access patterns from a second subspace including memory devices 542 controlled by a second pseudo channel controller 544-1 (and / or one or more additional odd pseudo channel controllers). In some embodiments, the first subspace may be configured to enable interleaving (e.g., across memory banks), while the second subspace may be configured to disable interleaving.

[0071] In some embodiments, the allocation logic 550 may determine which subspace to use for a particular memory allocation request (e.g., from which pseudo channel to allocate memory) based at least in part on the access mode indicator 552. For example, a user such as an application, service, process, operating system, compiler, runtime environment, interpreter, etc. may provide an access mode indicator 552 (e.g., by setting or clearing a flag) along with an allocation request to indicate that the requested memory may be accessed more sequentially or less sequentially. The allocation logic 550 may then use the access mode indicator 552 to allocate the requested memory from a particular subspace. For example, if a user submits an allocation request to the virtual memory system 518 along with an access mode indicator 552 indicating that the allocated memory may be accessed sequentially, the allocation logic 550 may select the allocated memory from a memory subspace implemented with one or more pseudo channels with interleaving enabled.

[0072] Additionally or alternatively, the access pattern indicator 552 may be generated based on one or more observations of access patterns. For example, in some embodiments, monitoring logic internal or external to the allocation logic 550 may observe access patterns to memory allocated to a particular user and generate the access pattern indicator 552, which the allocation logic 550 may use to determine which subspace to use for additional memory allocation requests from the particular user. For example, if the monitoring logic observes that a particular application tends to perform more sequential memory accesses, the monitoring logic may provide the access pattern indicator 552 in the form of a sequential access flag and an application identifier to the allocation logic 550, which may use the information to allocate additional memory to the particular application from a memory subspace mapped to a pseudo channel with interleaving enabled.

[0073] Figure 6 An embodiment of a memory system with disturb tracking according to the present disclosure is shown. Figure 6 The system shown may include a CPU 616 and a physical memory system 640. Although not limited to any particular type of memory architecture, in some embodiments, the physical memory system 640 may include an arrangement of memory devices that may be configured to be accessed using two or more pseudo channels, which may be similar to, for example, Figure 5 The pseudo channel shown in . Figure 6 The illustrated system may include one or more elements that may be similar to those shown in other figures, where similar elements may be indicated by reference numerals ending with and / or containing the same numbers, letters, etc.

[0074] refer to Figure 6, the physical memory system 640 may include interference tracking logic 656 that may track one or more types of interference caused by memory accesses in the physical memory system 640. For example, the interference tracking logic 656 may monitor memory accesses and record instances of pseudo channel interference (e.g., C / A bus contention by two different traffic flows), bank interference (e.g., two different traffic flows attempting to activate different rows in the same bank), etc. The interference tracking logic 656 may send interference information 658 (e.g., information about instances of pseudo channel interference, bank interference, etc.) to the CPU 616. The interference information 658 may be in any form, such as a count of interference events (e.g., bus conflicts, bank interference, etc.), an average number of interference events over one or more time periods, etc. The interference information 658 may be provided to the CPU 616 by the interference tracking logic 656 actively (e.g., periodically and / or each time an interference event occurs). Additionally or alternatively, the interference tracking logic 656 may provide the interference information 658 to the CPU 616 in response to a query by the CPU 616. Interference information 658 may be tracked on any basis, such as per pseudo channel, per channel, per memory bank, per memory device, etc.

[0075] The CPU 616 may implement a virtual memory system 618 including an adjustment logic 654 that may adjust a memory allocation scheme, an interleaving scheme, etc. based on interference information 658 from interference tracking logic 656. For example, the interference tracking logic 656 may track pseudo-channel contention in a portion of an address space (e.g., an interleaved set of pseudo-channels that are initially disabled) from which pages may be allocated for less sequential traffic flows. If the interference information 658 from the interference tracking logic 656 indicates that pseudo-channel contention exceeds a threshold, the adjustment logic 654 may enable interleaving in the pseudo-channel group. Additionally or alternatively, if the pseudo-channel contention exceeds a threshold, the adjustment logic 654 may cause the virtual memory system 618 to allocate pages for less sequential traffic flows from different channels.

[0076] The virtual memory system 618 and the physical memory system 640 may be connected using one or more connections 617, which may implement any type of memory interface, protocol, etc., as described above with respect to Figure 3 as described.

[0077] Figure 7 An embodiment of a memory system with address subspaces and disturb tracking according to the present disclosure is shown. Figure 6 The system shown in can be used, for example, to implement Figure 4 The memory addressing scheme shown in Figure 5 A memory system with address subspaces as shown in and / or Figure 6One or more aspects of a memory system with disturb tracking as shown in . Figure 7 The illustrated system may include one or more elements that may be similar to those shown in other figures, where similar elements may be indicated by reference numerals ending with and / or containing the same numbers, letters, etc.

[0078] refer to Figure 7 , the CPU 716 may implement a virtual memory system 718 that may allocate memory pages from the physical memory system 740. The virtual memory system 718 may include a TLB 722 that may map a virtual address 724 to a physical address 726 using an alias identifier 728 to implement an alias 712-1 that enables both channel and bank interleaving, an alias 712-2 that enables bank interleaving but the channels are partitioned, and / or an alias 712-3 that disables interleaving (e.g., the banks and channels are partitioned). In some embodiments, to ensure that only one alias is allowed to use each block of physical memory, the virtual memory system 718 may maintain mappings 730-1, 730-2, and 730-3 of the blocks corresponding to the aliases 712-1, 712-2, and 712-3, and only bring blocks of memory (indicated by shading) online with only one alias.

[0079] The virtual memory system 718 and the physical memory system 740 may be connected using one or more connections 717, which may implement any type of memory interface, protocol, etc., as described above with respect to Figure 3 as described.

[0080] The physical memory system 740 may include a memory device 742 and one or more pseudo channel controllers 744 that may be arranged in pairs to implement pseudo channel pairs. For example, each of the even pseudo channel controllers 744-0, 744-2, ..., 744-(C-2) (also referred to as PC controller 0, PC controller 2, ..., PC controller C-2) may be arranged in pairs with a corresponding odd pseudo channel controller 744-0, 744-2, ..., 744-(C-1)) (also referred to as PC controller 1, PC controller 3, ..., PC controller (C-1)), where C may indicate the total number of pseudo channels.

[0081] In some embodiments, the pseudo channel controller pair 744 can use separate data buses 746 but a shared C / A bus 748 to access the memory device 742. For example, each of the even pseudo channel controllers 744-0, 744-2, ..., 744-(C-2) can use the even data bus 746-0, 746-2, ..., 746-(C-2), and each of the odd pseudo channel controllers 744-0, 744-2, ..., 744-(C-1) can use the odd data bus 746-1, 746-3, ..., 746-(C-1). However, the first pseudo channel controller pair 744-0 and 744-1 can share the first C / A bus 748-0 / 1, the second pseudo channel controller pair 744-0 and 744-1 can share the second C / A bus 748-2 / 3, and so on, until the last pseudo channel controller pair 744-(C-2) and 744-(C-1) can share the last C / A bus 748-(C-2) / (C-1).

[0082] Although the memory devices 742 are not limited to any particular type of device, in some embodiments, one or more of the memory devices 742 may be implemented with an HBM device, which may have at least one operation mode that may implement at least two pseudo channels, wherein a first pseudo channel may use a first data bus (e.g., 746-0), a second pseudo channel may use a second data bus (e.g., 746-1), and the two pseudo channels of the HBM device may share a command and / or address bus (e.g., 748-0 / 1). Additionally or alternatively, one or more of the memory devices 742 may be implemented with two groups of memory devices (e.g., DDR devices), which may be arranged with an interface circuit that may implement a pseudo channel interface, wherein one group of memory devices 742 may use a first data bus (e.g., 746-0), a second group of memory devices 742 may use a second data bus (e.g., 746-1), and the two groups of memory devices 742 may share a C / A bus (e.g., 748-0 / 1).

[0083] The CPU 716 may run an operating system 719. A user 760 (e.g., an application, a service, a process, a compiler (e.g., a just-in-time compiler), a runtime environment, an interpreter, etc.) may send a memory allocation request 762 to the operating system 719. In some embodiments, the user 760 may send an access mode indication 752 to the operating system 719 to indicate an expected access mode for the requested memory. Additionally or alternatively, the access mode indication 752 may be provided to the operating system 719 by monitoring logic that may observe access patterns to memory allocated to the user 760 and generate an access mode indicator 752 based on the observed access patterns.

[0084] In response to receiving a memory allocation request 762 from a user 760, the operating system 719 may generate a memory allocation request 721 that includes one or more partition and / or interleave alias selections that the operating system 719 may send to the virtual memory system 718. In some embodiments, the operating system 719 may also forward an access mode indication 752 along with the corresponding memory allocation request 721 to the virtual memory system 718. In some embodiments, the operating system 719 may select a partition or interleave alias at runtime, for example, in response to the access mode indication 752, interference information as described below, and / or other information.

[0085] In some embodiments, the virtual memory system 718 may include allocation logic 750, which may be configured to allocate memory (e.g., one or more memory pages) to one or more users using a memory addressing scheme having one or more address subspaces according to the present disclosure. For example, the allocation logic 750 may allocate memory in a manner that may implement a first subspace and a second subspace, which may be similar to Figure 4 The first subspace 407-0 and the second subspace 407-1 are shown. The first subspace can be mapped to a pseudo channel implemented by an even pseudo channel controller 744-0, 744-2, ..., 744-(C-2), and the second subspace can be mapped to a pseudo channel implemented by an odd pseudo channel controller 744-1, 744-3, ..., 744(C-1).

[0086] In some embodiments, the allocation logic 750 may determine which subspace to use for a particular memory allocation request (e.g., from which pseudo channel to allocate memory) based at least in part on the access mode indicator 752. For example, the user 760 may provide the access mode indicator 752 (e.g., by setting or clearing a flag) and a corresponding allocation request 762 to the operating system 719 to indicate that the requested memory may be accessed more sequentially or less sequentially. The operating system 719 may use the allocation request 762 from the user 760 to generate a memory allocation request 721 including one or more alias selections that the operating system 719 may send to the virtual memory system 718. The operating system 719 may also forward the access mode indication 752 along with the corresponding memory allocation request 721 to the virtual memory system 718.

[0087] The allocation logic 750 may then use the access mode indicator 752 to allocate the requested memory from a particular subspace. For example, if the memory allocation request 721 is accompanied by an access mode indicator 752 indicating that the allocated memory may be accessed sequentially, the allocation logic 750 may select the allocated memory from a memory subspace implemented with one or more even pseudo channels from mapping aliases 712-1 (both channel and bank interleaving are enabled) or 712-2 (bank interleaving is enabled but the channel is partitioned). In some embodiments, the selection between mapping aliases 712-1 and mapping aliases 712-2 may be made by an operating system 719. In other embodiments, the selection between mapping aliases 712-1 and mapping aliases 712-2 may be made by the allocation logic 750. In some embodiments, the partitioning or interleaving scheme may be selected at runtime (e.g., by an operating system), and / or the virtual memory system 718 and / or the physical memory system 740 may ensure that only one alias is allowed to use each block of physical memory.

[0088] Figure 8 An example embodiment of a method for allocating memory according to the present disclosure is shown. Figure 8 The illustrated embodiment can be used, for example, to implement Figure 7 Allocation logic 750 is shown.

[0089] refer to Figure 8 , the method may begin at operation 868-1, where the method may receive a request for a memory allocation (e.g., memory allocation request 721) (e.g., at allocation logic 750). At operation 868-2, the method may check an access mode indication (e.g., access mode indication 752) to determine a possible, expected, planned, and / or similar access mode for the requested memory. If the access mode of the requested memory is sequential, the method may proceed to operation 868-3, where the method may allocate a memory allocation (e.g., one or more pages of memory) from a memory subspace implemented with one or more pseudo channels with interleaving enabled (e.g., by one or more of even pseudo channel controllers 744-0, 744-2, ..., 744-(C-2)). For example, the requested memory may be allocated using one or more even pseudo channels from mapping alias 712-1 (both channel and bank interleaving enabled) or 712-2 (bank interleaving enabled but channel partitioned).

[0090] However, if at operation 868-2, the method determines that the access pattern to the requested memory is non-sequential, the method may proceed to operation 868-4, where the method may allocate memory allocations (e.g., one or more pages of memory) from a memory subspace implemented with one or more pseudo channels having partitioning (e.g., having disabled interleaving), such as with one or more of the odd pseudo channel controllers 744-1, 744-3, ..., 744(C-1). For example, the requested memory may be allocated using one or more odd pseudo channels from 712-3 (with both channel and bank interleaving disabled).

[0091] refer to Figure 7 In some embodiments, one or more of the pseudo channel controllers 744 may include interference tracking logic 756-0, 756-1, ..., 756-(C-1) for tracking pseudo channel interference. An instance of interference tracking logic 756 (e.g., 756-0 in pseudo channel controller 744-0) may include a data structure 764 and one or more counters 766, which may maintain a list of addresses of memory blocks that have experienced C / A bus contention events (e.g., on C / A bus 748-0 / 1), and one or more counters 766 may maintain a count of C / A bus contention events corresponding to the memory block addresses.

[0092] The interference tracking logic 756 may send interference information 758-0, 758-1, ..., 758-(C-1) (e.g., a list of one or more memory block addresses and one or more counts of C / A bus contention events corresponding to the memory block addresses) to the adjustment logic 754 at the virtual memory system 718. In some embodiments, the adjustment logic 754 may include aggregate interference tracking logic 755, which may aggregate (e.g., combine, add, etc.) the interference information 758, for example, by adding counts of C / A bus contention events for memory block addresses from respective instances of the interference tracking logic 756-0, 756-1, ..., 756-(C-1). The aggregate interference tracking logic 755 may include a data structure 770 that may maintain an aggregate list of memory block addresses that have experienced C / A bus contention events (e.g., on the C / A bus 748) and one or more counters 772 that may maintain one or more aggregate counts of C / A bus contention events for corresponding memory block addresses.

[0093] Any suitable technique may be used to send the interference information 758 to the virtual memory system 718. For example, some embodiments may use one or more registers, such as registers that may be used to configure the pseudo channel controller 744, the memory device 742, etc., but any other communication path from the pseudo channel controller 744 to the virtual memory system 718 may be used.

[0094] In some embodiments, the adjustment logic 754 can adjust the memory allocation scheme, interleaving scheme, etc. based on the aggregate list of memory block addresses and / or the aggregate count of C / A bus contention events for the corresponding memory block addresses. For example, the interference tracking logic 756 and / or the aggregate interference tracking logic 755 can track pseudo-channel contention in a portion of the address space (e.g., a group of pseudo-channels with initially disabled interleaving), from which pages can be allocated for less sequential business flows. If one or more aggregate counts of C / A bus contention events indicate that pseudo-channel contention exceeds a threshold, the adjustment logic 754 can enable interleaving in the group of pseudo-channels. Additionally or alternatively, if pseudo-channel contention exceeds a threshold, the adjustment logic 754 can cause the virtual memory system 718 to allocate pages for less sequential business flows from different channels.

[0095] In some example embodiments, the allocation logic 750 and the adjustment logic 754 may operate in a collaborative manner to implement a memory allocation scheme with combined address subspaces and interference tracking according to the present disclosure. For example, in some embodiments, the allocation logic 750 may implement the first feature with a coarse-grained pseudo-channel partitioning scheme based on an access mode indication 752 that may be implemented with sequential access flags.

[0096] In such an embodiment, a user 760 (e.g., higher level software such as an application, compiler, runtime, etc.) may send a memory access request 762 and provide an in-sequential access flag to the operating system, which may generate an allocation request 721 (e.g., with alias selection) and pass a flag to the virtual memory system 718 to indicate whether the memory allocated based on the request 721 is likely to be accessed in-sequentially or non-sequentially. Allocations indicated as in-sequential are likely to be accessed in-sequentially by the in-sequential access flag and may be taken from interleaving-enabled even pseudo-channels (e.g., pseudo-channels implemented by even pseudo-channel controllers 744-0, 744-2, ..., 744-(c-2)) across some or all of the even pseudo-channels, while allocations indicated as non-sequential are likely to be accessed non-sequentially by the in-sequential access flag and may be taken from odd pseudo-channels (e.g., pseudo-channels implemented by odd pseudo-channel controllers 744-1, 744-3, ..., 744(c-1)).

[0097] Depending on implementation details, this shared system may tend to reduce C / A bus contention and / or improve performance. For example, by directing sequential and non-sequential allocations to different subsets of pseudo-channels, traffic flows that tend to have a large number of row commands (e.g., non-sequential accesses) may tend to share the C / A bus with traffic flows that tend to have a smaller number of row commands (e.g., sequential accesses).

[0098] In addition, in such an embodiment, the adjustment logic 754 in combination with the allocation logic 750 can implement a second feature of adaptive allocation based on pseudo channel interference tracking. For example, in some cases, non-sequential allocations allocated from odd pseudo channels that disable interleaving may eventually accidentally map to the same pseudo channel (e.g., during the time when other pseudo channels are not activated). In one example of this case, the workload may initially start with six memory service flows, two of which may be allocated to the first pseudo channel, and four of which may be allocated to four other available pseudo channels, and therefore, there may be little or no interference on the workload that can be extended across several pseudo channels. However, the workload may change in such a way that the four flows allocated to the four other pseudo channels may become idle (e.g., may be completed), and therefore, the workload may be concentrated in two memory service flows that may be allocated to one pseudo channel, while the four other available pseudo channels are not activated, resulting in a relatively large amount of pseudo channel interference on the first pseudo channel.

[0099] Depending on implementation details, the adjustment logic 754 can help avoid this type of interference situation. For example, in some embodiments, the interference tracking logic 756 in one or more of the pseudo channel controllers 744 may include a counter for each activated block that is incremented each time a command to an address within the block experiences a C / A bus conflict. The virtual memory system 718 may periodically query the interference tracking logic 756 in the pseudo channel controller 744 to obtain the values ​​of the counters and store them in the aggregate interference tracking logic 755 (e.g., in the data structure 770 and / or the counter 772). The virtual memory system 718 may check the aggregate interference tracking logic 755 when allocating an allocation to an alias. If an attempt is made to allocate a page in a non-sequential portion of an address subspace (e.g., a subspace implemented with odd pseudo channel controllers 744-1, 744-3, ..., 744(C-1)) within a block having a corresponding counter that has reached a threshold to disable channel interleaving, the allocation logic 750 and / or the adjustment logic 754 within the virtual memory system 718 may instead allocate the page from within a block that has channel interleaving enabled. Alternatively or additionally, the allocation logic 750 and / or the adjustment logic 754 within the virtual memory system 718 may allocate the page within a region assigned to a different channel.

[0100] In some embodiments, one or more thresholds (e.g., one or more counter thresholds) for interference tracing may be configurable, for example, by an application, service, process, operating system, compiler, runtime environment, interpreter, system administrator, vendor, etc. Additionally or alternatively, one or more elements (e.g., one or more counters) of tracing logic 756 and / or 755 may be reset, for example, periodically and / or at one or more intervals, which may be configurable by an application, service, process, operating system, compiler, runtime environment, interpreter, system administrator, vendor, etc.

[0101] In some embodiments, and depending on implementation details, the second feature with adaptive allocation based on pseudo channel interference tracking can substantially cause the virtual memory system 718 to use an at least partially interleaved memory allocation scheme even if the first feature with pseudo channel partitioning based on access pattern indication 752 would otherwise allocate memory using a partitioning scheme (or at least allocate memory allocations to different blocks within a partitioned even pseudo channel). In some embodiments, the second feature with adaptive allocation based on pseudo channel interference tracking can substantially override the first feature with pseudo channel partitioning based on access pattern indication 752, for example, by overriding the in-order access flag if the amount of contention exceeds another threshold.

[0102] Although allocation logic 750 and / or adjustment logic 754 may be illustrated as separate components, in some embodiments, some or all of allocation logic 750 and / or adjustment logic 754 may be implemented as an integrated component, part of operating system 719, and / or part of any other component.

[0103] Fig. 9 An example embodiment of a method for allocating memory using address subspaces and disturbance tracking according to the present disclosure is shown. Fig. 9 The illustrated embodiment can be used, for example, to implement Figure 7 Distribution logic 750 and / or adjustment logic 754 are shown.

[0104] refer to Fig. 9, the method may begin at operation 974-1, where the method may receive a request for a memory allocation (e.g., memory allocation request 721) (e.g., at allocation logic 750). At operation 974-2, the method may check an access mode indicator (e.g., access mode indicator 752) to determine a possible, expected, planned, and / or similar access mode for the requested memory. If the access mode of the requested memory is sequential, the method may proceed to operation 974-3, where the method may allocate a memory allocation (e.g., one or more pages of memory) from a memory subspace implemented with one or more pseudo channels with interleaving enabled (e.g., by one or more of even pseudo channel controllers 744-0, 744-2, ..., 744-(C-2)). For example, the requested memory may be allocated using one or more even pseudo channels from mapping alias 712-1 (both channel and bank interleaving enabled) or 712-2 (bank interleaving enabled but channel partitioned).

[0105] However, if at operation 974-2, the method determines that the access pattern to the requested memory is non-sequential, the method can proceed to operation 974-4, where the method can determine whether interference has been detected (e.g., if the count of contention events for the block of memory associated with the allocation request has reached a threshold). If interference has not been detected (e.g., the count has not reached the threshold), the method can proceed to operation 974-5, where the method can allocate memory (e.g., one or more pages of memory) from a memory subspace implemented with one or more pseudo channels having partitioning (e.g., with interleaving disabled, such as by using one or more of the odd pseudo channel controllers 744-1, 744-3, ..., 744(C-1)). For example, the requested memory can be allocated using one or more odd pseudo channels from the mapping alias 712-3 (both channel and bank interleaving disabled).

[0106] However, if interference has been detected at operation 974-4 (e.g., the count has reached a threshold), the method may proceed to operation 974-6, where the method may allocate memory from a memory subspace implemented with one or more pseudo channels with interleaving enabled (e.g., by one or more of odd pseudo channel controllers 744-1, 744-3, ..., 744(C-1)). For example, the requested memory may be allocated using one or more odd pseudo channels from mapping alias 712-1 (both channel and bank interleaving enabled) or 712-2 (bank interleaving enabled but channel partitioned).

[0107] Fig.10An embodiment of a memory configuration according to the present disclosure is shown. Fig.10 The embodiments shown in can be used, for example, to implement any of the virtual memory systems, physical memory systems, etc. referenced herein.

[0108] exist Fig.10 In the illustrated embodiment, the memory banks of the memory device may be arranged in two channels, which may also be referred to as channel 0 and channel 1 .

[0109] The memory banks of the memory devices in channel 0 may be arranged in two pseudo channels, which may be referred to as pseudo channel 0.0 and pseudo channel 0.1.

[0110] The memory banks of the memory devices in channel 1 may be arranged in two pseudo channels, which may be referred to as pseudo channel 1.0 and pseudo channel 1.1.

[0111] The banks of the memory devices within pseudo channel 0.0 may be indicated as bank 0.0.0, bank 0.0.1, bank 0.0.2, and bank 0.0.3.

[0112] The banks of the memory devices within pseudo channel 0.1 may be indicated as bank 0.1.0, bank 0.1.1, bank 0.1.2, and bank 0.1.3.

[0113] The banks of the memory devices within pseudo channel 1.0 may be indicated as bank 1.0.0, bank 1.0.1, bank 1.0.2, and bank 1.0.3.

[0114] The memory banks of the memory devices within pseudo channel 1.1 may be indicated as bank 1.1.0, bank 1.1.1, bank 1.1.2, and bank 1.1.3.

[0115] For illustrative purposes, Fig.10 The embodiment shown in includes two channels, each channel includes two dummy channels, and each dummy channel includes four memory banks. However, in other embodiments, any number of channels, dummy channels, memory banks, etc. may be used.

[0116] Fig.11 An embodiment of a partition memory allocation sequence according to the present disclosure is shown. For the purpose of illustration, in the use Fig.10 The memory configuration shown in the Fig.11 , but other memory configurations may be used. For example, if the memory devices in the physical memory system 740 are at least partially configured as Fig.10 The arrangement shown, Figure 7 The virtual memory system 718 shown may be used Fig.11The illustrated embodiment responds to a memory request 721 from Figure 7 A physical memory system 740 is shown allocating memory.

[0117] Fig.11 The embodiments shown in can be used, for example, to implement a partitioned (eg, non-interleaved) memory allocation scheme such as Figure 7 The mapping alias 712-3 shown in FIG. Depending on the implementation details, Fig.11 The illustrated embodiment may be used to implement a memory subspace with pseudo channel interleaving disabled, e.g. Figure 8 Operation 868-4 is shown.

[0118] refer to Fig.11 , allocations may be made in response to memory allocation requests indicated as request 0, request 1, ..., request 15 as shown.

[0119] In response to request 0, request 1, request 2, and request 3, memory may be allocated from bank 0.0.0.

[0120] In response to request 4, request 5, request 6, and request 7, memory may be allocated from bank 0.0.1.

[0121] In response to request 8, request 9, request 10, and request 11, memory may be allocated from memory bank 0.0.2.

[0122] In response to request 12, request 13, request 14, and request 15, memory may be allocated from bank 0.0.3.

[0123] Fig.12 An embodiment of a memory allocation sequence according to the present disclosure is shown, wherein memory banks within a memory subspace are interleaved. For illustration purposes, in the example of FIG. Fig.10 The memory configuration shown in the Fig.12 , but other memory configurations may be used. For example, if the memory devices in the physical memory system 740 are at least partially configured as Fig.10 The arrangement shown, Figure 7 The virtual memory system 718 shown may be used Fig.12 The illustrated embodiment responds to a memory request 721 from Figure 7 A physical memory system 740 is shown allocating memory.

[0124] Fig.12 The embodiments shown in can be used, for example, to implement an interleaved memory allocation scheme, such as Figure 7 712-2 (bank interleaving enabled but channels partitioned). Depending on implementation details, Fig.11The embodiments shown in can be used to implement interleaved enabled memory subspaces between memory banks, for example, as Figure 8 Operation 868-3 shown in .

[0125] refer to Fig.12 , allocations may be made in response to memory allocation requests indicated as request 0, request 1, ..., request 15 as shown.

[0126] In response to request 0, request 1, request 2, and request 3, memory may be allocated from bank 0.0.0, bank 0.0.1, bank 0.0.2, and bank 0.0.3, respectively.

[0127] In response to request 4, request 5, request 6, and request 7, memory may be allocated from bank 0.0.0, bank 0.0.1, bank 0.0.2, and bank 0.0.3, respectively.

[0128] In response to request 8, request 9, request 10, and request 11, memory may be allocated from bank 0.1.0, bank 0.1.1, bank 0.1.2, and bank 0.1.3, respectively.

[0129] In response to request 12, request 13, request 14, and request 15, memory may be allocated from bank 0.1.0, bank 0.1.1, bank 0.1.2, and bank 0.1.3, respectively.

[0130] Fig.13 An embodiment of a memory allocation sequence according to the present disclosure is shown, wherein banks and channels are interleaved within a memory subspace. For illustration purposes, in the example of FIG. Fig.10 The memory configuration shown in the Fig.13 , but other memory configurations may be used. For example, if the memory devices in the physical memory system 740 are at least partially configured as Fig.10 Arranged as shown in Figure 7 The virtual memory system 718 shown in FIG. 1 may be used to Fig.13 The embodiment shown in FIG. 7 is to respond to a memory request 721 from Figure 7 The physical memory system 740 shown in FIG. 7 allocates memory.

[0131] Fig.13 The embodiments shown in can be used, for example, to implement an interleaved memory allocation scheme, such as Figure 7 712-1 (bank and channel interleaving enabled). Fig.13 The embodiments shown in can be used to implement memory subspaces that enable interleaving between memory banks and channels, for example, as Figure 8Operation 868-3 shown in .

[0132] refer to Fig.13 , allocations may be made in response to memory allocation requests indicated as request 0, request 1, ..., request 15 as shown.

[0133] In response to request 0, request 1, request 2, and request 3, memory may be allocated from bank 0.0.0, bank 1.0.0, bank 0.0.1, and bank 1.0.1, respectively.

[0134] In response to request 4, request 5, request 6, and request 7, memory may be allocated from bank 0.0.2, bank 1.0.2, bank 0.0.3, and bank 1.0.3, respectively.

[0135] In response to request 8, request 9, request 10, and request 11, memory may be allocated from bank 0.1.0, bank 1.1.0, bank 0.1.1, and bank 1.1.1, respectively.

[0136] In response to request 12, request 13, request 14, and request 15, memory may be allocated from bank 0.1.2, bank 1.1.2, bank 0.1.3, and bank 1.1.3, respectively.

[0137] Fig.14 An embodiment of a memory allocation sequence according to the present disclosure is shown, wherein banks, channels, and pseudo channels are interleaved. For illustration purposes, in the example of FIG. Fig.10 The memory configuration shown in the Fig.14 The embodiment shown in , however other memory configurations may be used.

[0138] refer to Fig.14 , in response to memory allocation requests indicated as request 0, request 1, ..., request 15, allocation may be performed as shown.

[0139] In response to request 0, request 1, request 2, and request 3, memory may be allocated from bank 0.0.0, bank 0.1.0, bank 1.0.0, and bank 1.1.0, respectively.

[0140] In response to request 4, request 5, request 6, and request 7, memory may be allocated from bank 0.0.1, bank 0.1.1, bank 1.0.1, and bank 1.1.1, respectively.

[0141] In response to request 8, request 9, request 10, and request 11, memory may be allocated from bank 0.0.2, bank 0.1.2, bank 1.0.2, and bank 1.1.2, respectively.

[0142] In response to request 12, request 13, request 14, and request 15, memory may be allocated from bank 0.0.3, bank 0.1.3, bank 1.0.3, and bank 1.1.3, respectively.

[0143] Any functionality described herein, including any logic and / or other functionality that may be implemented as part of a virtual memory system, a physical memory system, etc., may be implemented in hardware (e.g., circuitry), software, firmware, or any combination thereof, including, for example, hardware and / or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memory (such as DRAM and / or SRAM), non-volatile memory (including flash memory), persistent memory (such as cross-grid non-volatile memory, memory with body resistance change, phase change memory (PCM), etc.), one or more complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), processors that execute instructions stored in any type of memory, (including one or more complex instruction set computer (CISC) processors (such as x86 processors) and / or reduced instruction set computer (RISC) processors (such as ARM processors), graphics processing units (GPUs), neural processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), etc.), or any combination thereof. In some embodiments, one or more components may be implemented as a system on a chip (SOC).

[0144] In some embodiments, elements identified with reference numerals having an expansion of the base numeral (e.g., using a dash, a period, etc.) may be referred to collectively and / or individually by the base numeral. Thus, for example, pseudo channel controllers 544-0 and / or 544-1 may be collectively and / or individually referred to as 544.

[0145] Some embodiments disclosed herein have been described in the context of various implementation details, but the principles of the present disclosure are not limited to these or any other specific details. For example, some functions have been described as being implemented by certain components, but in other embodiments, functions may be distributed between different systems and components in different locations and with various user interfaces. Certain embodiments have been described as having specific processes, operations, etc., but these terms also cover embodiments in which specific processes, operations, etc. can be implemented with multiple processes, operations, etc., or embodiments in which multiple processes, operations, etc. can be integrated into a single process, step, etc. References to components or elements may refer only to a portion of a component or element. For example, references to blocks may refer to the entire block or one or more sub-blocks. Terms such as "first" and "second" used in the present disclosure and claims may be used only for the purpose of distinguishing the elements they modify, and may not indicate any spatial or temporal order unless otherwise apparent from the context. In some embodiments, references to elements may refer to at least a portion of an element, for example, "based on" may refer to "based at least in part on", etc. References to the first element may not imply the presence of the second element. The principles disclosed herein have independent utility and may be embodied separately, and not every embodiment may utilize every principle. However, these principles can also be embodied in various combinations, some of which can amplify the benefits of the individual principles in a synergistic manner. The various details and embodiments described above can be combined to produce additional embodiments according to the inventive principles of this patent disclosure.

[0146] Since the inventive concepts of this patent disclosure may be modified in arrangement and detail without departing from the inventive concept, such changes and modifications are considered to fall within the scope of the appended claims.

Claims

1. A method for interference avoidance in a memory system, comprising: allocating a first memory page from a first portion of an address space based on a first access pattern to the first memory page; as well as Based on a second access pattern to a second memory page, the second memory page is allocated from a second portion of the address space.

2. The method according to claim 1, wherein: The first portion of the address space is configured for interleaved operations.

3. The method according to claim 2, wherein: The second portion of the address space is configured for partitioned operations.

4. The method according to claim 1, wherein: The first memory page is allocated based on an access pattern indication.

5. The method according to claim 4, wherein: The first memory page is allocated based on a request received from a user; and The access mode indication is received from the user.

6. The method according to claim 1, wherein: The first portion of the address space is mapped to a first pseudo channel; as well as The second portion of the address space is mapped to a second pseudo channel.

7. The method according to claim 6, wherein: The first pseudo channel uses a command bus; and The second pseudo channel uses the command bus.

8. The method according to claim 6, wherein: The first portion of the address space is mapped to a third pseudo channel; and The first pseudo channel and the third pseudo channel are configured for interleaved operation.

9. The method according to claim 8, wherein: The interleaving operation includes channel interleaving.

10. The method according to claim 8, wherein: The interleaving operation includes memory bank interleaving.

11. The method according to claim 1, further comprising: monitoring access to the first memory page; based on the monitoring, detecting a disturbance associated with the first memory page; as well as Based on the detecting, a third memory page is allocated.

12. The method according to claim 11, wherein: The third memory page is allocated from a portion of the address space configured for interleaved operations.

13. The method according to claim 11, wherein: The first memory page is allocated from a first block of memory associated with a first channel; and The third memory page is allocated from a second block of memory associated with a second channel.

14. The method according to claim 11, wherein: The interference includes command bus contention.

15. A method for interference avoidance in a memory system, comprising: allocating a first memory page using a first memory mapping scheme; detecting a disturbance associated with the first memory page; as well as Based on the interference, a second memory page is allocated using a second memory mapping scheme.

16. The method of claim 15, wherein: The first memory mapping scheme comprises a partitioned memory mapping scheme; and The second memory mapping scheme includes an interleaved memory mapping scheme.

17. The method of claim 15, wherein: The first memory page is allocated from a first portion of an address space mapped to a first pseudo channel; and The interference includes bus contention between the first pseudo channel and the second pseudo channel.

18. A memory system comprising: at least one processing circuit configured to: allocating a first memory page from a first portion of an address space based on a first access pattern to the first memory page; as well as Based on a second access pattern to a second memory page, the second memory page is allocated from a second portion of the address space.

19. The memory system of claim 18, wherein: The at least one processing circuit is configured to: receiving an access mode indication; and Based on the access pattern indication, the first memory page is allocated.

20. The memory system of claim 18, wherein: The at least one processing circuit is configured to allocate the first memory page using a first memory mapping scheme; The memory system also includes a monitoring circuit configured to detect a disturbance associated with the first memory page; and The at least one processing circuit is configured to allocate a third memory page using a second memory mapping scheme based on the interference.

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