A high-speed IOMMU circuit suitable for SIOV virtualization devices

Abstract

The present invention discloses a high-speed IOMMU circuit suitable for SIOV virtualization equipment, which mainly includes a CSR configuration module, a substitution processing module, a page substitution module, a PCACHE (page high-speed cache memory), a TLB (fast table) module, and a memory access interface module; wherein the TLB module includes PAGETLB (fast table of page table) and PDTLB (fast table of device table); in order to improve the substitution speed of IOMMU, IOMMU integrates a TLB circuit to speed up the substitution speed. In the case of PAGETLB missing, PDTLB is first queried. If PDTLB hits, the base address of the first-level page table can be obtained to speed up the page table substitution, otherwise, a five-level page table query is entered. Any first-level missing of the five-level page table requires memory access to read the missing content. The present invention meets the requirements of SIOV virtualization function of IO equipment, supports multiple page sizes and high-speed virtual-real address substitution.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a high-speed IOMMU circuit suitable for SIOV virtualization equipment. Background Art

[0002] With the development of virtualization technology, SIOV (Scable I / O Virtualization) virtualization has become an important direction of virtualization development. In order to support SIOV virtualization function, IO devices need to convert virtual addresses into physical addresses in units of PASSID. As a circuit for implementing the conversion between virtual addresses and physical addresses of IO devices, IOMMU (Input / Output Memory Management Unit) needs to support the conversion between virtual addresses and physical addresses in units of PASSID.

[0003] In different application scenarios, the system has different requirements for memory access page size. Therefore, in order to meet the system's requirements for multiple page sizes, IOMMU needs to support the replacement requirements of multiple page sizes.

[0004] The replacement performance of IOMMU will affect the memory access speed of IO devices. In order to improve the memory access speed of IO devices, IOMMU needs to support the TLB function to achieve fast address replacement. At the same time, it also needs to integrate the page table cache to reduce the memory access frequency and speed up the table lookup speed. Summary of the invention

[0005] The object of the present invention is to provide a high-speed IOMMU circuit suitable for SIOV virtualization equipment to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a high-speed IOMMU circuit suitable for SIOV virtualization devices, which supports the conversion between virtual addresses and physical addresses of virtualization devices, and mainly includes a CSR configuration module, a substitution processing module, a page substitution module, a PCACHE, a TLB module, and a memory access interface module; wherein the TLB module includes PAGETLB and PDTLB; PCACHE is a page high-speed cache memory; TLB is a fast table; PAGETLB is a fast table of a page table; PDTLB is a fast table of a device table;

[0007] The CSR configuration module is mainly responsible for configuring the IOMMU circuit;

[0008] The substitution processing module receives the substitution request and returns the substitution response, and checks the substitution request;

[0009] The page replacement module reads data of PAGETLB, PDTLB, and PCACHE, and initiates a memory access request when the page replacement module is missing;

[0010] The memory access interface module is mainly responsible for sending memory access requests to the memory;

[0011] When the PAGETLB hits, the physical address is quickly queried; when the PDTLB hits, the base address of the first-level page table is quickly queried, thereby speeding up the query of the page table;

[0012] The PCACHE is mainly used to cache the first-level page table, the second-level page table and the third-level page table, reduce the frequency of memory access, and thus speed up the replacement of virtual and real addresses.

[0013] In one implementation, the IOMMU circuit needs to perform address substitution in units of PASSID, where PASSID is associated with an IO transaction of an external IO device, and the PASSID bit width is 20 bits. Different designs set the PASSID bit width according to actual needs; PASSID is a process address space identifier.

[0014] In one embodiment, the IOMMU circuit adopts page replacement, and the page replacement adopts a five-level page management method, which is respectively composed of a first-level PASID table, a second-level PASID table, a first-level page table, a second-level page table and a third-level page table;

[0015] The index of the first-level PASID table and the second-level PASID table is PASSID, and the index of the first-level page table, the second-level page table, and the third-level page table is the device virtual address;

[0016] The table entries of the first-level PASID table contain the base address of the second-level PASID table; the table entries of the second-level PASID table contain the base address of the first-level page table; the table entries of the first-level page table contain the base address of the second-level page table, and the table entries of the second-level page table contain the base address of the third-level page table; the table entries of the third-level page table contain physical page table entries.

[0017] In one embodiment, the virtual address bit width of the replacement request is 64 bits, wherein [61:42] is the PASSID; [41:0] is the device virtual address, and [63:62] is set with corresponding meaning according to actual conditions; wherein PASID[19:10] is the index of the first-level PASID, and the base address of the first-level PASID is generated by the CSR configuration module of the system register; PASID[9:0] contains the index of the second-level PASID; DVA[41:32] is the index of the first-level page table; DVA[31:23] is the index of the second-level page table; DVA[22:13] is the index of the third-level page table; and DVA[12:0] is the offset within the page.

[0018] In one implementation, the five-level page table lookup process is as follows:

[0019] (1) Use the "PASID table base address" plus PASID[19:10] to form an address, access the "first-level PASID table", and obtain the "second-level PASID table base address";

[0020] (2) Use the "secondary PASID table base address" plus PASID[9:0] to form an address, access the "secondary PASID table", and obtain the "first-level page table base address";

[0021] (3) Use the "first-level page table base address" plus DVA[41:32] to form an address, access the "first-level page table", and obtain the "second-level page table base address";

[0022] (4) Use the "secondary page table base address" plus DVA[31:32] to form an address, access the "secondary page table", and obtain the "third-level page table base address";

[0023] (5) Use the "third-level page table base address" plus DVA[22:13] to form an address, access the "secondary page table", and obtain the "physical page table entry".

[0024] In one embodiment, the workflow of the IOMMU circuit is as follows: before the IOMMU circuit performs virtual-real address substitution, the IOMMU circuit is configured through the CSR configuration module; after the configuration is completed, the substitution processing module receives the substitution request, checks the substitution request, and sends the substitution request that meets the requirements to the page substitution module; the page substitution module first queries PAGETLB, and once PAGETLB hits, the application engine returns a substitution response. If PAGETLB is missing, it is necessary to query PDTLB; after PDTLB hits, PCACHE is further queried to obtain the physical address. If PDTLB is missing, it is necessary to enter the five-level page management, first initiate a memory access request, and read the first-level PASID table and the second-level PASID table in the memory; after the PASID table is read, the first-level page table, the second-level page table and the third-level page table in PCACHE are queried, and the PCACHE query hits, and a substitution response is returned to the application engine. If PCACHE is missing, it is necessary to initiate a memory access request, read the corresponding content from the external memory Memory, and return a substitution response to the application engine.

[0025] In one embodiment, the IOMMU circuit supports multiple page sizes. The page size supported by the first-level page table is 8GB; the size supported by the second-level page table is 512MB or 8MB; the page size supported by the third-level page table is 8KB. Different designs set the page size according to actual needs.

[0026] The invention provides a high-speed IOMMU circuit suitable for SIOV virtualization equipment, which meets the requirements of SIOV virtualization function of IO equipment, supports multiple page sizes and high-speed virtual-real address substitution. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a block diagram of the location of IOMMU in IO devices;

[0028] Figure 2 This is the overall architecture diagram of IOMMU;

[0029] Figure 3 It is a five-level page management structure diagram;

[0030] Figure 4 This is the IOMMU replacement flow chart. DETAILED DESCRIPTION

[0031] The following is a further detailed description of a high-speed IOMMU circuit suitable for SIOV virtualization devices proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0032] The present invention provides a high-speed IOMMU circuit suitable for SIOV virtualization equipment, and its position in the IO equipment is as follows: Figure 1 As shown in the figure, the workflow of IOMMU in the whole system is as follows: the host Host will configure the register CSR of the IO device through the system interface to start the application engine of the IO device. The application engine of the IO device will initiate a memory access request DMAQ according to the configuration of the register CSR. The address of the DMAQ memory access request is a virtual address, so it is necessary to initiate a virtual-real address substitution request to the IOMMU. If the IOMMU substitution hits, it can directly return a substitution response to the application engine. Otherwise, it is necessary to access the memory to read and replace the missing content. Once the missing content is read, it returns a substitution response to the application engine. After receiving the substitution response, the application engine needs to fill the physical address into the memory access request DMAP (that is, DMAQ is converted to DMAP) for the correct substitution response, and send the DMAP to the system interface through the memory access interface to read and write the memory. If the substitution is an error response, the IO device will initiate an interrupt request to the host HOST. After receiving the memory access data, the application engine can process the data accordingly.

[0033] The structure of a high-speed IOMMU circuit suitable for SIOV virtualization equipment provided by the present invention is as follows: Figure 2As shown in the figure, it mainly consists of register CSR configuration module, substitution processing module, page substitution module, PCACHE (page cache memory), TLB (Translation Lookaside Buffer, fast table) module (TLB is divided into page table fast table PAGETLB and device table fast table PDTLB), memory access interface module. CSR configuration module is mainly responsible for configuring IOMMU; substitution processing module is mainly responsible for receiving substitution request and returning substitution response, and checking substitution request; page substitution module is mainly responsible for reading data of PAGETLB, PDTLB, and PCACHE, and initiating memory access request in the absence of page substitution module; memory access interface module is mainly responsible for sending memory access request to memory; PAGETLB can quickly query physical address in the case of hit; PDTLB can quickly query the base address of first-level page table in the case of hit, thereby speeding up page table query; PCACHE is mainly used to cache first-level page table, second-level page table and third-level page table, reduce the frequency of memory access, thereby speeding up virtual and real address substitution.

[0034] The overall workflow of IOMMU is as follows: before IOMMU performs virtual-real address substitution, the system needs to configure IOMMU through the CSR configuration module. After the configuration is completed, the substitution processing module can receive the substitution request and check the substitution request, such as whether there is a verification error. For substitution requests that meet the requirements, they are sent to the page substitution module. The page substitution module first queries PAGETLB. Once PAGETLB hits, the application engine can return a substitution response. If PAGETLB is missing, it is necessary to query PDTLB. After PDTLB hits, it is necessary to further query PCACHE to obtain the physical address. If PDTLB is missing, it is necessary to enter the five-level page management. First, a memory access request is initiated to read the first-level PASID table and the second-level PASID table in the memory. After the PASID table is read, the first-level page table, the second-level page table, and the third-level page table in PCACHE are queried. If the query PCACHE hits, the substitution response can be returned to the application engine. If PCACHE is missing, it is necessary to initiate a memory access request to read the corresponding content from the memory Memory and return the substitution response to the application engine.

[0035] In order to save the main memory space occupied by storing the "page table", the high-speed IOMMU circuit of the present invention adopts a five-level page management, such as Figure 3The virtual address width of the substitution request is 64 bits, where [61:42] is the PASSID; [41:0] is the device virtual address, and [63:62] can be set to the corresponding meaning according to the actual situation. In order to support SIOV virtualization, IOMMU uses PASSID (Process Adddress Space Identifier) ​​as the unit to replace virtual and real addresses. PASID[19:10] is the index of the first-level PASID. The base address of the first-level PASID is generated by the system register CSR configuration module. The first-level PASID table entry contains the base address of the second-level PASID; PASID[9:0] contains the index of the second-level PASID. The second-level PASID table entry contains the base address of the first-level page table; DVA[41:32] is the index of the first-level page table. The first-level page table entry contains the base address of the second-level page table; DVA[31:23] is the index of the second-level page table. The second-level page table entry contains the base address of the third-level page table; DVA[22:13] is the index of the third-level page table. The third-level page table entry contains the physical page table entry; DVA[12:0] is the page offset. During the replacement process, IOMMU first queries PAGETLB. If PAGETLB hits, it can directly return the replacement response; if PAGETLB is missing, it queries PDTLB; if PDTLB hits, it only needs to query the first-level page table, the second-level page table, and the third-level page table; if PDTLB is missing, it needs to query the first-level PASID table, the second-level PASID table, the first-level page table, the second-level page table, and the third-level page table. Figure 3 As shown, the five-level page table lookup process is as follows:

[0036] (1) Use the "PASID table base address" plus PASID[19:10] to form an address, access the "first-level PASID table", and obtain the "second-level PASID table base address";

[0037] (2) Use the "secondary PASID table base address" plus PASID[9:0] to form an address, access the "secondary PASID table", and obtain the "first-level page table base address";

[0038] (3) Use the "first-level page table base address" plus DVA[41:32] to form an address, access the "first-level page table", and obtain the "second-level page table base address";

[0039] (4) Use the "secondary page table base address" plus DVA[31:32] to form an address, access the "secondary page table", and obtain the "third-level page table base address";

[0040] (5) Use the "third-level page table base address" plus DVA[22:13] to form an address, access the "secondary page table", and obtain the "physical page table entry" (PTE).

[0041] Figure 4 The following is a detailed substitution process of IOMMU. As mentioned above, IOMMU first queries PAGETLB. If PAGETLB is missing, IOMMU will query PDTLB and PCACHE. Due to the existence of TLB and PCACHE, the substitution of virtual and real addresses is accelerated. Figure 4 As shown in the flow chart, the first-level PASID table and the second-level PASID table are distributed in the memory, and the first-level page table, the second-level page table and the third-level page table are distributed in the PCACHE. The high-speed IOMMU circuit of the present invention supports multiple page sizes. The page size corresponding to the first-level page table is 8GB, the page size corresponding to the second-level page table is 512MB or 8MB, and the page size corresponding to the third-level page table is 8KB. For queries of different page sizes, Figure 4 As shown, when the first-level page table is queried, the page table entry indicates that the page table of this level is the last level page table, then the page table query ends, and the system supports a page size of 8GB; when the second-level page table is queried, the page table entry indicates that the page table of this level is the last level page table, then the page table query ends, and the system supports a page size of 512MB or 8MB, and the size of 512MB and 8MB pages is determined by the system's configuration of the page table entries for the second-level page table; when the third-level page table is queried, the page table entry indicates that the page table of this level is the last level page table, then the page table query ends, and the system supports a page size of 8KB.

[0042] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A high-speed IOMMU circuit suitable for SIOV virtualization devices, characterized in that: Supports the conversion between virtual address and physical address of virtualized devices, mainly including CSR configuration module, substitution processing module, page substitution module, PCACHE, TLB module, memory access interface module; TLB module includes PAGETLB and PDTLB; PCACHE is page cache memory; TLB is a fast table; PAGETLB is a fast table of page table; PDTLB is a fast table of device table; The CSR configuration module is mainly responsible for configuring the IOMMU circuit; The substitution processing module receives the substitution request and returns the substitution response, and checks the substitution request; The page replacement module reads data of PAGETLB, PDTLB, and PCACHE, and initiates a memory access request when the page replacement module is missing; The memory access interface module is mainly responsible for sending memory access requests to the memory; When the PAGETLB hits, the physical address is quickly queried; when the PDTLB hits, the base address of the first-level page table is quickly queried, thereby speeding up the query of the page table; The PCACHE is mainly used to cache the first-level page table, the second-level page table and the third-level page table, reduce the frequency of memory access, and thus speed up the replacement of virtual and real addresses.

2. The high-speed IOMMU circuit suitable for SIOV virtualization devices according to claim 1, characterized in that: The IOMMU circuit needs to perform address substitution in units of PASSID. PASSID is associated with the IO transaction of the external IO device. The PASSID bit width is 20 bits. Different designs set the PASSID bit width according to actual needs. PASSID is a process address space identifier.

3. The high-speed IOMMU circuit suitable for SIOV virtualization devices according to claim 1, characterized in that: The IOMMU circuit adopts page replacement, and the page replacement adopts a five-level page management method, which is composed of a first-level PASID table, a second-level PASID table, a first-level page table, a second-level page table and a third-level page table; The index of the first-level PASID table and the second-level PASID table is PASSID, and the index of the first-level page table, the second-level page table, and the third-level page table is the device virtual address; The table entries of the first-level PASID table contain the base address of the second-level PASID table; the table entries of the second-level PASID table contain the base address of the first-level page table; the table entries of the first-level page table contain the base address of the second-level page table, and the table entries of the second-level page table contain the base address of the third-level page table; the table entries of the third-level page table contain physical page table entries.

4. The high-speed IOMMU circuit suitable for SIOV virtualization devices as claimed in claim 3, characterized in that: The virtual address bit width of the replacement request is 64 bits, where [61:42] is the PASSID; [41:0] is the device virtual address, and [63:62] is set with the corresponding meaning according to the actual situation; where PASID[19:10] is the index of the first-level PASID, and the base address of the first-level PASID is generated by the CSR configuration module of the system register; PASID[9:0] contains the index of the second-level PASID; DVA[41:32] is the index of the first-level page table; DVA[31:23] is the index of the second-level page table; DVA[22:13] is the index of the third-level page table; DVA[12:0] is the offset within the page.

5. The high-speed IOMMU circuit suitable for SIOV virtualization device according to claim 4, characterized in that: The five-level page table lookup process is as follows: (1) Use the "PASID table base address" plus PASID[19:10] to form an address, access the "first-level PASID table", and obtain the "second-level PASID table base address"; (2) Use the "secondary PASID table base address" plus PASID[9:0] to form an address, access the "secondary PASID table", and obtain the "first-level page table base address"; (3) Use the "first-level page table base address" plus DVA[41:32] to form an address, access the "first-level page table", and obtain the "second-level page table base address"; (4) Use the "secondary page table base address" plus DVA[31:32] to form an address, access the "secondary page table", and obtain the "third-level page table base address"; (5) Use the "third-level page table base address" plus DVA[22:13] to form an address, access the "secondary page table", and obtain the "physical page table entry".

6. The high-speed IOMMU circuit suitable for SIOV virtualization devices as claimed in claim 5, characterized in that: The working process of the IOMMU circuit is as follows: before the IOMMU circuit performs virtual-real address substitution, the IOMMU circuit is configured through the CSR configuration module; after the configuration is completed, the substitution processing module receives the substitution request, checks the substitution request, and sends the substitution request that meets the requirements to the page substitution module; the page substitution module first queries PAGETLB, and once PAGETLB hits, the application engine returns a substitution response. If PAGETLB is missing, it is necessary to query PDTLB; after PDTLB hits, PCACHE is further queried to obtain the physical address. If PDTLB is missing, it is necessary to enter the five-level page management, first initiate a memory access request, and read the first-level PASID table and the second-level PASID table in the memory; after the PASID table is read, the first-level page table, the second-level page table and the third-level page table in PCACHE are queried, and the PCACHE query hits, and the substitution response is returned to the application engine. If PCACHE is missing, it is necessary to initiate a memory access request, read the corresponding content from the external memory Memory, and return the substitution response to the application engine.

7. The high-speed IOMMU circuit suitable for SIOV virtualization devices according to claim 1, characterized in that: The IOMMU circuit supports multiple page sizes, the first-level page table supports a page size of 8GB; the second-level page table supports a size of 512MB or 8MB; The page size supported by the three-level page table is 8KB, and different designs set the page size according to actual needs.

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