Communication method and system of field programmable logic device

Abstract

The invention provides a communication method and system of a field programmable logic device, a computer readable storage medium and electronic equipment. The method comprises the steps that a field programmable logic device host receives a control instruction sent by an upper computer; a first processor on the field programmable logic device host controls a first intellectual property core to send a control instruction to a second processor on the field programmable logic device slave through an inter-chip bus; a second processor on the slave of the field programmable logic device processes the control instruction and obtains a processing result, and the processing result is sent to the host of the field programmable logic device through a link layer protocol based on a second intellectual property core; and the field programmable logic device host stores the processing result to a memory or uploads the processing result to an upper computer. According to the application, the data transmission efficiency between the field programmable logic device host and the field programmable logic device slave can be improved, and the control process of the field programmable logic device is simplified.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a communication method, system, computer-readable storage medium and electronic device for a field programmable logic device. Background Art

[0002] Field-Programmable Gate Array (FPGA) has evolved from a peripheral device in electronic design to the core of digital systems in recent years. At the same time, various application scenarios have put forward higher requirements for logic resources, greater data interaction, higher transmission rate, lower latency, etc. The logic resources of a single FPGA chip are gradually unable to meet the requirements. In order to meet the requirements of real-time, high-speed, and high-complexity digital signal processing, two or even more FPGAs may be required for collaborative processing.

[0003] The interconnection communication between multiple field programmable logic device development boards mainly adopts low voltage differential signaling (LVDS), which is usually used for parallel data transmission, with a data rate of 155MHz, 622MHz or 1.25GHz. The transmission speed of this scheme is too low. The traditional parallel transmission method increases the transmission rate by increasing the clock frequency and data bit width, which causes problems such as difficulty in system layout and wiring, offset of clock and data signals, difficulty in multi-endpoint interconnection, and poor scalability. Summary of the invention

[0004] The purpose of this application is to provide a communication method, system, computer-readable storage medium and electronic device for a field programmable logic device, which processes control instructions through a first intellectual property core and improves the efficiency of inter-board communication through a link layer of a second intellectual property core.

[0005] In order to solve the above technical problems, the present application provides a communication method of a field programmable logic device, and the specific technical solution is as follows:

[0006] The FPGA host receives control instructions sent by the host computer;

[0007] The first processor on the field programmable logic device host controls the first intellectual property core to send the control instruction to the second processor on the field programmable logic device slave through the inter-chip bus;

[0008] The second processor on the field programmable logic device slave processes the control instruction and obtains a processing result, and sends the processing result to the field programmable logic device host through a link layer protocol based on a second intellectual property core;

[0009] The field programmable logic device host stores the processing result in a memory, or uploads it to the host computer.

[0010] Before the field programmable logic device host receives the control instruction sent by the host computer, the following steps are also included:

[0011] A hardware platform project is established, in which the first intellectual property core and the second intellectual property core, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller and a data control module are configured on both the field programmable logic device host and the field programmable logic device slave; the data control module is used for data communication through the high-speed transceiver.

[0012] Wherein, the method further comprises:

[0013] An embedded software project is established in which an electrical consistency check is performed on the high-speed transceiver, on-board processor, bus routing, Ethernet controller, serial port controller and interface controller, and pin configuration is performed, a bitstream file is generated and a hardware platform file is exported.

[0014] Wherein, the method further comprises:

[0015] Connecting a first high-speed transceiver on the field programmable logic device host and a second high-speed transceiver on the field programmable logic device slave through an optical fiber;

[0016] The first on-board processor on the field programmable logic device host and the second on-board processor on the field programmable logic device slave are connected via a universal input and output interface.

[0017] Wherein, after connecting the first on-board processor on the field programmable logic device host and the second on-board processor on the field programmable logic device slave through the universal input and output interface, it also includes:

[0018] The host computer is connected to the Ethernet controller of the field programmable logic device host, and after the field programmable logic device host is powered on, the first intellectual property core is initialized.

[0019] After generating the bitstream file and exporting the hardware platform file, it also includes:

[0020] Writing a host program corresponding to the first intellectual property core into the field programmable logic device host;

[0021] A slave program corresponding to the first intellectual property core is written into the field programmable logic device slave.

[0022] Wherein, if the control instruction is a reset instruction, the second processor on the field programmable logic device slave processes the control instruction and obtains a processing result, which includes:

[0023] The second processor on the field programmable logic device slave controls the first intellectual property core to reset according to the reset instruction;

[0024] The first intellectual property core controls the phase-locked loop reset of the second high-speed transceiver and cancels the reset of the first intellectual property core;

[0025] The second on-board processor on the FPGA slave sends a reset completion signal to the first on-board processor on the FPGA host.

[0026] The present application also provides a communication system of a field programmable logic device, comprising:

[0027] A receiving module is used to receive control instructions sent by the host computer;

[0028] An instruction sending module, used for controlling the first intellectual property core to send the control instruction to the second processor on the field programmable logic device slave through the inter-chip bus;

[0029] A result receiving module, configured to receive the processing result sent by the field programmable logic device slave through a link layer protocol based on a second intellectual property core after the second processor on the field programmable logic device slave processes the control instruction and obtains the processing result;

[0030] The communication result processing module is used for the field programmable logic device host to store the processing result into the memory, or upload it to the host computer.

[0031] Wherein, the communication system further includes:

[0032] A hardware configuration module is used to establish a hardware platform project, in which the first intellectual property core and the second intellectual property core, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller and a data control module are configured on both the field programmable logic device host and the field programmable logic device slave; the data control module is used to perform data communication through the high-speed transceiver.

[0033] Wherein, the communication system further includes:

[0034] The software configuration module is used to establish an embedded software project, in which an electrical consistency check is performed on the high-speed transceiver, on-board processor, bus routing, Ethernet controller, serial port controller and interface controller, and pin configuration is performed, a bitstream file is generated and a hardware platform file is exported.

[0035] Wherein, the communication system further includes:

[0036] A host computer configuration module, used to connect the first high-speed transceiver on the field programmable logic device host and the second high-speed transceiver on the field programmable logic device slave through an optical fiber;

[0037] The first on-board processor on the field programmable logic device host and the second on-board processor on the field programmable logic device slave are connected via a universal input and output interface.

[0038] The communication system further includes an initialization module for connecting the host computer to the Ethernet controller of the field programmable logic device host, and initializing the first intellectual property core after the field programmable logic device host is powered on.

[0039] Wherein, the communication system also includes

[0040] The intellectual property core configuration module is used to write the host program corresponding to the first intellectual property core into the field programmable logic device host after generating a bitstream file and exporting a hardware platform file; and write the slave program corresponding to the first intellectual property core into the field programmable logic device slave.

[0041] If the control instruction is a reset instruction, the method further includes:

[0042] The slave processing module is arranged on the field programmable logic device slave and is used to control the reset of the first intellectual property core through the second processor according to the reset instruction; the first intellectual property core controls the phase-locked loop reset of the second high-speed transceiver and cancels the reset of the first intellectual property core; and controls the second on-board processor to send a reset completion signal to the first on-board processor on the field programmable logic device host.

[0043] The present application also provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the steps of the above-mentioned method when executed by a processor.

[0044] The present application also provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps of the above-mentioned method when calling the computer program in the memory.

[0045] The present application provides a communication method for a field programmable logic device, comprising: a field programmable logic device host receives a control instruction sent by a host computer; a first processor on the field programmable logic device host controls a first intellectual property core through an inter-chip bus to send the control instruction to a second processor on a field programmable logic device slave; the second processor on the field programmable logic device slave processes the control instruction and obtains a processing result, and sends the processing result to the field programmable logic device host through a link layer protocol based on the second intellectual property core; the field programmable logic device host stores the processing result in a memory, or uploads it to the host computer.

[0046] This application sets a first intellectual property core and a second intellectual property core, so that the FPGA host can quickly process control instructions, and quickly send them to the FPGA slave through the second intellectual property core containing the link layer protocol, thereby improving the data transmission efficiency between the FPGA host and the FPGA slave. At the same time, with the connection between the FPGA host and the FPGA slave, the host computer only needs to control the FPGA host to synchronously operate the FPGA slave, simplifying the control process of the FPGA and improving the control efficiency in one-to-many application scenarios.

[0047] The present application also provides a communication system of a field programmable logic device, a computer-readable storage medium and an electronic device, which have the above-mentioned beneficial effects and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0049] Figure 1 A flow chart of a communication method of a field programmable logic device provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the hardware structure provided for an embodiment of the present application;

[0051] Figure 3 A schematic diagram of a reset operation flow of a field programmable logic device provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of the communication system structure of a field programmable logic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] Please refer to Figure 1 , Figure 1 A flow chart of a communication method of a field programmable logic device provided in an embodiment of the present application, the method comprising:

[0055] S101: The FPGA host receives a control instruction sent by a host computer;

[0056] S102: The first processor on the field programmable logic device host controls the first intellectual property core to send the control instruction to the second processor on the field programmable logic device slave through the inter-chip bus;

[0057] S103: the second processor on the field programmable logic device slave processes the control instruction and obtains a processing result, and sends the processing result to the field programmable logic device host through a link layer protocol based on a second intellectual property core;

[0058] S104: The FPGA host stores the processing result in a memory, or uploads it to the host computer.

[0059] The specific application object of the host computer is not limited here, and it can be any device to which a user can issue control instructions, such as a terminal device, etc. At the same time, the host computer only needs to establish a communication connection with the field programmable logic device host.

[0060] There is no limitation on the control instructions sent by the host computer, which may include control instructions sent to the field programmable logic device host, the field programmable logic device slave or both, including but not limited to data read, write, delete and modify instructions, as well as reset, initialization or resetting instructions.

[0061] After receiving the control instruction, the FPGA host uses the first processor on it to control the first intellectual property core through the inter-chip bus to send it to the second processor on the FPGA slave. Usually, the FPGA host and the FPGA slave can use the same type of processor, or different types of processors, such as MicroBlaze embedded soft core, which is a reduced instruction set processor soft core that can be embedded in the FPGA, and has the advantages of fast running speed, less resource occupation, and strong configurability.

[0062] The inter-chip bus may be an AXI (Advanced eXtensible Interface) bus, which is an on-chip bus for high performance, high bandwidth, and low latency. The first intellectual property core and the second intellectual property core are both intellectual property cores, i.e., IP cores (intellectual property cores), which are reusable modules in the form of logic units and chip designs. There is no limitation on which first intellectual property core and which second intellectual property core are used, but the first intellectual property core is used to implement a bridge based on the inter-chip bus, and can connect two devices through the AXI bus. Its bridging function can also allow all AXI channels to operate independently by sending and receiving data and control information of each channel, in accordance with the "valid-ready" handshake of each AXI channel. The second intellectual property core is used to accelerate data transmission between a field programmable logic device host and a field programmable logic device slave. For example, Chip2chip can be used as the first intellectual property core, and Aurora64b / 66b can be used as the second intellectual property core, which is an extensible lightweight link layer protocol for high-speed serial communication. It is usually used in applications that require the construction of low-cost, high data rate, extensible, and flexible serial data channels. Using the Aurora protocol as a transmission protocol can solve the problem of high-speed signal communication between multiple reconfigurable storage and computing chips. The Aurora protocol is an open, scalable, small, link layer protocol that can be used for point-to-point serial channel data transmission. At the same time, it eliminates the resource inefficiency problem of other serial protocols and can be implemented in any silicon device / technology including reconfigurable storage and computing chips. The Aurora protocol can use one or more high-speed serial channels. If Chip2chip and Aurora ip cores are used as the first intellectual property core and the second intellectual property core respectively, the high-speed transceiver GT (gimbit transceiver) can be used to send and receive data, and the communication line rate can reach 25Gb / s. On this basis, the embedded MicroBlaze soft-core processor and related peripherals can also be used, so that users can flexibly configure according to their needs.

[0063] The FPGA host can store the processing results obtained by the FPGA slave in its own corresponding memory or upload them to the host computer. The specific processing method can be determined according to the specific control instruction type. If the host computer needs the processing results corresponding to the control instruction, it needs to be uploaded to the host computer.

[0064] This application sets a first intellectual property core and a second intellectual property core, so that the FPGA host can quickly process control instructions, and quickly send them to the FPGA slave through the second intellectual property core containing the link layer protocol, thereby improving the data transmission efficiency between the FPGA host and the FPGA slave. At the same time, with the connection between the FPGA host and the FPGA slave, the host computer only needs to control the FPGA host to synchronously operate the FPGA slave, simplifying the control process of the FPGA and improving the control efficiency in one-to-many application scenarios.

[0065] The following describes the construction and configuration process between the field programmable logic device host and the field programmable logic device slave of the present application:

[0066] Establish a hardware platform project, in which the first intellectual property core and the second intellectual property core, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller, and a data control module are configured on both the field programmable logic device host and the field programmable logic device slave; the data control module is used to communicate data through the high-speed transceiver. Specifically, the hardware platform project can be established using Vivado software, Chip2chip is added as the first intellectual property core, Aurora is used as the second intellectual property core, MicroBlaze is used as the on-chip processor and other intellectual property cores and configured, the rtl code is mainly written for the data control module, and electrical consistency checks are performed after connecting each intellectual property core and module, pin constraints are performed, synthesis, implementation, bitstream files are generated, and hardware platform .xsa files are exported. The bitstream file mainly contains the generation results of the software, a binary file that can be executed when downloaded to the field programmable logic device, and the .xsa file mainly contains software related information.

[0067] Then establish an embedded software project, in which the electrical consistency check is performed on the high-speed transceiver, on-board processor, bus routing, Ethernet controller, serial port controller and interface controller, and pin configuration is performed to generate a bitstream file and export a hardware platform file. Specifically, Vitis software can be used to establish an embedded software project, import the .xsa file obtained in the previous step, use the Ethernet "lwip tcp" template, write C language code, compile and generate an .elf file, which can be directly written to the field programmable logic device host or field programmable logic device slave.

[0068] In addition, you can choose whether to fix the program to the flash memory. The program mainly includes the bitstream file and the compiled .elf file. After fixing it to the flash memory, you don't have to perform the file compilation process every time you start it.

[0069] It should be noted that, in order to simplify the operation, the hardware configuration of the FPGA host and the FPGA slave can be the same. However, if Chip2chip is used as the first intellectual property core, the software program corresponding to Chip2chip itself distinguishes between the host and the slave, that is, there are differences in the software programs corresponding to the FPGA host and the FPGA slave. Figure 2 , Figure 2 A schematic diagram of the hardware structure provided in the embodiment of the present application, comprising Figure 2 It can be seen that the FPGA host and the FPGA slave are connected by optical fiber, and the connection between the first processor and the second processor is also established by using a universal input and output interface. The host computer is connected to the FPGA host by a network cable and a serial port. After that, the FPGA host is powered on and controls the initialization of the first intellectual property core. At the same time or after the FPGA host is powered on, the FPGA slave is powered on, and the first intellectual property core on the FPGA slave is also powered on. After the link is established, the host computer can control it to achieve inter-chip communication between the FPGA host and the FPGA slave.

[0070] In the above process, the hardware requirements are: two Xilinx Vitex UltraScale+ series field programmable logic device development boards, a computer as a host computer, optical fiber, network cable, etc. Required software tools: Vivado IDE, Vitis IDE, network debugging assistant.

[0071] The FPGA includes a processor part and a programmable logic part. The processor part includes an on-chip processor, which can use a MicroBlaze processor, an AXI bus router, an Ethernet controller, a Uart serial port controller, a Quad SPI interface controller as a serial peripheral interface, and a DDR4 controller. This part needs to be jointly developed by vivado and vitis. The programmable logic part includes a data controller module, a first intellectual property core, and a second intellectual property core. This part is only developed by vivado. The data controller module is a self-written Verilog HDL language code that realizes the function of data communication through a high-speed transceiver GTY. It can communicate between the FPGA host and the FPGA slave, and can also store or read data through the inter-chip bus and the double data rate synchronous dynamic random access memory (Double Data Rate, DDR). Registers can also be defined for key configuration information such as data bit width, address bit width, reset control, etc., to facilitate flexible control of the processor.

[0072] If Chip2Chip is used as the first intellectual property core, the global configuration option must be selected as the master or slave during configuration. For the selection of the port physical layer type, if SelectI0 is used, the number of hardware pins will be greatly increased, and the communication rate will be low. Therefore, the second intellectual property core is selected to realize the conversion between chip2chip data and high-speed serial transceiver data. In an embodiment of the present application, if Aurora64B66B is used as the second intellectual property core, when configuring the second intellectual property core, a physical layer high-speed transceiver is used, and the line rate and number of channels can be selected according to demand. In this example, the line rate is 25Gbps and the number of channels is 1.

[0073] If the MicroBlaze processor is used as the on-chip processor, in the embedded development process, C language code needs to be written according to the driver library to implement the basic functions of processor peripheral access, including access to Ethernet, UART serial port printing, flash memory reading and writing, memory reading and writing, input and output control of the general input and output interface, and data controller module related register configuration. Furthermore, additional code logic is added to achieve more user-friendly operation.

[0074] For example, the communication status between the FPGA host and the FPGA slave can be displayed in real time through the Uart serial port. For example, if the Qualcomm access channel link is not established, "link error" can be displayed on the host computer interface. If there is an error in the inter-chip bus access, "AXI error" will be displayed on the host computer interface; if the communication between the FPGA host and the FPGA slave is normal, "lane up, receive and send correctly at high speed" will be displayed.

[0075] The following describes the reset operation of the field programmable logic device master and the field programmable logic device slave executed by the host computer in this application:

[0076] S201: the second processor on the field programmable logic device slave controls the first intellectual property core to reset according to the reset instruction;

[0077] S202: The first intellectual property core controls the phase-locked loop of the second high-speed transceiver to reset, and cancels the reset of the first intellectual property core;

[0078] S203: The second on-board processor on the FPGA slave sends a reset completion signal to the first on-board processor on the FPGA host.

[0079] First, the working state of the first intellectual property core of the second on-chip processor of the field programmable logic device slave is placed in a reset state; the QPLL phase-locked loop of the high-speed transceiver is reset, and the phase-locked loop is checked to see if it is locked, and the reset operation of the first intellectual property core of the second on-chip processor is canceled; the first intellectual property core of the first on-chip processor is reset, and the link establishment is checked to see if it is successful. The first intellectual property core reset of the field programmable logic device host requires the host processor to send a reset instruction to the data controller module via the AXI bus, and the first intellectual property core is reset; the first intellectual property core reset of the field programmable logic device slave requires the host processor to send a reset instruction to the slave processor via the universal input and output interface, and the on-chip processor of the field programmable logic device slave sends a reset instruction to the data controller module via the AXI bus after receiving the instruction, and resets.

[0080] When performing the upgrade, the host computer remotely updates and upgrades the programs of the FPGA host and the FPGA slave through Ethernet. The host computer first accesses the FPGA host through Ethernet, and then burns the new .bin file into the flash memory of the FPGA host through QSPI (Quad schedule performance index, six-wire serial peripheral interface) and the first intellectual property core, and then power off and restart the FPGA to complete the upgrade. For the specific process, please refer to Figure 3 , Figure 3 A schematic diagram of the reset operation flow of a field programmable logic device provided in an embodiment of the present application.

[0081] The communication system of the field programmable logic device provided in the embodiment of the present application is introduced below. The communication system of the field programmable logic device described below and the communication method of the field programmable logic device described above can be referred to each other.

[0082] Figure 4 A schematic diagram of a communication system structure of a field programmable logic device provided in an embodiment of the present application. The present application also provides a communication system of a field programmable logic device, including:

[0083] A receiving module is used to receive control instructions sent by the host computer;

[0084] An instruction sending module, used for controlling the first intellectual property core to send the control instruction to the second processor on the field programmable logic device slave through the inter-chip bus;

[0085] A result receiving module, configured to receive the processing result sent by the field programmable logic device slave through a link layer protocol based on a second intellectual property core after the second processor on the field programmable logic device slave processes the control instruction and obtains the processing result;

[0086] The communication result processing module is used for the field programmable logic device host to store the processing result into the memory, or upload it to the host computer.

[0087] Based on the above embodiments, as a preferred embodiment, it also includes:

[0088] A hardware configuration module is used to establish a hardware platform project, in which the first intellectual property core and the second intellectual property core, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller and a data control module are configured on both the field programmable logic device host and the field programmable logic device slave; the data control module is used to perform data communication through the high-speed transceiver.

[0089] Based on the above embodiment, as a preferred embodiment, the system further includes:

[0090] The software configuration module is used to establish an embedded software project, in which an electrical consistency check is performed on the high-speed transceiver, on-board processor, bus routing, Ethernet controller, serial port controller and interface controller, and pin configuration is performed, a bitstream file is generated and a hardware platform file is exported.

[0091] Based on the above embodiment, as a preferred embodiment, the system further includes:

[0092] A host computer configuration module, used to connect the first high-speed transceiver on the field programmable logic device host and the second high-speed transceiver on the field programmable logic device slave through an optical fiber;

[0093] The first on-board processor on the field programmable logic device host and the second on-board processor on the field programmable logic device slave are connected via a universal input and output interface.

[0094] Based on the above embodiments, as a preferred embodiment, it also includes:

[0095] The initialization module is used to connect the host computer to the Ethernet controller of the field programmable logic device host, and initialize the first intellectual property core after the field programmable logic device host is powered on.

[0096] Based on the above embodiments, as a preferred embodiment, it also includes:

[0097] The intellectual property core configuration module is used to write the host program corresponding to the first intellectual property core into the field programmable logic device host after generating a bitstream file and exporting a hardware platform file; and write the slave program corresponding to the first intellectual property core into the field programmable logic device slave.

[0098] Based on the above embodiment, as a preferred embodiment, if the control instruction is a reset instruction, it also includes:

[0099] The slave processing module is arranged on the field programmable logic device slave and is used to control the reset of the first intellectual property core through the second processor according to the reset instruction; the first intellectual property core controls the phase-locked loop reset of the second high-speed transceiver and cancels the reset of the first intellectual property core; and controls the second on-board processor to send a reset completion signal to the first on-board processor on the field programmable logic device host.

[0100] The present application also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed, the steps provided in the above embodiment can be implemented. The storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0101] The present application also provides an electronic device, which may include a memory and a processor, wherein a computer program is stored in the memory, and when the processor calls the computer program in the memory, the steps provided in the above embodiment may be implemented. Of course, the electronic device may also include various network interfaces, power supplies and other components.

[0102] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the system provided in the embodiment, since it corresponds to the method provided in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0103] Specific examples are used herein to illustrate the principles and implementation methods of the present application, and the description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0104] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A communication method for a field programmable logic device, characterized in that: include: The FPGA host receives control instructions sent by the host computer; The first processor on the field programmable logic device host controls the first intellectual property core to send the control instruction to the second processor on the field programmable logic device slave through the inter-chip bus; After the second processor on the field programmable logic device slave processes the control instruction and obtains a processing result, receiving the processing result sent by the field programmable logic device slave through a link layer protocol based on a second intellectual property core; The field programmable logic device host stores the processing result in a memory, or uploads it to the host computer.

2. The communication method according to claim 1, characterized in that: Before the field programmable logic device host receives the control instruction sent by the host computer, it also includes: A hardware platform project is established, in which the first intellectual property core and the second intellectual property core, as well as a high-speed transceiver, an on-board processor, a bus router, an Ethernet controller, a serial port controller, an interface controller and a data control module are configured on both the field programmable logic device host and the field programmable logic device slave; the data control module is used for data communication through the high-speed transceiver.

3. The communication method according to claim 2, characterized in that: Also includes: An embedded software project is established in which an electrical consistency check is performed on the high-speed transceiver, on-board processor, bus routing, Ethernet controller, serial port controller and interface controller, and pin configuration is performed, a bitstream file is generated and a hardware platform file is exported.

4. The communication method according to claim 3, characterized in that: Also includes: Connecting a first high-speed transceiver on the field programmable logic device host and a second high-speed transceiver on the field programmable logic device slave through an optical fiber; The first on-board processor on the field programmable logic device host and the second on-board processor on the field programmable logic device slave are connected via a universal input and output interface.

5. The communication method according to claim 4, characterized in that: After connecting the first on-board processor on the field programmable logic device host and the second on-board processor on the field programmable logic device slave through a universal input and output interface, the method further includes: The host computer is connected to the Ethernet controller of the field programmable logic device host, and after the field programmable logic device host is powered on, the first intellectual property core is initialized.

6. The communication method according to claim 4, characterized in that: After generating the bitstream file and exporting the hardware platform file, it also includes: Writing a host program corresponding to the first intellectual property core into the field programmable logic device host; A slave program corresponding to the first intellectual property core is written into the field programmable logic device slave.

7. The communication method according to claim 4, characterized in that: If the control instruction is a reset instruction, the second processor on the field programmable logic device slave processes the control instruction and obtains a processing result, which includes: The second processor on the field programmable logic device slave controls the first intellectual property core to reset according to the reset instruction; The first intellectual property core controls the phase-locked loop reset of the second high-speed transceiver and cancels the reset of the first intellectual property core; The second on-board processor on the field programmable logic device slave sends a reset completion signal to the first on-board processor on the field programmable logic device host.

8. A communication system for a field programmable logic device, characterized in that: include: A receiving module is used to receive control instructions sent by the host computer; An instruction sending module, used for controlling the first intellectual property core to send the control instruction to the second processor on the field programmable logic device slave through the inter-chip bus; A result receiving module, configured to receive the processing result sent by the field programmable logic device slave through a link layer protocol based on a second intellectual property core after the second processor on the field programmable logic device slave processes the control instruction and obtains the processing result; The communication result processing module is used for the field programmable logic device host to store the processing result into the memory, or upload it to the host computer.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the communication method of the field programmable logic device according to any one of claims 1 to 7 are implemented.

10. An electronic device, characterized in that: It comprises a memory and a processor, wherein the memory stores a computer program, and when the processor calls the computer program in the memory, the steps of the communication method of the field programmable logic device as claimed in any one of claims 1 to 7 are implemented.

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