Simulation method for total dose effect modeling of SRAM based on fdsoi device

Abstract

The application discloses a kind of SRAM total dose effect modeling simulation methods based on FDSOI device, it is related to integrated circuit technical field, the SRAM total dose effect modeling simulation methods based on FDSOI device of the embodiment of the application, the FDSOI device state after total dose irradiation simulation is saved to be used for the total dose effect simulation of SRAM circuit, the influence of total dose effect on the threshold voltage, mutual coupling capacitance, parasitic resistance etc. Electrical parameters of device in circuit can be considered comprehensively, so that the noise margin etc. Parameter of SRAM under irradiation condition is more accurate result analysis, this method can overcome the limitation of existing circuit level simulation.In TCAD directly carried out simulation can avoid the error caused by the device model of existing circuit level simulation, so that simulation result is more accurate.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a total dose effect modeling and simulation method of an SRAM (Static Random-Access Memory) based on an FDSOI (fully depleted silicon on insulator) device. Background Art

[0002] In recent years, my country's integrated circuit market has grown rapidly, and the demand for independent chip technology has become increasingly strong. FDSOI devices, with their advantages such as high speed, low power consumption, high integration density, and excellent subthreshold characteristics, have attracted much attention and are expected to receive increasing attention in the near future. In the field of aerospace radiation-resistant integrated circuits, the FDSOI structure has become a new driving force in the aerospace industry due to its inherent resistance to single-event effects. The emergence of FDSOI technology has alleviated some of these issues. The devices are naturally resistant to single-event effects and transient dose rate radiation, and have broad applications and prospects in aerospace technology and national military affairs. However, the presence of the BOX layer makes the device extremely sensitive to total-dose radiation. Therefore, studying the total-dose effect mechanism of FDSOI devices and SRAM is of far-reaching significance and can provide theoretical support for improving the circuit's resistance to total-dose radiation.

[0003] Existing circuit-level total dose effects are typically simulated using tools like HSPICE or Candence. After extracting device model parameters and electrical characteristic parameters from TCAD simulations, the threshold voltage of the device model is modified to simulate the impact of total dose effects on the circuit under different irradiation doses. This method is simple to operate and fast to calculate, but it only addresses the impact of total dose effects on a single electrical parameter, threshold voltage, and its simulation accuracy needs to be improved. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a method for modeling and simulating the total dose effect of SRAM based on FDSOI devices. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a method for modeling and simulating the total dose effect of an SRAM based on an FDSOI device, comprising:

[0006] Step 1: Structural modeling of the FDSOI NMOS device and the FDSOIPMOS device is performed to obtain the corresponding device structure models;

[0007] Step 2: Adding a Radiation model and a first Traps model to the device structure model, setting model parameters, and performing a total dose irradiation simulation to obtain total dose irradiation simulation results corresponding to the FDSOI NMOS device and the FDSOI NMOS device, and saving the total dose irradiation simulation results;

[0008] Step 3: constructing an SRAM circuit model based on the FDSOI NMOS device and the FDSOIPMOS device, performing circuit simulation on the SRAM circuit model based on the total dose irradiation simulation results of the FDSOI NMOS device and the FDSOI NMOS device, and obtaining a voltage curve of a storage node of the SRAM circuit model after total dose irradiation;

[0009] Step 4: Determine the influence of the total dose irradiation effect on the SRAM circuit model according to the voltage curve of the storage node of the SRAM circuit model after the total dose irradiation.

[0010] Compared with the prior art, the present invention has the following beneficial effects:

[0011] The present invention's total dose effect modeling and simulation method for SRAM based on FDSOI devices saves the FDSOI device state after total dose irradiation simulation for use in total dose effect simulation of SRAM circuits. This method comprehensively considers the impact of total dose effects on electrical parameters such as threshold voltage, mutual coupling capacitance, and parasitic resistance of circuit devices, thereby providing more accurate analysis of parameters such as SRAM noise margin under irradiation conditions. This method overcomes the limitations of existing circuit-level simulations. Simulations performed directly in TCAD can avoid errors introduced by device models in existing circuit-level simulations, resulting in more accurate simulation results.

[0012] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a flow chart of a method for modeling and simulating the total dose effect of an SRAM based on an FDSOI device provided in an embodiment of the present invention;

[0014] Figure 2 This is a three-dimensional structural diagram of a 22nm FDSOI NMOS device provided by an embodiment of the present invention;

[0015] Figure 3is a two-dimensional cross-sectional view of a 22nm FDSOI NMOS device provided by an embodiment of the present invention;

[0016] Figure 4 This is an Id-Vg electrical characteristic curve after total dose irradiation simulation of an FDSOI NMOS device provided by an embodiment of the present invention;

[0017] Figure 5 1 is an Id-Vg electrical characteristic curve after total dose irradiation simulation of an FDSOIPMOS device provided by an embodiment of the present invention;

[0018] Figure 6 This is a physical structural characteristic diagram related to the radiation charge generation rate of the buried oxide layer after the total dose radiation simulation of the FDSOI NMOS device provided by an embodiment of the present invention;

[0019] Figure 7 This is a physical structural characteristic diagram related to the radiation charge generation rate of the buried oxide layer after the total dose radiation simulation of the FDSOIPMOS device provided by an embodiment of the present invention;

[0020] Figure 8 6T-SRAM circuit diagram of circuit simulation provided by an embodiment of the present invention;

[0021] Figure 9 This is a timing diagram of the working state of the 6T-SRAM circuit provided by an embodiment of the present invention;

[0022] Figure 10 The figure shows the Q-node voltage change of the 6T-SRAM circuit of the FDSOI device provided by the embodiment of the present invention under the total dose effect;

[0023] Figure 11 The figure shows the voltage change of the QN node of the 6T-SRAM circuit of the FDSOI device provided by the embodiment of the present invention under the total dose effect;

[0024] Figure 12 1 is a voltage transfer characteristic curve of two cross-coupled inverters on the left and right during irradiation of a 6T-SRAM circuit of an FDSOI device provided by an embodiment of the present invention.

[0025] Figure 13 The following are simulation results of the static noise margin (HSNM) of the 6T-SRAM circuit of the FDSOI device provided by the embodiment of the present invention before and after irradiation with a total dose of 1 Mrad;

[0026] Figure 14 This is a graph showing the static noise margin (HSNM) results of the 6T-SRAM circuit of the FDSOI device provided by an embodiment of the present invention under different irradiation doses. DETAILED DESCRIPTION

[0027] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of a total dose effect modeling and simulation method of SRAM based on FDSOI devices proposed in accordance with the present invention, in combination with the accompanying drawings and specific implementation methods.

[0028] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0029] The embodiment of the present invention provides a method for modeling and simulating the total dose effect of SRAM based on FDSOI devices. The simulation method is implemented based on Sentaurus TCAD simulation software. Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for modeling and simulating the total dose effect of an SRAM based on an FDSOI device provided by an embodiment of the present invention. Figure 1 As shown, the SRAM total dose effect modeling and simulation method based on FDSOI devices of this embodiment includes:

[0030] Step 1: Structural modeling is performed on the FDSOI NMOS device and the FDSOIPMOS device respectively to obtain corresponding device structure models.

[0031] In an optional embodiment, step 1 includes:

[0032] According to the device structure parameters of FDSOI NMOS device and FDSOI PMOS device, the device structure models of FDSOI NMOS device and FDSOI PMOS device are established using the sde tool of Sentaurus TCAD simulation software.

[0033] Optionally, the device structure parameters include: device geometry, size, doping concentration and grid density.

[0034] For example, the device structure model of 22nm FDSOI NMOS device is established by using the sde tool of TCAD simulation software. Figure 2 and 3 As shown, Figure 2 This is a three-dimensional structural diagram of a 22nm FDSOI NMOS device provided by an embodiment of the present invention; Figure 3 2 is a two-dimensional cross-sectional view of a 22nm FDSOI NMOS device provided by an embodiment of the present invention. Figure 2 It can be seen that the device structure model of the FDSOI NMOS device includes, from bottom to top, the substrate, the back gate doping layer, the buried oxide layer (buried layer BOX), the source terminal, the drain terminal, and the channel region. The source terminal, the drain terminal, and the channel region are located above the buried oxide layer. There is also a gate oxide layer above the channel region, and there are sidewalls on both sides of the gate oxide layer. Figure 2 The numbers and color areas in the substrate represent the doping concentrations corresponding to the colors of the corresponding layers of the device.

[0035] In this embodiment, the device structural parameters of the 22nm FDSOI NMOS device modeled using Sentaurus software are shown in Table 1.

[0036] Table 1

[0037] Device structure parameters Numerical Channel length 22nm Channel thickness 6nm Channel width 92nm Gate oxide thickness 5nm Drain / source region length 28nm Silicon film thickness 6nm Buried oxide layer thickness 20nm Substrate thickness 130nm Side wall height 30nm Side wall thickness 15nm Gate metal work function 4.5eV

[0038] Step 2: Add the Radiation model and the first Traps model to the device structure model, set the model parameters, and perform a total dose irradiation simulation to obtain the total dose irradiation simulation results corresponding to the FDSOI NMOS device and the FDSOI NMOS device, and save the total dose irradiation simulation results.

[0039] In an optional embodiment, the model parameters include: the irradiation dose rate and irradiation time of the Radiation model and the hole energy level position and hole concentration of the first Traps model.

[0040] In this embodiment, during the total dose irradiation simulation process, the bias states of the FDSOI NMOS device and the FDSOI NMOS device are set to the ON state.

[0041] In this embodiment, the specific process of step 2 is as follows: First, the Radiation model is activated in the Physics model definition of the device. Optionally, the Radiation model parameters are defined as follows: the dose rate is set to 200 rad / s, and the irradiation time is set to 1000s, 2000s, 3000s, 4000s and 5000s, corresponding to a total dose irradiation of 200Krad, 400Krad, 600Krad, 800Krad and 1Mrad, respectively. The first Traps model is set, and the hole energy level position and hole concentration are set to 5e18. It is understandable that these model parameters can be set according to the needs of the actual device. During the total dose irradiation simulation process, the bias state of the device is set to the ON state, and then the total dose irradiation simulation is performed to obtain the total dose irradiation simulation results corresponding to the FDSOI NMOS device and the FDSOI NMOS device. The total dose irradiation simulation results include the device electrical characteristics and device physical structure characteristics after total dose irradiation.

[0042] The device electrical characteristics are the Id-Vg electrical characteristics curve, see Figure 4 and Figure 5 , Figure 4 This is an Id-Vg electrical characteristic curve after total dose irradiation simulation of an FDSOI NMOS device provided by an embodiment of the present invention; Figure 5 This is the Id-Vg electrical characteristic curve after the total dose irradiation simulation of the FDSOIPMOS device provided by the embodiment of the present invention. The physical structural characteristics of the device include the radiation charge generation rate of the buried oxide layer, see Figure 6 and Figure 7 , Figure 6 This is a physical structural characteristic diagram related to the radiation charge generation rate of the buried oxide layer after the total dose radiation simulation of the FDSOI NMOS device provided by an embodiment of the present invention; Figure 7 This is a physical structural characteristic diagram related to the radiation charge generation rate of the buried oxide layer after the total dose radiation simulation of the FDSOIPMOS device provided by an embodiment of the present invention.

[0043] In this embodiment, in the Solve part of the total dose irradiation simulation, the device electrical characteristic files and physical structure characteristic files of the FDSOI NMOS device and the FDSOI NMOS device after total dose irradiation are saved using Plot and Save statements to obtain a physical structure characteristic file with a suffix of .tdr and an electrical characteristic file with a suffix of .sav. The above files are subsequently imported into the SRAM circuit model for circuit simulation to realize the total dose effect simulation of the SRAM circuit model.

[0044] Step 3: Construct an SRAM circuit model based on FDSOI NMOS devices and FDSOIPMOS devices, perform circuit simulation on the SRAM circuit model based on the total dose irradiation simulation results of FDSOINMOS devices and FDSOI NMOS devices, and obtain the voltage curve of the storage node of the SRAM circuit model after total dose irradiation.

[0045] Optionally, the SRAM circuit model can be a 6T-SRAM circuit, an 8T-SRAM circuit, a 10T-SRAM circuit, or a DICE-SRAM circuit. The 6T-SRAM circuit is the most basic SRAM circuit model, and other SRAM circuits are based on the 6T-SRAM circuit and modified to strengthen the 6T-SRAM and increase stability.

[0046] In an optional embodiment, step 3 includes:

[0047] Step 3.1: Import the FDSOI NMOS device and the total dose irradiation simulation results corresponding to the FDSOI NMOS device in the Device section of Sdevice, and set the second Traps model and corresponding model parameters in the Physics section.

[0048] In this embodiment, the physical structure characteristic file with the suffix .tdr and the electrical characteristic file with the suffix .sav are imported into the device part for the total dose effect simulation of the SRAM circuit model. Specifically, the following statement is used in the File setting of the Device part to import them:

[0049] Grid="filename.tdr"

[0050] Load="filename.sav"

[0051] Doping="filename.tdr"

[0052] It should be noted that the file name used for file import must be the same as the file name of the .trd file and .sav file saved by the Save and Plot statements at the end of the Solve step in the FDSOI NMOS device and total dose irradiation simulation. Otherwise, the file will not be recognized and the import will fail. Similarly, for the second Traps model, the parameters defined in the Device section must be exactly the same as the model parameters of the first Traps model. Otherwise, the import of the Traps model will fail.

[0053] Step 3.2: Build the SRAM circuit model in the System section of Sdevice and set the operating voltage of the SRAM circuit model.

[0054] In this embodiment, the SRAM circuit model is a 6T-SRAM circuit. Specifically, in the System section of Sdevice, four FDSOI NMOS transistors and two FDSOIPMOS transistors are connected. Each electrode in the device is set as a circuit node, and these circuit nodes are connected to form an actual 6T-SRAM circuit.

[0055] See Figure 8 , Figure 8 6T-SRAM circuit diagram of the circuit simulation provided by the embodiment of the present invention, such as Figure 8As shown, the 6T-SRAM circuit consists of six transistors M1-M6, of which transistors M2 and M4 are FDSOIPMOS, and the remaining transistors M1, M3, M5, and M6 are FDSOI NMOS. The gate of transistor M1 is connected to the gate of transistor M2, the drain of transistor M3, the drain of transistor M4, and the drain of transistor M6, respectively; the source of transistor M1 and the source of transistor M3 are both connected to the ground terminal Gnd; the drain of transistor M1 is connected to the drain of transistor M2, the gate of transistor M3, the gate of transistor M4, and the drain of transistor M5, respectively; the source of transistor M2 and the source of transistor M4 are both connected to the power supply voltage terminal Vdd; the gates of transistors M5 and M6 are both connected to the word line WL; the source of transistor M5 is connected to the bit line BL; and the source of transistor M6 is connected to the bit line BLN.

[0056] In this embodiment, the voltages of the storage nodes of the 6T-SRAM circuit, namely, nodes Q and QN, are determined by word line WL and bit lines BL and BLN. When word line WL is high, transistors M5 and M6 conduct, causing the potentials of nodes Q and QN to change. Transistors M1 and M2 form one inverter, while transistors M3 and M4 form another inverter. These two inverters, connected end-to-end, ensure that the potentials of nodes Q and QN are always opposite. When node Q is high, node QN is necessarily low, and vice versa.

[0057] It should be noted that when actually building a 6T-SRAM circuit, the different width-to-length ratios of the NMOS pull-down transistor, the PMOS pull-up transistor, and the transmission transistor must be taken into account. Therefore, when constructing the SRAM circuit model, the width-to-length ratios of different MOS transistors in the SRAM circuit model are adjusted by setting the area factor.

[0058] In this embodiment, in the simulation input file, the setting command is as follows:

[0059] PMOS pmos1(source=DD drain=CH gate=CL substrate=0){physics{areafactor=1.0}}

[0060] NMOS nmos1(source=0drain=CH gate=CL substrate=0){physics{areafactor=3.0}}

[0061] PMOS pmos2(source=DD drain=CL gate=CH substrate=0){physics{areafactor=1.0}}

[0062] NMOS nmos2(source=0drain=CL gate=CH substrate=0){physics{areafactor=3.0}}

[0063] NMOS nmos3(source=BL drain=CH gate=WL substrate=0){physics{areafactor=2.0}}

[0064] NMOS nmos4(source=BLN drain=CL gate=WL substrate=0){physics{areafactor=2.0}}

[0065] Step 3.3: Set the control voltages of the word lines and bit lines of the SRAM circuit model, perform circuit simulation, and obtain the voltage curve of the storage node of the SRAM circuit model after total dose irradiation.

[0066] In this embodiment, the low and high level durations of the word line and bit line are set to 0.5 μs, and the pulse period is 1 μs. The high and low level settings of the word line WL can control the on and off of the transmission tube. The simulation time is set to 2 μs. Figure 9 , Figure 9 This is a timing diagram of the working state of the 6T-SRAM circuit provided by an embodiment of the present invention. From the diagram, we can observe how the voltages of the Q node and the QN node change with time.

[0067] In this embodiment, after importing the device parameter file and building the 6T-SRAM circuit, no other simulation parameter settings need to be changed, and circuit simulation can be performed directly. Svisual is then used to extract the voltage curve of the storage node of the 6T-SRAM circuit after total dose irradiation.

[0068] Step 4: Determine the impact of the total dose irradiation effect on the SRAM circuit model based on the voltage curve of the storage node of the SRAM circuit model after total dose irradiation.

[0069] In an optional embodiment, step 4 includes:

[0070] Step 4.1: Compare the voltage curve of the storage node of the SRAM circuit model after total dose irradiation with the voltage curve of the storage node of the SRAM circuit model without total dose irradiation.

[0071] In this embodiment, Svisual can be used to extract the voltage curves of the storage nodes of the 6T-SRAM circuit after and without total dose irradiation. Figure 10and Figure 11 , Figure 10 The Q-node voltage change of the 6T-SRAM circuit of the FDSOI device provided by the embodiment of the present invention under the total dose effect; Figure 11 This is the QN node voltage change of the 6T-SRAM circuit of the FDSOI device provided by the embodiment of the present invention under the total dose effect.

[0072] like Figure 10 As shown in the figure, the initial voltage of the Q node is set to 1V, indicating a high potential state. Within the 400Krad irradiation dose, the node voltage curve does not fluctuate. As the irradiation dose gradually increases to 600Krad, the high potential voltage amplitude corresponding to the output logic "1" drops to 0.6V, and even flips from 1V to 0V before 0.5μs; the low potential voltage amplitude corresponding to the logic "0" increases to 0.1V within 1.0μs to 1.5μs. Figure 11 As shown in the figure, the initial voltage of the QN node is set to 0V, indicating a low potential state. Within an irradiation dose of 400 krad, the node voltage remains unchanged. As the irradiation dose gradually increases to 600 krad, the node voltage changes, not only in the form of a decrease in the high potential voltage corresponding to a logic "1" to 0.6V and fluctuations in the low potential voltage, but also in the narrowing of the high potential pulse width as the irradiation dose increases. When the QN node transitions from a logic "1" to a logic "0," the output logic value flips from 1.5 μs to 1.0 μs.

[0073] Step 4.2: Based on the voltage curve of the storage node of the SRAM circuit model after total dose irradiation, determine the voltage transfer characteristic curves of the left and right cross-coupled inverters in the SRAM circuit model under different irradiation doses.

[0074] In this embodiment, in order to measure the voltage transfer characteristic curve (VTC) of the left inverter and the right inverter of the 6T-SRAM, it is also necessary to add probes PL and PR to the 6T-SRAM circuit. By inserting a high resistor (1×10 12 Ω) resistor, set the resistance value in the Solve section to activate or deactivate the probe as needed. Figure 12 , Figure 12 1 is a voltage transfer characteristic curve of two cross-coupled inverters on the left and right during irradiation of a 6T-SRAM circuit of an FDSOI device provided by an embodiment of the present invention.

[0075] Step 4.3: Determine the static noise margin of the SRAM circuit model under different irradiation doses based on the voltage transfer characteristic curve of the inverter.

[0076] In this embodiment, the static noise margin (SNM) of the SRAM cell can be measured by the VTC curve. Taking the SRAM retention state as an example, see Figure 13 , Figure 13 The simulation results of the static noise margin (HSNM) of the 6T-SRAM circuit of the FDSOI device provided by the embodiment of the present invention before and after irradiation with a total dose of 1 Mrad are shown, including the high-level noise margin (HSNMH) and the low-level noise margin (HSNML), with the noise margin being the minimum of the two. According to this method, the static noise margin of the 6T-SRAM under different irradiation doses can be measured in sequence, as shown in FIG. Figure 14 The figure shows the results of the static noise margin (HSNM) of the 6T-SRAM circuit of the FDSOI device provided by the embodiment of the present invention under different irradiation doses. It can be seen from the figure that the HSNM of the 6T-SRAM circuit gradually decreases during the irradiation process. It can be calculated that the stability of the memory cell retention state is reduced by 21%.

[0077] In this embodiment, the SRAM total dose effect modeling and simulation method based on FDSOI devices can be applied to metal oxide semiconductor field effect transistors and is suitable for various SRAM circuit structures. According to the changes in the node voltage in the circuit and the changes in the SNM of the SRAM, it is judged whether the circuit fails after irradiation, thereby effectively evaluating the irradiation reliability of the SRAM circuit.

[0078] The present invention's FDSOI device-based SRAM total dose effect modeling and simulation method saves the FDSOI device state after total dose irradiation simulation for use in total dose effect simulation of the SRAM circuit. This method comprehensively considers the impact of the total dose effect on electrical parameters such as the threshold voltage, mutual coupling capacitance, and parasitic resistance of the circuit's devices, thereby providing a more accurate analysis of parameters such as the SRAM's noise margin under irradiation conditions. This method overcomes the limitations of existing circuit-level simulations. Simulations performed directly in TCAD can avoid errors introduced by existing circuit-level simulation device models, resulting in more accurate simulation results.

[0079] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0080] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A method for modeling and simulating the total dose effect of SRAM based on FDSOI devices, characterized in that: include: Step 1: Structural modeling of the FDSOI NMOS device and the FDSOI PMOS device is performed to obtain corresponding device structure models; Step 2: Adding a Radiation model and a first Traps model to the device structure model, setting model parameters, and performing a total dose irradiation simulation to obtain total dose irradiation simulation results corresponding to the FDSOI NMOS device and the FDSOI NMOS device, and saving the total dose irradiation simulation results; wherein the model parameters include: the irradiation dose rate and irradiation time of the Radiation model, and the hole energy level position and hole concentration of the first Traps model; Step 3: constructing an SRAM circuit model based on the FDSOI NMOS device and the FDSOI PMOS device, performing circuit simulation on the SRAM circuit model based on the total dose irradiation simulation results of the FDSOI NMOS device and the FDSOI NMOS device, and obtaining a voltage curve of a storage node of the SRAM circuit model after total dose irradiation; Step 4: determining the influence of the total dose irradiation effect on the SRAM circuit model according to the voltage curve of the storage node of the SRAM circuit model after the total dose irradiation; Step 4 includes: Step 4.1: comparing a voltage curve of a storage node of the SRAM circuit model after the total dose irradiation with a voltage curve of a storage node of the SRAM circuit model without the total dose irradiation; Step 4.2: Determine voltage transfer characteristic curves of the left and right cross-coupled inverters in the SRAM circuit model under different irradiation doses based on the voltage curve of the storage node of the SRAM circuit model after the total dose irradiation; Step 4.3: Determine the static noise margin of the SRAM circuit model under different irradiation doses according to the voltage transfer characteristic curve of the inverter.

2. The SRAM total dose effect modeling and simulation method based on FDSOI devices according to claim 1, characterized in that: The step 1 comprises: According to the device structural parameters of the FDSOI NMOS device and the FDSOI PMOS device, the device structural models of the FDSOI NMOS device and the FDSOI PMOS device are established using the sde tool of Sentaurus TCAD simulation software; the device structural parameters include: device geometry, size, doping concentration and grid density.

3. The SRAM total dose effect modeling and simulation method based on FDSOI devices according to claim 1, characterized in that: During the total dose irradiation simulation process, the FDSOI NMOS device and the bias state of the FDSOI NMOS device are set to an ON state.

4. The SRAM total dose effect modeling and simulation method based on FDSOI devices according to claim 1, characterized in that: The total dose irradiation simulation result includes the electrical characteristics and physical structure characteristics of the device after total dose irradiation; the physical structure characteristics of the device include the irradiation charge generation rate of the buried oxide layer.

5. The SRAM total dose effect modeling and simulation method based on FDSOI devices according to claim 1, characterized in that: The SRAM circuit model includes a 6T-SRAM circuit, an 8T-SRAM circuit, a 10T-SRAM circuit or a DICE-SRAM circuit.

6. The SRAM total dose effect modeling and simulation method based on FDSOI devices according to claim 1, characterized in that: The step 3 comprises: Step 3.1: Import the FDSOI NMOS device and the total dose irradiation simulation results corresponding to the FDSOI NMOS device in the Device section of Sdevice, and set the second Traps model and corresponding model parameters in the Physics section; Step 3.2: Build the SRAM circuit model in the System section of Sdevice and set the operating voltage of the SRAM circuit model; Step 3.3: Setting control voltages of word lines and bit lines of the SRAM circuit model, performing circuit simulation, and obtaining a voltage curve of a storage node of the SRAM circuit model after the total dose irradiation.

7. The SRAM total dose effect modeling and simulation method based on FDSOI devices according to claim 6, characterized in that: The model parameters of the second Traps model are consistent with the model parameters of the first Traps model.

8. The SRAM total dose effect modeling and simulation method based on FDSOI devices according to claim 6, characterized in that: In step 3.2, when constructing the SRAM circuit model, the width-to-length ratios of different MOS transistors in the SRAM circuit model are adjusted by setting an area factor.

Images