Compilation control method, device, medium and electronic equipment

Abstract

The present application provides a compilation control method, device, medium and electronic device. The compilation control method includes obtaining a project to be compiled; performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled; obtaining a tcl script based on N preset synthesis strategies and M preset implementation strategies; performing parallel operation processing on the preset synthesis strategies based on the tcl script to obtain a synthesis dcp file of the preset synthesis strategy; performing parallel operation processing on the preset implementation strategies based on the synthesis netlist in the synthesis dcp file to obtain a timing result associated with the preset implementation strategy; terminating the operation of the preset implementation strategy, otherwise continuing to operate the preset implementation strategy until the implementation dcp file is obtained after the operation of the preset implementation strategy is completed. The compilation control method can improve the timing convergence efficiency of FPGA, greatly speed up the iteration speed of engineering development, and improve the efficiency of engineering development debugging.

Description

Technical Field

[0001] The present application belongs to the field of FPGA engineering and relates to a compilation control method, and in particular to a compilation control method, device, medium and electronic equipment. Background Art

[0002] Field Programmable Gate Array (FPGA) is a programmable logic device widely used in various engineering fields due to its high flexibility and reconfigurability. As FPGA designs grow larger and their logic becomes more complex, achieving timing closure in FPGA projects becomes increasingly difficult and a growing challenge. For example, the widely used Xilinx XCVU9P-FLGA2104 can contain millions of logic cells. Timing closure becomes challenging when only around 30% of the FPGA's resources are utilized. However, in typical projects, 70%-80% of the FPGA's resources are used to ensure an appropriate FPGA model and avoid wasted resources. Therefore, achieving timing closure in FPGAs presents a significant challenge. Since FPGAs require repeated modification and debugging during project development, the ability to quickly generate timing-closed bit files and accelerate FPGA design iterations is crucial for on-time project delivery.

[0003] When a design is extremely complex and difficult to achieve timing closure, it is common to iterate through various strategies to produce the optimal result. When actually compiling a project to generate a bitstream, the number of strategies that can be selected is limited by the compile server. For example, if a server is configured with 16 cores and 128GB of RAM (Random Access Memory), and resources are utilized at approximately 30%, and the compilation of eight strategies is run simultaneously, the synthesis and implementation run time is approximately 6-8 hours. Under normal resource utilization, the entire compilation process is slower, so only a few strategies can be implemented in a day. It may take several days to compile a bitstream file that can be used with timing closure, which significantly impacts the progress of project development and debugging. Therefore, current compilation control methods suffer from low timing closure efficiency. Summary of the Invention

[0004] The purpose of the present application is to provide a compilation control method, device, medium and electronic device, which are used to solve the problem of low timing convergence efficiency in current compilation control methods.

[0005] In a first aspect, the present application provides a compilation control method, comprising: obtaining a project to be compiled; performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled, wherein during the FPGA compilation process of the project to be compiled: obtaining a tool command language Tcl (tool command language) script based on N preset synthesis strategies and M preset implementation strategies, the preset synthesis strategies and the preset implementation strategies being used to solve timing problems of the project to be compiled during the FPGA compilation process, where N and M are both positive integers; performing parallel running processing on the preset synthesis strategies based on the Tcl script to obtain a synthesis design checkpoint DCP (design checkpoint) file of the preset synthesis strategy; performing parallel running processing on the preset implementation strategies based on the synthesis netlist in the synthesis DCP file to obtain a timing result associated with the preset implementation strategy; if the timing result is less than a preset timing result threshold, terminating the operation of the preset implementation strategy, otherwise continuing to operate the preset implementation strategy until the implementation DCP file is obtained after the preset implementation strategy is completed.

[0006] In the compilation control method, by controlling whether the preset implementation strategy is run according to the timing results associated with the preset implementation strategy, it is possible to avoid wasting more time on strategies that are not suitable for this design. More strategies can be traversed within a given time, thereby obtaining the bitstream file faster, improving the timing convergence efficiency of the FPGA, greatly accelerating the iteration speed of engineering development, and improving the engineering development debugging efficiency.

[0007] In one embodiment of the present application, a method for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled includes: performing timed detection on the project to be compiled based on a default path, a preset number of times, and a preset periodic interval of the project to be compiled to obtain a detection result; and based on the detection result, performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0008] In one embodiment of the present application, the detection result is that the version of the project to be compiled has changed or the version of the project to be compiled has not changed. Based on the detection result, FPGA compilation is performed on the project to be compiled to obtain a bitstream file of the project to be compiled: when the detection result is that the version of the project to be compiled has changed, FPGA compilation is performed on the project to be compiled to obtain a bitstream file of the project to be compiled; when the detection result is that the version of the project to be compiled has not changed, FPGA compilation is not performed on the project to be compiled.

[0009] In one embodiment of the present application, the preset implementation strategy includes an optimization design (Optimization Design) stage, a layout design (Placement Design) stage, and a routing design (Routing Design) stage. The timing results associated with the preset implementation strategy include the timing results of the Opt Design stage, the timing results of the Place Design stage, and the timing results of the Route Design stage. If the timing result is less than a preset timing result threshold, the preset implementation strategy is terminated; otherwise, the preset implementation strategy is continued to be executed. The implementation method of the preset implementation strategy includes: if the timing result of the Opt Design stage is less than a first preset timing result threshold, the preset implementation strategy is terminated; otherwise, the preset implementation strategy is continued to be executed; if the timing result of the Place Design stage is less than a second preset timing result threshold, the preset implementation strategy is terminated; otherwise, the preset implementation strategy is continued to be executed; if the timing result of the Route Design stage is less than a third preset timing result threshold, the preset implementation strategy is terminated; otherwise, the preset implementation strategy is continued to be executed.

[0010] In one embodiment of the present application, the implementation method of continuing to run the preset implementation strategy until obtaining the implementation DCP file after the preset implementation strategy is completed includes: performing a timing check on the preset implementation strategy after the preset implementation strategy is completed to obtain a timing check result; if the timing check result meets the requirements, obtaining the implementation DCP file, otherwise not obtaining the implementation DCP file.

[0011] In one embodiment of the present application, the preset implementation strategy is run in parallel based on the synthesis netlist in the synthesis DCP file to obtain the timing result associated with the preset implementation strategy. The implementation method includes: running the preset implementation strategy in parallel based on the synthesis netlist in the synthesis DCP file to obtain the worst negative timing margin WNS (worst negative slack) timing result and the total negative timing margin TNS (total negative slack) timing result associated with the preset implementation strategy.

[0012] In one embodiment of the present application, the compilation control method further includes: automatically generating a report through a notifier after the bitstream file is generated; and automatically pushing the report to a user through a tool API (Application Programming Interface).

[0013] In a second aspect, the present application provides a compilation control device, which includes: a project acquisition module for acquiring a project to be compiled and checking whether the project to be compiled has any version update changes; a project compilation module for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled; a script acquisition module for acquiring a Tcl script based on N preset synthesis strategies and M preset implementation strategies, wherein the synthesis strategy and the implementation strategy are used to solve the timing problem of the project to be compiled during the FPGA compilation process, and N and M are both positive integers; a synthesis strategy running module for performing parallel running processing on the preset synthesis strategy based on the Tcl script to obtain a synthesis DCP file of the preset synthesis strategy; an implementation strategy running module for performing parallel running processing on the preset implementation strategy based on the synthesis netlist in the synthesis DCP file to obtain a timing result associated with the preset implementation strategy; and an implementation DCP bitstream file acquisition module for terminating the operation of the preset implementation strategy if the timing result is less than a preset timing result threshold, otherwise continuing to run the preset implementation strategy until the implementation DCP file is obtained after the preset implementation strategy is completed.

[0014] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the compilation control method described in any one of the first aspects of the present application.

[0015] In a fourth aspect, the present application provides an electronic device, comprising: a memory storing a computer program; and a processor communicatively connected to the memory, for executing the compilation control method described in any one of the first aspects of the present application when calling the computer program.

[0016] As described above, the compilation control method, device, medium, and electronic device of the present application have the following beneficial effects:

[0017] In the compilation control method, by controlling whether the preset implementation strategy is run according to the timing results associated with the preset implementation strategy, it is possible to avoid wasting too much time on strategies that are not suitable for this design. More strategies can be traversed within a given time, thereby obtaining the bitstream file faster, improving the timing convergence efficiency of the FPGA, greatly accelerating the iteration speed of engineering development, and improving the engineering development debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a schematic diagram of the hardware structure for running the compilation control method according to an embodiment of the present application.

[0019] Figure 2Shown is a flowchart of the compilation control method according to an embodiment of the present application.

[0020] Figure 3 Shown is a schematic diagram of the synthesis strategy provided by Vivado in an embodiment of the present application.

[0021] Figure 4 Shown is a schematic diagram of the implementation strategy provided by Vivado in an embodiment of the present application.

[0022] Figure 5 Shown is a flowchart of an implementation method of the present application for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0023] Figure 6 Shown is a flowchart of an implementation method of the present application for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0024] Figure 7 Shown is a flowchart of an implementation method of the preset implementation strategy that terminates the execution of the preset implementation strategy in an embodiment of the present application, otherwise continues to execute the preset implementation strategy.

[0025] Figure 8 It shows a flowchart of an implementation method of the present application that continues to run the preset implementation strategy until the preset implementation strategy is completed and the implementation method of the DCP file is obtained.

[0026] Figure 9 Shown is a flowchart of the compilation control method described in an embodiment of the present application.

[0027] Figure 10 Shown is a flowchart of the compilation control method described in an embodiment of the present application.

[0028] Figure 11 Shown is a flowchart of the script automation implementation process of the embodiment of the present application.

[0029] Figure 12 Shown is a flowchart of the compilation control method described in an embodiment of the present application.

[0030] Figure 13 Shown is a structural diagram of the compilation control device according to an embodiment of the present application.

[0031] Component number description

[0032] 10 Computing Devices

[0033] 110 Memory

[0034] 120 processors

[0035] 130 bus

[0036] 140 Access Device

[0037] 20 FPGA chips

[0038] 1300 Compilation Control Device

[0039] 1310 Project Acquisition Module

[0040] 1320 Project Compilation Module

[0041] 1330 Script Acquisition Module

[0042] 1340 Comprehensive Strategy Operation Module

[0043] 1350 Implementing the Strategy Operation Module

[0044] 1360 Implement dcp file acquisition module

[0045] Steps S11-S14

[0046] Steps S21-S23

[0047] Steps S31-S32

[0048] Steps S41-S43

[0049] Steps S51-S53

[0050] Steps S61-S62 DETAILED DESCRIPTION

[0051] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0052] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0053] The technical solutions in the embodiments of the present application are described in detail below in conjunction with the drawings in the embodiments of the present application.

[0054] The compilation control method provided in the embodiment of the present application can be run in a computing device. Figure 1 For example, Figure 1 This is a hardware block diagram of a computing device running the compilation control method. Computing device 10 includes, but is not limited to, memory 110 and processor 120. Processor 120 and memory 110 are connected via bus 130, and computing device 10 is in communication with FPGA chip 20. The bitstream file obtained by running the compilation control method on computing device 10 can be downloaded to FPGA chip 20 for implementing specific hardware functions.

[0055] The computing device 10 also includes an access device 140 that enables the computing device 10 to communicate via one or more networks. Examples of such networks include a public switched telephone network, a local area network, a wide area network, a personal area network, or a combination of communication networks such as the Internet. The access device 140 may include any type of network interface, whether wired or wireless, such as one or more network interface cards, such as an IEEE 802.11 wireless local area network radio interface, a World Wide Interoperability for Microwave Access interface, an Ethernet interface, a universal serial bus interface, a cellular network interface, a Bluetooth interface, a near field communication interface, and the like.

[0056] In the embodiment of the present application, the above components of the computing device 10 and Figure 1 Other components not shown in the figure may also be connected to each other, for example, via a bus. Figure 1 The computing device structure block diagram shown is for illustrative purposes only and is not intended to limit the scope of the present application. Those skilled in the art may add or replace other components as needed.

[0057] Computing device 10 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., a tablet computer, a personal digital assistant, a laptop computer, a notebook computer, a netbook computer, etc.), a mobile phone (e.g., a smartphone), a wearable computing device (e.g., a smartwatch, smart glasses, etc.), or other types of mobile devices, or a stationary computing device such as a desktop computer or PC. Computing device 10 may also be a mobile or stationary server.

[0058] like Figure 2 As shown, this embodiment provides a compilation control method, which can be executed by a computer processor and includes:

[0059] S11, obtain the project to be compiled.

[0060] Optionally, the project to be compiled may refer to a project to be compiled by FPGA, and the project to be compiled may include a higher-level circuit written in a hardware description language such as Verilog or VHDL (Very High Speed ​​Integrated Circuit Hardware Description Language).

[0061] S12, performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0062] In the FPGA compilation process of the project to be compiled, the following steps S13-S15 are also performed:

[0063] Optionally, the FPGA compilation process can include: Synthesis—the process of converting a higher-level circuit description written in a hardware description language such as Verilog or VHDL into a lower-level circuit description, that is, generating a netlist file that describes the connection between logic gates and flip-flops. During this process, the synthesis tool optimizes the design to meet constraints such as timing and area; Implementation—mapping the netlist generated by synthesis to the actual physical resources on the FPGA. This process includes placement, routing, and bitstream generation. Placement is the process of placing logic cells in appropriate locations on the FPGA chip; routing is the process of connecting these logic cells to form a circuit. The result of implementation is a bitstream file that can be run on the FPGA and describes the specific configuration of the circuit on the FPGA.

[0064] When using Xilinx Vivado to compile and generate bitstream, each stage must be completed before entering the next stage, and the implementation process is particularly time-consuming. In response to various reasons that may cause timing convergence difficulties, Vivado provides a variety of synthesis and implementation strategies that can be optimized for various actual situations, such as strategies for avoiding congestion, optimizing fan-out, optimizing logic levels, and other reasons that may cause timing problems. The synthesis strategies provided by Vivado are as follows: Figure 3 As shown, the implementation strategy provided by Vivado is as follows Figure 4 shown.

[0065] Optionally, the bitstream file is a binary file that meets timing requirements and is generated after steps such as synthesis, layout and routing, and timing analysis. The file can be downloaded to an FPGA chip to implement specific hardware functions.

[0066] Optionally, the FPGA compilation of the project to be compiled has FPGA hardware limitations. If this limitation is exceeded, insufficient resources will result in failure. Therefore, it is generally necessary to first evaluate whether the resources are sufficient before the subsequent process is feasible.

[0067] S13, obtaining a Tcl script based on N preset synthesis strategies and M preset implementation strategies, wherein the preset synthesis strategies and the preset implementation strategies are used to solve the timing problem of the to-be-compiled project during the FPGA compilation process, and N and M are both positive integers.

[0068] Optionally, the Tcl script may be a script rewritten by calling a Python program and combining n pre-set synthesis strategies and m implementation strategies. The Tcl script may be regarded as a configuration file of the preset synthesis strategy and the preset implementation strategy.

[0069] Optionally, the preset synthesis strategy may refer to the preset synthesis strategy provided by Vivado, and the preset implementation strategy may refer to the preset implementation strategy provided by Vivado. The values ​​of N and M may be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0070] S14, performing parallel operation processing on the preset comprehensive strategy based on the Tcl script to obtain a comprehensive DCP file of the preset comprehensive strategy.

[0071] Optionally, the DCP file is a unique encrypted compressed file of Vivado that is equivalent to the HDL (Hardware Description Language) source file in FPGA design and can be easily loaded and replaced.

[0072] Optionally, running the preset comprehensive strategies in parallel may refer to running the preset comprehensive strategies in parallel in a multi-process manner through a Python program, and generating a corresponding DCP file after each comprehensive strategy is completed. The comprehensive DCP file may refer to the DCP file generated after the comprehensive strategy is completed.

[0073] S15 , performing parallel execution processing on the preset implementation strategies based on the integrated netlist in the integrated DCP file to obtain timing results associated with the preset implementation strategies.

[0074] Optionally, the synthesized DCP file contains a synthesized netlist, which is an intermediate representation used to describe the logic structure of a digital circuit in the FPGA design process. It is converted from a high-level hardware description language and contains all the logic elements in the circuit and the connections between them.

[0075] Optionally, the implementation strategy may generally be divided into multiple phases and executed sequentially, and the timing result associated with the preset implementation strategy may refer to the timing result of the preset implementation strategy in a specified implementation phase.

[0076] Optionally, the stages of the preset implementation strategy include: Opt Design stage, Place Design stage and Route Design stage, etc., and the timing results associated with the preset implementation strategy may include: the timing results of the Opt Design stage, the timing results of the Place Design stage and the timing results of the Route Design stage.

[0077] Optionally, the associated timing results of the preset implementation strategy may also include timing results of various stages of the implementation strategy.

[0078] Optionally, the implementation method of parallel running of the preset implementation strategy based on the integrated netlist in the integrated DCP file includes: when the Python program detects that the integrated DCP file is generated, the script will load the integrated DCP file and run the implementation strategy in parallel according to the integrated netlist in the integrated DCP file.

[0079] Optionally, the method for executing parallel processing on the preset implementation strategy based on the integrated netlist in the integrated DCP file to obtain the timing result associated with the preset implementation strategy includes: executing parallel processing on the preset implementation strategy based on the integrated netlist in the integrated DCP file to obtain the WNS (Worst Negative Slack) timing result and TNS (Total Negative Slack) timing result associated with the preset implementation strategy. The WNS is the worst slack value, which represents the worst performance of the chip, and the TNS is the sum of all negative slack values, which represents a performance range of the chip.

[0080] S16, if the timing result is less than the preset timing result threshold, then terminate the running of the preset implementation strategy, otherwise continue to run the preset implementation strategy until the implementation DCP file is obtained after the running of the preset implementation strategy is completed.

[0081] Optionally, the preset timing result threshold and the timing result are values ​​at the same implementation stage in the preset implementation strategy. The preset timing result threshold can be flexibly set based on actual circumstances, and this embodiment does not explicitly limit this. If the timing result is less than the preset timing result threshold, it indicates that Vivado will have difficulty converging in the subsequent implementation stages and completing the mapping of the synthesized netlist to the actual physical resources on the FPGA. Therefore, the script will terminate the execution of the preset implementation strategy.

[0082] Optionally, a corresponding DCP file will be generated after each implementation strategy is completed. The implementation DCP file may refer to a DCP file generated after the implementation strategy is completed.

[0083] According to the above description, the compilation control method includes: obtaining a project to be compiled; performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled, wherein during the FPGA compilation process of the project to be compiled: obtaining a tcl script based on N preset synthesis strategies and M preset implementation strategies, the preset synthesis strategies and the preset implementation strategies are used to solve the timing problem of the project to be compiled during the FPGA compilation process, and N and M are both positive integers; performing parallel running processing on the preset synthesis strategies based on the tcl script to obtain a synthesis dcp file of the preset synthesis strategy; performing parallel running processing on the preset implementation strategies based on the synthesis netlist in the synthesis dcp file to obtain a timing result associated with the preset implementation strategy; if the timing result is less than a preset timing result threshold, terminating the operation of the preset implementation strategy, otherwise continuing to operate the preset implementation strategy until the implementation dcp file is obtained after the preset implementation strategy is completed.

[0084] In the compilation control method, by controlling whether the preset implementation strategy is run according to the timing results associated with the preset implementation strategy, it is possible to avoid wasting too much time on strategies that are not suitable for this design. More strategies can be traversed within a given time, thereby obtaining the bitstream file faster, improving the timing convergence efficiency of the FPGA, greatly accelerating the iteration speed of engineering development, and improving the engineering development debugging efficiency.

[0085] See also Figure 5 ,like Figure 5 As shown, this embodiment provides a method for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled, including:

[0086] S21 , performing a timed detection on the project to be compiled based on a default path, a preset number of times, and a preset periodic interval of the project to be compiled to obtain a detection result.

[0087] Optionally, the default path may refer to the default path set in the project plan to be compiled. The preset number of times may represent a preset number of detections, and more comprehensive and accurate detection results can be obtained through multiple detections. The preset period interval may represent the period interval between two adjacent detections. The preset number of times and the preset period interval may be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0088] Optionally, the detection result is that the version of the project to be compiled has changed or the version of the project to be compiled has not changed.

[0089] S22: Based on the detection result, perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0090] See also Figure 6 ,like Figure 6 As shown, this embodiment provides a method for performing FPGA compilation on the project to be compiled based on the detection result to obtain a bitstream file of the project to be compiled, including:

[0091] S31 : When the detection result indicates that the version of the project to be compiled has changed, perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0092] S32: When the detection result shows that the version of the project to be compiled has not changed, FPGA compilation is not performed on the project to be compiled.

[0093] Optionally, the purpose of this step is to reduce the active intervention of engineers, increase the degree of automation, and improve the overall iteration efficiency.

[0094] See also Figure 7 ,like Figure 7 As shown, this embodiment provides an implementation method for terminating the preset implementation strategy if the timing result is less than a preset timing result threshold, and continuing to execute the preset implementation strategy otherwise, including:

[0095] S41: If the timing result of the Opt Design phase is less than a first preset timing result threshold, then terminate the execution of the preset implementation strategy; otherwise, continue to execute the preset implementation strategy.

[0096] Optionally, the first preset timing result threshold is a timing result threshold preset in the Opt Design stage. The first preset timing result threshold can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0097] S42: If the timing result of the Place Design stage is less than a second preset timing result threshold, terminate the execution of the preset implementation strategy; otherwise, continue to execute the preset implementation strategy.

[0098] Optionally, the second preset timing result threshold is a timing result threshold preset in the Place Design stage. The second preset timing result threshold can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0099] S43: If the timing result of the Route Design stage is less than a third preset timing result threshold, then terminate the execution of the preset implementation strategy; otherwise, continue to execute the preset implementation strategy.

[0100] Optionally, the third preset timing result threshold is a timing result threshold preset in the Route Design stage. The third preset timing result threshold can be flexibly set according to actual conditions, and this embodiment does not explicitly limit this.

[0101] See also Figure 8 ,like Figure 8 As shown, this embodiment provides an implementation method for continuing to run the implementation strategy until obtaining the implementation DCP file after the preset implementation strategy is completed, including:

[0102] S51 , after the preset implementation strategy is executed, a timing check is performed on the preset implementation strategy to obtain a timing check result.

[0103] Optionally, the timing check may refer to a check on timing details involved in the implementation DCP file, and the timing check result may be a timing check result that satisfies the requirement, i.e., satisfies the timing requirement, or a timing check result that does not meet the requirement, i.e., does not meet the timing requirement.

[0104] S52: If the timing check result meets the requirement, the implementation DCP file is obtained; otherwise, the implementation DCP file is not obtained.

[0105] See also Figure 9 ,like Figure 9 As shown, this embodiment provides a compilation control method, further comprising:

[0106] S61: After the bitstream file is generated, a report is automatically generated through a notifier.

[0107] S62: Automatically push the report to the user through an API (Application Programming Interface).

[0108] Optionally, the user, i.e. the corresponding engineer, automatically generates a report, i.e. a report, through notifer, i.e. a notifier, and sends a message to the corresponding engineer through api, saving the trouble of frequently logging into the server, i.e. a server.

[0109] In one embodiment of the present application, the compilation control method sets a default path according to the project plan, and sets the number of times and periodic intervals for regular detection. If a version change is found, the process will be automatically started and multiple tasks will be carried out in parallel. By automating the entire compilation process, strategies with poor timing can be discovered and terminated early, and other strategies can be quickly replaced for compilation. In this way, as many strategies as possible can be traversed within a limited time, thereby greatly increasing the probability of generating a timing-converged bitstream.

[0110] In the compilation process, after each compilation stage is completed, the report timing tool can be used, and the script will automatically analyze the timing results, mainly looking at the two indicators WNS and TNS. These are indicators that measure the quality of timing in the timing report. WNS: worst negative slack, the worst slack value, represents the worst performance of the chip; TNS: total negative slack, the sum of all negative slack values, represents a performance range of the chip. If these two values ​​are less than expected, the compilation is terminated early, and other strategies that have not detected anomalies are maintained, so as to avoid wasting time under inappropriate strategies. The compilation control method can automatically and quickly traverse multiple comprehensive implementation strategies, greatly accelerating the time to generate a bitstream with timing convergence, thereby greatly accelerating the time required for engineering development and debugging.

[0111] See also Figure 10 ,like Figure 10 As shown, the compilation control method first calls the python program in the script, combines n comprehensive strategies and m implementation strategies that are set in advance, and rewrites the tcl script (configuration file) accordingly.

[0112] Second, the Python program runs n synthesis strategies in parallel as a multi-process process. Each synthesis strategy generates a corresponding synthesis DCP file after completion. The DCP file is a Vivado-specific encrypted, compressed file equivalent to the HDL source file in FPGA design, allowing for easy loading and replacement.

[0113] Afterwards, when the Python program detects that a synthesis DCP file has been generated, the script will load the DCP file and parallelize m implementation strategies based on the synthesis netlist in this DCP file. The implementation strategy is usually divided into multiple stages (such as OptDesign, Place Design, Route Design, etc.) and executed sequentially. The program will check the timing results WNS and TNS at the specified implementation stage. If the WNS and TNS at this stage are less than the specified threshold, it means that Vivado will find it difficult to converge in the subsequent implementation stage and complete the mapping of the synthesis netlist to the actual physical resources on the FPGA. Therefore, the script will terminate the execution of the implementation strategy. After the implementation strategy is completed, the script will perform another timing check. If the requirements are met, the implementation DCP file will be generated for subsequent bitstream file generation.

[0114] Finally, when the entire process is completed, this method will generate rpt and log files, and automatically push messages to the corresponding engineers through the tool API, which can enable more effective collaboration and improve efficiency.

[0115] The compilation control method automatically starts the process at a fixed time and can automatically and concurrently traverse various comprehensive implementation strategies in conjunction with computing resources. It also monitors the compilation process, performing timing analysis after each compilation sub-process. If the current running result does not meet the requirements, the compilation is terminated promptly and the next strategy is selected to start a new compilation. This avoids wasting time and computing resources on inappropriate strategies, allowing for traversal of more strategies within a given timeframe, thereby more quickly generating FPGA bitstream files that can be downloaded and debugged. Reports are automatically generated through a notifier and sent to corresponding engineers via an API, eliminating the need for frequent server logins. This semi-automated approach can significantly reduce engineers' manual operations while balancing resources, efficiency, and flexibility. By reducing iteration cycles, it significantly improves engineering development and debugging efficiency.

[0116] See also Figure 11 ,like Figure 11 The flowchart of the script automation implementation process is shown. Figure 11 The phys_opt_design in the figure may refer to the physical optimization design stage, which will not be described in detail in this embodiment.

[0117] In one embodiment of the present application, please refer to Figure 12 ,like Figure 12 As shown, the compilation control method may include the following steps:

[0118] 1. Set the project warehouse and path according to the project arrangement.

[0119] 2. Implement the policy profiles that need to be tried in advance.

[0120] 3. Implement regular program monitoring, set the number and interval period, generally according to the project cycle and milestone stages.

[0121] 4. Process execution: Whenever a version update is detected, the process of generating the project version will be executed.

[0122] 5. Task monitoring and control will be carried out during the process.

[0123] 6. Generate results, generate reports, and send notification messages.

[0124] The protection scope of the compilation control method described in the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing, or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.

[0125] See also Figure 13 ,like Figure 13 As shown, this embodiment provides a compilation control device 1300, and the compilation control device 1300 includes:

[0126] The project acquisition module 1310 is used to acquire the project to be compiled.

[0127] The project compilation module 1320 is used to perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled.

[0128] The script acquisition module 1330 is used to acquire TCL scripts based on N preset synthesis strategies and M preset implementation strategies, wherein the synthesis strategies and the implementation strategies are used to solve the timing problem of the project to be compiled during the FPGA compilation process, and N and M are both positive integers.

[0129] The comprehensive strategy running module 1340 is used to perform parallel running processing on the preset comprehensive strategy based on the TCL script to obtain a comprehensive DCP file of the preset comprehensive strategy.

[0130] The implementation strategy running module 1350 is used to perform parallel running processing on the preset implementation strategy based on the synthesis netlist in the synthesis DCP file to obtain the timing result associated with the preset implementation strategy.

[0131] The implementation DCP file acquisition module 1360 is used to terminate the operation of the preset implementation strategy if the timing result is less than the preset timing result threshold, otherwise continue to operate the preset implementation strategy until the implementation DCP file is obtained after the preset implementation strategy is completed.

[0132] In the compilation control device 1300 provided in this embodiment, the project acquisition module 1310 and Figure 2 The project compilation module 1320 corresponds to step S11 of the compilation control method shown in FIG. Figure 2 The script acquisition module 1330 corresponds to step S12 of the compilation control method shown in FIG. Figure 2 The integrated strategy operation module 1340 corresponds to step S13 of the compilation control method shown in FIG. Figure 2 The implementation strategy execution module 1350 corresponds to step S14 of the compilation control method shown in FIG. Figure 2 The step S15 of the compilation control method shown in FIG. 1 corresponds to the step S15 of the compilation control method shown in FIG. 1 , wherein the dcp file acquisition module 1360 is implemented with Figure 2 This corresponds to step S16 of the compilation control method shown.

[0133] In the several embodiments provided in this application, it should be understood that the disclosed devices or methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of modules / units is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules or units, which can be electrical, mechanical or other forms.

[0134] The modules / units described as separate components may or may not be physically separate, and the components displayed as modules / units may or may not be physical modules, that is, they may be located in one place or distributed across multiple network elements. Some or all of the modules / units may be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in the various embodiments of the present application may be integrated into a processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into a single module / unit.

[0135] Those skilled in the art should further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0136] This embodiment provides an electronic device, which includes a memory storing a computer program; a processor connected to the memory for executing the computer program when the computer program is called; Figure 2 The compilation control method shown.

[0137] The embodiment of the present application also provides a computer-readable storage medium. Those skilled in the art will understand that all or part of the steps in the method for implementing the above embodiment can be completed by instructing the processor through a program, and the program can be stored in a computer-readable storage medium, and the storage medium is a non-transitory medium, such as a random access memory, a read-only memory, a flash memory, a hard disk, a solid-state drive, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid-state drive (SSD)), etc.

[0138] The embodiment of the present application may also provide a computer program product, the computer program product including one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the process or function described in the embodiment of the present application is generated in whole or in part. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer or data center to another website, computer or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method.

[0139] When the computer program product is executed by a computer, the computer executes the method described in the above method embodiment. The computer program product can be a software installation package. When the above method is needed, the computer program product can be downloaded and executed on the computer.

[0140] The descriptions of the processes or structures corresponding to the above figures have different emphases. For parts that are not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

[0141] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A compilation control method, characterized in that: The compilation control method includes: Get the project to be compiled; Perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled, wherein during the FPGA compilation process of the project to be compiled: Obtaining a tool command language Tcl script based on N preset synthesis strategies and M preset implementation strategies, wherein the preset synthesis strategies and the preset implementation strategies are used to solve a timing problem of the to-be-compiled project during an FPGA compilation process, where N and M are both positive integers; The preset synthesis strategy is run in parallel based on the TCL script to obtain a synthesis design checkpoint DCP file of the preset synthesis strategy; the preset implementation strategy is run in parallel based on the synthesis netlist in the synthesis DCP file to obtain a timing result associated with the preset implementation strategy; If the timing result is less than the preset timing result threshold, the preset implementation strategy is terminated; otherwise, the preset implementation strategy is continued to be executed until the implementation DCP file is obtained after the preset implementation strategy is completed. The preset implementation strategy includes an optimization design Opt Design stage, a layout design Place Design stage, and a routing design Route Design stage. The timing results associated with the preset implementation strategy include the timing results of the Opt Design stage, the timing results of the Place Design stage, and the timing results of the Route Design stage. If the timing result is less than a preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues. The implementation method of the preset implementation strategy includes: if the timing result of the Opt Design stage is less than a first preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues; if the timing result of the Place Design stage is less than a second preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues; if the timing result of the Route Design stage is less than a third preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues.

2. The compilation control method according to claim 1, wherein: The method for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled includes: Performing a timed detection on the project to be compiled based on a default path, a preset number of times, and a preset periodic interval of the project to be compiled to obtain a detection result; Based on the detection result, FPGA compilation is performed on the project to be compiled to obtain a bitstream file of the project to be compiled.

3. The compilation control method according to claim 2, wherein: The detection result is that the version of the project to be compiled has changed or the version of the project to be compiled has not changed. Based on the detection result, the method for performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled includes: When the detection result indicates that the version of the project to be compiled has changed, performing FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled; When the detection result shows that the version of the project to be compiled has not changed, FPGA compilation is not performed on the project to be compiled.

4. The compilation control method according to claim 1, wherein: The implementation method of continuing to run the preset implementation strategy until obtaining the implementation DCP file after the preset implementation strategy is completed includes: After the preset implementation strategy is completed, a timing check is performed on the preset implementation strategy to obtain a timing check result; If the timing check result meets the requirements, the implementation DCP file is obtained; otherwise, the implementation DCP file is not obtained.

5. The compilation control method according to claim 1, wherein: The implementation method of performing parallel operation processing on the preset implementation strategy based on the integrated netlist in the integrated DCP file to obtain the timing result associated with the preset implementation strategy includes: The preset implementation strategies are run in parallel based on the synthesis netlist in the synthesis DCP file to obtain the worst negative timing margin WNS timing result and the total negative timing margin TNS timing result associated with the preset implementation strategy.

6. The compilation control method according to claim 1, wherein: The compilation control method further includes: After the bitstream file is generated, a report is automatically generated via a notifier; The report is automatically pushed to the user through the tool API.

7. A compilation control device, characterized in that: The compile control device comprises: Project acquisition module, used to obtain the project to be compiled; The project compilation module is used to perform FPGA compilation on the project to be compiled to obtain a bitstream file of the project to be compiled; A script acquisition module is used to acquire a TCL script based on N preset synthesis strategies and M preset implementation strategies, wherein the synthesis strategy and the implementation strategy are used to solve the timing problem of the project to be compiled during the FPGA compilation process, where N and M are both positive integers; A comprehensive strategy running module, configured to run the preset comprehensive strategy in parallel based on the TCL script to obtain a comprehensive DCP file of the preset comprehensive strategy; An implementation strategy running module, configured to execute a parallel running process on the preset implementation strategy based on the integrated netlist in the integrated DCP file, so as to obtain a timing result associated with the preset implementation strategy; Implementing a DCP file acquisition module, configured to terminate the execution of the preset implementation strategy through the TCL script if the timing result is less than a preset timing result threshold, otherwise continue to execute the preset implementation strategy until the implementation DCP file is acquired after the preset implementation strategy is completed; The preset implementation strategy includes an optimization design Opt Design stage, a layout design Place Design stage, and a routing design Route Design stage. The timing results associated with the preset implementation strategy include the timing results of the Opt Design stage, the timing results of the Place Design stage, and the timing results of the Route Design stage. If the timing result is less than a preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues. The implementation method of the preset implementation strategy includes: if the timing result of the Opt Design stage is less than a first preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues; if the timing result of the Place Design stage is less than a second preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues; if the timing result of the Route Design stage is less than a third preset timing result threshold, the operation of the preset implementation strategy is terminated, otherwise, the operation of the preset implementation strategy continues.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the compilation control method according to any one of claims 1 to 6 is implemented.

9. An electronic device, characterized in that: The electronic device comprises: a memory storing a computer program; A processor is communicatively connected to the memory, and executes the compilation control method according to any one of claims 1 to 6 when calling the computer program.

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