Performance test architecture, method and device for IP (Internet Protocol) of Nand flash memory controller
By adding multiple FPGA chips to the test subcard and placing the flash channel IP module into the FPGA chip on the test subcard, the problem of excessive resources after IP synthesis on the FPGA platform is solved, and more efficient layout and routing are achieved. Timing closure improves functional verification coverage and efficiency of Nand flash controllers.
Patent Information
- Application Number
- CN202411530816.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-01-21
AI Technical Summary
With the increase in the number of channels and CEs in the Nand flash controller design, the resource occupied by IP integration on the FPGA platform exceeds the FPGA resource limit, resulting in difficulty in layout and routing and timing convergence, and it is impossible to achieve full channel and full CE. Functional verification.
By adding multiple FPGA chips to the test daughter card, the flash memory channel IP modules originally set in the FPGA platform are placed into the FPGA chips on the test daughter card, thereby reducing the resources occupied by IP synthesis on the FPGA platform and optimizing Place and route and timing closure.
It effectively reduces the occupied resources after IP synthesis on the FPGA platform, improves the efficiency of layout and routing and timing closure, enables full-channel and full-CE functional verification, and improves verification coverage and efficiency.
Smart Images
Figure CN119337791A_ABST
Abstract
Description
Technical Field
[0001] This article relates to flash memory controller technology, and more particularly to a performance test architecture, method, and device for a Nand flash memory controller IP. Background Art
[0002] Data throughput is an important performance indicator of Nand flash memory controller, and FPGA hardware simulation is one of the main means to verify it.
[0003] In the related art, software simulation, FPGA and dedicated hardware accelerator are usually used to verify the Nand flash memory controller IP.
[0004] However, as the number of channels and CEs in the design increases, the resources occupied by the IP after synthesis are often too large, thus exceeding the FPGA resource limit. Summary of the invention
[0005] The present application provides a performance test architecture, method and device for a Nand flash memory controller IP, which can reduce the occupied resources of the IP after synthesis on an FPGA platform, and is beneficial to layout and routing and timing convergence.
[0006] In a first aspect, the present application provides a performance test architecture for a Nand flash controller IP, including: an FPGA platform, a test daughter card; the FPGA platform includes: a subsystem IP module and a Nand flash controller IP module, the test daughter card includes: a plurality of FPGA chips and a plurality of Nand flash particle groups, each FPGA chip corresponds to a group of Nand flash particle groups, each FPGA chip includes: a flash channel IP module, the flash channel IP module is used to implement the function of a group of channels corresponding to the Nand flash particle group; The Nand flash controller IP module is used to receive the sub instructions from the subsystem IP module, combine and arrange the received sub instructions, and send the combined and arranged sub instructions to the corresponding flash channel IP module; Each of the flash channel IP modules is used to perform protocol conversion on the sub instruction using the FPGA resources of the corresponding FPGA chip, and to perform data communication with the Nand flash memory particle group according to the protocol-converted instruction; The Nand flash memory particle group refers to a group of Nand flash memory particle groups corresponding to the corresponding FPGA chip.
[0007] In a second aspect, the present application provides a performance testing method for a Nand flash memory controller IP, which is applied to the performance testing architecture of the above-mentioned Nand flash memory controller IP, and the method includes: The Nand flash controller IP module receives the sub instructions from the subsystem IP module, combines and arranges the received sub instructions, and sends the combined and arranged sub instructions to the corresponding flash channel IP module; Each of the flash channel IP modules uses the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the sub instruction, and performs data communication with the Nand flash memory particle group according to the protocol-converted instruction; The Nand flash memory particle group refers to a group of Nand flash memory particle groups corresponding to the corresponding FPGA chip.
[0008] In a third aspect, the present application provides an FPGA platform located in the above-mentioned Nand flash controller IP performance test architecture, the FPGA platform comprising: a subsystem IP module and a Nand flash controller IP module; The subsystem IP module is used to send a sub instruction to the Nand flash controller IP module; The Nand flash memory controller IP module is used to receive sub instructions from the subsystem IP module, combine and arrange the received sub instructions, and send the combined and arranged sub instructions to the corresponding flash memory channel IP module in the test daughter card.
[0009] In a fourth aspect, the present application provides a test daughter card, which is located in the performance test architecture of the above-mentioned Nand flash memory controller IP, and the test daughter card includes: multiple FPGA chips and multiple groups of Nand flash memory particle groups, each FPGA chip corresponds to a group of Nand flash memory particle groups, and each FPGA chip includes: a flash memory channel IP module, and the flash memory channel IP module is used to implement the function of a group of channels corresponding to the Nand flash memory particle group; Each of the flash channel IP modules is used to perform protocol conversion on the sub instructions from the Nand flash controller IP module using the FPGA resources of the corresponding FPGA chip, and to perform data communication with the Nand flash particle group according to the protocol-converted instructions; The Nand flash memory particle group is used to perform data communication with the corresponding flash memory channel IP module.
[0010] Compared with the related art, the embodiment of the present application adds multiple FPGA chips to the test daughter card, and places the flash channel IP originally set in the FPGA platform into the FPGA chips added to the test daughter card, thereby reducing the occupied resources of the IP on the FPGA platform after synthesis, which is beneficial to layout and routing and timing convergence.
[0011] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0013] Figure 1 A schematic diagram of a performance test architecture of a Nand flash memory controller IP in the related art; Figure 2 This is a schematic diagram of a performance test architecture of a Nand flash memory controller IP according to an embodiment of the present application; Figure 3 A schematic diagram of a performance test method for a Nand flash memory controller IP according to an embodiment of the present application; Figure 4 This is a schematic diagram of the structure of an FPGA platform according to an embodiment of the present application; Figure 5 This is a schematic diagram of the structure of a test daughter card according to an embodiment of the present application. DETAILED DESCRIPTION
[0014] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.
[0015] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.
[0016] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation for the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.
[0017] Data throughput is an important performance indicator of Nand flash storage controller chips. Among them, Nand flash read and write bandwidth is closely related to the performance of Nand flash controller IP, so comprehensive verification of Nand flash controller functions is particularly important for the development of Nand flash storage controller chips. Nand flash storage controller chips usually use the method of increasing concurrent channels to increase the read and write bandwidth of storage particles. With the explosion of big data and the increase in CPU speed, the requirements for storage read and write speed and storage capacity are getting higher and higher, so the number of channels and CEs of storage controller chips have also increased, which has brought greater challenges to the verification of Nand flash controller IP.
[0018] In the related art, software simulation, FPGA and dedicated hardware accelerator are usually used to verify the Nand flash memory controller IP. When the FPGA verification method is used, the schematic diagram of the performance test architecture of the Nand flash memory controller IP in the related art can be as follows: Figure 1As shown, it includes: an FPGA platform 101 and a test daughter card 102; the FPGA platform 101 includes: a subsystem IP module (i.e., a Subsystem IP module) 103 and a Nand flash memory controller IP module 104, the Nand flash memory controller IP module 104 includes: a plurality of flash memory channel IP modules 105, and the test daughter card 102 includes: a plurality of Nand flash memory particle groups 106, each flash memory channel IP module 104 corresponds to a group of Nand flash memory particle groups 106.
[0019] However, due to the increase in the number of design channels and CEs, this architecture inevitably leads to an area after synthesis that is too large, exceeding the FPGA resource limit, and the timing cannot converge well. In this case, it is necessary to cut the number of channels or CEs required by the design on the FPGA platform, resulting in the inability to perform functional verification of all channels and all CEs, which seriously reduces the verification coverage and leads to insufficient verification. In addition, due to the above problems, if the functions of all channels and all CEs are to be verified on the FPGA test, it is necessary to generate the running binary files required by the FPGA for each channel separately, and it is impossible to make all channels and all CEs work at the same time, which will inevitably cause a decrease in the efficiency of Nand flash controller IP testing and verification.
[0020] To this end, the embodiment of the present application provides a performance test architecture for a Nand flash memory controller IP, such as Figure 2 As shown, it includes: an FPGA platform 101, a test daughter card 102; the FPGA platform 101 includes: a subsystem IP module 103 and a Nand flash memory controller IP module 104, the test daughter card 102 includes: a plurality of FPGA chips 107 and a plurality of Nand flash memory particle groups 106, each FPGA chip 107 corresponds to a group of Nand flash memory particle groups 106, each FPGA chip 107 includes: a flash memory channel IP module 105, the flash memory channel IP module 105 is used to implement the function of a group of channels corresponding to the Nand flash memory particle group 106; The Nand flash controller IP module 104 is used to receive the sub instructions from the subsystem IP module 103, combine and arrange the received sub instructions, and send the combined and arranged sub instructions to the corresponding flash channel IP module 105; Each of the flash channel IP modules 105 is used to perform protocol conversion on the sub instructions using the FPGA resources of the corresponding FPGA chip, and to perform data communication with the Nand flash memory particle group 106 according to the protocol-converted instructions; The Nand flash memory particle group refers to a group of Nand flash memory particle groups corresponding to the corresponding FPGA chip.
[0021] Exemplarily, a group of Nand flash memory particle groups corresponding to each flash channel IP module includes multiple Nand flash memory particle groups.
[0022] Exemplarily, the protocol conversion may be to convert Nandflash operations into ONFI signals.
[0023] The performance test architecture of the Nand flash controller IP provided in the embodiment of the present application adds multiple FPGA chips to the test daughter card, and respectively places the flash channel IP originally set in the FPGA platform into the FPGA chips added to the test daughter card, thereby reducing the occupied resources of the IP on the FPGA platform after synthesis, which is beneficial to layout and routing and timing convergence.
[0024] The performance test architecture of the Nand flash controller IP provided in the embodiment of the present application reduces the area of the IP after integration on the FPGA platform by independently separating the flash channel control part in the Nand flash controller IP, which is conducive to timing convergence. Then, the independent flash channel IP modules of each channel group are placed on the channel-specific FPGA chip on the test subcard (each flash channel IP module is connected to a group of Nand flash particles through the ONFI bus), and since only the flash channel IP modules are placed on the FPGA chip, the area is within the controllable range and the timing is easier to converge.
[0025] In an exemplary embodiment, each of the flash channel IP modules 105 is further used to obtain the data communication result of the Nand flash particle group 106, and use the FPGA resources of the corresponding FPGA chip to perform protocol conversion on the data communication result, and send the data communication result after protocol conversion to the Nand flash controller IP module 104; The Nand flash controller IP module 104 is further used to receive data communication results from at least one of the flash channel IP modules 105 , combine and arrange the received data communication results, and feed back the combined and arranged data communication results to the subsystem IP module 103 .
[0026] Exemplarily, the protocol conversion may be converting ONFI signals into Nandflash operations.
[0027] In an exemplary embodiment, the number of FPGA chips in the test daughter card is equal to the number of Nand flash memory particle groups and equal to the number of channel groups.
[0028] Exemplarily, the channel group is a channel group of the flash channel control part originally located in the flash controller IP. The number of FPGA chips set in the test daughter card can be equal to the number of channel groups, that is, the number of flash channel IP modules originally located in the Nand flash controller IP module. When the number of FPGA chips set in the test daughter card is equal to the number of channel groups, each flash channel IP module originally located in the Nand flash controller IP module can be removed from the FPGA platform and placed on the test daughter card, thereby minimizing the area size of the FPGA platform after IP synthesis, which is beneficial to timing convergence.
[0029] In an exemplary embodiment, each of the flash channel IP modules stores a bit file for implementing the functions of a group of channels corresponding to the Nand flash memory particle group, and the bit file for the functions of a group of channels is obtained by synthesizing the design source files of the functions of a group of channels.
[0030] In an exemplary embodiment, each of the flash channel IP modules uses the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the sub instruction, and performs data communication with the Nand flash memory particle group according to the protocol-converted instruction, including: Each of the flash channel IP modules utilizes the FPGA resources of the FPGA chip to which it belongs, and performs protocol conversion on the sub instructions according to the bit file stored in itself, and performs data communication with the Nand flash memory particle group according to the bit file and the protocol-converted instructions.
[0031] In an exemplary embodiment, each of the flash channel IP modules uses the FPGA resources of the corresponding FPGA chip to perform protocol conversion on the data communication result, and sends the data communication result after the protocol conversion to the Nand flash controller IP module, including: Each of the flash channel IP modules utilizes the FPGA resources of the FPGA chip to which it belongs, and performs protocol conversion on the data communication results according to the bit file saved by itself, and sends the data communication results after protocol conversion to the Nand flash controller IP module according to the bit file.
[0032] In an exemplary embodiment, the design source files of the group of channel functions include: a group of channel function logic files and a flash memory physical layer logic file.
[0033] In an exemplary embodiment, the Nand flash memory controller IP module is connected to each flash memory channel IP module via a group of signal lines.
[0034] In an exemplary embodiment, the Nand flash controller IP module sends the combined and arranged sub instructions to the corresponding flash channel IP module, including: The Nand flash memory controller IP module sends the combined and arranged sub instructions to the corresponding flash channel IP module through the signal line group between the Nand flash memory controller IP module to which the sub instructions are to be sent; In an exemplary embodiment, the Nand flash controller IP module receives a data communication result from at least one of the flash channel IP modules, including: The Nand flash memory controller IP module receives the data communication result from at least one of the flash channel IP modules through a signal line group between the Nand flash memory controller IP module to receive the data communication result.
[0035] The present application also provides a Nand flash memory controller IP performance test method, which is applied to the Nand flash memory controller IP performance test architecture described in any of the above embodiments, such as Figure 3 As shown, including: Step 201, the Nand flash memory controller IP module receives the sub instructions from the subsystem IP module, combines and arranges the received sub instructions, and sends the combined and arranged sub instructions to the corresponding flash memory channel IP module; Step 202: Each flash channel IP module uses the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the sub instruction, and performs data communication with the Nand flash memory particle group according to the protocol-converted instruction; The Nand flash memory particle group refers to a group of Nand flash memory particle groups corresponding to the corresponding FPGA chip.
[0036] The performance testing method of the Nand flash controller IP provided in the embodiment of the present application adds multiple FPGA chips to the test daughter card, and respectively places the flash channel IP originally set in the FPGA platform into the FPGA chips added to the test daughter card, thereby reducing the occupied resources of the IP on the FPGA platform after synthesis, which is beneficial to layout and routing and timing convergence.
[0037] In an exemplary embodiment, the method further comprises: Step 203: Each of the flash channel IP modules obtains the data communication result of the Nand flash particle group, and uses the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the data communication result, and sends the data communication result after protocol conversion to the Nand flash controller IP module; Step 204: the Nand flash controller IP module receives the data communication result from at least one of the flash channel IP modules, combines and arranges the received data communication result, and feeds back the combined and arranged data communication result to the subsystem IP module.
[0038] The present application embodiment also provides an FPGA platform, which is located in the performance test architecture of the Nand flash memory controller IP described in any of the above embodiments, such as Figure 4 As shown, the FPGA platform 101 includes: a subsystem IP module 103 and a Nand flash memory controller IP module 104; The subsystem IP module 103 is used to send a sub instruction to the Nand flash controller IP module 104; The Nand flash controller IP module 104 is used to receive sub instructions from the subsystem IP module 103, combine and arrange the received sub instructions, and send the combined and arranged sub instructions to the corresponding flash channel IP module in the test daughter card.
[0039] In an exemplary embodiment, the Nand flash controller IP module 104 is further used to receive data communication results from at least one of the flash channel IP modules, combine and arrange the received data communication results, and feed back the combined and arranged data communication results to the subsystem IP module 103; The subsystem IP module 103 is further configured to receive the data communication result fed back by the Nand flash controller IP module 104 .
[0040] The FPGA platform provided in the embodiment of the present application no longer includes the original flash channel IP, thereby reducing the occupied resources after the IP synthesis itself, which is beneficial to layout and routing and timing convergence.
[0041] The present application also provides a test daughter card, which is located in the performance test architecture of the Nand flash memory controller IP described in any of the above embodiments, such as Figure 5 As shown, the test daughter card 102 includes: multiple FPGA chips 107 and multiple groups of Nand flash memory particle groups 106, each FPGA chip 107 corresponds to a group of Nand flash memory particle groups 106, and each FPGA chip 107 includes: a flash memory channel IP module 105, and the flash memory channel IP module 105 is used to implement the function of a group of channels corresponding to the Nand flash memory particle group 106; Each of the flash channel IP modules 105 is used to perform protocol conversion on the sub instructions from the Nand flash controller IP module using the FPGA resources of the corresponding FPGA chip, and to perform data communication with the Nand flash particle group 106 according to the protocol-converted instructions; The Nand flash memory particle group 106 is used to perform data communication with the corresponding flash memory channel IP module 105 .
[0042] In an exemplary embodiment, the Nand flash memory particle group 106 is also used to send data communication results to at least one flash channel IP module 105; Each of the flash channel IP modules 105 is also used to obtain the data communication results of the Nand flash particle group 106, and use the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the data communication results, and send the data communication results after protocol conversion to the Nand flash controller IP module.
[0043] The test sub-card provided in the embodiment of the present application adds multiple FPGA chips to itself, and places the flash channel IP originally set in the FPGA platform into the added FPGA chips, thereby reducing the occupied resources of the IP located on the FPGA platform after synthesis, which is beneficial to layout and routing and timing convergence.
[0044] An embodiment of the present application further provides a computer-readable storage medium, on which computer-executable commands are stored, and the computer-executable commands are used to execute the performance testing method of the Nand flash memory controller IP as described in any of the above embodiments.
[0045] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
Claims
1. A performance test architecture for Nand flash memory controller IP, characterized in that: include: FPGA platform, test daughter card; The FPGA platform includes: a subsystem IP module and a Nand flash memory controller IP module, the test daughter card includes: multiple FPGA chips and multiple groups of Nand flash memory particle groups, each FPGA chip corresponds to a group of Nand flash memory particle groups, each FPGA chip includes: a flash memory channel IP module, the flash memory channel IP module is used to implement the function of a group of channels corresponding to the Nand flash memory particle group; The Nand flash controller IP module is used to receive the sub instructions from the subsystem IP module, combine and arrange the received sub instructions, and send the combined and arranged sub instructions to the corresponding flash channel IP module; Each of the flash channel IP modules is used to perform protocol conversion on the sub instruction using the FPGA resources of the corresponding FPGA chip, and to perform data communication with the Nand flash memory particle group according to the protocol-converted instruction; The Nand flash memory particle group refers to a group of Nand flash memory particle groups corresponding to the corresponding FPGA chip.
2. The performance test framework according to claim 1, characterized in that: Each of the flash channel IP modules is further used to obtain the data communication results of the Nand flash particle group, and use the FPGA resources of the corresponding FPGA chip to perform protocol conversion on the data communication results, and send the data communication results after protocol conversion to the Nand flash controller IP module; The Nand flash controller IP module is also used to receive data communication results from at least one of the flash channel IP modules, combine and arrange the received data communication results, and feed back the combined and arranged data communication results to the subsystem IP module.
3. The performance test framework according to claim 1, characterized in that: The number of FPGA chips in the test daughter card is equal to the number of Nand flash memory particle groups and equal to the number of channel groups.
4. The performance test framework according to claim 2, characterized in that: Each of the flash channel IP modules stores a bit file for realizing the functions of a group of channels corresponding to the Nand flash memory particle group, and the bit file for the functions of a group of channels is obtained by synthesizing the design source files of the functions of a group of channels; Each of the flash channel IP modules uses the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the sub instruction, and performs data communication with the Nand flash memory particle group according to the protocol-converted instruction, including: Each of the flash channel IP modules utilizes the FPGA resources of the FPGA chip to which it belongs, and performs protocol conversion on the sub instruction according to the bit file saved by itself, and performs data communication with the Nand flash memory particle group according to the bit file and the protocol-converted instruction; Each of the flash channel IP modules uses the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the data communication result, and sends the data communication result after the protocol conversion to the Nand flash controller IP module, including: Each of the flash channel IP modules utilizes the FPGA resources of the FPGA chip to which it belongs, and performs protocol conversion on the data communication results according to the bit file saved by itself, and sends the data communication results after protocol conversion to the Nand flash controller IP module according to the bit file.
5. The performance test architecture according to claim 4, characterized in that: The design source files of the functions of the group of channels include: a group of channel function logic files and a flash memory physical layer logic file.
6. The performance test framework according to claim 2, characterized in that: The Nand flash memory controller IP module is connected to each flash memory channel IP module via a group of signal lines; The Nand flash controller IP module sends the combined and organized sub instructions to the corresponding flash channel IP module, including: The Nand flash memory controller IP module sends the combined and arranged sub instructions to the corresponding flash channel IP module through the signal line group between the Nand flash memory controller IP module to which the sub instructions are to be sent; The Nand flash controller IP module receives a data communication result from at least one of the flash channel IP modules, including: The Nand flash memory controller IP module receives the data communication result from at least one of the flash channel IP modules through a signal line group between the Nand flash memory controller IP module to receive the data communication result.
7. A performance test method for Nand flash memory controller IP, characterized in that: A performance test architecture for a Nand flash memory controller IP as claimed in any one of claims 1 to 6, the method comprising: The Nand flash memory controller IP module receives the sub instructions from the subsystem IP module, combines and arranges the received sub instructions, and sends the combined and arranged sub instructions to the corresponding flash memory channel IP module; Each flash channel IP module uses the FPGA resources of the FPGA chip to which it belongs to perform protocol conversion on the sub instructions, and performs data communication with the Nand flash memory particle group according to the protocol-converted instructions; The Nand flash memory particle group refers to a group of Nand flash memory particle groups corresponding to the corresponding FPGA chip.
8. The performance testing method according to claim 7, characterized in that: The method further comprises: Each of the flash channel IP modules obtains the data communication result of the Nand flash particle group, and uses the FPGA resources of the corresponding FPGA chip to perform protocol conversion on the data communication result, and sends the data communication result after protocol conversion to the Nand flash controller IP module; The Nand flash memory controller IP module receives data communication results from at least one of the flash channel IP modules, combines and arranges the received data communication results, and feeds back the combined and arranged data communication results to the subsystem IP module.
9. An FPGA platform, characterized in that: In the performance test architecture of the Nand flash controller IP as described in any one of claims 1 to 6, the FPGA platform includes: a subsystem IP module and a Nand flash controller IP module; The subsystem IP module is used to send a sub instruction to the Nand flash controller IP module; The Nand flash memory controller IP module is used to receive sub instructions from the subsystem IP module, combine and arrange the received sub instructions, and send the combined and arranged sub instructions to the corresponding flash memory channel IP module in the test daughter card.
10. A test daughter card, characterized in that: In the performance test architecture of the Nand flash controller IP as described in any one of claims 1 to 6, the test subcard comprises: a plurality of FPGA chips and a plurality of Nand flash particle groups, each FPGA chip corresponds to a group of Nand flash particle groups, each FPGA chip comprises: a flash channel IP module, the flash channel IP module is used to implement the function of a group of channels corresponding to the Nand flash particle group; Each of the flash channel IP modules is used to perform protocol conversion on the sub instructions from the Nand flash controller IP module using the FPGA resources of the corresponding FPGA chip, and to perform data communication with the Nand flash particle group according to the protocol-converted instructions; The Nand flash memory particle group is used to perform data communication with the corresponding flash memory channel IP module.