Peak maximum pooling neurons

Abstract

The invention relates to spiking maximum pooling neurons. In accordance with an embodiment, a maximum pooled neuron is provided having first and second integrator circuits, a comparator circuit, a Schmitt trigger circuit, and a pair of switches. The first integrator circuit and the second integrator circuit filter the first input string and the second input string from the first neuron and the second neuron of the previous layer, respectively, to generate corresponding first filtered input string and second filtered input string. A comparator circuit amplifies a difference between the first filtered input string and the second filtered input string and generates an amplified differential signal. The Schmitt trigger circuit generates a binary output signal based on the amplified differential signal. A pair of switches has a common first terminal coupled to the output node of the maximum pooling neuron and a common control terminal coupled to the output terminal of the Schmitt trigger circuit. The other terminal of the pair of switches is coupled to a corresponding input string.

Description

Technical Field

[0001] The present disclosure relates generally to neural networks, and in particular embodiments to max-pooling neurons of spiking neural networks. Background Art

[0002] Spiking neural networks (SNNs) are artificial neural networks that more closely mimic natural neural networks. In addition to neuronal and synaptic states, SNNs incorporate the concept of time into their operational models. The idea is that neurons in SNNs do not transmit information in every propagation cycle (like a typical multilayer perceptron network), but only when the membrane potential (an intrinsic quality of a neuron related to its membrane charge) reaches a certain value (called a threshold). When the membrane potential reaches the threshold, the neuron triggers and generates a signal that propagates to other neurons, which increase or decrease their potential in response to the signal. Summary of the invention

[0003] Technical advantages are generally achieved through embodiments of the present disclosure describing max-pooling neurons of spiking neural networks.

[0004] The first aspect relates to a maximum pooling neuron. The maximum pooling neuron includes a first integrator circuit, a second integrator circuit, a comparator circuit, a Schmitt trigger circuit, and a pair of switches. The first integrator circuit is configured to filter a first input string (train) of a first neuron from a previous layer and generate a first filtered input string. The second integrator circuit is configured to filter a second input string of a second neuron from a previous layer and generate a second filtered input string. The comparator circuit is configured to amplify the difference between the first filtered input string and the second filtered input string and generate an amplified differential signal. The Schmitt trigger circuit is configured to generate a binary output signal at an output terminal of the Schmitt trigger circuit based on the amplified differential signal. The paired switches include a first switch and a second switch. The paired switches have a common first terminal and a common control terminal, the common first terminal is coupled to the output node of the maximum pooling neuron, and the common control terminal is coupled to the output terminal of the Schmitt trigger circuit. The second terminal of the first switch is coupled to the first input string. The second terminal of the second switch is coupled to the second input string.

[0005] A second aspect relates to a maximum pooling layer with a maximum pooling neuron. The maximum pooling neuron includes a first integrator circuit, a second integrator circuit, a comparator circuit, a Schmitt trigger circuit, and a pair of switches. The first integrator circuit is configured to filter a first input string from a first neuron of a previous layer and generate a first filtered input string. The second integrator circuit is configured to filter a second input string from a second neuron of a previous layer and generate a second filtered input string. The comparator circuit is configured to amplify the difference between the first filtered input string and the second filtered input string and generate an amplified differential signal. The Schmitt trigger circuit is configured to generate a binary output signal at an output terminal of the Schmitt trigger circuit based on the amplified differential signal. The paired switches include a first switch and a second switch. The paired switches have a common first terminal and a common control terminal, the common first terminal is coupled to the output node of the maximum pooling neuron, and the common control terminal is coupled to the output terminal of the Schmitt trigger circuit. The second terminal of the first switch is coupled to the first input string. The second terminal of the second switch is coupled to the second input string.

[0006] A third aspect relates to a neural network. The neural network includes a first layer and a maximum pooling layer. The first layer includes a first neuron and a second neuron. The first neuron is configured to provide a first input string. The second neuron is configured to provide a second input string. The maximum pooling layer includes a maximum pooling neuron. The maximum pooling neuron includes a first integrator circuit, a second integrator circuit, a comparator circuit, a Schmitt trigger circuit, and a pair of switches. The first integrator circuit is configured to filter a first input string from a first neuron of a previous layer and generate a first filtered input string. The second integrator circuit is configured to filter a second input string from a second neuron of a previous layer and generate a second filtered input string. The comparator circuit is configured to amplify the difference between the first filtered input string and the second filtered input string and generate an amplified differential signal. The Schmitt trigger circuit is configured to generate a binary output signal at an output terminal of the Schmitt trigger circuit based on the amplified differential signal. The paired switches include a first switch and a second switch. The paired switches have a common first terminal and a common control terminal, the common first terminal is coupled to the output node of the maximum pooling neuron, and the common control terminal is coupled to the output terminal of the Schmitt trigger circuit. The second terminal of the first switch is coupled to the first input string. The second terminal of the second switch is coupled to the second input string.

[0007] Embodiments may be implemented in hardware, software or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 It is a block diagram of an artificial neuron in a traditional artificial neural network;

[0010] Figure 2 is a block diagram of a leaky integrate and fire (LIF) neuron in an embodiment spiking neural network (SNN);

[0011] Figure 3 is a timing diagram corresponding to the membrane potential of the LIF neuron;

[0012] Figure 4 is a block diagram of an embodiment single photon avalanche diode (SPAD) system using a spiking neural network implemented in a vehicle;

[0013] Figure 5 is a block diagram of an embodiment spiking neural network;

[0014] Figure 6 is a block diagram of a maximum pooling neuron of an embodiment;

[0015] Figure 7 is a schematic diagram of a maximum pooling neuron of an embodiment;

[0016] Figure 8 is a schematic diagram of a maximum pooling neuron of an embodiment;

[0017] Fig. 9 A signal showing an example sequence of operations of a max pooling neuron;

[0018] Fig.10 A signal showing an example sequence of operations of a max pooling neuron;

[0019] Fig.11 A signal showing an example sequence of operations of a max pooling neuron; and

[0020] Fig.12 A signal showing an example sequence of operations of a max pooling neuron. DETAILED DESCRIPTION

[0021] The present disclosure provides many applicable inventive concepts that can be embodied in a variety of specific contexts. Specific embodiments are merely illustrations of specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments can be combined to form additional embodiments.

[0022] The changes or modifications described in one embodiment may also be applied to other embodiments. In addition, various changes, substitutions and modifications may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0023] Although the inventive aspects are primarily described in the context of max pooling neurons in a max pooling layer of a spiking neural network, it should also be understood that these inventive aspects can also be applied to any neuron of a neural network layer that can benefit from the embodiments disclosed herein. Furthermore, in addition to application to remote sensing devices and image sensing applications, these inventive aspects can also benefit other devices and applications that utilize low-power learning systems, such as autonomous vehicles, drones, and robots. Furthermore, aspects of the present disclosure can be similarly applied to commercial and industrial applications.

[0024] Figure 1 A block diagram of an artificial neuron 106 in a conventional artificial neural network 100 is illustrated. In the conventional artificial neural network 100, the artificial neuron 106 operates within a fixed update period (T) and has a constant activation level. The input 102 is biased using a bias term (i.e., weight) 104 and added together by the artificial neuron 106. The output of the artificial neuron 106 then passes through an activation function (f) 108, typically a rectified linear unit (ReLU), and is provided to, for example, the next artificial neuron of the conventional artificial neural network 100.

[0025] Figure 2 A block diagram of a leaky integrate and fire (LIF) neuron 206 in an embodiment spiking neural network (SNN) 200 is illustrated. Figure 3 Illustrated is a timing diagram 300 corresponding to the membrane potential 302 of the LIF neurons 206. Note that each LIF neuron 206 maintains its respective membrane potential.

[0026] Compared to the conventional artificial neural network 100 which operates synchronously, the spiking neural network 200 operates asynchronously. When the spiking neural network 200 introduces time in its operation model, a continuous string of inputs 202 is continuously biased using the bias term 204 and provided to the LIF neuron 206. In response to an input spike in the continuous string of inputs 202 arriving at the LIF neuron 206, the potential (v t ) increases over time. Conversely, the absence of input spikes in a continuous train of inputs 202 decreases the potential of membrane potential 302 (v t ). When the membrane potential 302 reaches the firing threshold 304, an output spike is generated in a continuous train of outputs 306, and the membrane potential 302 is reset, represented in the timing diagram 300 as times t1 and t2.

[0027] The use of spikes allows for better integration of time, frequency, and phase information. Other attractive qualities offered by spiking neural networks are greater data sparsity and lower power consumption than traditional synchronous networks.

[0028] While the advantages of the spiking neural network 200 are well known, the main problem that has prevented its widespread use is the need to develop training methods that limit its size to a few layers. One way to avoid this is to convert the traditionally trained artificial neural network to a spiking equivalent. However, the conversion process imposes restrictions on the types of layers and activations that can be used in the modified network. Since the activations of the original artificial neural network are approximated using spiking equivalents, the overall accuracy for each layer in the modified network decreases.

[0029] Figure 4 Illustrated is a block diagram of an embodiment single photon avalanche diode (SPAD) system 400 using a spiking neural network 402 implemented in, for example, a vehicle 404, which may (or may not) be arranged as shown. SPAD system 400 may include additional components not depicted.

[0030] As training techniques and resources for deep neural networks have improved, so too has the use of spiking neural networks 402. These neuromorphic networks tend to exploit the event-based nature of single photon avalanche diode (SPAD) sensors 406, for example.

[0031] Vehicle 404 is equipped with a SPAD sensor 406, which is a remote sensing device, such as a light detection and ranging (LIDAR) sensor. In an embodiment, SPAD sensor 406 provides laser pulses to a transmission device within vehicle 404 and receives reflected photons 408 from objects around vehicle 404. Reflected photons 408 pass through spiking neural network 402 and are classified, analyzed, and processed by processor 410.

[0032] Figure 5 A block diagram of an embodiment spiking neural network 500 is illustrated, which can be implemented in the spiking neural network 402 of the SPAD sensor 406. The spiking neural network 500 includes an input layer 502, a convolutional layer 504, a max pooling layer 506, and an output layer 508, which may (or may not) be arranged as shown. Although five neurons are shown in the input layer 502 and the convolutional layer 504, and four neurons are shown in the max pooling layer 506 and the output layer 508, it should be understood that more or fewer neurons are similarly contemplated in embodiments. The number of neurons is generally set based on the number of features in the input data set. In addition, the spiking neural network 500 may include additional layers between the input layer 502 and the output layer 508.

[0033] The input layer 502 includes artificial input neurons. The input layer 502 provides initial data for further processing, such as the convolution layer 504 and the maximum pooling layer 506. The input layer 502 is the beginning of the workflow for the spiking neural network 500, and typically does not perform any transformations on the data. Although five artificial input neurons are shown in the input layer 502, more or fewer neurons may be considered and are generally set based on the number of features in the input data set.

[0034] Convolutional layer 504 is typically used to analyze visual images, such as data collected from SPAD sensor 406. Convolutional layer 504 uses a mathematical operation called convolution, rather than a general matrix multiplication. In effect, convolutional layer 504 allows a three-dimensional frame or image to be used as input data for a neural network. Although five artificial input neurons are shown in input layer 502, more or fewer neurons may be considered and are generally set based on the number of features in the input data set. It should be understood that the use of convolutional layer 504 in spiking neural network 402 is non-limiting.

[0035] In a spiking neural network, the maximum activation in the field of view is the input neuron that produces spikes at the highest frequency. The neurons in the max pooling layer 506 find the maximum activation within the field of view, which is propagated to the next layer. The max pooling operation involves extracting a window from the input feature map and outputting the maximum value of each channel. When the max pooling layer 506 is added to the neural network model, the dimensionality of the image is reduced by reducing the number of pixels in the output from the previous layer.

[0036] Conventionally, spiking neural networks have limited implementations of the max pooling layer 506. Existing solutions typically apply some function to each neuron individually, and then use external electronics to evaluate which neurons' spike trains will be propagated to the next layer.

[0037] The first existing solution is the time to first spike, which operates by simply passing the spike train of the input neuron that spikes first. This approach works only under the assumption that the neuron that spikes first is also the neuron that will spike at a higher rate; however, this assumption does not reflect reality because not all neurons have a membrane potential of zero at the beginning of any integration period.

[0038] A second existing solution uses a pooling gate to connect the input neuron to the output neuron based on a function that defines a criterion for the maximally excited neuron. While this solution can avoid some of the problems with the first spike time, it is difficult to switch dynamically due to the decay of the additional second term over time. The only way to ensure that dynamic frequency switching is represented is to introduce a fixed integration period that resets at the end, allowing to take into account any changes in the input frequency. This solution is limited to being implemented in software.

[0039] A third solution uses spike approximation, such as in Maximum Joint Operation (MJOP) or Joint Max (AVAM). MJOP is a method specific to the architecture of the Loihi neuromorphic hardware platform. It first passes the incoming spike train through a low-pass filter that charges the membrane potential of their corresponding compartment. For multiple inputs, the maximum is calculated in a binary tree. The solution provided by MJOP is limited by the specific hardware platform it requires for its operation.

[0040] AVAM is a more general hardware model built on the principle of neural engineering framework (NEF). In AVAM, the maximum function is realized by first filtering the incoming spike train and passing the signal to the maximum pooling neuron. The maximum pooling process is performed by dividing the maximum function into two terms. The first term is realized by multiplying the two inputs by, for example, 0.5 and connecting them to the output node P. The second term is realized by passing the input to a set containing neurons A and B, where the weight of input 1 is 0.5 and the weight of input 2 is -0.5. The inputs are added together, and the absolute term is realized via the tuning curves of A and B neurons, where if the result of the addition is negative, A spikes, and if the result of the addition is positive, B spikes. The output is then multiplied by r / Φ to connect it to the output node, where r is the radius of the range of values ​​that can be represented, and Φ represents the maximum excitation rate. Although the system operates well on the trigger rate, it still causes significant errors when recreating the input of the maximum triggering neuron spike train. This error is caused by the slew rate introduced by the filtering process, which means that the filtered current initially charges the membrane potential of the max-pooling neuron at a slower rate.

[0041] Unfortunately, these solutions do not typically allow for dynamic switching between neurons if the spike rate of the input neurons varies due to changes in external stimuli. Additionally, existing solutions typically require external synchronization hardware to sample and clock the electronics required for implementation, reducing the benefits of the asynchronous nature of spiking neural networks.

[0042] Figure 6A block diagram of an embodiment max pooling neuron 600 is illustrated, which can be implemented as a neuron in the max pooling layer 506 of the spiking neural network 500. The max pooling neuron 600 includes integrator circuits 602, 604, a comparator circuit 606, an optional Schmitt trigger circuit 608, and transistors 610, 612, which may (or may not) be arranged as shown. The max pooling neuron 600 may include additional components that are not depicted.

[0043] The input spike signal 614 received at the first integrator circuit 602 is the output (V a ). In contrast, the input spike signal 616 received at the second integrator circuit 604 is the output (V b ). At a high level, the max pooling neuron 600 operates as a switch that connects the maximum firing input neuron (ie, the first neuron or the second neuron) from the previous layer to the output of the max pooling neuron and, for example, to the next layer.

[0044] One of the main drawbacks of existing improved spiking neural networks is that they do not respond well to changes in input frequency. For example, in previous solutions, when the second neuron providing the input spike signal 616 begins to fire at a higher rate than the first neuron providing the input spike signal 614, the previous max pooling solution responds slowly or cannot respond (i.e., in the case of the exponential decay method solution). The embodiments of the present disclosure provide a max pooling neuron 600 that is able to respond quickly to changes in input frequency.

[0045] The integrator circuits 602, 604 perform mathematical integration on the input spike signals 614, 616. The first integrator circuit 602 provides a first voltage based on the input spike signal 614, and the second integrator circuit 604 provides a second voltage to the comparator circuit 606 based on the input spike signal 616. In an embodiment, the integrator circuits 602, 604 are low-pass filters, which can be implemented using, for example, operational amplifiers (op-amps) and passive components such as resistors and capacitors. In an embodiment, the integrator circuits 602, 604 form a filter stage of the max-pooling neuron 600. In an embodiment, the integrator circuits 602, 604 average the input spike signals 614, 616 so that the output voltage (at the output of the integrator circuits 602, 604) is proportional to the firing rate.

[0046] The comparator circuit 606 compares the first voltage and the second voltage (i.e., the proportional voltage levels of the input spike signals 614, 616) received from the integrator circuits 602, 604. The comparator circuit 606 determines which neuron fires at a higher rate based on the amplitude of the first voltage and the amplitude of the second voltage. The comparator circuit 606 generates an amplified signal to the Schmitt trigger circuit 608 based on the comparison result. In an embodiment, the amplified signal is a digital binary signal indicating a high state or a low state based on a voltage comparison. In other embodiments, the amplified signal is an analog value. The comparator circuit 606 can be implemented using, for example, an operational amplifier and a resistor. In an embodiment, the comparator circuit 606 forms a voltage comparison stage of the maximum pooling neuron 600.

[0047] The Schmitt trigger circuit 608 is used to stabilize (ie, improve stability) the output voltage of the comparator circuit 606 and prevent frequent switching due to small oscillations by introducing hysteresis on the output of the comparator circuit 606 .

[0048] In an embodiment, the Schmitt trigger circuit 608 converts the analog amplified signal into a binary output signal that switches between two voltage levels based on a specified threshold. In an embodiment, the Schmitt trigger circuit 608 includes an upper threshold voltage and a lower threshold voltage. When the input voltage rises above the upper threshold voltage, the output of the Schmitt trigger circuit 608 switches to a high state and remains in the high state until the input voltage drops below the lower threshold voltage; at this time, the output switches to a low state. This hysteresis between the upper threshold and the lower threshold helps to eliminate fluctuations caused by noise and provide a more stable and clear output.

[0049] Advantageously, the Schmitt trigger circuit 608 provides a stable output from the comparator circuit 606. Therefore, it should be understood that implementing the Schmitt trigger circuit 608 in the max pooling neuron 600 is non-limiting. In an embodiment, the max pooling neuron 600 may not include the Schmitt trigger circuit 608. In other embodiments, other circuits or methods may be implemented in the max pooling neuron 600 to improve stability at the output of the comparator circuit 606.

[0050] The transistors 610, 612 are arranged as a complementary metal oxide semiconductor (CMOS) formed by a complementary and symmetrical pair of a p-type metal oxide semiconductor field effect transistor (MOSFET) (i.e., the second transistor 612) and an n-type MOSFET (i.e., the first transistor 610). The control (i.e., gate) terminal of the p-type MOSFET (i.e., the second transistor 612) is coupled to the control terminal of the n-type MOSFET (i.e., the first transistor 610) and to the output terminal of the Schmitt trigger circuit 608. The drain (e.g., output) terminal of the p-type MOSFET (i.e., the second transistor 612) is coupled to the drain terminal of the n-type MOSFET (i.e., the first transistor 610) and is coupled to the output node 618 of the max pooling neuron 600. The source (e.g., input) terminal of the n-type MOSFET (i.e., the first transistor 610) is coupled to the first neuron and receives the input spike signal 614. The source terminal of the p-type MOSFET (i.e., the second transistor 612) is coupled to the second neuron and receives the input spike signal 616.

[0051] The composition of the p-type transistor (i.e., the second transistor 612) creates a low resistance between its source and drain contacts when a low gate voltage from the Schmitt trigger circuit 608 is applied, and creates a high resistance when a high gate voltage from the Schmitt trigger circuit 608 is applied. On the other hand, the composition of the n-type transistor (i.e., the first transistor 610) creates a high resistance between the source and drain when a low gate voltage from the Schmitt trigger circuit 608 is applied, and creates a low resistance when a high gate voltage from the Schmitt trigger circuit 608 is applied. Therefore, the first transistor 610 is configured to be activated in a high state at its gate terminal. In contrast, the second transistor 612 is configured to be activated in a low state at its gate terminal.

[0052] Transistors 610 , 612 are used as switches to control which frequency spike signal is passed to the next layer (eg, output layer 508 ) at output node 618 . In an embodiment, transistors 610 , 612 form a switching stage of max pooling neuron 600 .

[0053] The transistors 610, 612 effectively couple one of the input spike signal 614 or the input spike signal 616 to the output node 618 of the max pooling neuron 600. In the high state of the output of the Schmitt trigger circuit 608, the first transistor 610 is selected to couple the input spike signal 614 from the first neuron to the output node 618. In the low state of the output of the Schmitt trigger circuit 608, the second transistor 612 is selected to couple the input spike signal 616 from the second neuron to the output node 618. Either the first transistor 610 or the second transistor 612 is always active, so the spike signal is always propagated to the next layer.

[0054] As the system settles down from changes in input frequency, there can be small errors in the output of the max pooling neuron 600 (i.e., it may miss one or two spikes in a continuous train along the input); however, for most applications, such errors are believed to have a negligible effect on the overall firing rate.

[0055] Previous solutions to implement max pooling layers for spiking neural networks use spikes in the input signal to charge a capacitor. The resulting charge is then measured after a period of time to determine the higher firing rate. In addition, previous solutions introduce an integration period before the higher frequency signal can be passed to the next level. Disadvantageously, these solutions require external timing and additional electronics for measurement, resulting in higher power consumption, complexity, and increased chip space. The integration period increases the neural network processing time and introduces information loss due to paralysis of the neural network while the signal is integrated. In addition, since the amplitude of the updates to the stored value decreases over time, dynamic switching does not occur in a reasonable time, which means that even if another neuron subsequently begins to fire at a higher frequency, it will not be selected as the highest frequency without a system reset.

[0056] Figure 7 A schematic diagram of an embodiment max-pooling neuron 700 is illustrated, which can be implemented as max-pooling neuron 600. Max-pooling neuron 700 is an analog circuit with passive analog components that do not rely on external electronic devices or clock signals. Max-pooling neuron 700 includes integrator circuits 602, 604, comparator circuits 606, Schmitt trigger circuits 608, and transistors 610, 612, which may (or may not) be arranged as shown. Max-pooling neuron 700 may include additional components that are not depicted.

[0057] The use of passive components reduces design complexity and reduces power consumption. In addition, the circuit design allows for dynamic switching of neurons because there is no integration period or set update period, preventing information loss. Specifically, the dynamic switching of neurons can be controlled by the filter time constant (τ c ), the gain (G) of the comparator circuit 606 and the trigger level (β) of the Schmitt trigger circuit 608 are controlled.

[0058] The integrator circuits 602, 604 are implemented as low-pass filter circuits in the max-pooling neuron 700. In an embodiment, the first integrator circuit 602 is composed of a resistor (R f ) and capacitor (C f ) are formed, and the capacitors are arranged as parallel capacitors. Similarly, the second integrator circuit 604 is composed of a resistor (R f ) and capacitor (C f ) is formed. By appropriately selecting the resistors (R f ) and capacitor (C f ) value, you can set the cutoff frequency of the low-pass filter circuit.

[0059] In an embodiment, the low pass filter circuit is set to have a low cutoff frequency to integrate the incoming spike train. The first integrator circuit 602 provides a first voltage (V af ), and the second integrator circuit 604 provides a second voltage (V bf ).

[0060] The comparator circuit 606 is implemented as an operational amplifier having a non-inverting input (+) and an inverting input (-), the non-inverting input (+) being coupled to a first voltage (V af ), and the inverting input (-) is coupled to a second voltage (V bf ). The op amp compares the two filtered peak string currents with the gain applied to increase the output voltage.

[0061] In an embodiment, the comparator circuit 606 includes a first resistor (R1) arranged between the inverting input (-) and the output of the second integrator circuit 604, a second resistor (R2) arranged between the non-inverting input (+) and the output of the first integrator circuit 602, and a first resistor (R3) arranged between the output (V c) and the inverting input (-), and a fourth resistor (R4) arranged between the non-inverting input (+) and the reference ground. By appropriately selecting the resistance values ​​of the first resistor (R1), the second resistor (R2), the third resistor (R3) and the fourth resistor (R4), the gain of the operational amplifier can be set.

[0062] The Schmitt trigger circuit 608 is implemented as an operational amplifier having an output (V c ) is connected to the inverting input (-) of the operational amplifier (V s ) and the non-inverting input (+) of the Schmitt trigger circuit 608op-amp. The sixth resistor (R6) is coupled between the reference ground and the non-inverting input (+) of the Schmitt trigger circuit 608op-amp. By appropriately selecting the resistance values ​​of the fifth resistor (R5) and the sixth resistor (R6), the trigger level (β) of the Schmitt trigger circuit 608 can be set.

[0063] The AVAM max pooling neuron includes two LIF neurons, six synaptic connections, and two filters. Each AVAM max pooling neuron requires at least three transistors, although some may require up to 21. For each synapse of the AVAM max pooling neuron, at least two transistors may be required, and possibly up to 12. Therefore, the AVAM max pooling neuron includes at least eighteen transistors, six capacitors, four resistors, and a pnpn diode. However, implementing the AVAM max pooling neuron may require more resources.

[0064] In contrast, the max pooling neuron 600 can be implemented using ten transistors, eight resistors, and two capacitors. Although the max pooling neuron 600 uses fewer transistors and capacitors, it may require more resistors, which may be expensive. However, in other embodiments, alternative configurations of the max pooling neuron 600 with fewer resistors are contemplated.

[0065] Figure 8A schematic diagram of an embodiment max pooling neuron 800 is illustrated, which can be implemented as a neuron in the max pooling layer 506 of the spiking neural network 500. In contrast to the analog circuit max pooling neuron 700, the max pooling neuron 800 is implemented as a digital circuit. The max pooling neuron 800 includes inverters 802, 808, counters 804, 810, registers 806, 812 and 816, a subtraction circuit 814, a sign circuit 818, and a digital circuit 820, which may (or may not) be arranged as shown. The max pooling neuron 800 may include additional components that are not depicted.

[0066] The input spike signal 614 from the first neuron is inverted by the inverter 802 and received at the first counter 804. The input spike signal 616 from the second neuron is inverted by the inverter 808 and received at the second counter 810. The counters 804, 810 continuously count the clock (CLK) from the clock signal coupled to the node 828 between the respective peaks of the input spike signals 614, 616.

[0067] In response to a spike occurring in the input spike signal 614, the value of the first counter 804 is stored in the first register (Reg A )806. However, if no spike occurs and the number of clocks counted by the first counter 804 is greater than the number of clocks currently stored in the first register (Reg A )806, the number of clocks and the value currently stored in the first register (Reg A )806 to update the first register (Reg A )806. Otherwise, the first register (Reg A ) 806 is not updated (if no spike occurs and the number of clocks counted by the first counter 804 is less than or equal to the number currently stored in the first register (Reg A )The value in 806).

[0068] In an embodiment, the occurrence of a spike may cause the corresponding counter to be reset, for example to zero. In an embodiment, the current value of the corresponding counter is stored before it is reset.

[0069] In response to a spike occurring in the input spike signal 616, the value of the second counter 810 is stored in the second register (Reg B )812. However, if no spike occurs and the number of clocks counted by the second counter 810 is greater than the number of clocks currently stored in the second register (Reg B )812, the number of clocks and the value currently stored in the second register (Reg B)812 to update the second register (Reg B )812. Otherwise, the second register (Reg B ) 812 is not updated (if no spike occurs and the number of clocks counted by the second counter 810 is less than or equal to the number currently stored in the second register (Reg B )The value in 812).

[0070] The subtraction circuit 814 receives the data stored in the first register (Reg A )806, and stores it in the second register (Reg B )812 as a differential signal. The differential signal is stored in a third register 816. A sign circuit 818 receives the differential signal from the third register 816 and provides a high state output if the value stored in the third register 816 is positive; otherwise, the sign circuit 818 provides a low state output (i.e., when the value stored in the third register 816 is negative).

[0071] The digital circuit 820 is arranged between the sign circuit 818 and the output node 822 of the max pooling neuron 800. The digital circuit 820 includes a first AND gate having a first input coupled to the input spike signal 614 and a second input coupled to the output of the sign circuit 818. In addition, the digital circuit 820 includes a second AND gate having a first input coupled to the input spike signal 616 and a second input coupled to the inverted output of the sign circuit 818 through an inverter gate.

[0072] Fig. 9 Illustrated is a signal 900 of an embodiment sequence of operations of a max pooling neuron as implemented in a max pooling layer of a spiking neural network. Signal 900 includes an input spike signal 902 from a first neuron in a previous layer, an input spike signal 904 from a second neuron in a previous layer, a Schmitt trigger mode signal 906, an output signal 908, a comparator signal 910, a first integrator signal 912, and a second integrator signal 914.

[0073] In an embodiment, the input spike signal 902 corresponds to, for example, the input spike signal 614. In an embodiment, the input spike signal 904 corresponds to, for example, the input spike signal 616. In an embodiment, the first integrator signal 912 corresponds to, for example, the output of the first integrator circuit 602. In an embodiment, the second integrator signal 914 corresponds to, for example, the output of the second integrator circuit 604. In an embodiment, the comparator signal 910 corresponds to, for example, the output of the comparator circuit 606. In an embodiment, the Schmitt trigger mode signal 906 corresponds to the output of the Schmitt trigger circuit 608 and is fed to the transistors 610, 612. In an embodiment, the output signal 908 corresponds to the output node 618, which is fed to the next neuron.

[0074] From the beginning until the halfway point, the input spike signal 902 has a higher firing rate than the input spike signal 904. From the halfway point until the end, the input spike signal 904 has a higher firing rate than the input spike signal 902. As shown, the input spike signal 902 transitions from a high frequency (e.g., 436 Hz) to a low frequency (e.g., 110 Hz) spike at the halfway point of the timing step (x-axis). The first integrator signal 912 represents the input spike signal 902. Conversely, the input spike signal 904 transitions from a low frequency (e.g., 74 Hz) to a high frequency (e.g., 475 Hz) spike at the same halfway point of the timing step. The second integrator signal 914 represents the input spike signal 904.

[0075] At approximately the halfway point (with an additional delay), when the comparator signal 910 transitions from a lower voltage to a higher voltage, the Schmitt trigger mode signal 906 transitions from high (eg, '1') to low (eg, '-1').

[0076] The output signal 908 corresponds to the input spike signal 902 from the first neuron until the halfway point (e.g., at a frequency of 420 Hz). After a slight delay, the output signal 908 corresponds to the input spike signal 904 from the second neuron (e.g., at a frequency of 440 Hz).

[0077] Thus, the spike train of the maximally fired neuron (from the previous layer) is passed through almost unaffected. Errors may occur due to the slew rate of the filtered input, which causes a delay in the input change, corresponding to the voltage drop across the transistor in a hardware implementation. The delay in switching can be reduced by setting the filter time constant (τ) of the integrator circuits 602, 604. c ), the trigger level (β) of the Schmitt trigger circuit 608, or a combination thereof. However, the reduction of the delay may cause input instability.

[0078] Fig.10Illustrated is a signal 1000 of an embodiment sequence of operations of a max pooling neuron implemented in a max pooling layer of a spiking neural network. Signal 1000 includes an input spike signal 1002 from a first neuron in a previous layer, an input spike signal 1004 from a second neuron in a previous layer, a Schmitt trigger mode signal 1006, an output signal 1008, a comparator signal 1010, a first integrator signal 1012, and a second integrator signal 1014.

[0079] In an embodiment, the input spike signal 1002 corresponds to, for example, the input spike signal 614. In an embodiment, the input spike signal 1004 corresponds to, for example, the input spike signal 616. In an embodiment, the first integrator signal 1012 corresponds to, for example, the output of the first integrator circuit 602. In an embodiment, the second integrator signal 1014 corresponds to, for example, the output of the second integrator circuit 604. In an embodiment, the comparator signal 1010 corresponds to, for example, the output of the comparator circuit 606. In an embodiment, the Schmitt trigger mode signal 1006 corresponds to the output of the Schmitt trigger circuit 608 and is fed to transistors 610, 612. In an embodiment, the output signal 1008 corresponds to the output node 618 and is fed to the next neuron.

[0080] The input spike signal 1004 has a higher firing rate across the timing step than the input spike signal 1002. As shown, the input spike signal 1002 maintains approximately the same low frequency spike across the timing step (e.g., 260 Hz from the beginning to the middle and 235 Hz from the middle to the end). The first integrator signal 1012 represents the input spike signal 1002. In contrast, the input spike signal 1004 transitions from a low frequency (although having a higher frequency than the frequency of the input spike signal 1002) (e.g., 320 Hz) to a higher frequency (e.g., 645 Hz) at the midpoint of the timing step. The second integrator signal 1014 represents the input spike signal 1004.

[0081] From the beginning to the end of the timing step, the Schmitt trigger mode signal 1006 remains low (e.g., '-1') even though the comparator signal transitions from a lower voltage to a higher voltage. As shown, the output of the comparator signal 1010 increases in magnitude, but does not increase in polarity (e.g., from negative to positive, or vice versa). This is because the spike train of the second neuron remains the maximum excitation neuron throughout the cycle. Therefore, the spike corresponding to the second neuron is propagated to the next stage.

[0082] Thus, the spike train of the maximally firing neuron (from the previous layer) (in this case, the second neuron) across the time steps (e.g., 320 Hz from start to halfway and 630 Hz from halfway to end) is provided as output signal 1008. In this example, apart from a brief delay at the beginning of the initial integration period, no spikes are lost due to the transition - the frequency remains unchanged.

[0083] Fig.11 Illustrated is a signal 1100 of an embodiment sequence of operations of a max pooling neuron implemented in a max pooling layer of a spiking neural network. The signal 1100 includes an input spike signal 1102 from a first neuron in a previous layer, an input spike signal 1104 from a second neuron in a previous layer, a Schmitt trigger mode signal 1106, an output signal 1108, a comparator signal 1110, a first integrator signal 1112, and a second integrator signal 1114.

[0084] In an embodiment, the input spike signal 1102 corresponds to, for example, the input spike signal 614. In an embodiment, the input spike signal 1104 corresponds to, for example, the input spike signal 616. In an embodiment, the first integrator signal 1112 corresponds to, for example, the output of the first integrator circuit 602. In an embodiment, the second integrator signal 1114 corresponds to, for example, the output of the second integrator circuit 604. In an embodiment, the comparator signal 1110 corresponds to, for example, the output of the comparator circuit 606. In an embodiment, the Schmitt trigger mode signal 1106 corresponds to the output of the Schmitt trigger circuit 608 and is fed to transistors 610, 612. In an embodiment, the output signal 1108 corresponds to the output node 618 and is fed to the next neuron.

[0085] From the midpoint until the end point, the input spike signal 1102 has a higher firing rate than the input spike signal 1104. From the beginning until the midpoint, the input spike signal 1104 has a higher firing rate than the input spike signal 1102. As shown, the input spike signal 1102 transitions from a low frequency (e.g., 174 Hz) to a high frequency (e.g., 808 Hz) spike at the midpoint of the timing step (x-axis). The first integrator signal 1112 represents the input spike signal 1102. In contrast, the input spike signal 1104 maintains approximately the same low frequency spike (e.g., 400 Hz) across the timing step. The second integrator signal 1114 represents the input spike signal 1104.

[0086] At approximately the halfway point (with an additional delay), when the comparator signal transitions from a higher voltage to a lower voltage, the Schmitt trigger mode signal 1106 transitions from low (eg, '-1') to high (eg, '1').

[0087] The output signal 1108 corresponds to the input spike signal 1104 from the second neuron until the halfway point (e.g., at a frequency of 390 Hz). After a slight delay, the output signal 1108 corresponds to the input spike signal 1102 from the first neuron (e.g., at a frequency of 780 Hz).

[0088] Thus, the spike train of the maximally fired neuron (from the previous layer) is passed on almost unaffected. Errors may occur due to the slew rate of the filtered input, which causes a delay in the change of the input, corresponding to the voltage drop across the transistor in a hardware implementation. The delay in switching can be adjusted by changing the cutoff frequency of the integrator circuits 602, 604 and the trigger point of the Schmitt trigger circuit 608.

[0089] Fig.12 Illustrated is a signal 1200 of an embodiment sequence of operations of a max pooling neuron implemented in a max pooling layer of a spiking neural network. The signal 1200 includes an input spike signal 1202 from a first neuron in a previous layer, an input spike signal 1204 from a second neuron in a previous layer, a Schmitt trigger mode signal 1206, an output signal 1208, a comparator signal 1210, a first integrator signal 1212, and a second integrator signal 1214.

[0090] In an embodiment, the input spike signal 1202 corresponds to, for example, the input spike signal 614. In an embodiment, the input spike signal 1204 corresponds to, for example, the input spike signal 616. In an embodiment, the first integrator signal 1212 corresponds to, for example, the output of the first integrator circuit 602. In an embodiment, the second integrator signal 1214 corresponds to, for example, the output of the second integrator circuit 604. In an embodiment, the comparator signal 1210 corresponds to, for example, the output of the comparator circuit 606. In an embodiment, the Schmitt trigger mode signal 1206 corresponds to the output of the Schmitt trigger circuit 608 and is fed to transistors 610, 612. In an embodiment, the output signal 1208 corresponds to the output node 618 and is fed to the next neuron.

[0091] The input spike signal 1202 has approximately the same firing rate as the input spike signal 1204. As shown, the input spike signal 1202 maintains approximately the same frequency spike (e.g., 400 Hz) across the timing steps. The first integrator signal 1212 represents the input spike signal 1202. Likewise, the input spike signal 1204 maintains approximately the same frequency as the input spike signal 1202 (e.g., 390 Hz from the beginning to the middle and 410 Hz from the middle to the end). The second integrator signal 1214 represents the input spike signal 1204.

[0092] Based on the output of the comparator signal 1210, the Schmitt trigger mode signal 1106 transitions between low (e.g., '-1') to high (e.g., '1') - some rapid switching between states can occur. When the Schmitt trigger mode signal 1106 transitions between the low signal and the high signal, the max pooling neuron 600 avoids double counting of spikes due to the similar spike rates of the input spike signals 1202, 1204, which is a problem in previous solutions.

[0093] Output signal 1208 corresponds to either input spike signal 1202 or input spike signal 1204, but there is no double counting of spikes at output signal 1208. Fast switching between states can be addressed by increasing the trigger level (β) of Schmitt trigger circuit 608, for example.

[0094] Embodiments of the present disclosure improve power efficiency, reduce information loss, allow dynamic switching, and provide greater freedom in architecture design.

[0095] The first aspect relates to a maximum pooling neuron. The maximum pooling neuron includes a first integrator circuit, a second integrator circuit, a comparator circuit, a Schmitt trigger circuit, and a pair of switches. The first integrator circuit is configured to filter a first input string from a first neuron of a previous layer and generate a first filtered input string. The second integrator circuit is configured to filter a second input string from a second neuron of a previous layer and generate a second filtered input string. The comparator circuit is configured to amplify the difference between the first filtered input string and the second filtered input string and generate an amplified differential signal. The Schmitt trigger circuit is configured to generate a binary output signal at an output terminal of the Schmitt trigger circuit based on the amplified differential signal. The paired switches include a first switch and a second switch. The paired switches have a common first terminal and a common control terminal, the common first terminal is coupled to the output node of the maximum pooling neuron, and the common control terminal is coupled to the output terminal of the Schmitt trigger circuit. The second terminal of the first switch is coupled to the first input string. The second terminal of the second switch is coupled to the second input string.

[0096] In a first implementation form of the max-pooling neuron according to the first aspect, the output node of the max-pooling neuron is coupled to the first input string in response to the spike rate of the first input string being greater than the spike rate of the second input string. The output node of the max-pooling neuron is coupled to the second input string in response to the spike rate of the second input string being greater than the spike rate of the first input string.

[0097] In the second implementation form of the maximum pooling neuron according to the first aspect or in any of the preceding implementation forms of the first aspect, the first integrator circuit and the second integrator circuit are low pass filter circuits. The cutoff frequency of the low pass filter circuit can be configured to integrate the first input string and the second input string.

[0098] In a third implementation form of the max pooling neuron according to the first aspect or in any preceding implementation form of the first aspect, the comparator circuit comprises a differential amplifier configured to provide an amplified differential signal.

[0099] In a fourth implementation form of the maximum pooling neuron according to the first aspect or in any of the preceding implementation forms of the first aspect, the Schmitt trigger circuit comprises a differential amplifier. The differential amplifier is configured to generate a first binary output signal in response to the amplified differential signal being greater than an upper threshold, and to generate a second binary output signal in response to the amplified differential signal being less than a lower threshold. The second binary output signal is different from the first binary output signal.

[0100] In the fifth implementation form of the max-pooling neuron according to the first aspect or in any of the preceding implementation forms of the first aspect, a trigger level of the Schmitt trigger circuit is adjustable to set an upper threshold and a lower threshold.

[0101] In a sixth implementation form of the maximum pooling neuron according to the first aspect or in any of the preceding implementation forms of the first aspect, the first switch is a p-type metal oxide semiconductor field effect transistor (MOSFET), the second switch is an n-type MOSFET, and the first switch and the second switch are arranged as complementary MOSFETs (CMOS).

[0102] A second aspect relates to a maximum pooling layer with a maximum pooling neuron. The maximum pooling neuron includes a first integrator circuit, a second integrator circuit, a comparator circuit, a Schmitt trigger circuit, and a pair of switches. The first integrator circuit is configured to filter a first input string from a first neuron of a previous layer and generate a first filtered input string. The second integrator circuit is configured to filter a second input string from a second neuron of a previous layer and generate a second filtered input string. The comparator circuit is configured to amplify the difference between the first filtered input string and the second filtered input string and generate an amplified differential signal. The Schmitt trigger circuit is configured to generate a binary output signal at an output terminal of the Schmitt trigger circuit based on the amplified differential signal. The paired switches include a first switch and a second switch. The paired switches have a common first terminal and a common control terminal, the common first terminal is coupled to the output node of the maximum pooling neuron, and the common control terminal is coupled to the output terminal of the Schmitt trigger circuit. The second terminal of the first switch is coupled to the first input string. The second terminal of the second switch is coupled to the second input string.

[0103] In a first implementation form of the max pooling layer according to the second aspect, the output node of the max pooling neuron is coupled to the first input string in response to the spike rate of the first input string being greater than the spike rate of the second input string. The output node of the max pooling neuron is coupled to the second input string in response to the spike rate of the second input string being greater than the spike rate of the first input string.

[0104] In the second implementation form of the maximum pooling layer according to the second aspect or in any of the preceding implementation forms of the second aspect, the first integrator circuit and the second integrator circuit are low pass filter circuits. The cutoff frequency of the low pass filter circuit can be configured to integrate the first input string and the second input string.

[0105] In a third implementation form of the max pooling layer according to the second aspect or in any preceding implementation form of the second aspect, the comparator circuit comprises a differential amplifier configured to provide an amplified differential signal.

[0106] In the fourth implementation form of the maximum pooling layer according to the second aspect or in any of the foregoing implementation forms of the second aspect, the Schmitt trigger circuit includes a differential amplifier. The differential amplifier is configured to generate a first binary output signal in response to the amplified differential signal being greater than an upper threshold, and to generate a second binary output signal in response to the amplified differential signal being less than a lower threshold. The second binary output signal is different from the first binary output signal.

[0107] In the fifth implementation form of the maximum pooling layer according to the second aspect or in any of the preceding implementation forms of the second aspect, a trigger level of the Schmitt trigger circuit is adjustable to set an upper threshold and a lower threshold.

[0108] In a sixth embodiment of the maximum pooling layer according to the second aspect or in any of the preceding embodiments of the second aspect, the first switch is a p-type metal oxide semiconductor field effect transistor (MOSFET), the second switch is an n-type MOSFET, and the first switch and the second switch are arranged as complementary MOSFETs (CMOS).

[0109] A third aspect relates to a neural network. The neural network includes a first layer and a maximum pooling layer. The first layer includes a first neuron and a second neuron. The first neuron is configured to provide a first input string. The second neuron is configured to provide a second input string. The maximum pooling layer includes a maximum pooling neuron. The maximum pooling neuron includes a first integrator circuit, a second integrator circuit, a comparator circuit, a Schmitt trigger circuit, and a pair of switches. The first integrator circuit is configured to filter a first input string from a first neuron of a previous layer and generate a first filtered input string. The second integrator circuit is configured to filter a second input string from a second neuron of a previous layer and generate a second filtered input string. The comparator circuit is configured to amplify the difference between the first filtered input string and the second filtered input string and generate an amplified differential signal. The Schmitt trigger circuit is configured to generate a binary output signal at an output terminal of the Schmitt trigger circuit based on the amplified differential signal. The paired switches include a first switch and a second switch. The paired switches have a common first terminal and a common control terminal, the common first terminal is coupled to the output node of the maximum pooling neuron, and the common control terminal is coupled to the output terminal of the Schmitt trigger circuit. The second terminal of the first switch is coupled to the first input string. The second terminal of the second switch is coupled to the second input string.

[0110] In a first implementation form of the neural network according to the third aspect, the first layer is a convolutional layer.

[0111] In the second implementation form of the neural network according to the third aspect or in any preceding implementation form of the third aspect, the neural network is a spiking neural network (SNN).

[0112] In a third implementation form of the neural network according to the third aspect or in any of the preceding implementation forms of the third aspect, the first integrator circuit and the second integrator circuit are low pass filter circuits. The cutoff frequency of the low pass filter circuit can be configured to integrate the first input string and the second input string. The comparator circuit includes a differential amplifier configured to provide an amplified differential signal.

[0113] In a fourth implementation form of the neural network according to the third aspect or in any of the preceding implementation forms of the third aspect, the Schmitt trigger circuit comprises a differential amplifier. The differential amplifier is configured to generate a first binary output signal in response to the amplified differential signal being greater than an upper threshold, and to generate a second binary output signal in response to the amplified differential signal being less than a lower threshold. The second binary output signal is different from the first binary output signal. The trigger level of the Schmitt trigger circuit is adjustable to set the upper threshold and the lower threshold.

[0114] In a fifth implementation form of the neural network according to the third aspect or in any of the preceding implementation forms of the third aspect, the first switch is a p-type metal oxide semiconductor field effect transistor (MOSFET), the second switch is an n-type MOSFET, and the first switch and the second switch are arranged as complementary MOSFETs (CMOS).

[0115] Although the specification has been described in detail, it should be understood that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. In different figures, the same elements are represented by the same reference numerals. In addition, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, because it will be readily understood by those of ordinary skill in the art from the present disclosure that existing or later developed processes, machines, manufactures, material compositions, equipment, methods or steps can perform substantially the same functions as the corresponding embodiments described herein or achieve substantially the same results as them. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, equipment, methods or steps within their scope.

[0116] Accordingly, the specification and drawings should be regarded only as illustrative of the present disclosure as defined by the appended claims, and any and all modifications, variations, combinations or equivalents within the scope of the present disclosure should be covered.

Claims

1. A maximum pooling neuron, comprising: a first integrator circuit configured to filter a first input string from a first neuron of a previous layer and generate a first filtered input string; a second integrator circuit configured to filter a second input string from a second neuron of the previous layer and generate a second filtered input string; a comparator circuit configured to amplify a difference between the first filtered input string and the second filtered input string and generate an amplified differential signal; a Schmitt trigger circuit configured to generate a binary output signal at an output terminal of the Schmitt trigger circuit based on the amplified differential signal; as well as A pair of switches, the pair of switches comprising a first switch and a second switch, the pair of switches having a common first terminal, the common first terminal being coupled to the output node of the maximum pooling neuron, the pair of switches having a common control terminal, the common control terminal being coupled to the output terminal of the Schmitt trigger circuit, the second terminal of the first switch being coupled to the first input string, and the second terminal of the second switch being coupled to the second input string.

2. The maximum pooling neuron of claim 1 , wherein the output node of the maximum pooling neuron is coupled to the first input string in response to a spike rate of the first input string being greater than a spike rate of the second input string, and wherein the output node of the maximum pooling neuron is coupled to the second input string in response to a spike rate of the second input string being greater than a spike rate of the first input string.

3. The maximum pooling neuron of claim 1 , wherein the first integrator circuit and the second integrator circuit are low-pass filter circuits, and wherein a cutoff frequency of the low-pass filter circuit is configurable to integrate the first input string and the second input string.

4. The maximum pooling neuron of claim 1 , wherein the comparator circuit comprises a differential amplifier configured to provide an amplified differential signal.

5. The maximum pooling neuron of claim 1 , wherein the Schmitt trigger circuit comprises a differential amplifier configured to: In response to the amplified differential signal being greater than an upper threshold, generating a first binary output signal; and In response to the amplified differential signal being less than a lower threshold, a second binary output signal is generated, the second binary output signal being different from the first binary output signal.

6. The maximum pooling neuron according to claim 5, wherein a trigger level of the Schmitt trigger circuit is adjustable to set the upper threshold and the lower threshold.

7. The maximum pooling neuron of claim 1, wherein the first switch is a p-type metal oxide semiconductor field effect transistor (MOSFET), wherein the second switch is an n-type MOSFET, and wherein the first switch and the second switch are arranged as complementary MOSFET CMOS.

8. A maximum pooling layer, comprising a maximum pooling neuron, wherein the maximum pooling layer comprises: a first integrator circuit configured to filter a first input string from a first neuron of a previous layer and generate a first filtered input string; a second integrator circuit configured to filter a second input string from a second neuron of the previous layer and generate a second filtered input string; a comparator circuit configured to amplify a difference between the first filtered input string and the second filtered input string and generate an amplified differential signal; a Schmitt trigger circuit configured to generate a binary output signal based on the amplified differential signal; as well as A pair of switches, including a first switch and a second switch, the pair of switches having a common first terminal, the common first terminal being coupled to the output node of the maximum pooling neuron, the pair of switches having a common control terminal, the common control terminal being configured to receive the binary output signal of the Schmitt trigger circuit, the second terminal of the first switch being coupled to the first input string, and the second terminal of the second switch being coupled to the second input string.

9. The maximum pooling layer of claim 8, wherein the output node of the maximum pooling neuron is coupled to the first input string in response to a spike rate of the first input string being greater than a spike rate of the second input string, and wherein the output node of the maximum pooling neuron is coupled to the second input string in response to a spike rate of the second input string being greater than a spike rate of the first input string.

10. The maximum pooling layer of claim 8, wherein the first integrator circuit and the second integrator circuit are low-pass filter circuits, and wherein a cutoff frequency of the low-pass filter circuit is configurable to integrate the first input string and the second input string.

11. The maximum pooling layer of claim 8, wherein the comparator circuit comprises a differential amplifier configured to provide an amplified differential signal.

12. The maximum pooling layer of claim 8, wherein the Schmitt trigger circuit comprises a differential amplifier, wherein the differential amplifier is configured to: In response to the amplified differential signal being greater than an upper threshold, generating a first binary output signal; and In response to the amplified differential signal being less than a lower threshold, a second binary output signal is generated, the second binary output signal being different from the first binary output signal.

13. The maximum pooling layer according to claim 12, wherein a trigger level of the Schmitt trigger circuit is adjustable to set the upper threshold and the lower threshold.

14. The maximum pooling layer of claim 8, wherein the first switch is a p-type metal oxide semiconductor field effect transistor (MOSFET), wherein the second switch is an n-type MOSFET, and wherein the first switch and the second switch are arranged as complementary MOSFET CMOS.

15. A neural network comprising: a first layer, the first layer having a first neuron and a second neuron, the first neuron being configured to provide a first input string, the second neuron being configured to provide a second input string; as well as A maximum pooling layer, wherein the maximum pooling layer has a maximum pooling neuron, and the maximum pooling neuron includes: a first integrator circuit configured to filter the first input string and generate a first filtered input string, a second integrator circuit configured to filter the second input string and generate a second filtered input string, a comparator circuit configured to amplify a difference between the first filtered input string and the second filtered input string and generate an amplified differential signal, a Schmitt trigger circuit configured to generate a binary output signal based on the amplified differential signal, and A pair of switches, including a first switch and a second switch, the pair of switches having a common first terminal, the common first terminal being coupled to the output node of the maximum pooling neuron, the pair of switches having a common control terminal, the common control terminal being configured to receive the binary output signal of the Schmitt trigger circuit, the second terminal of the first switch being coupled to the first input string, and the second terminal of the second switch being coupled to the second input string.

16. The neural network of claim 15, wherein the first layer is a convolutional layer.

17. The neural network of claim 15, wherein the neural network is a spiking neural network (SNN).

18. The neural network of claim 15, wherein the first integrator circuit and the second integrator circuit are low pass filter circuits, wherein a cutoff frequency of the low pass filter circuit is configurable to integrate the first input string and the second input string, and wherein the comparator circuit comprises a differential amplifier configured to provide an amplified differential signal.

19. The neural network of claim 15, wherein the Schmitt trigger circuit comprises a differential amplifier configured to: In response to the amplified differential signal being greater than an upper threshold, generating a first binary output signal; and In response to the amplified differential signal being less than a lower threshold, a second binary output signal is generated, the second binary output signal being different from the first binary output signal, wherein a trigger level of the Schmitt trigger circuit is adjustable to set the upper threshold and the lower threshold.

20. The neural network of claim 15, wherein the first switch is a p-type metal oxide semiconductor field effect transistor (MOSFET), wherein the second switch is an n-type MOSFET, and wherein the first switch and the second switch are arranged as complementary MOSFETs (CMOS).

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