Quantum chip control method, quantum control system and quantum computer

Abstract

The invention discloses a quantum chip control method, a quantum control system and a quantum computer, and the method comprises the steps: constructing a three-dimensional analysis model which comprises the coupling relation between same-class elements and the coupling relation between different-class elements on a quantum chip; and then adjusting the working point of the quantum bit in the to-be-measured sub-chip based on the three-dimensional analysis model. According to the scheme provided by the invention, the three-dimensional analysis model for analyzing and reading the coupling relationship among the bus layer, the resonant cavity layer and the quantum bit layer is constructed, and the overall structure of the chip and the environment are considered, so that the requirements of a large-scale quantum chip can be met, and the blank in the prior art is filled.

Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, and in particular to a quantum chip control method, a quantum control system and a quantum computer. Background Art

[0002] Quantum computing and quantum information are interdisciplinary subjects that use the principles of quantum mechanics to achieve computing and information processing tasks. They are closely related to quantum physics, computer science, informatics and other disciplines. They have developed rapidly in the past two decades. Quantum algorithms based on quantum computers in scenarios such as factorization and unstructured search have shown performance far beyond that of existing algorithms based on classical computers, and this direction has been expected to exceed existing computing capabilities. Since quantum computing has the potential to far exceed the performance of classical computers in solving specific problems, in order to realize quantum computers, it is necessary to obtain a quantum chip that contains a sufficient number and quality of quantum bits, and can perform quantum logic gate operations and read quantum bits with extremely high fidelity. Quantum chips are to quantum computers what CPUs are to traditional computers. Quantum chips are the core components of quantum computers, and quantum chips are processors that perform quantum computing. Before each quantum chip is officially put into use, it is necessary to test and characterize the various parameters of the quantum bits in the quantum chip.

[0003] For each qubit in a quantum chip, in order to complete as many calculations as possible within the limited life of the qubit, it is necessary to implement the fastest qubit logic gates possible. Generally speaking, the execution completion time of a qubit logic gate is generally three to four orders of magnitude faster than the qubit lifetime. However, fast qubit logic gate operations may cause errors in the execution of qubit logic gates. There are many reasons for qubit logic gate errors, such as parasitic coupling between nearest neighbor and next nearest neighbor qubits, spectrum diffusion two-level system (TLS) defects, parasitic microwave modes, coupling with control lines and readout resonators, frequency control electronic device noise, frequency control pulse distortion, microwave control pulse distortion, and microwave carrier leakage. When each qubit in a quantum chip is at a suitable operating point, the above interference effects can be effectively reduced. At present, in order to improve the accuracy of quantum chips in performing quantum computing tasks, the working point problem of a few quantum bits is generally considered, and there is a lack of solutions that consider the quantum chip as a whole. The existing solutions are feasible when the number of quantum bits in the quantum chip is small, such as only a few quantum bits or a dozen quantum bits. However, in the foreseeable future, the number of quantum chips will inevitably increase significantly, and by then, the existing solutions will not be able to meet the needs of large-scale quantum chips.

[0004] Therefore, it is necessary to propose a solution that can consider the adjustment of the quantum bit working point from the perspective of the quantum chip as a whole.

[0005] It should be noted that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0006] The purpose of the present invention is to provide a quantum chip control method, a quantum control system and a quantum computer, which are used to solve the problem that the solutions in the prior art cannot meet the needs of large-scale quantum chips.

[0007] In order to solve the above technical problems, the present invention proposes a control method for a quantum chip, comprising:

[0008] Constructing a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on a quantum chip, wherein the components include all read buses of the sub-chip to be measured, all resonant cavities of the sub-chip to be measured, and all quantum bits of the sub-chip to be measured;

[0009] The operating point of the quantum bit in the sub-chip to be measured is adjusted based on the three-dimensional analysis model.

[0010] Optionally, the constructing of a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on a quantum chip includes:

[0011] A first coupling relationship between read busses is acquired, where the first coupling relationship includes a coupling relationship between adjacent read busses.

[0012] Optionally, the first coupling relationship is obtained by the following formula:

[0013]

[0014] Among them, b1 and b2 are two adjacent read buses, ω b1 is the frequency of the signal read on b1, ω b2 is the frequency of the signal read on b2, C bus is the parasitic capacitance between b1 and b2, v1 is the speed of light in b1, v2 is the speed of light in b2, c1 is the capacitance per unit length of the transmission line of b1, c2 is the capacitance per unit length of the transmission line of b2, λ(ω b1 ,ω b2 ) is the coupling strength between b1 and b2.

[0015] Optionally, the constructing of a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on the quantum chip further includes:

[0016] A second coupling relationship between the read bus and the resonant cavity is acquired, wherein the second coupling relationship includes a coupling relationship between the read bus and an adjacent resonant cavity.

[0017] Optionally, the second coupling relationship is obtained by the following formula:

[0018]

[0019] Among them, C bus-reson is the parasitic capacitance between the reading bus and the resonant cavity, c is the capacitance per unit length of the reading bus transmission line, Cr is the capacitance of the resonant cavity, ω r is the frequency of the signal in the resonant cavity, ω is the frequency of the signal on the read bus, v is the speed of light in the read bus, and λ(ω) is the coupling strength between the read bus and an adjacent resonant cavity.

[0020] Optionally, the constructing of a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on the quantum chip further includes:

[0021] A third coupling relationship between the resonant cavities is obtained, where the third coupling relationship includes a coupling relationship between two adjacent or sub-adjacent resonant cavities, where sub-adjacent means that the two resonant cavities are in a diagonal relationship in the physical structure of the sub-chip to be measured.

[0022] Optionally, the third coupler relationship is obtained by the following formula:

[0023]

[0024] Among them, r1 and r2 are two adjacent or sub-adjacent resonant cavities, ω r1 ,ω r2 is the frequency of the two resonant cavities, Cr1 and Cr2 are the capacitances of the two resonant cavities, and C reson is the parasitic capacitance between the two resonant cavities, J ωr1，ωr2 is the coupling strength between the two resonant cavities.

[0025] Optionally, the constructing of a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on the quantum chip further includes:

[0026] A fourth coupling relationship between the resonant cavity and the quantum bit is obtained, wherein the fourth coupling relationship includes a coupling relationship between the resonant cavity and the corresponding first quantum bit, and a coupling relationship between the resonant cavity and the second quantum bit, wherein the resonant cavity is used to read information carried by the first quantum bit, and the second quantum bit is another quantum bit that is in a neighboring relationship with the first quantum bit.

[0027] Optionally, the fourth coupling relationship is obtained by the following formula:

[0028]

[0029] Among them, ω r is the frequency of the resonant cavity, ω q / c is the frequency of the first qubit or the second qubit, C reson-qc is the coupling capacitance between the resonant cavity and the first qubit or the second qubit, C r is the capacitance of the resonator, C q / c is the capacitance of the first qubit or the second qubit, J ωr，ωq / c is the coupling strength between the resonant cavity and the first quantum bit or the second quantum bit.

[0030] Optionally, the constructing of a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on the quantum chip further includes:

[0031] A fifth coupling relationship between quantum bits is obtained, wherein the fifth coupling relationship includes a coupling relationship between two adjacent quantum bits and a coupling relationship between two sub-adjacent quantum bits, wherein the two adjacent quantum bits are two quantum bits that have a direct coupling relationship in the sub-chip to be measured, and the two sub-adjacent quantum bits are two quantum bits that do not have a direct coupling relationship in the sub-chip to be measured.

[0032] Optionally, the fifth coupling relationship is obtained by the following formula:

[0033]

[0034] Among them, ω1 and ω2 are the frequencies of two adjacent qubits or two sub-adjacent qubits, C qc is the coupling capacitance between two adjacent qubits or two sub-adjacent qubits, C1 and C2 are the capacitances of two adjacent qubits or two sub-adjacent qubits, and J ω1，ω2 is the coupling strength between two adjacent qubits or two next-neighboring qubits.

[0035] Optionally, adjusting the working point of the quantum bit in the sub-chip to be measured based on the three-dimensional analysis model includes:

[0036] Constructing a constraint on the working point of a target quantum bit based on the three-dimensional analysis model, wherein the constraint is used to limit the target quantum bit from being affected by coupling with surrounding elements, and the target quantum bit is any quantum bit in the sub-chip to be measured;

[0037] The constraints are used to allocate the working point of each quantum bit in the sub-chip to be measured.

[0038] Based on the same inventive concept, the present invention also proposes a control device for a quantum chip, comprising:

[0039] A model building unit, used to build a three-dimensional analysis model including coupling relationships between elements of the same category and coupling relationships between elements of different categories on a quantum chip, wherein the elements include all read buses of the sub-chip to be measured, all resonant cavities of the sub-chip to be measured, and all quantum bits of the sub-chip to be measured;

[0040] A working point adjustment unit is used to adjust the working point of the quantum bit in the sub-chip to be measured based on the three-dimensional analysis model.

[0041] Based on the same inventive concept, the present invention also proposes a quantum control system, using the control method of the quantum chip described in any one of the above-mentioned feature descriptions, or a control device including the quantum chip described in the above-mentioned feature descriptions.

[0042] Based on the same inventive concept, the present invention also proposes a quantum computer, including the quantum control system described in the above feature description.

[0043] Based on the same inventive concept, the present invention also proposes a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it can implement the control method of the quantum chip described in any one of the above-mentioned feature descriptions.

[0044] Compared with the prior art, the present invention has the following beneficial effects:

[0045] The control method of the quantum chip proposed in the present invention constructs a three-dimensional analysis model including the coupling relationship between the same type of elements and the coupling relationship between different types of elements on the quantum chip, and then adjusts the working point of the quantum bit in the sub-chip to be measured based on the three-dimensional analysis model. The solution proposed in this application can meet the needs of large-scale quantum chips from the perspective of the overall structure and environment of the chip, and fills the gap in the prior art by constructing a three-dimensional analysis model to analyze the coupling relationship between the read bus layer, the resonant cavity layer, and the quantum bit layer.

[0046] The control device, quantum control system, quantum computer and readable storage medium of the quantum chip proposed in the present invention belong to the same inventive concept as the control method of the quantum chip, and therefore have the same beneficial effects, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A schematic diagram of a flow chart of a method for controlling a quantum chip according to an embodiment of the present invention;

[0048] Figure 2 A schematic diagram of the structure of a three-dimensional analysis model proposed in an embodiment of the present invention;

[0049] Figure 3 This is a simplified schematic diagram of the structure of a quantum chip control device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0050] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0051] In the description of the present invention, it is necessary to understand that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0052] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0053] Please refer to Figure 1 , an embodiment of the present invention provides a control method for a quantum chip, comprising:

[0054] S100: constructing a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on a quantum chip, wherein the components include all read buses of the sub-chip to be measured, all resonant cavities of the sub-chip to be measured, and all quantum bits of the sub-chip to be measured;

[0055] S200: Adjusting the operating point of the quantum bit in the quantum chip to be measured based on the three-dimensional analysis model.

[0056] The difference from the prior art is that the control method of the quantum chip proposed in the present invention constructs a three-dimensional analysis model including the coupling relationship between the same category elements and the coupling relationship between different categories of elements on the quantum chip, and then adjusts the working point of the quantum bit in the sub-chip to be measured based on the three-dimensional analysis model. The scheme proposed in this application, by constructing a three-dimensional analysis model to analyze the coupling relationship between the read bus layer, the resonant cavity layer, and the quantum bit layer, can meet the needs of large-scale quantum chips from the perspective of the overall structure and environment of the chip, and fills the gap in the prior art. It can be understood by those skilled in the art that in this embodiment, the working point of the quantum bit refers to the working frequency of the quantum bit.

[0057] In order to solve the problem of allocating the working points of qubits in quantum chips, there are currently solutions that consider two types of influencing factors: qubits and couplers. Simply put, the size of the mutual influence between qubits and qubits, and between qubits and couplers is used as a constraint to select and adjust the working points of qubits. However, the applicant found that there are many other factors that influence each other in the actual application of quantum chips, including but not limited to the influence between adjacent qubits, between resonant cavities and qubits, between adjacent resonant cavities, between resonant cavities and read buses, etc. Some mutual influences are what we expect to happen. For example, when two adjacent qubits are executing a two-qubit logic gate, we hope that the coupling strength between them is as large as possible to support the operation of the two-qubit logic gate. Some mutual influences are what we do not want to happen. For example, when a qubit is executing a single-qubit logic gate, we hope that the coupling strength of the surrounding qubits to the qubit is as small as possible to ensure the accurate execution of the single-qubit logic gate. Based on the above considerations, the applicant has proposed a three-dimensional analysis model that includes the coupling relationship between elements of the same category and the coupling relationship between elements of different categories on a quantum chip, and uses the three-dimensional analysis model to allocate and adjust the working points of quantum bits. Compared with existing solutions, the solution of the present application takes into account more influencing factors and is more in line with the actual situation of quantum chips. The three-dimensional analysis model can be used to allocate working points of quantum bits that are more in line with the actual situation. In addition, we can also use the three-dimensional analysis model to more accurately characterize quantum bits.

[0058] Please refer to Figure 2 , Figure 2 A structural schematic diagram of a three-dimensional analysis model proposed for this embodiment, the main idea of ​​which is to divide the specific structure of the quantum chip into three layers for layer-by-layer analysis, the top layer is a read bus layer including a read bus 10, the middle layer is a resonant cavity layer including a resonant cavity 11, and the bottom layer is a quantum bit layer including quantum bits 12 and a coupler 13.

[0059] In this embodiment, the applicant considers the coupling effect between two adjacent read buses, and the construction of a three-dimensional analysis model including the coupling relationship between the same type of elements and the coupling relationship between different types of elements on the quantum chip includes:

[0060] A first coupling relationship between read busses is acquired, where the first coupling relationship includes a coupling relationship between adjacent read busses.

[0061] Specifically, the first coupling relationship is obtained by the following formula:

[0062]

[0063] Among them, b1 and b2 are two adjacent read buses, ω b1 is the frequency of the signal read on b1, ω b2 is the frequency of the signal read on b2, C bus is the parasitic capacitance between b1 and b2, v1 is the speed of light in b1, v2 is the speed of light in b2, c1 is the capacitance per unit length of the transmission line of b1, c2 is the capacitance per unit length of the transmission line of b2, λ(ω b1 ,ω b2 ) is the coupling strength between b1 and b2.

[0064] In this embodiment, the applicant also considers the coupling effect between the read bus and the resonant cavity, and the construction of a three-dimensional analysis model including the coupling relationship between the same type of elements and the coupling relationship between different types of elements on the quantum chip also includes:

[0065] A second coupling relationship between the read bus and the resonant cavity is obtained, wherein the second coupling relationship includes a coupling relationship between the read bus and an adjacent resonant cavity. It should be noted that a read bus is generally used to read multiple resonant cavities. In this embodiment, the second coupling relationship may only consider the coupling relationship between the resonant cavity read by the same read bus and the read bus, and may also consider the coupling relationship between the resonant cavity not read by the current read bus and the current read bus. This is not limited here and can be set according to actual needs.

[0066] Specifically, the second coupling relationship is obtained by the following formula:

[0067]

[0068] Among them, C bus-reson is the parasitic capacitance between the reading bus and the resonant cavity, c is the capacitance per unit length of the reading bus transmission line, Cr is the capacitance of the resonant cavity, ω ris the frequency of the signal in the resonant cavity, ω is the frequency of the signal on the read bus, v is the speed of light in the read bus, and λ(ω) is the coupling strength between the read bus and an adjacent resonant cavity.

[0069] In this embodiment, the applicant also considers the coupling effect between resonant cavities, and the construction of a three-dimensional analysis model including the coupling relationship between the same type of elements on the quantum chip and the coupling relationship between different types of elements also includes:

[0070] A third coupling relationship between the resonant cavities is obtained, where the third coupling relationship includes a coupling relationship between two adjacent or sub-adjacent resonant cavities, where sub-adjacent means that the two resonant cavities are in a diagonal relationship in the physical structure of the sub-chip to be measured.

[0071] Specifically, the third coupler relationship is obtained by the following formula:

[0072]

[0073] Among them, r1 and r2 are two adjacent or sub-adjacent resonant cavities, ω r1 ,ω r2 is the frequency of the two resonant cavities, Cr1 and Cr2 are the capacitances of the two resonant cavities, and C reson is the parasitic capacitance between the two resonant cavities, J ωr1，ωr2 is the coupling strength between the two resonant cavities.

[0074] In this embodiment, the applicant also considers the coupling effect between the resonant cavity and the quantum bit, and the construction of a three-dimensional analysis model including the coupling relationship between the same type of elements on the quantum chip and the coupling relationship between different types of elements also includes:

[0075] A fourth coupling relationship between the resonant cavity and the quantum bit is obtained, wherein the fourth coupling relationship includes a coupling relationship between the resonant cavity and the corresponding first quantum bit, and a coupling relationship between the resonant cavity and the second quantum bit, wherein the resonant cavity is used to read information carried by the first quantum bit, and the second quantum bit is another quantum bit that is in a neighboring relationship with the first quantum bit.

[0076] Specifically, the fourth coupling relationship is obtained by the following formula:

[0077]

[0078] Among them, ω r is the frequency of the resonant cavity, ω q / c is the frequency of the first qubit or the second qubit, C reson-qc is the coupling capacitance between the resonant cavity and the first qubit or the second qubit, Cr is the capacitance of the resonator, C q / c is the capacitance of the first qubit or the second qubit, J ωr，ωq / c is the coupling strength between the resonant cavity and the first qubit or the second qubit. It should be noted that the applicant has also found that in addition to the coupling effect between the resonant cavity and the qubit, it may also have a coupling effect with the coupler. Therefore, in this embodiment, ω q / c In addition to being the frequency of the first qubit or the second qubit, it can also be the frequency of the coupler. Similarly, C reson-qc In addition to the coupling capacitance between the resonant cavity and the first qubit or the second qubit, it can also be the coupling capacitance between the resonant cavity and the coupler, C q / c It may be the capacitance of the first quantum bit or the second quantum bit, or it may be the capacitance of the coupler.

[0079] In this embodiment, the applicant also considers the coupling effect between quantum bits, and the construction of a three-dimensional analysis model including the coupling relationship between the same type of elements and the coupling relationship between different types of elements on the quantum chip also includes:

[0080] A fifth coupling relationship between quantum bits is obtained, wherein the fifth coupling relationship includes a coupling relationship between two adjacent quantum bits and a coupling relationship between two sub-adjacent quantum bits, wherein the two adjacent quantum bits are two quantum bits that have a direct coupling relationship in the sub-chip to be measured, and the two sub-adjacent quantum bits are two quantum bits that do not have a direct coupling relationship in the sub-chip to be measured.

[0081] Specifically, the fifth coupling relationship is obtained by the following formula:

[0082]

[0083] Among them, ω1 and ω2 are the frequencies of two adjacent qubits or two sub-adjacent qubits, C qc is the coupling capacitance between two adjacent qubits or two sub-adjacent qubits, C1 and C2 are the capacitances of two adjacent qubits or two sub-adjacent qubits, and J ω1，ω2 is the coupling strength between two adjacent qubits or two next-neighboring qubits.

[0084] Specifically, in this embodiment, adjusting the working point of the quantum bit in the sub-chip to be measured based on the three-dimensional analysis model includes:

[0085] Based on the three-dimensional analysis model, a constraint on the working point of the target quantum bit is constructed, wherein the constraint is used to limit the target quantum bit from being affected by the coupling of surrounding elements, and the target quantum bit is any quantum bit in the sub-chip to be measured.

[0086] Specifically, in this embodiment, adjusting the working point of the quantum bit in the quantum chip to be measured based on the three-dimensional analysis model further includes:

[0087] The working point of each quantum bit in the sub-chip to be measured is allocated by utilizing the physical topological structure and the constraints, wherein the physical topological structure is the physical layout of each device in the sub-chip to be measured.

[0088] It should be noted that in the embodiment of the present application, when allocating the working point of the quantum bit, the five coupling relationships mentioned above are mainly considered. Therefore, the five coupling relationships obtained will be used when constructing the constraints. In this embodiment, the constraints can be understood as constraint equations, that is, constraint equations are constructed. The constraint equations contain λ(ω b1 ,ω b2 ),λ(ω),,J ωr1，ωr2 , J ωr，ωq / c , J ω1，ω2 These five parameters need to be assigned respective weight coefficients according to the influence of these coupling relationships. The type of constraint equation is not limited and can be configured according to actual conditions. In this embodiment, it is assumed that the constraint equation Func is:

[0089] Func=aλ(ω b1 ,ω b2 )+bλ(ω)+cJ ωr1，ωr2 +dJ ωr，ωq / c +eJ ω1，ω2 , where a, b, c, d, e

[0090] For each coupling relationship, the respective weight coefficients, those skilled in the art will understand that a, b, c, d, e can be positive or negative. When we construct a constraint, we need to set a target value, and the constraint equation can be considered to meet the requirements when the set target value is reached. It should be noted that the weight coefficient needs to be determined according to the actual situation of the quantum chip to be measured, and no restrictions are made here. By constructing this constraint, we can minimize the noise interference to the final quantum bit, which makes it easier for us to characterize the various parameters of the quantum bit during the testing phase of the quantum chip.

[0091] Specifically, in this embodiment, the physical topological structure and the constraint model may also be used to sequentially allocate the working point of each quantum bit in the quantum chip in a set order.

[0092] Furthermore, in this embodiment, the working points of the quantum bits that are close to the center of the physical topological structure can be obtained first, and then the working points of the quantum bits that are far from the center of the physical topological structure can be obtained. This solution can guarantee the performance of the quantum chip to the greatest extent, and make the quantum bits that cannot determine the appropriate working points appear at the edge of the physical topological structure of the quantum chip as much as possible, effectively improving the utilization rate of resources in the quantum chip. It should be noted that when there are several quantum bits with the same distance from the center of the physical topological structure, the corresponding working points are obtained from the several quantum bits in a random order.

[0093] Based on the same inventive concept, the present invention also provides a control device for a quantum chip. Please refer to Figure 3 , the control device of the quantum chip comprises:

[0094] The model construction unit 100 is used to construct a three-dimensional analysis model including the coupling relationship between the same type of elements and the coupling relationship between different types of elements on the quantum chip, wherein the elements include a read bus layer, a resonant cavity layer, and a quantum bit layer, wherein the read bus layer includes all read buses of the sub-chip to be measured, the resonant cavity layer includes all resonant cavities of the sub-chip to be measured, and the quantum bit layer includes all quantum bits of the sub-chip to be measured;

[0095] The operating point adjustment unit 200 is used to adjust the operating point of the quantum bit in the sub-chip to be measured based on the three-dimensional analysis model.

[0096] It can be understood that the model building unit 100 and the operating point adjustment unit 200 can be combined in one device, or any one of the modules can be split into multiple sub-modules, or at least part of the functions of one or more modules in the model building unit 100 and the operating point adjustment unit 200 can be combined with at least part of the functions of other modules and implemented in one functional module. According to an embodiment of the present invention, at least one of the model building unit 100 and the operating point adjustment unit 200 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable way of integrating or packaging the circuit, or in a proper combination of software, hardware and firmware. Alternatively, at least one of the model building unit 100 and the operating point adjustment unit 200 can be at least partially implemented as a computer program module, and when the program is run by a computer, the function of the corresponding module can be executed.

[0097] Based on the same inventive concept, an embodiment of the present invention further proposes a quantum control system, using the control method of the quantum chip described in any one of the above-mentioned feature descriptions, or a control device including the quantum chip described in the above-mentioned feature descriptions.

[0098] Based on the same inventive concept, an embodiment of the present invention further proposes a quantum computer, including the quantum control system described in the above feature description.

[0099] Based on the same inventive concept, an embodiment of the present invention further proposes a readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it can implement the control method of the quantum chip described in any one of the above-mentioned feature descriptions.

[0100] The readable storage medium can be a tangible device that can keep and store the instructions used by the instruction execution device, such as but not limited to an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device or any suitable combination of the above. The more specific example (non-exhaustive list) of the readable storage medium includes: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination of the above. The computer program described here can be downloaded from the readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device through a network, such as the Internet, a local area network, a wide area network and / or a wireless network. The network can include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer program from the network and forwards the computer program for storage in a readable storage medium in each computing / processing device. The computer program for performing the operation of the present invention may be an assembly instruction, an instruction set architecture (ISA) instruction, a machine instruction, a machine-dependent instruction, a microcode, a firmware instruction, a state setting data, or a source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The computer program may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect through the Internet). In some embodiments, by utilizing the state information of a computer program to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute computer-readable program instructions to implement various aspects of the present invention.

[0101] Here, various aspects of the present invention are described with reference to the flowchart and / or block diagram of the method, system and computer program product according to the embodiment of the present invention. It should be understood that each square frame of the flowchart and / or block diagram and the combination of the square frames in the flowchart and / or block diagram can be realized by a computer program. These computer programs can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so as to produce a machine, so that these programs, when executed by the processor of a computer or other programmable data processing device, produce a device for realizing the function / action specified in one or more square frames in the flowchart and / or block diagram. These computer programs can also be stored in a readable storage medium, and these computer programs make the computer, programmable data processing device and / or other equipment work in a specific way, so that the readable storage medium storing the computer program includes a manufactured product, which includes instructions for realizing various aspects of the function / action specified in one or more square frames in the flowchart and / or block diagram.

[0102] The computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are executed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0103] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "specific example" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0104] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for controlling a quantum chip, characterized in that: include: Constructing a three-dimensional analysis model including coupling relationships between components of the same category and coupling relationships between components of different categories on a quantum chip, wherein the components include all read buses of the sub-chip to be measured, all resonant cavities of the sub-chip to be measured, and all quantum bits of the sub-chip to be measured; The operating point of the quantum bit in the sub-chip to be measured is adjusted based on the three-dimensional analysis model.

2. The method according to claim 1, characterized in that The construction of a three-dimensional analysis model including the coupling relationship between components of the same category and the coupling relationship between components of different categories on the quantum chip includes: A first coupling relationship between read busses is acquired, where the first coupling relationship includes a coupling relationship between adjacent read busses.

3. The method according to claim 2, characterized in that The first coupling relationship is obtained by the following formula: Among them, b1 and b2 are two adjacent read buses, ω b1 is the frequency of the signal read on b1, ω b2 is the frequency of the signal read on b2, C bus is the parasitic capacitance between b1 and b2, v1 is the speed of light in b1, v2 is the speed of light in b2, c1 is the capacitance per unit length of the transmission line of b1, c2 is the capacitance per unit length of the transmission line of b2, λ(ω b1 ,ω b2 ) is the coupling strength between b1 and b2.

4. The method according to claim 2, characterized in that The construction of the three-dimensional analysis model including the coupling relationship between the same type of components and the coupling relationship between different types of components on the quantum chip also includes: A second coupling relationship between the read bus and the resonant cavity is acquired, wherein the second coupling relationship includes a coupling relationship between the read bus and an adjacent resonant cavity.

5. The method according to claim 4, characterized in that The second coupling relationship is obtained by the following formula: Among them, C bus-reson is the parasitic capacitance between the reading bus and the resonant cavity, c is the capacitance per unit length of the reading bus transmission line, Cr is the capacitance of the resonant cavity, ω r is the frequency of the signal in the resonant cavity, ω is the frequency of the signal on the read bus, v is the speed of light in the read bus, and λ(ω) is the coupling strength between the read bus and an adjacent resonant cavity.

6. The method according to claim 4, characterized in that The construction of the three-dimensional analysis model including the coupling relationship between the same type of components and the coupling relationship between different types of components on the quantum chip also includes: A third coupling relationship between the resonant cavities is obtained, where the third coupling relationship includes a coupling relationship between two adjacent or sub-adjacent resonant cavities, where sub-adjacent means that the two resonant cavities are in a diagonal relationship in the physical structure of the sub-chip to be measured.

7. The method according to claim 6, characterized in that The third coupler relationship is obtained by the following formula: Among them, r1 and r2 are two adjacent or sub-adjacent resonant cavities, ω r1 ,ω r2 is the frequency of the two resonant cavities, Cr1 and Cr2 are the capacitances of the two resonant cavities, and C reson is the parasitic capacitance between the two resonant cavities, J ωr1，ωr2 is the coupling strength between the two resonant cavities.

8. The method according to claim 6, characterized in that The construction of the three-dimensional analysis model including the coupling relationship between the same type of components and the coupling relationship between different types of components on the quantum chip also includes: A fourth coupling relationship between the resonant cavity and the quantum bit is obtained, wherein the fourth coupling relationship includes a coupling relationship between the resonant cavity and the corresponding first quantum bit, and a coupling relationship between the resonant cavity and the second quantum bit, wherein the resonant cavity is used to read information carried by the first quantum bit, and the second quantum bit is another quantum bit that is in a neighboring relationship with the first quantum bit.

9. The method according to claim 8, characterized in that The fourth coupling relationship is obtained by the following formula: Among them, ω r is the frequency of the resonant cavity, ω q / c is the frequency of the first qubit or the second qubit, C reson-qc is the coupling capacitance between the resonant cavity and the first qubit or the second qubit, C r is the capacitance of the resonator, C q / c is the capacitance of the first qubit or the second qubit, J ωr，ωq / c is the coupling strength between the resonant cavity and the first quantum bit or the second quantum bit.

10. The method according to claim 8, characterized in that The construction of the three-dimensional analysis model including the coupling relationship between the same type of components and the coupling relationship between different types of components on the quantum chip also includes: A fifth coupling relationship between quantum bits is obtained, wherein the fifth coupling relationship includes a coupling relationship between two adjacent quantum bits and a coupling relationship between two sub-adjacent quantum bits, wherein the two adjacent quantum bits are two quantum bits that have a direct coupling relationship in the sub-chip to be measured, and the two sub-adjacent quantum bits are two quantum bits that do not have a direct coupling relationship in the sub-chip to be measured.

11. The method according to claim 10, characterized in that The fifth coupling relationship is obtained by the following formula: Among them, ω1 and ω2 are the frequencies of two adjacent qubits or two sub-adjacent qubits, C qc is the coupling capacitance between two adjacent qubits or two sub-adjacent qubits, C1 and C2 are the capacitances of two adjacent qubits or two sub-adjacent qubits, and J ω1，ω2 is the coupling strength between two adjacent qubits or two next-neighboring qubits.

12. The method according to claim 10, characterized in that The step of adjusting the working point of the quantum bit in the quantum chip to be measured based on the three-dimensional analysis model includes: Constructing a constraint on the working point of a target quantum bit based on the three-dimensional analysis model, wherein the constraint is used to limit the target quantum bit from being affected by coupling with surrounding elements, and the target quantum bit is any quantum bit in the sub-chip to be measured; The constraints are used to allocate the working point of each quantum bit in the sub-chip to be measured.

13. A control device for a quantum chip, characterized in that: include: A model building unit, used to build a three-dimensional analysis model including coupling relationships between elements of the same category and coupling relationships between elements of different categories on a quantum chip, wherein the elements include all read buses of the sub-chip to be measured, all resonant cavities of the sub-chip to be measured, and all quantum bits of the sub-chip to be measured; A working point adjustment unit is used to adjust the working point of the quantum bit in the sub-chip to be measured based on the three-dimensional analysis model.

14. A quantum control system, characterized in that: A control method using the quantum chip as described in any one of claims 1 to 12, or a control device comprising the quantum chip as described in claim 13.

15. A quantum computer, characterized in that: Comprising the quantum control system as claimed in claim 14.

16. A readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it can implement the control method of the quantum chip according to any one of claims 1 to 12.

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