Field programmable gate array device including spin-orbit torque-magnetic random access memory and method of operation thereof

Abstract

A field programmable gate array device is disclosed that includes a plurality of lookup tables, each lookup table storing data. Each lookup table includes a cell array including cells connected to a plurality of word lines, a driving circuit connected to the cell array through the plurality of word lines, and a peripheral circuit connected to the cell array through a plurality of bit lines and source lines, and configured to control the driving circuit. The driving circuit drives a first word line among the word lines based on a first input signal. The peripheral circuit performs a data write operation on the first cell connected to the first word line based on the first command and the second input signal, and performs a data read operation on the first cell connected to the first word line based on the second command and the second input signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2023-0094560 filed on July 20, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety Technical Field

[0003] Embodiments of the present disclosure described herein relate to electronics, and more particularly, to a field programmable gate array device (FPGA) including a spin orbit torque-magnetic random access memory (SOT-MRAM) and a method of operating the same. Background Art

[0004] An FPGA is a semiconductor device including programmable metal wiring and programmable logic elements so that desired functions can be realized on site.

[0005] The programmable logic element included in the FPGA includes a lookup table configured to pre-store a processing result of data input to the FPGA. The lookup table includes a plurality of units, each of which includes a semiconductor memory device.

[0006] Since the FPGA requires high-speed operation and / or low operating voltage, the lookup table includes a magnetic memory element as a semiconductor memory device. For example, the lookup table may include a SOT-MRAM as a magnetic memory element.

[0007] Depending on how the cells included in the lookup table are designed, the area of ​​the lookup table may increase significantly, resulting in an increase in the time it takes to read the processing results from the lookup table. In addition, because the lookup table occupies a large portion of the total area of ​​the FPGA, it would be beneficial to change the design of the cells included in the lookup table in such a way that the area of ​​the FPGA is reduced and the time it takes to read the processing results from the FPGA is reduced. Summary of the invention

[0008] Embodiments of the present disclosure provide a field programmable gate array device and an operating method thereof, the field programmable gate array device being capable of providing a lookup table having a small area while including a SOT-MRAM.

[0009] According to an embodiment, a field programmable gate array device includes a plurality of lookup tables, each of which is configured to store data. Each of the plurality of lookup tables includes: a cell array including a plurality of cells connected to a plurality of word lines; a driving circuit connected to the cell array through a plurality of word lines and configured to drive at least a first word line of the plurality of word lines based on a first input signal received from an external device; and a peripheral circuit connected to the cell array through a plurality of bit lines and a plurality of source lines and configured to control the driving circuit. The peripheral circuit performs a data write operation on a first cell of the plurality of cells connected to the first word line based on a first command and a second input signal received from an external device, and performs a data read operation on a first cell of the plurality of cells connected to the first word line based on a second command and a second input signal received from an external device. Each cell connected to the first word line is connected to two bit lines of the plurality of bit lines and one source line of the plurality of source lines.

[0010] According to an embodiment, an operation method of a field programmable gate array device, the field programmable gate array device includes a cell array having a plurality of cells, a driving circuit connected to the cell array through a plurality of word lines, and a peripheral circuit connected to the cell array through a plurality of bit lines and a plurality of source lines, and controlling the driving circuit includes: receiving a first input signal from an external device at the driving circuit, driving a first word line among the plurality of word lines based on the first input signal at the driving circuit, receiving a command, an address, and a second input signal from the external device at the driving circuit, and performing a data read operation on a first cell among the plurality of cells connected to the first word line based on the command and the second input signal at the peripheral circuit. Each cell connected to the first word line is connected to two bit lines among the plurality of bit lines and one source line among the plurality of source lines.

[0011] According to an embodiment, a method for operating a field programmable gate array device includes a cell array having a plurality of cells, a driving circuit connected to the cell array through a plurality of word lines, and a peripheral circuit connected to the cell array through a plurality of bit lines and a plurality of source lines, and controlling the driving circuit includes: receiving a first input signal from an external device at the driving circuit, driving a first word line among the plurality of word lines at the driving circuit based on the first input signal, receiving a write command, a write address, write data, and a second input signal from the external device at the peripheral circuit, writing the write data to a first cell among the cells connected to the first word line among the plurality of cells at the peripheral circuit based on the write command and the second input signal, receiving a read command, a read address, and a second input signal from the external device at the peripheral circuit, and reading a second cell among the cells connected to the first word line among the plurality of cells at the peripheral circuit based on the read command and the second input signal. Writing the write data includes performing a first logic operation on the second input signal and a write enable signal at the peripheral circuit, applying different voltages to the plurality of source lines at the peripheral circuit based on the first input signal and the second input signal, and writing the write data to the first cell among the plurality of cells at the peripheral circuit based on the voltage and the result of the first logic operation. The write enable signal is generated by the peripheral circuit in response to the write command. Reading a second cell among the cells connected to the first word line among the plurality of cells includes performing a second logic operation on the second input signal and the read command at the peripheral circuit, and sensing a voltage change of a bit line among the plurality of bit lines connected to the second cell among the plurality of cells based on a result of the second logic operation at the peripheral circuit. The read enable signal is generated by the peripheral circuit in response to the read command, and each cell connected to the first word line is connected to two bit lines among the plurality of bit lines and one source line among the plurality of source lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0013] Figure 1A and Figure 1B is a diagram illustrating a field programmable gate array (FPGA) device according to at least one embodiment of the present disclosure.

[0014] Figure 2 is a diagram showing in detail one unit included in an FPGA device.

[0015] Figure 3A and Figure 3B is a diagram showing in detail a lookup table LUT included in an FPGA device.

[0016] FIG. 4A to FIG. 4CAn example is shown in which a data write operation and a data read operation are performed with respect to one unit included in the lookup table LUT.

[0017] Figure 5 is a diagram illustrating in detail two units included in an FPGA device according to at least one embodiment of the present disclosure.

[0018] Figure 6 is a diagram illustrating in detail a lookup table LUT included in an FPGA device according to at least one embodiment of the present disclosure.

[0019] Figure 7 is a diagram illustrating in detail a switch controller included in a lookup table LUT according to at least one embodiment of the present disclosure.

[0020] Fig. 8A yes Figure 2 A floor plan of one of the units.

[0021] Figure 8B According to at least one embodiment of the present disclosure Figure 5 Floor plans of the two units.

[0022] FIG. 8C to FIG. 8E It is along Figure 8B Cross-sectional views taken along line AA', line BB' and line CC'.

[0023] 9A to 9C is used to describe at least one embodiment of the present disclosure and is connected to Figure 6 A diagram of a data read operation associated with cells of a word line.

[0024] FIG. 10A to FIG. 11C is used to describe at least one embodiment of the present disclosure and is connected to Figure 6 A diagram of a data write operation associated with cells of a word line.

[0025] Fig.12 is a flowchart of a method for operating a lookup table LUT for performing a data writing operation according to at least one embodiment of the present disclosure.

[0026] Fig.13 is a flowchart of an operating method of a lookup table LUT for performing a data read operation according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Below, the embodiments of the present disclosure will be described in detail and clearly so that those of ordinary skill in the art can easily perform the present disclosure. In the accompanying drawings, the same reference numerals represent the same elements, and the size of the elements may be exaggerated for clarity and convenience of description. In addition, the embodiments described below are only examples, and various modifications may be made from these embodiments.

[0028] Additionally, for ease of explanation, spatially relative terms, such as "below," "beneath," "lower," "below," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, the device may be oriented in other ways, such as rotated 90 degrees or in other orientations, and the spatially relative descriptors used herein should be interpreted accordingly.

[0029] Figure 1A and Figure 1B is a diagram illustrating a field programmable gate array (FPGA) device according to at least one embodiment of the present disclosure. Figure 1A and Figure 1B , the FPGA device 10 may include a plurality of wiring design devices 20 , a plurality of internal blocks 30 , and a plurality of external blocks 40 .

[0030] The plurality of wiring design devices 20 may form a wiring structure that implements a connection relationship between the plurality of internal blocks 30 and the plurality of external blocks 40 included in the FPGA device 10. For example, the plurality of wiring design devices 20 may enable the formation of a communication path connecting the plurality of internal blocks 30 and the plurality of external blocks 40 included in the FPGA device 10. Figure 1A and Figure 1B An example in which the number of the wiring design devices 20 is “4” is shown in FIG. 1 , but the number of the wiring design devices 20 is not limited thereto.

[0031] The plurality of wiring design devices 20 may include therein connection information of a switch box SB. For example, the plurality of wiring design devices 20 may implement connection relations between the plurality of internal blocks (IB) 30 and the plurality of external blocks (OB) 40 based on the connection information of the switch box SB.

[0032] Each of the plurality of inner blocks 30 and the plurality of outer blocks 40 may include a plurality of horizontal bundles hb and a plurality of vertical bundles vb. Each of the plurality of horizontal bundles hb and the plurality of vertical bundles vb may include a wiring pattern.

[0033] The wiring pattern may be a pattern such as a single wiring pattern, a double wiring pattern, a hexagonal wiring pattern, a complex wiring pattern, etc. The plurality of internal blocks 30 and the plurality of external blocks 40 may be connected to each other through the wiring pattern based on connection information of the switch box SB. Each of the plurality of wiring design devices 20 may be electrically connected to the plurality of vertical bundles vb included in the two external blocks OB.

[0034] In addition to the plurality of vertical beams vb and the plurality of horizontal beams hb, each internal block 30 may further include a switch box SB and a lookup table LUT. Figure 1A and Figure 1B An example in which the number of the internal blocks 30 is “4” is shown in FIG. 1 , but the number of the internal blocks 30 is not limited thereto.

[0035] In addition to the plurality of vertical beams vb and the plurality of horizontal beams hb, each of the plurality of external blocks 40 may further include an input / output block I / O and a switch box SB. The FPGA device 10 may perform input / output with the outside (e.g., with an external device (not shown)) through the input / output block I / O. Figure 1A and Figure 1B An example in which the number of the external blocks 40 is “8” is shown in FIG. 1 , but the number of the external blocks 40 is not limited thereto.

[0036] The switch box SB may include a plurality of switches. The switch box SB is configured to receive connection information of the switches from a plurality of wiring design devices 20. Based on the received switch connection information, the switch box SB may be electrically connected to the input / output block I / O, the lookup table LUT, a plurality of horizontal bundles hb, and a plurality of vertical bundles vb by using a plurality of switches.

[0037] The FPGA device 10 is configured to receive a read command RCMD, a read address RADD R, a write command WCMD, a write address WADDR, and write data WDATA from the outside; and the FPGA device 10 is configured to output the read data RDATA to the outside. For example, the FPGA device 10 can be configured to be connected to a processing circuit that is configured to enable the FPGA device 10 to perform read and / or write operations. The processing circuit may include, for example, hardware, software, and / or a combination thereof. For example, the processing circuit may more specifically include (and / or be included in) but not limited to a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0038] For example, the FPGA device 10 is configured to receive a read command RCMD, a read address RADDR, a write command WCMD, a write address WADDR, and write data WDATA from an FPGA controller (not shown) located outside the FPGA device 10, and is configured to output the read data RDATA to the FPGA controller.

[0039] Figure 2 is a diagram showing in detail one unit included in an FPGA device. For example, Figure 1AEach and / or at least one of the multiple lookup tables LUT included in the F PGA device 10 may include multiple units shown. In at least one embodiment, Figure 2 In the description, the description will be given with reference to one unit, and the functions and operations of the remaining units may be similar to those of the unit.

[0040] refer to Figure 2 , the cell may include a read transistor RT, a write transistor WT, and a memory such as a spin-orbit torque-magnetic random access memory (hereinafter referred to as "SOT-MRAM"). The SOT-M RAM may include a heavy metal HM and a magnetic tunnel junction (hereinafter referred to as "MTJ"), and may be referred to as including a heavy metal magnetic tunnel junction structure ("HM-MTJ" or "MTJ-HM").

[0041] A first end portion of the heavy metal HM may be connected to a first source / drain terminal of the write transistor WT, and a second end portion of the heavy metal HM may be connected to a source line SL. An MTJ may be disposed on the heavy metal HM between the first end portion and the second end portion.

[0042] The heavy metal HM may be and / or include a semiconductor substrate including silicon, silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), or the like.

[0043] The MTJ may include a reference magnetic pattern PL, a free magnetic pattern FL, and a tunnel barrier pattern TBP interposed therebetween.

[0044] The free magnetic pattern FL may be interposed between the heavy metal HM and the tunnel barrier pattern TBP. The free magnetic pattern FL may be disposed to face the first direction from the heavy metal HM and may contact one surface of the heavy metal HM.

[0045] The free magnetic pattern FL may include a magnetic material configured to induce magnetic anisotropy at an interface of the free magnetic pattern FL and the tunnel barrier pattern TBP. For example, the free magnetic pattern FL may include cobalt iron boron (CoFeB).

[0046] The tunnel barrier pattern TBP may be interposed between the free magnetic pattern FL and the reference magnetic pattern PL. The tunnel barrier pattern TBP may be disposed to face the first direction from the free magnetic pattern FL and may contact one surface of the free magnetic pattern FL.

[0047] The tunnel barrier pattern TBP may include an insulator oxide, for example, at least one of magnesium oxide (Mg), titanium oxide (Ti), aluminum oxide (Al), magnesium zinc oxide (Mg—Zn), magnesium boron oxide (Mg—B), and the like.

[0048] The reference magnetic pattern PL may be spaced apart from the free magnetic pattern FL with the tunnel barrier pattern TBP interposed therebetween. The reference magnetic pattern PL may be disposed to face the first direction from the tunnel barrier pattern TBP and may contact one surface of the tunnel barrier pattern TBP.

[0049] In at least one embodiment, the reference magnetic pattern PL may include cobalt (Co), platinum (Pt), and a first non-magnetic element. The first non-magnetic element may include at least one of Nb, Cr, Mo, W, Zr, Hf, and Ti.

[0050] The cell may be configured such that when an in-plane current flows in the heavy metal HM, a spin-orbit torque SOT caused by a spin Hall effect or a Rashba effect may be applied to the free magnetic pattern FL, and thus, the magnetization direction of the free magnetic pattern FL may be switched.

[0051] The MTJ may be inserted between the first source / drain terminal of the read transistor RT and the heavy metal HM, and may be connected to the first source / drain terminal of the read transistor RT.

[0052] A second source / drain terminal of the write transistor WT may be connected to a write bit line WBL, and a second source / drain terminal of the read transistor RT may be connected to a read bit line RBL.

[0053] The read transistor RT may be connected between the MTJ and the read bit line RBL, and a gate electrode of the read transistor RT may be connected to the word line WL. The read transistor RT may control an electrical connection between the MTJ and the read bit line RBL.

[0054] The write transistor WT may be connected between a first end of the heavy metal HM and a write bit line WBL, and a gate electrode of the write transistor WT may be connected to the word line WL. The write transistor WT may control electrical connection between the heavy metal HM and the write bit line WBL.

[0055] In a write operation, the write transistor WT may be turned on by the word line WL. In this case, the write current I W The heavy metal HM may flow. The write current I may be adjusted according to the voltage conditions of the write bit line WBL and the source line SL. W The direction is set to the second direction or the fourth direction.

[0056] Write current I W It can act as an in-plane current that applies the spin-orbit torque SOT to the free magnetic pattern FL. The write current I WThe write current I W When flowing, the spin current caused by the spin Hall effect and / or the Rashba effect may flow in a direction perpendicular to the interface between the heavy metal HM and the free magnetic pattern FL, and therefore, the spin-orbit torque SOT may be applied to the MTJ. In this case, the magnetization direction of the free magnetic pattern FL may be switched to be antiparallel or parallel to the magnetization direction of the reference magnetic pattern PL. After setting the magnetization direction of the free magnetic pattern FL, the write transistor WT may be turned off. The direction of the magnetization direction (e.g., antiparallel or parallel) may represent a stored bit (e.g., 1 or 0).

[0057] In the read operation, the read transistor RT can be turned on by the word line WL. In this case, the read current I R The read current I R When the MTJ is set to "1", for example, the read current I R The flow through the MTJ may be in a direction perpendicular to the interface between the heavy metal HM and the MTJ (eg, the third direction).

[0058] Figure 3A and Figure 3B FIG. 1 is a diagram showing in detail a lookup table LUT included in an FPGA device. The FPGA device 10 of FIG. 1 may include a plurality of lookup tables LUT. In at least one embodiment, Figure 3A and Figure 3B In the description, the description will be described with reference to one lookup table 50. The functions and operations of the remaining lookup tables LUT may be similar to those of the lookup table 50.

[0059] refer to Figure 2 , Figure 3A and Figure 3B , the lookup table 50 may include a cell array 51 , a driving circuit 52 , and a peripheral circuit 53 .

[0060] The cell array 51 may include a plurality of cells (eg, cell1 to cell2 n ). Multiple cells cell1 to cell2 n may be arranged in a fourth direction and may be respectively connected to a plurality of word lines WL1 to WL2 n (For example, n is a positive integer of 1 or greater).

[0061] For example, gate electrodes of the write transistor WT and the read transistor RT included in the first cell cell1 may be connected to the first word line WL1. Gate electrodes of the write transistor WT and the read transistor RT included in the second cell cell2 may be connected to the second word line WL2.

[0062] As described above, included in the second n-1 cell2 n-1 The gate electrodes of the write transistor WT and the read transistor RT in the second n-1 Word line WL2 n-1 Included in Section 2 n cell2 n The gate electrodes of the write transistor WT and the read transistor RT in the second n Word line WL2 n .

[0063] Figure 3A Multiple cells cell1 to cell2 n The configuration and operation of each of the Figure 2 The configuration and operation of the described cells are the same (or substantially similar). Therefore, additional description will be omitted to avoid redundancy.

[0064] The driving circuit 52 can be driven by a plurality of word lines WL1 to WL2. n Connected to the cell array 51. The driving circuit 52 may include first to nth selection circuits SC1 to SCn. Each of the first to nth selection circuits SC1 to SCn may include a plurality of transistors MT. The number of transistors MT of the first to nth selection circuits SC1 to SCn may be different.

[0065] The plurality of transistors MT may be implemented with at least one of, for example, an n-type metal oxide semiconductor (NMOS) transistor, a p-type metal oxide semiconductor (PMOS) transistor, a high electron mobility transistor (HEMT), etc. Hereinafter, a description will be given assuming that each of the plurality of transistors MT is implemented with an NMOS transistor.

[0066] For example, the nth selection circuit SCn may include 2 n The (n-1)th selection circuit SCn-1 may include 2 n-1 NMOS transistors MT. As in the above description, the first selection circuit SC1 may include two NMOS transistors MT.

[0067] In addition to 2 n In addition to the NMOS transistor MT, the nth selection circuit SCn may also include 2 nWord line drivers Drv1 to Drv2 n . 2 n Word line drivers Drv1 to Drv2 n Can be connected to multiple word lines WL1 to WL2 respectively n . 2 n Word line drivers Drv1 to Drv2 n The first end can be connected to 2 n A first source / drain terminal of the NMOS transistor MT.

[0068] The driving circuit 52 is configured to receive input signals I(0) to I(n-1) from the outside (e.g., from the FPGA controller (not shown) described with reference to FIG. 1). The input signals I(0) to I(n-1) may constitute n-bit data. The n data bits may be applied to the first to nth selection circuits SC1 to SCn, respectively.

[0069] 2 included in the nth selection circuit SCn n Each of the gate electrodes of the NMOS transistors MT can be connected to a line to which an input signal I(n-1) is applied. n One half of the gate electrode of each NMOS transistor MT may be connected to a line to which an input signal I(n-1) having a non-inverting logic value (eg, "0" or "1") is applied. n The other half of the gate electrode of the NMOS transistor MT may be connected to a line to which an input signal I(n-1) having an inverted logic value (eg, “1” or “0”) is applied.

[0070] 2 n The second source / drain terminal of the NMOS transistor MT may be connected to the 2 included in the (n-1)th selection circuit SCn-1. n-1 A first source / drain terminal of the NMOS transistor MT.

[0071] 2 included in the (n-1)th selection circuit SCn-1 n-1 Each of the gate electrodes of the NMOS transistors MT can be connected to a line to which an input signal I(n-2) is applied. n-1 One half of the gate electrode of each N MOS transistor MT may be connected to a line to which an input signal I(n-2) having a non-inverting logic value (eg, "0" or "1") is applied. n The other half of the gate electrodes of the NMOS transistors MT may be connected to a line to which an input signal I(n-2) having an inverted logic value (eg, “1” or “0”) is applied.

[0072] 2 n-1The second source / drain terminal of the NMOS transistor MT may be connected to the 2-th selection circuit SCn-2 included in the (n-2)th selection circuit SCn-2. n-2 A first source / drain terminal of the NMOS transistor MT.

[0073] As described above, each of the gate electrodes of the two NMOS transistors MT included in the first selection circuit SC1 can be connected to a line to which an input signal I(0) is applied. For example, one of the gate electrodes of the two NMOS transistors MT can be connected to a line to which an input signal I(0) having a non-inverting logic value (e.g., "0" or "1") is applied. The other of the gate electrodes of the two NMOS transistors MT can be connected to a line to which an input signal I(0) having an inverting logic value (e.g., "1" or "0") is applied.

[0074] Second source / drain terminals of the two NMOS transistors MT may be connected to a ground terminal.

[0075] In this case, only the input signals connected to the word lines WL1 to WL2 may be driven according to the logic values ​​of the input signals I(0) to I(n-1). n One of the word line drivers. This will refer to Figure 4A Detailed description.

[0076] exist Figure 3B Medium, 2 n Word line drivers Drv1 to Drv2 n The first word line driver Drv1 in may include a PMOS transistor and an inverter. A first source / drain terminal of the PMOS transistor may be connected to a first end of the inverter. A power supply voltage VDD may be applied to a second source / drain terminal of the PMOS transistor. A second end of the inverter may be connected to the first word line WL1.

[0077] The remaining word line drivers Drv2 to Drv2 n The configuration and operation of the first word line driver Drv1 are the same as (or substantially similar to) those of the first word line driver Drv1, and thus, additional description will be omitted to avoid redundancy.

[0078] The peripheral circuit 53 may also be connected to the cell array 51 through a plurality of bit lines WBL, RBL and source lines SL. The peripheral circuit 53 is configured to perform output control on the cell array 51 and the drive circuit 52. For example, the operation of the peripheral circuit 53 will be described with reference to FIG.

[0079] Although not shown, the peripheral circuit 53 may include a read amplifier, a write driver, a source line driver, an input / output circuit, and / or a control logic circuit, etc. However, the components of the peripheral circuit 53 are not limited thereto.

[0080] exist Figure 3A and Figure 3B In the embodiment, the peripheral circuit 53 is configured to receive the precharge command PRE_CMD before receiving the input signals I(0) to I(n-1) from the outside (e.g., from the FPGA controller (not shown) described with reference to FIG. 1). The peripheral circuit 53 may apply the precharge signal PRE to the 2 in response to receiving the precharge command PRE_CMD. n Word line drivers Drv1 to Drv2 n .

[0081] In this case, 2 n Word line drivers Drv1 to Drv2 n The first terminal of the inverter included in each of the word lines WL1 to WL2 can be charged with the power supply voltage VDD. n The second end of each of the inverters in the word lines WL1 to WL2 can be discharged to the ground voltage VSS. n Can remain inactive.

[0082] FIG. 4A to FIG. 4C An example of performing a data write operation and a data read operation on a unit included in a lookup table LUT is shown. In at least one embodiment, reference will be made to FIG. 4A to FIG. 4C Describes the data writing operation and data reading operation of the first cell cell1. Figure 3A and 3B The same (or substantially similar) description is given.

[0083] Reference FIG. 4A to FIG. 4C The peripheral circuit 53 is configured to receive an activation command ACT CMD from the outside (eg, from the FPGA controller (not shown) described with reference to FIG. 1 ). The peripheral circuit 53 may apply an activation signal ACT to the 2 in response to the activation command ACT CMD. n Word line drivers Drv1 to Drv2 n In this case, 2 n Word line drivers Drv1 to Drv2 n A first terminal of the inverter included in each of the may be in a state of being charged with the power supply voltage VDD.

[0084] The driving circuit 52 is configured to receive input signals I(0) to I(n-1) under the control of the peripheral circuit 53. Each of the input signals I(0) to I(n-1) may have a specific logic value; in this case, at least some of the plurality of transistors included in each of the first to nth selection circuits SC1 to SCn may be turned on.

[0085] For example, when the input signal I(n-1) is applied to the nth selection circuit SCn, 2 n Half of the NMOS transistors MT can be turned on. When the input signal I(n-2) is applied to the (n-1)th selection circuit SCn-1, 2 n-1 Half of the two NMOS transistors MT may be turned on. When the input signal I(0) is applied to the first selection circuit SC1, one of the two NMOS transistors MT may be turned on.

[0086] For example, when each of the input signals I(0) to I(n-1) has a specific logic value, a current path may be formed between the ground terminal and the first end of the first word line driver Drv1 connected to the first source / drain terminal of the NMOS transistor MT.

[0087] In this case, current may flow from the first end of the first word line driver Drv1 to the ground terminal due to the voltage difference, and thus the first end of the inverter included in the first word line driver Drv1 may be discharged to the ground voltage VSS.

[0088] In this way, the second terminal of the inverter included in the first word line driver Drv1 can be charged with the power supply voltage VDD. Therefore, the plurality of word lines WL1 to WL2 can be activated. n The first word line WL1 in .

[0089] For example, when each of the input signals I(0) to I(n-1) has a specific logic value, the ground terminal and the second terminal connected to the first source / drain terminal of the NMOS transistor MT may not be connected. n Word line driver Drv2 n A current path is formed between the first ends of the

[0090] In this case, the second n Word line driver Drv2 n A voltage level of a first terminal of an inverter included in may be maintained at a level of a power supply voltage VDD.

[0091] So, the second n Word line driver Drv2 n The voltage level of the second terminal of the inverter included in the circuit may be maintained at the level of the ground voltage VSS. Therefore, the plurality of word lines WL1 to WL2 may not be activated. n No.2 n Word line WL2 n .

[0092] After activating the first word line WL1, the peripheral circuit 53 is configured to receive a write command WCMD and write data WDATA from the outside. The peripheral circuit 53 may further include a table (not shown) configured to store operation results of input signals. The operation may be at least one of an addition operation and a multiplication operation.

[0093] The peripheral circuit 53 may refer to an operation result according to a specific logic value of the input signal from a table (not shown), and may determine voltage levels of the write bit line WBL and the source line SL based on the write data WDATA.

[0094] The peripheral circuit 53 can be configured to generate a voltage in the second direction (reference voltage) based on the voltage levels of the write bit line WBL and the source line SL. Figure 2 ) or the fourth direction (reference Figure 2 ) generates a write current I W The peripheral circuit 53 can be based on the write current I W Perform data write operation.

[0095] The peripheral circuit 53 may write write data WDATA (eg, '0' or '1') to the SOT-MRAM included in the first cell cell1 in a state in which the write transistor WT included in the first cell cell1 is turned on by the first word line WL1 and thus activated.

[0096] After the data write operation, the peripheral circuit 53 is configured to receive a read command RCM D from the outside. The peripheral circuit 53 can sense the voltage change of the read bit line RBL to generate a read current I in the third direction. R (refer to Figure 2 ).

[0097] The peripheral circuit 53 can also read the current I R The peripheral circuit 53 may read data RDATA (eg, “0” or “1”) stored in the SOT-MRAM included in the first cell cell1 in a state in which the read transistor RT included in the first cell cell1 is turned on by the first word line WL1 and thus activated.

[0098] As mentioned above, in Figure 3A and Figure 4A In the embodiment, the driving circuit 52 may include a first selection circuit SC1 to an nth selection circuit SCn. Therefore, the driving circuit 52 may include (2 n+1 -2) NMOS transistors MT. In this case, the driving circuit 52 may occupy most of the area of ​​the lookup table 50. Therefore, a method of designing a lookup table LUT capable of implementing an FPGA device 10 with a small area may be needed.

[0099] In addition, included in the reference Figure 3A and Figure 4A The read transistor RT in each cell described can be connected to a read bit line RBL. In this case, 2 n The parasitic capacitance of the read transistor RT (not shown) may be calculated. For example, the read bit line RBL may have a large capacitance value, thereby resulting in an increase in power consumption in the data read operation and an increase in the time taken to perform the data read operation. Therefore, a method of designing a lookup table LUT that can implement an FPGA device 10 that provides improved energy efficiency may be needed.

[0100] Figure 5 FIG. 1 is a diagram showing in detail two units included in an FPGA device according to at least one embodiment of the present disclosure. Figure 1A Each of the multiple lookup tables LUT in the FPGA device 10 may include multiple units. In at least one embodiment, Figure 5 In the description, the description will be given with reference to two units, and the functions and operations of the remaining units may be similar to those of the two units. Figure 2 The same (or substantially similar) description is given.

[0101] refer to Figure 5 , two cells (hereinafter referred to as “first and second cells”) cell and cell′ may be connected to one word line WL.

[0102] A first end portion of the heavy metal HM included in the first cell “cell” may be connected to the first source / drain terminal of the write transistor WT, and a second end portion of the heavy metal HM may be connected to the first source line SL1 .

[0103] The MTJ included in the first cell “cell” may be inserted between the first source / drain terminal of the read transistor RT and the heavy metal HM, and may be connected to the first source / drain terminal of the read transistor RT.

[0104] A second source / drain terminal of the write transistor WT included in the first cell “cell” may be connected to the third bit line BL3 . A second source / drain terminal of the read transistor RT included in the first cell “cell” may be connected to the first bit line BL1 .

[0105] A read transistor RT included in the first cell “cell” may be connected between the MTJ and the first bit line BL1 , and a gate electrode of the read transistor RT may be connected to the word line WL. The read transistor RT may control an electrical connection between the MTJ and the first bit line BL1 .

[0106] The write transistor WT may be connected between the first end of the heavy metal HM and the third bit line BL3, and a gate electrode of the write transistor WT may be connected to the word line WL. Therefore, the write transistor WT may control the electrical connection between the heavy metal HM and the third bit line BL3.

[0107] In a write operation, the write transistor WT included in the first cell “cell” may be turned on by the word line WL. In this case, the write current I flowing through the heavy metal HM may be turned on according to the voltage conditions of the third bit line BL3 and the first source line SL1. W The direction is set (or changed) to the first direction (reference Figure 2 ) or a third party (reference Figure 2 ).

[0108] In the read operation, the read transistor RT can be turned on by the word line WL. In this way, the read current I R The read current I can flow from the first bit line BL1 through the MTJ and the heavy metal HM. R The direction perpendicular to the interface between the heavy metal HM and the MTJ (ie, the fourth direction (reference Figure 2 )) flows through the MTJ.

[0109] A first end portion of the heavy metal HM included in the second cell cell′ may be connected to the first source / drain terminal of the write transistor WT, and a second end portion of the heavy metal HM may be connected to the second source line SL2 .

[0110] A second source / drain terminal of the write transistor WT included in the second cell cell' may be connected to the third bit line BL3. A second source / drain terminal of the read transistor RT included in the second cell cell' may be connected to the second bit line BL2.

[0111] The read transistor RT included in the second cell cell' may be connected between the MTJ and the second bit line BL2, and a gate electrode of the read transistor RT may be connected to the word line WL. The read transistor RT may control an electrical connection between the MTJ and the second bit line BL2.

[0112] In the write operation, the write transistor WT included in the second cell cell' may be turned on by the word line WL. In this case, the write current I flowing through the heavy metal HM may be adjusted according to the voltage conditions of the second bit line BL3 and the second source line SL2. W The direction is set (or changed) to the first direction (reference Figure 2 ) or a third party (reference Figure 2 ).

[0113] In the read operation, the read transistor RT can be turned on by the word line WL. In this way, the read current I R The read current I may flow from the second bit line BL2 through the MTJ and the heavy metal HM. R The direction perpendicular to the interface between the heavy metal HM and the MTJ (ie, the fourth direction (reference Figure 2 )) flows through the MTJ.

[0114] Figure 6 FIG. 1 is a diagram showing in detail a lookup table LUT included in an FPGA device according to at least one embodiment of the present disclosure. The FPGA device 10 of FIG. 1 may include a plurality of lookup tables LUT. In at least one embodiment, Figure 6 In the description, the description will be described with reference to one lookup table 100. Functions and operations of the remaining lookup tables LUT may be similar to those of the lookup table 100.

[0115] About Included Figure 6 The cell array 110, the driving circuit 120 and the peripheral circuit 130 in the lookup table LUT are omitted. Figure 3A and 3B Descriptions that are the same (or substantially similar) as the descriptions described.

[0116] refer to Figure 5 and Figure 6 , the first cell cell1 and the second cell cell2 included in the cell array 110 may be connected to the first word line WL1, and the second cell cell1 and the second cell cell2 included in the cell array 110 may be connected to the first word line WL1. n -1) cell(2 n -1) and 2 n cell2 n Can be connected to the 2nd n-1 Word line WL2 n-1 .

[0117] For example, gate electrodes of the write transistor WT and the read transistor RT included in the first cell cell1 and gate electrodes of the write transistor WT and the read transistor RT included in the second cell cell2 may be connected to the first word line WL1 .

[0118] For example, included in (2 n -1) cell(2 n -1) and the gate electrodes of the write transistor WT and the read transistor RT and the gate electrodes of the second n cell2 n The gate electrodes of the write transistor WT and the read transistor RT in the second n-1 Word line WL2 n-1 .

[0119] The first cell cell1, the second cell cell2, the second cell cell1 n -1) cell(2 n -1) and 2 n cell2 n Configuration and operation of Figure 5 The configurations and operations of the two cells cell and cell' described are the same (or substantially similar). Therefore, additional description will be omitted to avoid redundancy.

[0120] The driving circuit 120 can drive the plurality of word lines WL1 to WL2. n-1 is connected to the cell array 110. The driving circuit 120 may include first to (n-1)th selection circuits SC1 to SCn-1.

[0121] and Figure 3A and Figure 4A The driving circuit 52 is different, Figure 6 The driving circuit 120 may not include the nth selection circuit SCn. Therefore, the number of NMOS transistors MT included in the driving circuit 120 may be (2 n -2).

[0122] therefore, Figure 6 The area of ​​the driving circuit 120 can be smaller than Figure 3A and Figure 4A This may mean that the lookup table 100 can be designed with a smaller area.

[0123] In addition to 2 n-1 In addition to the NMOS transistor MT, the (n-1)th selection circuit SCn-1 may also include 2 n-1 Word line drivers Drv1 to Drv2 n-1 . 2 n-1 Word line drivers Drv1 to Drv2 n-1 Can be connected to multiple word lines WL1 to WL2 respectively n-1 . 2 n -1 Word line drivers Drv1 to Drv2 n-1 The first end can be connected to 2 n-1 A first source / drain terminal of the NMOS transistor MT.

[0124] That is to say, Figure 3A and Figure 4A The nth selection circuit SCn may include 2 n Word line drivers Drv1 to Drv2 n However, in Figure 6In the embodiment, the (n-1)th selection circuit SCn-1 may include half of the word line driver of the nth selection circuit SCn.

[0125] The driving circuit 120 is configured to receive first input signals I(0) to I(n-2) from the outside. Figure 3A The driving circuit 52 is different because Figure 6 The driving circuit 120 includes first to (n-1)th selection circuits SC1 to SCn-1, so that (n-1) data bits can be applied to the first to (n-1)th selection circuits SC1 to SCn-1, respectively. A second input signal I(n-1) different from the first input signals I(0) to I(n-2) can also be received from the peripheral circuit 130.

[0126] In these cases, only the first input signals I(0) to I(n-2) connected to the word lines WL1 to WL2 may be driven according to the logic values ​​of the first input signals I(0) to I(n-2). n-1 One of the word line drivers. This will refer to 9A to 11C Detailed description.

[0127] The peripheral circuit 130 may be connected to the cell array 110 through a plurality of bit lines BL1 , BL2 , and BL3 and a plurality of source lines SL1 and SL2 .

[0128] For example, Figure 3A and Figure 4A The peripheral circuit 53 can be connected to the cell array 51 through two bit lines RBL and WBL and one source line SL. Figure 6 The peripheral circuit 130 may be connected to the cell array 110 through three bit lines BL1 , BL2 , and BL3 and two source lines SL1 and SL2 .

[0129] The peripheral circuit 130 may generate a write enable signal WEN in response to a write command WCMD (refer to FIG. 3 ) received from the outside. The peripheral circuit 130 may generate a read enable signal REN in response to a read command R CMD (refer to FIG. 3 ) received from the outside.

[0130] exist Figure 6 In the embodiment, the peripheral circuit 130 may include a switch controller 131 , a sense amplifier (SA) 132 , a write driver (WD) 133 , and a plurality of switches 134 .

[0131] The switch controller 131 is configured to output control signals to the plurality of switches 134. The plurality of bit lines BL1, BL2, and BL3, the plurality of source lines SL1 and SL2, the sense amplifier 132, the write driver 133, and the ground terminal may be electrically connected based on the control signals. The switch controller 131 may control the plurality of switches 134.

[0132] The switch controller 131 is configured to receive a second input signal I(n-1), a write enable signal WEN, and a read enable signal REN. The switch controller 131 may output a control signal for controlling the plurality of switches 134 based on the second input signal I(n-1), the write enable signal WEN, and the read enable signal REN. Figure 7 The switch controller 131 is described in detail.

[0133] The peripheral circuit 130 may perform a data write operation based on the write enable signal WEN. The peripheral circuit 130 may perform a data read operation based on the read enable signal REN.

[0134] exist Figure 6 Medium, 2 n-1 The first cell can be connected to the first bit line BL1. n-1 The cells can be connected to the second bit line BL2. Figure 3A and Figure 4A Medium, 2 n Each cell can be connected to one read bit line RBL; however, Figure 6 In, only 2 n-1 Each cell can be connected to one bit line BL1 or BL2, and only 2 n Each cell can be connected to another bit line BL1 or BL2.

[0135] Figure 6 The capacitance value of one bit line BL1 or BL2 can be less than Figure 3A and Figure 4A Therefore, the speed of releasing the stored charge in the read operation can be increased, and the power consumption in the read operation and the time taken to perform the read operation can be reduced.

[0136] In addition, the energy consumed to charge the capacitor of one bit line BL1 or BL2 and generate a voltage level may be reduced. Therefore, the FPGA device 10 capable of improving energy efficiency in a read operation may be realized.

[0137] Figure 7 is a diagram illustrating in detail a switch controller included in a lookup table LUT according to at least one embodiment of the present disclosure.

[0138] Reference Figure 6 and Figure 7 , the peripheral circuit 130 may include a switch controller 131, a sense amplifier 132, and a write driver 133. The switch controller 131 may include first to fifth logic gates 131a to 131e.

[0139] The first to fifth logic gates 131 a to 131 e are configured to output control signals for controlling the first to seventh switches S1 to S7 .

[0140] In at least one embodiment, each of the first to seventh switches S1 to S7 may be implemented using a transmission gate TG. The transmission gate TG may be composed of a p-type metal oxide semiconductor (P MOS) transistor and an n-type MOS (NMOS) transistor connected in parallel. In the transmission gate TG, a control signal may be applied to a gate electrode of the PMOS transistor and a gate electrode of the NMOS transistor.

[0141] The control signal may include a signal of an inverted logic value applied to a gate electrode of the PMOS transistor and a signal of a non-inverted logic value applied to a gate electrode of the NMOS transistor.

[0142] The first logic gate 131 a and the second logic gate 131 b are configured to receive a read enable signal REN.

[0143] The first logic gate 131a may receive the non-inverted second input signal I(n-1). The first logic gate 131a may perform a logic operation based on the non-inverted second input signal I(n-1) and the read enable signal REN, and may output a control signal for controlling the first switch S1.

[0144] Although not shown, in the first switch S1, a gate electrode of the PMOS transistor and a gate electrode of the NMOS transistor may be connected to the first logic gate 131a. Therefore, in the first switch S1, a control signal may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor.

[0145] The second logic gate 131b may receive an inverted version of the second input signal I(n-1). The second logic gate 131b may perform a logic operation based on the inverted version of the second input signal I(n-1) and the read enable signal REN, and may output a control signal for controlling the second switch S2.

[0146] Although not shown, in the second switch S2, the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor may be connected to the second logic gate 131b. Therefore, in the second switch S2, a control signal may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor.

[0147] For example, when the second input signal I(n-1) has a first logic value (e.g., "1"), the read amplifier 132 included in the peripheral circuit 130 may also be connected to the first bit line BL1 based on the control signal of the first logic gate 131a. According to the control signal of the second logic gate 131b, the read amplifier 132 included in the peripheral circuit 130 may not be connected to the second bit line BL2.

[0148] For example, when the second input signal I(n-1) has a second logic value (e.g., "0"), the read amplifier 132 included in the peripheral circuit 130 may not be connected to the first bit line BL1 based on the control signal of the first logic gate 131a. The read amplifier 132 included in the peripheral circuit 130 may also be connected to the second bit line BL2 based on the control signal of the second logic gate 131b.

[0149] The third logic gate 131 c and the fourth logic gate 131 d are configured to receive a write enable signal WEN.

[0150] The third logic gate 131c may receive the non-inverted second input signal I(n-1). The third logic gate 131c may perform a logic operation based on the non-inverted second input signal I(n-1) and the write enable signal WEN, and may output a control signal for controlling the fourth switch S4 and the fifth switch S5.

[0151] Although not shown, in each of the fourth switch S4 and the fifth switch S5, the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor may be connected to the third logic gate 131c. Therefore, in the fourth switch S4 and the fifth switch S5, the control signal may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor.

[0152] The fourth logic gate 131d may receive an inverted version of the second input signal I(n-1). The fourth logic gate 131d may perform a logic operation based on the inverted version of the second input signal I(n-1) and the write enable signal WEN, and may output a control signal for controlling the sixth switch S6 and the seventh switch S7.

[0153] Although not shown, in each of the sixth switch S6 and the seventh switch S7, the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor may be connected to the fourth logic gate 131d. Therefore, in the sixth switch S6 and the seventh switch S7, the control signal may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor.

[0154] For example, when the second input signal I(n-1) has a first logic value (eg, "1"), the write driver 133 included in the peripheral circuit 130 may be connected to the third bit line BL3 and the plurality of source lines SL1 and SL2 based on a control signal of the third logic gate 131c.

[0155] For example, when the second input signal I(n-1) has a second logic value (eg, "0"), the write driver 133 included in the peripheral circuit 130 may be connected to the third bit line BL3 and the plurality of source lines SL1 and SL2 based on a control signal of the fourth logic gate 131d.

[0156] Each of the first to fourth logic gates 131 a to 131 d may include an AND gate; in this case, the logic operation may include an AND operation.

[0157] The fifth logic gate 131e is configured to receive the read enable signal REN. The fifth logic gate 131e is configured to output a control signal for controlling the third switch S3 based on the read enable signal REN.

[0158] Although not shown, in the third switch S3, the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor may be connected to the fifth logic gate 131e. Therefore, in the third switch S3, the control signal may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor.

[0159] For example, when the switch controller 131 receives the read enable signal REN, the third bit line BL3 may be connected to the ground terminal.

[0160] Fig. 8A yes Figure 2 A floor plan of a unit. Figure 2 and Fig. 8A The write transistor WT and the read transistor RT may be formed in a semiconductor substrate (not shown). The semiconductor substrate (not shown) may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like.

[0161] The word line WL and the first metal M1 may be disposed on the write transistor WT and the read transistor RT. The first metal M1 may be connected to the write transistor WT and the read transistor RT through a metal contact (not shown).

[0162] The read bit line RBL and the write bit line WBL may be disposed on the first metal M1. The read bit line RBL and the write bit line WBL may be connected to the first metal M1 through a metal contact (not shown). The read bit line RBL and the write bit line WBL may be disposed on a semiconductor substrate (not shown) so as to cross the word line WL.

[0163] The MTJ may be disposed on the first metal M1 disposed on the read transistor RT. The heavy metal HM may be disposed on the first metal M1, and the MTJ is disposed on the write transistor WT. The heavy metal HM may be connected to the first metal M1 disposed on the write transistor WT through a metal contact (not shown).

[0164] The source line SL may be disposed on the heavy metal HM. The source line SL may be connected to the heavy metal HM through a metal contact (not shown). Fig. 8A , a length of a cell in a horizontal direction may be “L1.” The length L1 may be defined as a horizontal distance from one side of the first metal M1 disposed on the read transistor RT to one side of the first metal M1 disposed on the write transistor WT.

[0165] Figure 8B According to at least one embodiment of the present disclosure Figure 5 Floor plans of the two units. FIG. 8C to FIG. 8E It is along Figure 8B The cross-sectional view taken along the lines A-A', B-B' and CC' of FIG. Fig. 8A The same (or substantially similar) description is given.

[0166] Reference FIG. 8B to FIG. 8E , the write transistor WT and the read transistor RT may also be formed in the semiconductor substrate.

[0167] The word line WL and the first metal M1 may be disposed on the write transistor WT and the read transistor RT. The first metal M1 may be connected to the write transistor WT and the read transistor RT through a metal contact M2.

[0168] The first to third bit lines BL1 to BL3 may be disposed on the first metal M1. The first to third bit lines BL1 to BL3 may be connected to the first metal M1 through metal contacts M2.

[0169] For example, the first bit line BL1 and the second bit line BL2 may be disposed on the first metal M1 disposed on the read transistor RT. The first bit line BL1 and the second bit line BL2 may be connected to the first metal M1 disposed on the read transistor RT through the metal contact M2. The first bit line BL1 and the second bit line BL2 may not be connected to the first metal M1 disposed on the write transistor WT.

[0170] The third bit line BL3 may be disposed on the first metal M1 disposed on the write transistor WT. The third bit line BL3 may be connected to the first metal M1 disposed on the write transistor WT through a metal contact M2.

[0171] exist Figure 8B, the first region P1 may indicate a portion in which the first metal M1 disposed on the write transistor WT included in the first cell cell1 is connected to the third bit line BL3 through the metal contact M2.

[0172] exist Figure 8B , the second region P2 may indicate a portion where the first metal M1 disposed on the write transistor WT included in the second cell cell2 is connected to the third bit line BL3 through the metal contact M2. The third bit line BL3 may not be connected to the first metal M1 disposed on the read transistor RT.

[0173] First to third bit lines BL1 to BL3 may be disposed on a semiconductor substrate to cross word lines WL.

[0174] The MJT may be disposed on the first metal M1 disposed on the read transistor RT, respectively. The heavy metal HM may be disposed on the first metal M1, and the MJT is disposed on the write transistor WT. The heavy metal HM may be connected to the first metal M1 disposed on the write transistor WT through a metal contact M2.

[0175] A plurality of source lines SL1 and SL2 may be disposed on the heavy metal HM. The plurality of source lines SL1 and SL2 may be connected to the heavy metal HM and the metal contacts M2, respectively.

[0176] exist Figure 8B , a length of a cell in a horizontal direction may be “L2.” The length L2 may be defined as a horizontal distance from one side of a first metal M1 disposed on a read transistor RT included in the first cell cell1 to one side of the first region P1.

[0177] exist Figure 8B In the example, two cells cell1 and cell2 are arranged in the first direction (reference Figure 2 ) can be connected to the first to third bit lines BL1 to BL3, and can share the third bit line BL3 and the word line WL. Fig. 8A In the example, a cell can be connected to a read bit line RBL and a write bit line WBL. Therefore, Figure 8B The length L2 can be less than Fig. 8A This may mean that an implementation of the FPGA device 10 with a small area is possible.

[0178] 9A to 9C is used to describe at least one embodiment of the present disclosure and is connected to Figure 6 A diagram of a data read operation associated with a cell of a word line. 9A to 9C Description of the connection to the plurality of word lines WL1 to WL2 n-1In at least one embodiment, a data read operation is performed on cells of the first word line WL1.

[0179] refer to FIG. 4A to FIG. 7 and 9A to 9C , in a data reading operation of the first cell cell1 and the second cell cell2 connected to the first word line WL1, the power supply voltage VDD may be applied to the first word line WL1 through the first word line driver Drv1. Thus, the plurality of word lines WL1 to WL2 may be activated. n-1 The driving circuit 120 may drive the plurality of word lines WL1 to WL2 based on first input signals I(0) to I(n-2) received from the outside. n-1 A word line WL1 in.

[0180] The first switch S1 may be turned on depending on a control signal of the first logic gate 131a based on a second input signal I(n-1) having a first logic value (eg, "1") and a read enable signal REN. In these cases, the sense amplifier 132 may be connected to the first bit line BL1.

[0181] The second switch S2 may be turned on depending on a control signal of the second logic gate 131b based on a second input signal I(n-1) having a second logic value (e.g., "0") and a read enable signal REN. In this case, the sense amplifier 132 may be connected to the second bit line BL2. Fig.9A and Fig. 9B In the embodiment, the write driver 133 may not be connected to the third bit line BL3 and the plurality of source lines SL1 and SL2.

[0182] The third switch S3 may be turned on according to a control signal of the fifth logic gate 131e, which is based on the read enable signal REN. In this case, the third bit line BL3 may be connected to a ground terminal. A ground voltage VSS may be applied to the third bit line BL3.

[0183] When the power supply voltage VDD is applied to the first word line WL1, the read transistors of the first cell cell1 and the second cell cell2 may be turned on. In this case, the first bit line BL1 and the second bit line BL2 may be charged with the power supply voltage VDD.

[0184] Under the above voltage conditions, the sense amplifier 132 can generate a read current I R , to sense the voltage change of the first bit line BL1 connected to the first cell cell1 or the voltage change of the second bit line BL2 connected to the second cell cell2. The read current I RThe signal may flow from the first bit line BL1 to the third bit line BL3, or from the second bit line BL2 to the third bit line BL3.

[0185] Read current I R Can flow through MTJ and heavy metal HM. Read current I R The direction perpendicular to the interface where the heavy metal HM and the MTJ contact each other (eg, the fourth direction (see Figure 2 )) flows through the MTJ.

[0186] The resistance state of the MTJ (eg, high resistance state or low resistance state) can be determined by reading the current I R For example, when the magnetization direction of the free magnetic pattern FL is parallel to the magnetization direction of the reference magnetic pattern PL, the MTJ can be in a first resistance state (e.g., a low resistance state). When the magnetization direction of the free magnetic pattern FL is antiparallel to the magnetization direction of the reference magnetic pattern PL, the MTJ can be in a second resistance state (e.g., a high resistance state). Data (e.g., "0" or "1") stored in the MTJ of the first cell cell1 or the second cell cell2 can be detected depending on the resistance state of the MTJ.

[0187] FIG. 10A to FIG. 11C is used to describe at least one embodiment of the present disclosure and is connected to Figure 6 A diagram of a data write operation associated with cells of a word line.

[0188] In at least one embodiment, reference will be made to FIG. 10A to FIG. 10C A description is given of a case in which write data having a first value (eg, “0”) is written to a plurality of word lines WL1 to WL2. n-1 The operation of the cells of the first word line WL1.

[0189] In at least one embodiment, reference will be made to FIG. 11A to FIG. 11C Description of the case where write data having a second value (eg, “1”) is written to the plurality of word lines WL1 to WL2 n-1 The operation of the cell of the first word line WL1 is omitted with reference to 9A to 9C The same (or substantially similar) description is given.

[0190] refer to Figure 6 , Figure 7 and FIG. 10A to FIG. 11C , when the power supply voltage VDD is applied to the first word line WL1, the write transistors of the first cell cell1 and the second cell cell2 may be turned on. In this case, the third bit line BL3 may be charged with the power supply voltage VDD.

[0191] The sixth switch S6 and the seventh switch S7 may be turned on depending on a control signal of the fourth logic gate 131d, the control signal of the fourth logic gate 131d being based on the second input signal I(n-1) having a second logic value (e.g., "0") and the write enable signal WEN. In this case, the write driver 133 may be connected to the first end of the first source line SL1 through the seventh switch S7. The second end of the first source line SL1 may also be connected to a source line driver (not shown) included in the peripheral circuit 130.

[0192] The fourth switch S4 and the fifth switch S5 may be turned on depending on a control signal of the third logic gate 131c, the control signal of the third logic gate 131c being based on the second input signal I(n-1) having a first logic value (e.g., "1") and the write enable signal WEN. In this case, the write driver 133 may be connected to a first end of the second source line SL2 through the fifth switch S5. A second end of the second source line SL2 may also be connected to a source line driver (not shown) included in the peripheral circuit 130.

[0193] Under the control of the peripheral circuit 130 , a source line driver (not shown) may drive the plurality of source lines SL1 and SL2 at a specific voltage level.

[0194] In the case where a write operation is performed on the first cell cell1 and the second cell cell2 so as to have a high resistance value (e.g., an antiparallel state) (e.g., write having a first value (e.g., "0")), or in the case where a write operation is performed on the first cell cell1 and the second cell cell2 so as to have a low resistance value (e.g., a parallel state) (e.g., write having a second value (e.g., "1")), the voltage levels applied from the source line driver (not shown) to the first source line SL1 and the second source line SL2 may be different from each other.

[0195] exist FIG. 10A to FIG. 10C In order to write write data having a first value (eg, '0') into the first cell cell1, the ground voltage VSS may be applied to the first source line SL1, and the power supply voltage VDD may be applied to the second source line SL2.

[0196] When the sixth switch S6 is turned on, the first end of the second source line SL2 and the third bit line BL3 may be connected to the write driver 133. Therefore, the third bit line BL3 may be maintained at the level of the power supply voltage VDD.

[0197] According to the above voltage conditions, the write current I WA spin current may flow from the third bit line BL3 (having the level of the power supply voltage VDD) to the first source line SL1 (having the level of the ground voltage VSS) through the heavy metal HM; at the same (or substantially similar) time, a spin current may flow through the MTJ to the first bit line BL1 in a direction parallel to the reference magnetic pattern PL of the MTJ or in a direction anti-parallel to the reference magnetic pattern PL of the MTJ.

[0198] Write current I W It can act as an in-plane current that applies spin-orbit torque to the free magnetic pattern FL. The write current I W The write current I W When flowing, the spin current (caused by the spin Hall effect, Rashba effect, etc.) can flow in a direction perpendicular to the interface between the heavy metal HM and the free magnetic pattern FL of the MTJ, and thus, the spin-orbit torque can be applied to the MTJ. W The magnetization direction of the free magnetic pattern FL of the MTJ may be switched to be antiparallel (or parallel) to the magnetization direction of the reference magnetic pattern PL.

[0199] In order to write write data having a first value (eg, '0') to the second cell cell2 , a power supply voltage VDD may be applied to the first source line SL1 , and a ground voltage VSS may be applied to the second source line SL2 .

[0200] When the fourth switch S4 is turned on, the first end of the first source line SL1 and the third bit line BL3 may be connected to the write driver 133. Therefore, the third bit line BL3 may be maintained at the level of the power supply voltage VDD.

[0201] According to the above voltage conditions, the write current I W The spin current may flow from the third bit line BL3 (having the level of the power supply voltage VDD) to the second source line SL2 (having the level of the ground voltage VSS) through the heavy metal HM; at the same (or substantially similar) time, the spin current may flow through the MTJ to the second bit line BL2 in a direction parallel to the reference magnetic pattern PL of the MTJ or in a direction anti-parallel to the reference magnetic pattern PL of the MTJ.

[0202] exist FIG. 11A to FIG. 11C In order to write write data having a second value (eg, '1') into the first cell cell1, the power supply voltage VDD may be applied to the first source line SL1, and the ground voltage VSS may be applied to the second source line SL2.

[0203] When the sixth switch S6 is turned on, the first end of the second source line SL2 and the third bit line BL3 may be connected to the write driver 133. Therefore, the third bit line BL3 may be discharged to the level of the ground voltage VSS.

[0204] According to the above voltage conditions, the write current I W A spin current may flow from the source line SL1 (having the level of the power supply voltage VDD) to the third bit line BL3 (having the level of the ground voltage VSS) through the heavy metal HM; at the same (or substantially similar) time, a spin current may flow through the MTJ to the first bit line BL1 in a direction parallel to the reference magnetic pattern PL of the MTJ or in a direction anti-parallel to the reference magnetic pattern PL of the MTJ.

[0205] In order to write write data having a second value (eg, '1') to the second cell cell2 , a ground voltage VSS may be applied to the first source line SL1 , and a power supply voltage VDD may be applied to the second source line SL2 .

[0206] When the fourth switch S4 is turned on, the first end of the first source line SL1 and the third bit line BL3 may be connected to the write driver 133. Therefore, the third bit line BL3 may be maintained at the level of the ground voltage VSS.

[0207] According to the above voltage conditions, the write current I W A spin current may flow from the second source line SL2 (having the level of the power supply voltage VDD) to the third bit line BL3 (having the level of the ground voltage VSS) through the heavy metal HM; at the same (or substantially similar) time, a spin current may flow to the second bit line BL2 through the MTJ in a direction parallel to the reference magnetic pattern PL of the MTJ or in a direction anti-parallel to the reference magnetic pattern PL of the MTJ.

[0208] Fig.12 is a flowchart of a method for operating a lookup table LUT for performing a data writing operation according to at least one embodiment of the present disclosure.

[0209] refer to Figure 6 , Figure 7 , FIG. 10A to FIG. 11C and Fig.12 In operation S110, a lookup table (L UT) 100 may drive one word line among a plurality of word lines based on a first input signal.

[0210] In operation S120 , the lookup table 100 may receive a second input signal, a write command WCMD, a write address WADDR, and write data WDATA from the outside. Unlike the first input signal input to the driving circuit 120 , the second input signal may also be input to the peripheral circuit 130 .

[0211] In operation S130, the lookup table 100 may generate a write enable signal WEN in response to the write command WCMD. The lookup table 100 may perform a data write operation based on the write enable signal WEN.

[0212] In operation S140 , the lookup table 100 may control the plurality of switches based on the second input signal and the write enable signal W EN When the write enable signal WEN is applied, the lookup table 100 may control the fourth to seventh switches S4 to S7 .

[0213] When it is determined in operation S150 that the logic value of the second input signal is "1", operation S160 may be performed. In operation S160, the lookup table 100 may write data "0" or "1" into the lower cell (ie, Fig. 10A and Fig. 10B The second cell in the cell2).

[0214] When it is determined in operation S150 that the logic value of the second input signal is not "1", operation S170 may be performed. In operation S170, the lookup table 100 may write data "0" or "1" into the upper cell (ie, Fig. 10A and Fig. 10B The first cell in the cell1).

[0215] Fig.13 is a flowchart of an operating method of a lookup table LUT for performing a data read operation according to at least one embodiment of the present disclosure.

[0216] refer to Figure 6 , Figure 7 , 9A to 9C and Fig.12 In operation S210, the lookup table (LUT) 100 may drive one word line among a plurality of word lines based on a first input signal.

[0217] In operation S220 , the lookup table 100 may receive a second input signal, a read command R CMD, and a read address RADDR from the outside.

[0218] In operation S230, the lookup table 100 may generate a read enable signal REN in response to the read command RCMD. The lookup table 100 may perform a data read operation based on the read enable signal REN.

[0219] In operation S240 , the lookup table 100 may control the plurality of switches based on the second input signal and the read enable signal R EN. When the read enable signal REN is applied, the lookup table 100 may control the first to third switches S1 to S3 .

[0220] When it is determined in operation S250 that the logic value of the second input signal is "1", operation S260 may be performed. In operation S260, the lookup table 100 may read the logic value stored in the upper unit (ie, Fig.9A and Fig. 9B The data in the first cell cell1) is "0" or "1."

[0221] When it is determined in operation S250 that the logic value of the second input signal is not "1", operation S270 may be performed. In operation S270, the lookup table 100 may read the logic value stored in the lower unit (ie, Fig. 10A and Fig. 10B The data in the second cell cell2) is "0" or "1."

[0222] According to at least one embodiment of the present disclosure, a field programmable gate array (FPGA) device and an operation method thereof can provide a small-area lookup table by changing the design scheme of the lookup table. In addition, as the design scheme of the lookup table is changed, the number of cells connected to a read bit line can be reduced, and therefore, the read energy and read time for the read operation of the FPGA can be reduced.

[0223] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A field programmable gate array device, comprising: A plurality of lookup tables, each lookup table being configured to store data, each lookup table in the plurality of lookup tables comprising: A cell array including a plurality of cells connected to a plurality of word lines, a driving circuit connected to the cell array through the plurality of word lines and configured to drive at least a first word line of the plurality of word lines based on a first input signal received from an external device, and a peripheral circuit connected to the cell array through a plurality of bit lines and a plurality of source lines and configured to control the drive circuit, Wherein, the peripheral circuit is configured as follows: performing a data write operation on a first cell among cells connected to the first word line among the plurality of cells based on a first command and a second input signal received from the external device, and performing a data read operation on the first cell among the cells connected to the first word line among the plurality of cells based on a second command received from the external device and the second input signal, and Each of the cells connected to the first word line is connected to two bit lines of the plurality of bit lines and one source line of the plurality of source lines.

2. The field programmable gate array device according to claim 1, wherein The driving circuit includes a plurality of selection circuits, each of which includes a plurality of transistors. setting the number of the plurality of transistors differently for each of the plurality of selection circuits, The first input signals are applied to the plurality of selection circuits, respectively, and In each of the plurality of selection circuits, at least some of the plurality of transistors are turned on based on the first input signal.

3. The field programmable gate array device according to claim 2, wherein: In each of the plurality of selection circuits, the plurality of transistors are implemented using at least one of an N-type metal oxide semiconductor (NMOS) transistor, a p-type MOS (PMOS) transistor, or a high electron mobility transistor (HEMT).

4. The field programmable gate array device according to claim 1, wherein The cells connected to the first word line include the first cell and a second cell, Each of the first cell and the second cell includes a write transistor connected to the first word line and one of the plurality of bit lines, A memory included in the first unit is connected to a first terminal of the write transistor included in the first unit and a first source line among the plurality of source lines, and The memory included in the second unit is connected to a first terminal of the write transistor included in the second unit and a second source line different from the first source line among the plurality of source lines. 5 . The field programmable gate array device of claim 4 , wherein each of the memories of the first unit and the second unit comprises a spin-orbit torque-magnetic random access memory (SOT-MRAM).

6. The field programmable gate array device according to claim 1, wherein The cells connected to the first word line include the first cell and a second cell, A read transistor included in the first cell is connected to the first word line and a first bit line among the plurality of bit lines, and A read transistor included in the second cell is connected to the first word line and a second bit line different from the first bit line among the plurality of bit lines.

7. The field programmable gate array device according to claim 1, wherein the peripheral circuit comprises: a plurality of switches connected to the cell array through the plurality of bit lines and the plurality of source lines, and A switch controller is configured to control the plurality of switches.

8. The field programmable gate array device according to claim 7, wherein the switch controller comprises: a first logic circuit configured to perform a first logic operation on the second input signal and a write enable signal to output a first control signal for controlling a first switch among the plurality of switches, and a second logic circuit configured to perform a second logic operation on the second input signal and a read enable signal to output a second control signal for controlling a second switch among the plurality of switches; Wherein the peripheral circuit is configured to generate the write enable signal in response to the first command and to generate the read enable signal in response to the second command.

9. The field programmable gate array device of claim 8, wherein each of the first logic operation and the second logic operation comprises an AND operation.

10. The field programmable gate array device according to claim 8, wherein The cells connected to the first word line include the first cell and a second cell, The peripheral circuit is configured to apply different voltages to the plurality of source lines based on the first input signal and the second input signal, and The peripheral circuit is configured to perform the data read operation with respect to one of the first cell or the second cell based on the different voltages and the first control signal.

11. The field programmable gate array device according to claim 10, wherein: The peripheral circuit is configured to perform the data write operation with respect to the second cell based on a difference between voltages applied to the plurality of source lines in response to the second input signal having a first logic value, and The peripheral circuit is configured to perform the data write operation with respect to the first cell based on a difference between voltages applied to the plurality of source lines in response to the second input signal having a second logic value.

12. The field programmable gate array device according to claim 10, wherein: When the second input signal has a first logic value, the peripheral circuit is configured to sense a voltage change of a bit line connected to the first cell among the plurality of bit lines based on the second control signal.

13. The field programmable gate array device according to claim 10, wherein: When the second input signal has a second logic value, the peripheral circuit is configured to sense a voltage change of a bit line connected to the second cell among the plurality of bit lines based on the second control signal.

14. A method for operating a field programmable gate array device, the field programmable gate array device comprising a cell array, a driving circuit and a peripheral circuit, the cell array comprising a plurality of cells, the driving circuit being connected to the cell array via a plurality of word lines, the peripheral circuit being connected to the cell array via a plurality of bit lines and a plurality of source lines and being configured to control the driving circuit, the method comprising: receiving, at the driving circuit, a first input signal from an external device; driving, at the driving circuit, a first word line of the plurality of word lines based on the first input signal; receiving, at the peripheral circuit, a command, an address, and a second input signal from the external device; as well as performing, at the peripheral circuit, a data read operation on a first cell among cells connected to the first word line among the plurality of cells based on the command and the second input signal, Each of the cells connected to the first word line is connected to two bit lines of the plurality of bit lines and one source line of the plurality of source lines.

15. The method according to claim 14, wherein The driving circuit includes a plurality of selection circuits, each of which includes a plurality of transistors. The number of the plurality of transistors is set differently for each of the plurality of selection circuits, and The driving of the first word line includes turning on at least some of a plurality of switches at the driving circuit based on the first input signal in response to the first input signal being applied to the plurality of selection circuits, respectively.

16. The method according to claim 14, wherein: Executing the data reading operation includes: performing a logic operation on the second input signal and a read enable signal at the peripheral circuit, and sensing a voltage change of one of the plurality of bit lines at the peripheral circuit based on a result of the logic operation, and The read enable signal is generated by the peripheral circuit in response to the command.

17. The method according to claim 16, wherein The cells connected to the first word line include the first cell and a second cell, in, Executing the data reading operation includes: In response to the second input signal having a first logic value, a voltage change of a bit line connected to the first cell among the plurality of bit lines is sensed at the peripheral circuit based on the result of the logic operation.

18. The method according to claim 16, wherein The cells connected to the first word line include the first cell and a second cell, in, Performing the data read operation includes sensing, at the peripheral circuit, a voltage change of a bit line connected to the second cell among the plurality of bit lines based on the result of the logic operation in response to the second input signal being a second logic value.

19. The method of claim 16, wherein each of the logical operations comprises an AND operation.

20. A method for operating a field programmable gate array device, the field programmable gate array device comprising a cell array, a driving circuit and a peripheral circuit, the cell array comprising a plurality of cells, the driving circuit being connected to the cell array via a plurality of word lines, the peripheral circuit being connected to the cell array via a plurality of bit lines and a plurality of source lines and being configured to control the driving circuit, the method comprising: receiving, at the driving circuit, a first input signal from an external device; driving, at the driving circuit, a first word line of the plurality of word lines based on the first input signal; receiving, at the peripheral circuit, a write command, a write address, write data, and a second input signal from the external device; writing the write data to a first cell among cells connected to the first word line among the plurality of cells at the peripheral circuit based on the write command and the second input signal; receiving, at the peripheral circuit, a read command, a read address, and the second input signal from the external device; as well as reading, at the peripheral circuit, a second cell among the cells connected to the first word line among the plurality of cells based on the read command and the second input signal, The writing of the writing data comprises: performing a first logic operation at the peripheral circuit with respect to the second input signal and a write enable signal, applying different voltages to the plurality of source lines based on the first input signal and the second input signal at the peripheral circuit, and writing the write data to the first cell among the plurality of cells based on the voltage and a result of the first logic operation at the peripheral circuit, wherein the write enable signal is generated by the peripheral circuit in response to the write command, wherein reading the second cell among the cells connected to the first word line among the plurality of cells comprises: performing a second logic operation at the peripheral circuit with respect to the second input signal and the read command, and sensing, at the peripheral circuit, a voltage change of a bit line of the plurality of bit lines connected to the second cell of the plurality of cells based on a result of the second logic operation, wherein the read enable signal is generated by the peripheral circuit in response to the read command, and Each of the cells connected to the first word line is connected to two bit lines of the plurality of bit lines and one source line of the plurality of source lines.

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