Stacked semiconductor device with scalable interface and semiconductor package including same

Abstract

The invention relates to a stacked semiconductor device with a scalable interface and a semiconductor package including the same. A semiconductor package includes: a package substrate; the adapter is arranged on the packaging substrate; a stacked semiconductor device including a lower chip and one or more upper chips sequentially stacked over the adapter; a first semiconductor chip stacked over the adapter and spaced apart from the stacked semiconductor device, and configured to interface with the lower chip; and one or more second semiconductor chips disposed over the package substrate to interface with the lower chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application Nos. 10-2023-0094599 and 10-2024-0008584, filed on Jul. 20, 2023 and Jan. 19, 2024, respectively, which are hereby incorporated by reference in their entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to a docking method for a stacked semiconductor device. Background Art

[0004] With the rapid development of semiconductor technology, semiconductor integrated devices (such as packages, etc.) are required to have higher integration and performance. For this reason, the current technology is moving away from a two-dimensional structure in which semiconductor chips are arranged on a plane on a printed circuit board (PCB) by using wires or bumps. Instead, various new technologies related to a three-dimensional structure in which multiple semiconductor chips are vertically stacked have emerged.

[0005] The three-dimensional structure can be realized by a stacked semiconductor device in which a plurality of semiconductor chips are stacked vertically. The semiconductor chips stacked in the vertical direction are electrically connected to each other through through electrodes (eg, through silicon vias, TSVs) and mounted on a semiconductor package substrate.

[0006] Recently, various scalable interfaces of semiconductor packages including such stacked semiconductor devices have been discussed. Summary of the invention

[0007] Embodiments of the present disclosure relate to a stacked semiconductor device having an expandable interface circuit and a semiconductor package including the stacked semiconductor device.

[0008] According to an embodiment of the present disclosure, a semiconductor package includes: a packaging substrate; an adapter arranged on the packaging substrate; a stacked semiconductor device, including a lower chip and one or more upper chips stacked sequentially on the adapter; a first semiconductor chip stacked on the adapter and separated from the stacked semiconductor device, and configured to connect with the lower chip; and one or more second semiconductor chips arranged on the packaging substrate to connect with the lower chip.

[0009] According to an embodiment of the present disclosure, a stacked semiconductor device includes: a lower chip; and one or more upper chips stacked on the lower chip, wherein the lower chip includes a first interface circuit for connecting to a first semiconductor chip, one or more second interface circuits for connecting to one or more second semiconductor chips, and a third interface circuit for connecting to one or more upper chips, and wherein the first interface circuit includes: a main interface logic configured to transmit a first signal for one or more upper chips between the first semiconductor chip and the third interface circuit; and one or more sub-interface logics configured to transmit a second signal for one or more second semiconductor chips between the first semiconductor chip and the one or more second interface circuits.

[0010] According to an embodiment of the present disclosure, the capacity of a semiconductor package including a stacked semiconductor device may be increased.

[0011] These and other features and advantages of the embodiments of the present disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view illustrating a semiconductor package including a stacked memory device according to an embodiment of the present disclosure.

[0013] Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 A perspective view of a stacked memory device shown in FIG.

[0014] Figure 3 The present invention is a diagram showing an embodiment of the present invention. Figure 2 Detailed configuration diagram of the base die shown in .

[0015] Figure 4 It is shown Figure 3 Configuration diagram of the main memory interface logic of the first physical interface circuit.

[0016] Figure 5 Another embodiment of the present disclosure is shown in FIG. Figure 2 Detailed configuration diagram of the base die shown in .

[0017] Figure 6 FIG. 2 is a diagram showing another embodiment according to the present disclosure. Figure 2 Detailed configuration diagram of the base die shown in .

[0018] Fig. 7A and Figure 7B is a perspective view showing a semiconductor package according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] Below, various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. However, the embodiment teachings can be implemented in different forms and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure conveys the scope of this teaching to those skilled in the art. In the present disclosure, the same reference numerals refer to the same parts in multiple figures and embodiments of the present disclosure.

[0020] It should be noted that references to "an embodiment," "another embodiment," etc. do not necessarily mean only one embodiment, and different references to any such phrases are not necessarily referring to the same embodiment.

[0021] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element described below may also be referred to as the second or third element without departing from the spirit and scope of the present disclosure.

[0022] It should be further understood that when the terms "include", "comprising", "including" and "comprising" are used in this specification, the presence of the elements described is specified, and the presence or addition of one or more other elements is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] As used herein, singular forms may also include plural forms and vice versa, unless the context clearly indicates otherwise. Unless otherwise specified or it is clear from the context that a singular form is intended, "a" and "an" used in this application and the appended claims should generally be interpreted as meaning "one or more."

[0024] A semiconductor system including a stacked semiconductor device will be described below. The semiconductor system according to an embodiment of the present disclosure can be implemented in the form of a system-level package, a multi-chip package, or a system on chip, and can also be implemented in the form of a package on a package. A memory system including a stacked memory device will be described below as an example of a stacked semiconductor device.

[0025] Figure 1 is a cross-sectional view showing a semiconductor package 100 including a stacked memory device 110 according to an embodiment of the present disclosure.

[0026] refer to Figure 1 , the semiconductor package 100 may include a stacked memory device 110 , a processor 120 , an expansion memory 130 , an interposer 140 , a printed circuit board (PCB) 150 , and a package substrate 160 .

[0027] The package substrate 160 may include a printed circuit board (PCB). A plurality of external bumps 170 may be provided on the lower surface of the package substrate 160, and a plurality of internal bumps 180A and 180B may be provided on the upper surface of the package substrate 160. A plurality of external bumps 170 may be electrically connected to an external system board, a main board, or a module board, etc. A plurality of external bumps 170 may include solder balls or metal bumps. For example, a plurality of external bumps 170 may include solder balls for supplying power to the stacked memory device 110, the processor 120, and the expansion memory 130, and solder balls for the processor 120 to communicate with the outside. A plurality of internal bumps 180A and 180B may include a first internal bump 180A for electrically connecting the package substrate 160 to the adapter 140 and a second internal bump 180B for electrically connecting the package substrate 160 to the printed circuit board 150. A plurality of internal bumps 180A and 180B may include solder balls or metal bumps.

[0028] The adapter 140 and the printed circuit board 150 may be mounted on the package substrate 160. The adapter 140 and the printed circuit board 150 may be arranged on the package substrate 160 spaced apart from each other. The adapter 140 may be a silicon substrate that only forms interconnections. The adapter 140 may be electrically connected to the package substrate 160 through a first inner bump 180A. The printed circuit board 150 may be electrically connected to the package substrate 160 through a second inner bump 180B.

[0029] The stacked memory device 110 and the processor 120 may be mounted on the adapter 140. The stacked memory device 110 and the processor 120 may be disposed on the adapter 140 to be spaced apart from each other. Figure 1 Only one stacked memory device 110 is shown in FIG. 1 , but the embodiment is not limited thereto, and one or more stacked memory devices may be formed on the adapter 140 around the processor 120 .

[0030] A plurality of processor microbumps 190A and 190B may be provided between the adapter 140 and the processor 120. The plurality of processor microbumps 190A and 190B may include solder balls or metal bumps. The plurality of processor microbumps 190A and 190B may include: a first processor microbump 190A for electrically connecting the processor 120 to the stacked memory device 110 through the adapter 140; and a second processor microbump 190B for electrically connecting the processor 120 to an external electronic device through the adapter 140 and the package substrate 160. The first processor microbump 190A may be provided closer to the stacked memory device 110 than the second processor microbump 190B.

[0031] The processor 120 may include a memory controller (MC) 121 and a physical interface (PHY) circuit 122 for interfacing with the memory controller 121. The memory controller 121 may be configured to control the stacked memory device 110 and the extended memory 130. The physical interface circuit 122 may be connected to the adapter 140 through the first processor microbump 190A to interface between the memory controller 121 and the stacked memory device 110. The physical interface circuit 122 may be used by the memory controller 121 to communicate with the stacked memory device 110. The physical interface circuit 122 may be an interface circuit that converts a signal transmitted from the memory controller 121 into a signal suitable for use in the stacked memory device 110 or the extended memory 130 and outputs it, or converts a signal transmitted from the stacked memory device 110 or the extended memory 130 into a signal suitable for use in the memory controller 121. For reference, the conversion operation may include an operation for improving signal quality (such as a serial-to-parallel or parallel-to-serial conversion operation), a buffering operation, an impedance matching operation, a training operation, and an alignment operation. The physical interface circuit mentioned in the following description may be an interface circuit that converts a signal transmitted from a previous stage circuit into a signal suitable for use in a next stage circuit.

[0032] The processor 120 may be one of a variety of processors, such as a microprocessing unit (MPU), a graphics processing unit (GPU), a central processing unit (CPU), and a host processing unit (HPU). The processor 120 may exchange electrical signals with an external processor, a power source, or an input / output device through the second processor microbump 190B via the adapter 140 and the package substrate 160.

[0033] A plurality of memory microbumps 192A and 192B may be disposed between the adapter 140 and the stacked memory device 110. The plurality of memory microbumps 192A and 192B may include solder balls or metal bumps. The plurality of memory microbumps 192A and 192B may include: a first memory microbump 192A for electrically connecting the stacked memory device 110 and the processor 120 through the adapter 140; and a second memory microbump 192B for electrically connecting the stacked memory device 110 and the extended memory 130 through the adapter 140, the package substrate 160, and the printed circuit board 150. The first memory microbump 192A may be electrically connected to the first processor microbump 190A through the interconnection inside the adapter 140, and may be disposed closer to the processor 120 than the second memory microbump 192B. The second memory microbump 192B may be electrically connected to the first inner bump 180A through the interconnection inside the adapter 140. The first inner bump 180A may be electrically connected to the second inner bump 180B through an interconnection in the package substrate 160. The second inner bump 180B may be electrically connected to the extended memory 130 through an interconnection in the printed circuit board 150. The second memory micro bump 192B may be disposed closer to the extended memory 130 than the first memory micro bump 192A. That is, the distance between the second memory micro bump 192B and the processor 120 may be greater than the distance between the first memory micro bump 192A and the processor 120. In addition, the distance between the first memory micro bump 192A and the extended memory 130 may be greater than the distance between the second memory micro bump 192B and the extended memory 130.

[0034] The stacked memory device 110 may include a lower chip 114 and one or more upper chips 112_0 to 112_3 vertically stacked on an adapter 140. An example of the stacked memory device 110 formed by stacking a plurality of chips as described above may be a high bandwidth memory (HBM). Hereinafter, the lower chip 114 is referred to as a base die 114, and the upper chips 112_0 to 112_3 are referred to as core dies 112_0 to 112_3. Figure 1 In the embodiment, the case where the first to fourth core dies 112_0 to 112_3 are stacked on the base die 114 is taken as an example for description.

[0035] Through-electrode TSVs may be formed between the stacked first to fourth core dies 112_0 to 112_3, so that signals (i.e., commands, addresses, and data) may be transmitted between the first to fourth core dies 112_0 to 112_3 and the base die 114. Between the first to fourth core dies 112_0 to 112_3, i.e., between the through-electrode TSVs, a plurality of inter-die microbumps 115 may be provided. The inter-die microbumps 115 may electrically connect the through-electrode TSVs between the first to fourth core dies 112_0 to 112_3. The inter-die microbumps 115 may include solder balls or metal bumps.

[0036] The base die 114 may include a first physical interface circuit (PHY1) 1142 for interfacing with the memory controller 121, and a second physical interface circuit (PHY2) 1144 for interfacing with the expansion memory 130. In another embodiment, the base die 114 may further include a third physical interface circuit for interfacing with the first to fourth core dies 112_0 to 112_3 through through-electrode TSVs.

[0037] The first physical interface circuit 1142 of the base die 114 may be electrically connected to the physical interface circuit 122 of the processor 120 through the first memory micro-bump 192A, the interconnection in the adapter 140, and the first processor micro-bump 190A. That is, the physical interface circuits 1142 and 122 may be electrically connected to and communicate with each other through the adapter 140. The second physical interface circuit 1144 of the base die 114 may be electrically connected to the printed circuit board 150 through the second memory micro-bump 192B, the interconnection in the adapter 140, the first inner bump 180A, the interconnection in the package substrate 160, and the second inner bump 180B.

[0038] The expansion memory 130 may be formed on the printed circuit board 150. The expansion memory 130 may include a core area for storing data and input and output (input / output) circuits for interfacing with external devices. The input / output circuits of the expansion memory 130 may include physical interface circuits. The expansion memory 130 may be configured as a low power double data rate (LPDDR) type dynamic random access memory (DRAM). When the expansion memory 130 is formed on the printed circuit board 150, the expansion memory 130 may have a dual in-line memory module (DIMM) form factor. However, the embodiment is not limited thereto, and the expansion memory 130 may be a DDR synchronous DRAM (SDRAM), a graphic DDR SDRAM, a Rambus DRAM (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. Although Figure 1 Only one expansion memory 130 is shown in the figure, but the embodiment is not limited thereto, and one or more expansion memories may be formed on the printed circuit board 150.

[0039] A plurality of extended micro bumps 194 may be disposed between the printed circuit board 150 and the extended memory 130. The plurality of extended micro bumps 194 may electrically connect the printed circuit board 150 and the extended memory 130. The plurality of extended micro bumps 194 may include solder balls or metal bumps.

[0040] The extended memory 130 can be coupled to the printed circuit board 150 through the extended micro bumps 194, and the printed circuit board 150 can be coupled to the adapter 140 through its internal interconnection, the second inner bump 180B and the first inner bump 180A. Therefore, the extended memory 130 and the second physical interface circuit 1144 can be electrically connected through the adapter 140, the package substrate 160 and the printed circuit board 150 to communicate with each other.

[0041] According to an embodiment, the adapter 140 and the expansion memory 130 may be disposed on the package substrate 160 to be spaced apart from each other, and the stacked memory device 110 and the processor 120 may be formed on the adapter 140. That is, the semiconductor package 100 may have a configuration in which the expansion memory 130 is spaced apart from each other. Figure 1 The configuration of removing the printed circuit board 150 and the extended micro bump 194. Therefore, the extended memory 130 and the second physical interface circuit 1144 can be electrically connected through the adapter 140 and the package substrate 160 to communicate with each other.

[0042] Figure 2 The present invention is shown in Figure 1 FIG. 1 is a perspective view of a stacked memory device 110 shown in FIG.

[0043] refer to Figure 2 , each of the first to fourth core dies 112_0 to 112_3 may include two or more channels. Each channel may constitute an independent command, address, and data interface. Figure 2 In the example of, since one core die includes four channels, the stacked memory device 110 may have first to sixteenth channels CH0 to CH15. For example, the first core die 112_0 may include a core region corresponding to the first to fourth channels CH0 to CH3, and the second core die 112_1 may include a core region corresponding to the fifth to eighth channels CH4 to CH7. The third core die 112_2 may include a core region corresponding to the ninth to twelfth channels CH8 to CH11, and the fourth core die 112_3 may include a core region corresponding to the thirteenth to sixteenth channels CH12 and CH15. The core region may include a plurality of memory banks, the memory banks include a cell array for storing data, and each memory bank may include a memory cell coupled to a word line and a bit line, a row decoder, a column decoder, and a sense amplifier, etc.

[0044] Furthermore, a plurality of through-electrode TSVs passing through the first to fourth core dies 112_0 to 112_3 may be respectively disposed in TSV regions 1122 corresponding to the first to sixteenth channels CH0 to CH15. When each channel has a bandwidth of 64 bits, the through-electrode TSVs and corresponding I / O cells may be configured to transmit 1024 bits of data.

[0045] The base die 114 can be connected to Figure 1 For example, the base die 114 may transmit signals between the memory controller 121 and the first to fourth core dies 112_0 to 112_3, or transmit signals between the memory controller 121 and the extended memory 130. The base die 114 may be divided into a first physical area SOC_PHY, a second physical area EXM_PHY, and a TSV area TSVA.

[0046] The first physical region SOC_PHY may be provided with an I / O circuit (ie, Figure 1 The first physical area SOC_PHY may be arranged in a first edge area of ​​the base die 114 adjacent to the memory controller 121. The second physical area EXM_PHY may be provided with an I / O circuit for interfacing with the expansion memory 130 (i.e., Figure 1The second physical interface circuit 1144 of the first to fourth core dies 112_0 to 112_3 may be provided. The second physical region EXM_PHY may be arranged in a second edge region of the base die 114 adjacent to the extended memory 130. The second edge region may be arranged in a direction opposite to the first edge region based on the TSV region TSVA. The TSV region TSVA may be provided with an I / O circuit (e.g., a third physical interface circuit 1146) for connecting to the through-electrode TSV passing through the first to fourth core dies 112_0 to 112_3. The TSV region TSVA may be located between the first physical region SOC_PHY and the second physical region EXM_PHY, that is, the TSV region TSVA may be arranged in the central region of the base die 114.

[0047] The first physical interface circuit 1142 may transfer signals between the memory controller 121 and the second physical interface circuit 1144, or between the memory controller 121 and the third physical interface circuit 1146. The first physical interface circuit 1142 may transfer signals (e.g., commands, addresses, and data) from the memory controller 121 to the second physical interface circuit 1144 or the third physical interface circuit 1146, and transfer signals (e.g., data) from the second physical interface circuit 1144 or the third physical interface circuit 1146 to the memory controller 121.

[0048] The second physical interface circuit 1144 may transfer signals between the first physical interface circuit 1142 and the extended memory 130. The second physical interface circuit 1144 may transfer signals (e.g., commands, addresses, and data) from the first physical interface circuit 1142 to the extended memory 130, and transfer signals (e.g., data) from the extended memory 130 to the first physical interface circuit 1142.

[0049] The third physical interface circuit 1146 may transmit signals between the first physical interface circuit 1142 and the first to fourth core dies 112_0 to 112_3 through the through-electrodes TSV. The third physical interface circuit 1146 may transmit signals (e.g., commands, addresses, and data) from the first physical interface circuit 1142 to the fourth core dies 112_0 to 112_3 through the through-electrodes TSV, and transmit signals (e.g., data) from the first to fourth core dies 112_0 to 112_3 to the first physical interface circuit 1142 through the through-electrodes TSV.

[0050] The configuration of the base die 114 according to an embodiment of the present disclosure will be described below with reference to the accompanying drawings. In the following embodiment, a case where two extended memories are formed on the printed circuit board 150 will be described as an example.

[0051] Figure 3 The present invention is shown in Figure 2 A detailed configuration diagram of the base die 114 is shown in FIG. Figure 4 It is shown Figure 3 Configuration diagram of the main memory interface logic 1142A of the first physical interface circuit 1142.

[0052] refer to Figure 3 The memory controller 121 of the processor 120 can generate signals (e.g., commands, addresses, and data) for respectively controlling the stacked memory device 110 and the first and second extended memories 132 and 134, and transmit the signals to the physical interface circuit 122, or receive signals (e.g., data) transmitted from the physical interface circuit 122.

[0053] The physical interface circuit 122 may include a main process interface logic 122A, a first sub-process interface logic 122B, and a second sub-process interface logic 122C. The main process interface logic 122A may transmit a first signal S1 for the stacked memory device 110 between the memory controller 121 and the first physical interface circuit 1142. The first sub-process interface logic 122B may transmit a second signal S2 for the first extended memory 132 between the memory controller 121 and the first physical interface circuit 1142. The second sub-process interface logic 122C may transmit a third signal S3 for the second extended memory 134 between the memory controller 121 and the first physical interface circuit 1142.

[0054] The first physical interface circuit 1142 of the base die 114 may include a main memory interface logic 1142A, a first sub-memory interface logic 1142B, and a second sub-memory interface logic 1142C. The main memory interface logic 1142A may transmit first signals S1 and S1' between the main process interface logic 122A and the third physical interface circuit 1146. The first sub-memory interface logic 1142B may transmit second signals S2 and S2' between the first sub-process interface logic 122B and the second physical interface circuit 1144. The second sub-memory interface logic 1142C may transmit third signals S3 and S3' between the second sub-process interface logic 122C and the second physical interface circuit 1144. Figure 4 As shown, the main memory interface logic 1142A may include first to sixteenth channel interfaces IF_CH0 to IF_CH15, and the first to sixteenth channel interfaces IF_CH0 to IF_CH15 are used to connect to the first to sixteenth channels CH0 to CH15 of the first to fourth core dies 112_0 to 112_3 respectively. The first to sixteenth channel interfaces IF_CH0 to IF_CH15 may be connected to the first to sixteenth channels CH0 to CH15 of the first to fourth core dies 112_0 to 112_3 respectively. Figure 1The first memory micro bump 192A is electrically connected to the main process interface logic 122A to transmit and receive the first signal S1, and can be electrically connected to the third physical interface circuit 1146 through internal interconnection to transmit and receive the first signal S1'.

[0055] The second physical interface circuit 1144 of the base die 114 may include a first extended memory interface logic 1144A and a second extended memory interface logic 1144B. The first extended memory interface logic 1144A may transmit second signals S2' and S2". between the first sub-memory interface logic 1142B and the first extended memory 132. For example, the first extended memory interface logic 1144A may perform an operation of converting the second signal S2' transmitted from the first sub-memory interface logic 1142B into the second signal S2" according to the input / output standard of the first extended memory 132, or may perform an operation of converting the second signal S2" transmitted from the first extended memory 132 into the second signal S2' according to the input / output standard of the base die 114. The second extended memory interface logic 1144B may transmit third signals S3' and S3" between the second sub-memory interface logic 1142C and the second extended memory 134. For example, the second extended memory interface logic 1144B may perform an operation of converting the third signal S3' transmitted from the second sub-memory interface logic 1142C into a third signal S3" according to the input / output standard of the second extended memory 134, or converting the third signal S3" transmitted from the second extended memory 134 into a third signal S3' according to the input / output standard of the base die 114.

[0056] For reference, the first signals S1 and S1' can be signals transmitted in accordance with the input / output standard of a stacked memory device (e.g., HBM) to provide high bandwidth, and the number of bits of data can be determined according to the bandwidth of the channel (or channel interface) of the core die. For example, when the bandwidth of each channel is 32 bytes, the first to sixteenth channel interfaces IF_CH0 to IF_CH15 can transmit and receive signals in units of 32 bytes, respectively. On the other hand, the second signals S2, S2' and S2" and the third signals S3, S3' and S3" can be signals transmitted in accordance with the input / output standard of an LPDDR type DRAM to provide low power consumption. For example, the number of bits of data can be transmitted and received in units of 32 bytes or less. That is, the second signals S2, S2' and S2" and the third signals S3, S3' and S3" can be transmitted with a lower bandwidth than the first signals S1 and S1'.

[0057] The operation of the base die 114 having the above-described configuration will be described as follows.

[0058] During a write operation, the memory controller 121 may generate a signal for controlling the stacked memory device 110, and the main process interface logic 122A may transmit the first signal S1 to the main memory interface logic 1142A. The main memory interface logic 1142A may convert the first signal S1 to transmit the first signal S1' to the third physical interface circuit 1146, and the third physical interface circuit 1146 may transmit the first signal S1' to the first to fourth core dies 112_0 to 112_3 through the through-electrode TSV. Alternatively, the memory controller 121 may generate a signal for controlling the first extended memory 132 and / or the second extended memory 134, the first sub-process interface logic 122B may transmit the second signal S2 to the first sub-memory interface logic 1142B, and the second sub-process interface logic 122C may transmit the third signal S3 to the second sub-memory interface logic 1142C. The first sub-memory interface logic 1142B can convert the second signal S2 to transmit the second signal S2' to the first extended memory interface logic 1144A, and the first extended memory interface logic 1144A can convert the second signal S2' to transmit the second signal S2" to the first extended memory 132. Similarly, the second sub-memory interface logic 1142C can convert the third signal S3 to transmit the third signal S3' to the second extended memory interface logic 1144B, and the second extended memory interface logic 1144B can convert the third signal S3' to transmit the third signal S3" to the second extended memory 134.

[0059] During a read operation, the third physical interface circuit 1146 may transmit a first signal S1′ transmitted from the first to fourth core dies 112_0 to 112_3 through the through-electrodes TSV to the main memory interface logic 1142A, and the main memory interface logic 1142A may convert the first signal S1′ to transmit the first signal S1 to the processor 120. The first extended memory interface logic 1144A may convert a second signal S2″ transmitted from the first extended memory 132 to transmit the second signal S2′ to the first sub-memory interface logic 1142B, and the first sub-memory interface logic 1142B may convert the second signal S2′ to transmit the second signal S2 to the processor 120. Similarly, the second extended memory interface logic 1144B may convert a third signal S3″ transmitted from the second extended memory 134 to transmit the third signal S3′ to the second sub-memory interface logic 1142C, and the second sub-memory interface logic 1142C may convert the third signal S3′ to transmit the third signal S3 to the processor 120.

[0060] For reference, during a write operation or a read operation, the first signals S1 and S1 ′, the second signals S2 , S2 ′ and S2 ″, and the third signals S3 , S3 ′ and S3 ′″ may be transmitted simultaneously or individually.

[0061] As described above, according to an embodiment of the present disclosure, an expandable interface circuit is provided on the base die 114 of the stacked memory device 110 to connect the additional expansion memories 132 and 134, and the memory controller 121 can control the stacked memory device 110 and the expansion memories 132 and 134. That is, by connecting the additional expansion memory in the semiconductor package, the capacity of the semiconductor package can be expanded.

[0062] Figure 5 Another embodiment of the present disclosure is shown in FIG. Figure 2 A detailed configuration diagram of the base die 114 is shown in FIG.

[0063] See also Figure 5 The memory controller 121 may generate signals (e.g., commands, addresses, and data) for controlling the stacked memory device 110 and the first and second extended memories 132 and 134, respectively, and transmit the signals to the physical interface circuit 122, or receive signals (e.g., data) transmitted from the physical interface circuit 122. The physical interface circuit 122 may transmit a signal S1 for controlling the stacked memory device 110 and the first and second extended memories 132 and 134 between the memory controller 121 and the first physical interface circuit 1142.

[0064] according to Figure 5 The base die 114 of the embodiment includes the following Figure 3 In addition to the first to third physical interface circuits 1142 to 1146 shown, an arbitrator 1143 and an expansion controller 1145 may also be included.

[0065] The arbitrator 1143 may receive a signal S1 transmitted from the first physical interface circuit 1142, and determine whether the input signal S1 corresponds to the core die or the extended memories 132 and 134 of the stacked memory device 110. The arbitrator 1143 may transmit the input signal S1 to the third physical interface circuit 1146 or the extended controller 1145 according to the determination result. In addition, the arbitrator 1143 may receive signals S2 and S3 transmitted from the third physical interface circuit 1146 or the extended controller 1145, and transmit the signals S2 and S3 to the first physical interface circuit 1142. The arbitrator 1143 may include a first arbitration logic 1143A and a second arbitration logic 1143B corresponding to the first extended memory 132 and the second extended memory 134, respectively. The arbitrator 1143 may be provided in the first physical region SOC_PHY together with the first physical interface circuit 1142.

[0066] The expansion controller 1145 may include a first expansion control logic 1145A and a second expansion control logic 1145B corresponding to the first expansion memory 132 and the second expansion memory 134, respectively. The first expansion control logic 1145A may generate a signal (e.g., command, address, and data) for controlling the first expansion memory 132 according to the signal S2 transmitted from the first arbitration logic 1143A, and schedule and transmit the generated signal to the second physical interface circuit 1144, or transmit the signal (e.g., data) provided from the second physical interface circuit 1144 to the first arbitration logic 1143A. The second expansion control logic 1145B may generate a signal (e.g., command, address, and data) for controlling the second expansion memory 134 according to the signal S3 transmitted from the second arbitration logic 1143B, and schedule and transmit the generated signal to the second physical interface circuit 1144, or transmit the signal (e.g., data) provided from the second physical interface circuit 1144 to the second arbitration logic 1143B. The expansion controller 1145 may be provided in the second physical area EXM_PHY together with the second physical interface circuit 1144.

[0067] The second physical interface circuit 1144 may include a first extended memory interface logic 1144A and a second extended memory interface logic 1144B. The first extended memory interface logic 1144A may transmit a signal S2" between the first extended control logic 1145A and the first extended memory 132. The second extended memory interface logic 1144B may transmit a signal S3" between the second extended control logic 1145B and the second extended memory 134.

[0068] The operation of the base die 114 having the above-described configuration will be described as follows.

[0069] During a write operation, when a signal S1 corresponding to the core die of the stacked memory device 110 is transmitted from the processor 120, the first physical interface circuit 1142 may convert and transmit the signal S1 to the first arbitration logic 1143A and the second arbitration logic 1143B, and the first arbitration logic 1143A and the second arbitration logic 1143B may transmit signals S2 and S3 to the third physical interface circuit 1146. On the other hand, when a signal S1 corresponding to the first extended memory 132 is transmitted from the processor 120, the first physical interface circuit 1142 may convert and transmit the signal S1 to the first arbitration logic 1143A, and the first arbitration logic 1143A may transmit the signal S2 to the first extended control logic 1145A. The first extended control logic 1145A may generate a signal (such as a command, an address, data) for controlling the first extended memory 132 according to the signal S2, and schedule and transmit the signal to the first extended memory 132 through the second physical interface circuit 1144. Substantially the same write operation may be performed on the second extended memory 134.

[0070] During a read operation, the third physical interface circuit 1146 may transmit signals S2 and S3 transmitted from the core die through the through-electrode TSV to the first arbitration logic 1143A and the second arbitration logic 1143B. The first arbitration logic 1143A and the second arbitration logic 1143B may transmit the signals S2 and S3 to the first physical interface circuit 1142, and the first physical interface circuit 1142 may transmit the signal S1 to the processor 120. On the other hand, the first extended memory interface logic 1144A may convert a signal S2″ transmitted from the first extended memory 132 to the first extended control logic 1145A, and the first extended control logic 1145A may transmit the signal S2 to the first arbitration logic 1143A. The first arbitration logic 1143A may transmit the signal S2 to the first physical interface circuit 1142, and the first physical interface circuit 1142 may transmit the signal S1 to the processor 120. Substantially the same read operation may be performed on the second extended memory 134.

[0071] Figure 6 To illustrate another embodiment of the present disclosure Figure 2 A detailed configuration diagram of the base die 114 is shown in FIG.

[0072] refer to Figure 6The memory controller 121 may generate signals (e.g., commands, addresses, and data) for controlling the stacked memory device 110 and the first and second extended memories 132 and 134, respectively, and transmit the signals to the physical interface circuit 122, or receive signals (e.g., data) transmitted from the physical interface circuit 122. The physical interface circuit 122 may transmit a signal S1 for controlling the stacked memory device 110 and the first and second extended memories 132 and 134 between the memory controller 121 and the first physical interface circuit 1142.

[0073] according to Figure 6 The base die 114 of the embodiment of the present invention may further include a path controller 1147 in addition to the first to third physical interface circuits 1142 to 1146. The path controller 1147 may determine whether the signal S1 transmitted from the first physical interface circuit 1142 corresponds to the core die or the extended memories 132 and 134 of the stacked memory device 110. The path controller 1147 may transmit the input signal S1 to the second physical interface circuit 1144 or the third physical interface circuit 1146, or transmit the signals S2 and S3 from the second physical interface circuit 1144 or the third physical interface circuit 1146 to the first physical interface circuit 1142, according to the determination result. The path controller 1147 may be provided in the first physical region SOC_PHY together with the first physical interface circuit 1142.

[0074] The path controller 1147 may include a first path control logic 1147A and a second path control logic 1147B corresponding to the first expansion memory 132 and the second expansion memory 134, respectively. The first path control logic 1147A and the second path control logic 1147B may determine whether the signal S1 transmitted from the first physical interface circuit 1142 corresponds to the core die of the stacked memory device 110 or the expansion memories 132 and 134.

[0075] According to the determination result, the first path control logic 1147A may transfer the input signal S1 to the second physical interface circuit 1144 or the third physical interface circuit 1146, or transfer the signal S2 from the second physical interface circuit 1144 or the third physical interface circuit 1146 to the first physical interface circuit 1142. For example, if it is determined that the input signal S1 corresponds to the first extension memory 132, the first path control logic 1147A may generate a signal for controlling the first extension memory 132, and schedule and transfer the signal S2 to the second physical interface circuit 1144.

[0076] According to the determination result, the second path control logic 1147B may transmit the input signal S1 to the second physical interface circuit 1144 or the third physical interface circuit 1146, or transmit the signal S3 from the second physical interface circuit 1144 or the third physical interface circuit 1146 to the first physical interface circuit 1142. For example, if it is determined that the signal S1 corresponds to the second extension memory 134, the second path control logic 1147B may generate a signal for controlling the second extension memory 134, and schedule and transmit the signal S3 to the second physical interface circuit 1144.

[0077] According to an embodiment, the path controller 1147 may further include an encryption key storage device storing a plurality of encryption keys. The path controller 1147 may select one of the encryption keys stored in the encryption key storage device during startup, and use the selected encryption key to encrypt the signal S1 transmitted from the first physical interface circuit 1142 to transmit the signal S2 (i.e., the encrypted signal) to the second physical interface circuit 1144 or the third physical interface circuit 1146. In addition, the path controller 1147 may decrypt the signals S2 and S3 transmitted from the second physical interface circuit 1144 or the third physical interface circuit 1146 using the selected encryption key, and transmit the signals S2 and S3 (i.e., the decrypted signals) to the first physical interface circuit 1142.

[0078] According to an embodiment, the path controller 1147 may further include a power storage device storing a plurality of voltage states. The path controller 1147 may select one of the plurality of voltage states by verifying the power consumption of the stacked memory device 110 and the expansion memories 132 and 134, and control the power distribution of the stacked memory device 110 and the expansion memories 132 and 134 according to the selected voltage state. For example, if it is determined that the power consumed by the stacked memory device 110 increases, the path controller 1147 may select a voltage state for increasing the power provided to the stacked memory device 110.

[0079] The second physical interface circuit 1144 may include a first extended memory interface logic 1144A and a second extended memory interface logic 1144B. The first extended memory interface logic 1144A may transmit signals S2 and S2″ between the first path control logic 1147A and the first extended memory 132. The second extended memory interface logic 1144B may transmit signals S3 and S3″ between the second path control logic 1147B and the second extended memory 134.

[0080] The operation of the base die 114 having the above-described configuration will be described as follows.

[0081] During a write operation, when a signal S1 corresponding to the core die of the stacked memory device 110 is transmitted from the processor 120, the first physical interface circuit 1142 may convert the signal S1 to transmit the signal to the first path control logic 1147A and the second path control logic 1147B, and the first path control logic 1147A and the second path control logic 1147B may transmit signals S2 and S3 to the third physical interface circuit 1146. On the other hand, when a signal S1 corresponding to the first extended memory 132 is transmitted from the processor 120, the first physical interface circuit 1142 may convert and transmit the signal S1 to the first path control logic 1147A, and the first path control logic 1147A may generate signals (e.g., commands, addresses, and data) for controlling the first extended memory 132, and schedule and transmit the signal S2 to the first extended memory interface logic 1144A. Substantially the same write operation may be performed on the second extended memory 134.

[0082] During a read operation, the third physical interface circuit 1146 may transmit signals S2 and S3 transmitted from the core die through the through-electrode TSV to the first path control logic 1147A and the second path control logic 1147B. The first path control logic 1147A and the second path control logic 1147B may transmit the signals to the first physical interface circuit 1142, and the first physical interface circuit 1142 may transmit the signal S1 to the processor 120. The first extended memory interface logic 1144A may convert a signal S2″ transmitted from the first extended memory 132 to transmit the signal S2 to the first path control logic 1147A, and the first physical interface circuit 1142 may transmit the first signal S1 to the processor 120. Substantially the same read operation may be performed on the second extended memory 134.

[0083] Fig. 7A and Figure 7B is a perspective view showing a semiconductor package 1000 according to an embodiment of the present disclosure.

[0084] refer to Fig. 7A , the semiconductor package 1000 may include a plurality of stacked memory devices 1100 , a processor 1200 , a plurality of expansion memories 1300 , an adapter 1400 , a plurality of printed circuit boards 1500 , and a package substrate 1600 .

[0085] A plurality of external bumps 1700 may be disposed on the bottom surface of the package substrate 1600. The adapter 1400 and the printed circuit board 1500 (eg, four printed circuit boards 1500) may be formed on the top surface of the package substrate 1600. The adapter 1400 and the printed circuit board 1500 may be disposed on the package substrate 1600 spaced apart from each other.

[0086] The stacked memory device 1100 (e.g., four stacked memory devices 1100) may be symmetrically formed around the processor 1200. The stacked memory device 1100 and the processor 1200 may be spaced apart from each other and disposed on the adapter 1400. The processor 1200 may include a memory controller (MC) 1210, and the memory controller 1210 may communicate with the processor 1200 through a physical interface circuit (e.g., the above-mentioned Figure 1-Figure 6 The processor 1200 may be electrically connected to the stacked memory device 1100 through a physical interface circuit. For example, the processor 1200 may include four physical interface circuits corresponding to four stacked memory devices 1100, respectively.

[0087] Each stacked memory device 1100 may include a base die and one or more core dies vertically stacked on an adapter 1400. Each base die may be electrically connected to one physical interface circuit of the processor 1200 through a first physical interface circuit and may be electrically connected to the printed circuit board 1500 through a second physical interface circuit.

[0088] A plurality of expansion memories 1300 may be formed on each printed circuit board 1500. One or more expansion memories 1300 may be electrically connected to the second physical interface circuit of the base die through the printed circuit board 1500, the package substrate 1600, and the adapter 1400. Therefore, the expansion memory 1300 and the second physical interface circuit of the base die may be electrically connected through the adapter 1400, the package substrate 1600, and the printed circuit board 1500 to communicate with each other.

[0089] According to an embodiment, the semiconductor package 1000 may have a Fig. 7A The semiconductor package 1000 is configured by removing the printed circuit board 1500. That is, referring to Figure 7B , the semiconductor package 1000 may include a plurality of stacked memory devices 1100, a processor 1200, a plurality of expansion memories 1300, an adapter 1400, and a package substrate 1600. The adapter 1400 and the expansion memory 1300 may be disposed on the package substrate 1600 spaced apart from each other, and the stacked memory device 1100 and the processor 1200 may be formed on the adapter 1400. Therefore, the expansion memory 1300 and the second physical interface circuit of the base die may be electrically connected through the adapter 1400 and the package substrate 1600 to communicate with each other.

[0090] While embodiments of the present disclosure have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims.

[0091] For example, the logic gates and transistors described in the above embodiments may have different locations and types depending on the polarity of the input signal. Furthermore, the embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor package, comprising: Package substrate; An adapter, which is arranged on the packaging substrate; A stacked semiconductor device comprising a lower chip and one or more upper chips sequentially stacked on the adapter; A first semiconductor chip stacked on the adapter and spaced apart from the stacked semiconductor device and connected to the lower chip; as well as One or more second semiconductor chips are disposed on the package substrate to be connected with the lower chip.

2. The semiconductor package according to claim 1, wherein The lower chip comprises: A first interface circuit is disposed in the first region to interface with the first semiconductor chip through the adapter; and One or more second interface circuits are disposed in the second region to interface with the one or more second semiconductor chips through the adapter and the package substrate.

3. The semiconductor package according to claim 2, in, The first region is disposed closer to the first semiconductor chip than to the one or more second semiconductor chips, and The second region is disposed closer to the one or more second semiconductor chips than to the first semiconductor chip.

4. The semiconductor package according to claim 3, wherein: The lower chip further includes a third interface circuit disposed between the first region and the second region to interface with the one or more upper chips through the through electrodes.

5. The semiconductor package according to claim 4, wherein: The first interface circuit comprises: a main interface logic that transmits a first signal for the one or more upper chips between the first semiconductor chip and the third interface circuit; and One or more sub-interface logics that transmit second signals for the one or more second semiconductor chips between the first semiconductor chip and the one or more second interface circuits.

6. The semiconductor package according to claim 5, wherein: The second signal is transmitted with a lower bandwidth than the first signal.

7. The semiconductor package according to claim 5, in, Each of the one or more upper chips includes a plurality of channels, and The main interface logic includes a plurality of channel interfaces, the plurality of channel interfaces respectively correspond to the plurality of channels, and each channel interface inputs and outputs signals with a corresponding channel.

8. The semiconductor package according to claim 4, wherein: The lower chip further comprises: an arbiter that determines whether a signal input from the first interface circuit corresponds to the one or more upper chips or one or more second semiconductor chips, and provides the input signal to the third interface circuit or one or more expansion controllers according to the determination result; and The one or more expansion controllers generate signals corresponding to the one or more second semiconductor chips according to the input signal transmitted from the arbitrator, and transmit the generated signals to the second interface circuit.

9. The semiconductor package according to claim 4, wherein: The lower chip also includes one or more path controllers, which determine whether the signal input from the first interface circuit corresponds to the one or more upper chips or the one or more second semiconductor chips, and provide the input signal to the second interface circuit or the third interface circuit based on the determination result.

10. The semiconductor package according to claim 1, further comprising: a printed circuit board, which is disposed on the packaging substrate and is spaced apart from the adapter, Wherein, the one or more second semiconductor chips are arranged on the printed circuit board.

11. The semiconductor package according to claim 1, in, The stacked semiconductor device includes an HBM, and the lower chip includes a base die of the HBM, HBM referring to High Bandwidth Memory.

12. The semiconductor package according to claim 1, in, The first semiconductor chip includes a memory controller, and the one or more second semiconductor chips include LPDDR type DRAM, LPDDR refers to Low Power Double Data Rate, DRAM refers to Dynamic Random Access Memory.

13. The semiconductor package according to claim 1, further comprising: a plurality of first micro bumps disposed between the adapter and the lower chip and electrically connected to the first semiconductor chip through the adapter; as well as A plurality of second micro bumps are disposed between the interposer and the lower chip and are electrically connected to the one or more second semiconductor chips through the interposer and the package substrate.

14. The semiconductor package according to claim 13, in, The distance between the second microbump and the first semiconductor chip is greater than the distance between the first microbump and the first semiconductor chip, and Wherein, a distance between the first micro-bump and the one or more second semiconductor chips is greater than a distance between the second micro-bump and the one or more second semiconductor chips.

15. A stacked semiconductor device comprising: Chip down; as well as one or more upper chips stacked on the lower chip, The lower chip includes: a first interface circuit for connecting to the first semiconductor chip, one or more second interface circuits for connecting to one or more second semiconductor chips, and a third interface circuit for connecting to the one or more upper chips, and Wherein, the first interface circuit comprises: a main interface logic that transmits a first signal for the one or more upper chips between the first semiconductor chip and the third interface circuit; and One or more sub-interface logics that transmit second signals for the one or more second semiconductor chips between the first semiconductor chip and the one or more second interface circuits.

16. The stacked semiconductor device according to claim 15, in, The stacked semiconductor device and the first semiconductor chip are disposed on an adapter, the adapter is disposed on a packaging substrate, and Wherein, the one or more second semiconductor chips are arranged on the packaging substrate.

17. The stacked semiconductor device according to claim 15, in, The stacked semiconductor device and the first semiconductor chip are disposed on an adapter, and The one or more second semiconductor chips are spaced apart from the adapter and are disposed on a printed circuit board spaced apart from the adapter.

18. The stacked semiconductor device according to claim 15, in, The first interface circuit is disposed in a first region, the first region being arranged closer to the first semiconductor chip than to the one or more second semiconductor chips, wherein the second interface circuit is disposed in a second region, the second region being closer to the one or more second semiconductor chips than to the first semiconductor chip, and Wherein, the third interface circuit is arranged between the first area and the second area.

19. The stacked semiconductor device according to claim 15, wherein: The second signal is transmitted with a lower bandwidth than the first signal.

20. The stacked semiconductor device according to claim 15, wherein: The lower chip further comprises: an arbiter that determines whether a signal input from the first interface circuit corresponds to the one or more upper chips or the one or more second semiconductor chips, and provides the input signal to the third interface circuit or the one or more expansion controllers according to the determination result; and The one or more expansion controllers generate signals corresponding to the one or more second semiconductor chips according to the input signal transmitted from the arbitrator, and transmit the generated signals to the second interface circuit.

21. The stacked semiconductor device according to claim 15, wherein: The lower chip further comprises: One or more path controllers determine whether a signal input from the first interface circuit corresponds to the one or more upper chips or the one or more second semiconductor chips, and provide the input signal to the second interface circuit or the third interface circuit according to the determination result.

22. The stacked semiconductor device according to claim 21, wherein: Each of the path controllers encrypts a signal input from the first interface circuit using an encryption key selected from among a plurality of encryption keys.

23. The stacked semiconductor device according to claim 21, wherein: Each of the path controllers stores a plurality of voltage states, selects one of the plurality of voltage states by verifying power consumption of the stacked semiconductor device and the one or more second semiconductor chips, and controls power distribution of the stacked semiconductor device and the one or more second semiconductor chips according to the selected voltage state.

Images