Method for packaging offset stacked DRAM structure

Abstract

The present invention relates to the technical field of packaging structure, and more particularly to a method for packaging an offset stacked DRAM structure. Steps: The DRAM chip is a chip, and the back of the first chip is pasted on a temporary base; the back of another chip is pasted offset on the front of the first chip; the remaining chips are also pasted in this way, and plastic-sealed, and multiple through holes are formed in the stacked chip after plastic sealing by drilling, and each through hole is connected to a chip respectively; conductive material is filled in each through hole to form a TMV structure, and a redistribution layer is formed on the front of the stacked chip after the TMV, and a bump is formed on the redistribution layer, and the temporary base is removed to obtain the required structure; wherein, when offset stacking, it is not calculated from the first chip, but from the second chip thereafter, and the offset direction of every two chips is the same, and the offset direction is changed after every two chips are stacked. The present invention realizes the stacking of multiple DRAM chips, optimizes the packaging structure, and reduces the difficulty of packaging.

Description

Technical Field

[0001] The present invention relates to the technical field of packaging structures, and more particularly, to a method for packaging an offset stacked DRAM structure. Background Art

[0002] Although existing technologies such as through silicon via (TSV) packaging and ball grid array (BGA) packaging can reduce the volume to a certain extent, their complex manufacturing process and high cost are still problems that need to be solved. The stability of the interlayer connection during the packaging process directly affects the reliability and performance of the final product. In addition, the offset stacking of multiple chips further increases the difficulty of constructing the packaging structure. Therefore, those skilled in the art are faced with the problem of how to optimize the relevant packaging structure and packaging method. Summary of the invention

[0003] In view of the prior art, the present invention provides a method for packaging an offset stacked DRAM structure to solve the above-mentioned problems.

[0004] The present invention provides a method for packaging an offset stacked DRAM structure, comprising the following steps:

[0005] Glue the back of the first DRAM chip to the temporary base;

[0006] Offset stacking: Paste the back of another DRAM chip offset from the front of the first DRAM chip; the remaining DRAM chips are also pasted on the back of the previous DRAM chip in this way to obtain multi-layer offset stacked DRAM chips, which are then plastic-sealed to obtain plastic-sealed stacked chips;

[0007] A plurality of through holes are formed in the stacked chip after plastic encapsulation by drilling, and each through hole is connected to a DRAM chip; a conductive material is filled in each through hole to form a TMV structure, and a stacked chip after TMV is obtained; a redistribution layer is formed on the front of the stacked chip after TMV by RDL technology, and the redistribution layer is connected to the TMV structure, and a stacked chip after RDL is obtained; a bump is formed on the redistribution layer of the stacked chip after RDL by bump technology, and a temporary base attached to the back of the stacked chip is removed to obtain an offset stacked DRAM structure;

[0008] When offset stacking is performed, the calculation is not started from the first DRAM chip, but from the second DRAM chip thereafter. The offset direction of every two DRAM chips is the same, and the offset direction is changed after every two DRAM chips are stacked.

[0009] In some embodiments, when drilling, the direction of the through hole connected to the first DRAM chip is the same as the direction of the through hole connected to the second DRAM chip, and the direction of the through hole connected to each subsequent DRAM chip is different from the previous one.

[0010] Furthermore, in some embodiments, a more specific packaging method is provided by taking 4 DRAMs as an example.

[0011] In some embodiments, a grinding process is used to thin the front side of the plastic-encapsulated stacked chips, and drilling is performed after the front side is thinned.

[0012] In some embodiments, the conductive material includes conductive paste and self-made conductive material; the conductive paste includes conductive silver paste.

[0013] The following is a method for preparing a homemade conductive material, comprising the following steps:

[0014] adding copper nanoparticles to ethylene glycol under stirring conditions, and performing ultrasonic treatment to mix the mixture to obtain treated nanoparticles;

[0015] Under heating conditions, epoxy resin is added to xylene, and the mixture is stirred. A plasticizer is added while stirring, and the mixture is stirred evenly to obtain a resin solution.

[0016] Under stirring conditions, a portion of the treated nanoparticles are added to the resin solution and stirred, and the remaining treated nanoparticles are added again and stirred to ensure uniform dispersion, thereby obtaining a self-made conductive material.

[0017] In some embodiments, when the homemade conductive material is used, the homemade conductive material is taken, a curing agent is added during stirring, and the stirring is continued to be uniform to obtain a usable conductive material, which is then filled into the through hole and cured.

[0018] In some embodiments, the copper nanoparticles have a particle size of 50-200 nm.

[0019] In some embodiments, the epoxy resin has a viscosity of 500-1500 cP.

[0020] In some embodiments, the plasticizer comprises at least one of a renewable vegetable oil-based plasticizer, glycerol, and the renewable vegetable oil-based plasticizer comprises epoxidized soybean oil.

[0021] In some embodiments, when the homemade conductive material is used, the homemade conductive material is taken, polyetheramine is added while stirring, and the stirring is continued to be uniform, and then heated and stirred until it is evenly dispersed to obtain a usable conductive material, which is filled into the through hole and cured by heating.

[0022] According to the inventive concept of the present invention, the advantages and beneficial effects of the present invention are as follows:

[0023] There are at least two difficulties in the offset stacking structure. One is how to offset the stacking, and the other is how to construct the interconnection structure. The interconnection technology of the offset stacking structure is more complicated than that of the non-offset stacking structure.

[0024] With regard to the first difficulty mentioned above, the present invention is configured as follows: when performing offset stacking, the calculation is not started from the first DRAM chip, but from the second DRAM chip thereafter, and the offset direction of every two DRAM chips is the same, and the offset direction is changed after every two DRAM chips are stacked.

[0025] As for the second difficulty mentioned above, the prior art usually uses a thicker solder layer with a larger number of leads. The difference is that the present invention is configured as follows: a plurality of through holes are formed in the stacked chips after plastic packaging by drilling, and each through hole is connected to a DRAM chip respectively; conductive material is filled into each through hole to form a TMV structure, thereby obtaining the stacked chip after TMV.

[0026] It is further arranged that: when drilling, the direction of the through hole connected to the first DRAM chip is the same as the direction of the through hole connected to the second DRAM chip, and the direction of the through hole connected to each subsequent DRAM chip is different from the previous one.

[0027] In summary, firstly, the present invention realizes the stacking of multiple DRAM chips, optimizes the spatial layout, and can adapt to diverse application requirements. Secondly, the offset stacking design enhances the interconnection path between chips, improves the signal transmission efficiency, and reduces the difficulty and layout complexity of the overall packaging. The combination of laser drilling and TMV structure ensures good electrical connection. In addition, the conductive materials are self-made to reduce costs while retaining good conductivity and mechanical strength. The reasonable selection of conductive materials also further improves the reliability of the TMV structure, making the packaging technology more competitive in the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0029] Figure 1 It is a structural schematic diagram of the temporary base of the present invention;

[0030] Figure 2 It is a schematic diagram of the structure of the chip offset stacking on the temporary base of the present invention;

[0031] Figure 3 This is a schematic diagram of the structure of the plastic-encapsulated stacked chips of the present invention;

[0032] Figure 4 This is a schematic diagram of the structure of drilling holes in stacked chips according to the present invention;

[0033] Figure 5 It is a schematic diagram of the structure of the TMV structure and the redistribution layer of the present invention;

[0034] Figure 6 It is a structural schematic diagram of the bump of the present invention;

[0035] Figure 7 is a schematic diagram of the structure of the chip unit of the present invention; it should be noted that, Figure 7 It can also be seen as a flow chart, reflecting the process of chip unit formation;

[0036] Figure 1 to Figure 7 The combined embodiment shows the changes in the packaging structure in the packaging method of the present invention;

[0037] The following are marked in the figure: 1. Temporary base; 2. Paste material; 3. DRAM 01 chip; 4. DRAM 02 chip; 5. DRAM 03 chip; 6. DRAM 04 chip; 7. Molding compound; 8. Laser via; 9. TMV structure; 10. Insulation layer; 11. Lines and contacts; 12. Bumps. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in the field without creative work belong to the scope of protection of the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0039] The present invention provides a method for packaging an offset stacked DRAM structure, and obtains a corresponding offset stacked DRAM packaging structure according to the method. The number of DRAMs can be multiple, and the specific number is not limited.

[0040] In order to more clearly describe the technical solution, the following provides specific process steps by taking four DRAMs as an example. The DRAMs are DRAM 01, DRAM 02, DRAM 03, and DRAM 04. It is not required that the four DRAMs are completely identical, for example, it is not required that the size and thickness of the four DRAMs must be the same.

[0041] The method of packaging an offset stacked DRAM structure includes the following steps:

[0042] refer to Figure 1 , temporarily stick the back side of DRAM 01 chip 3 on the temporary base 1.

[0043] The back of DRAM 02 chip 4 is pasted on the front of DRAM 01 chip 3, the back of DRAM 03 chip 5 is pasted on the front of DRAM 02 chip 4, and the back of DRAM 04 chip 6 is pasted on the front of DRAM 03 chip 5. When pasting, the chips are stacked with an offset, and the chip offset directions can be inconsistent or consistent. After stacking, a multi-layer stacked chip is obtained.

[0044] The multi-layer stacked chips are integrally encapsulated with a molding compound 7 to obtain encapsulated stacked chips.

[0045] Optional step: Use a grinding process to thin the front side of the stacked chip after plastic encapsulation. The purpose of grinding is to thin the plastic encapsulation layer and reduce the thickness of the stacked chip. This step can be performed or not according to actual needs.

[0046] Drilling: Laser drilling is performed on the stacked chips after plastic encapsulation to form vertical laser through holes 8 in the stacked chips after plastic encapsulation. The front sides of the DRAM 04 chip 6 to the DRAM 01 chip 3 are connected to at least one laser through hole 8. The number of laser through holes 8 is determined according to actual conditions. Then, conductive materials are deposited, electroplated, or filled in the laser through holes 8 to form a TMV structure 9, thereby obtaining the stacked chips after TMV.

[0047] RDL: An insulating layer 10 is formed on the front side of the stacked chip after TMV, and a metal pattern is formed by photolithography, development, and metal deposition on the insulating layer 10. A redistribution layer is formed on the stacked chip after TMV, and the redistribution layer is connected to the TMV structure 9 to obtain the stacked chip after RDL.

[0048] By means of the bump technology, a bump 12 is formed on the redistribution layer of the stacked chip after the RDL, and then the temporary base 1 attached to the back of the stacked chip is removed, and then a cutting process is performed to obtain a chip unit. The bump technology and the cutting process use conventional methods in the art, and the principles thereof are known to those skilled in the art and will not be described in detail.

[0049] Example 1

[0050] The method of packaging an offset stacked DRAM structure includes the following steps:

[0051] refer to Figure 1 , temporarily stick the back of DRAM 01 chip 3 on the temporary base 1. Among them, the temporary sticking method can be to attach the sticking material 2 on the temporary base 1, the sticking material 2 can be a tape, and the corresponding sticking method is to use a sticking machine to stick the tape on the temporary base 1, the tape can be LC TAPE, and the chip back protection tape of Adwill LC can be purchased, and the tape can also be a double-sided adhesive tape. The sticking material 2 can also be a temporary bonding glue, and the corresponding sticking method is to solidify the temporary bonding glue on the temporary base 1. The temporary bonding glue can be purchased from 3M Company. The purchase method is provided here to better implement this embodiment, but it does not limit its purchase source.

[0052] Next, the back of DRAM 01 chip 3 is pasted on pasting material 2. The back of DRAM 02 chip 4 is pasted on the front of DRAM 01 chip 3, the back of DRAM 03 chip 5 is pasted on the front of DRAM 02 chip 4, and the back of DRAM 04 chip 6 is pasted on the front of DRAM 03 chip 5. The pasting method can be to use adhesive to paste the back of DRAM 02 chip 4 on the front of DRAM 01 chip 3. The pasting method of other chips is the same. The adhesive can be a polymer material, an adhesive material, or a DAF film. When pasting, the chips are offset and stacked, and the chip offset direction can be inconsistent or consistent.

[0053] refer to Figure 2 In this embodiment, when stacking with offset, DRAM 02 chip 4 is offset to the right relative to DRAM 01 chip 3, DRAM 03 chip 5 is offset to the right relative to DRAM 02 chip 4, and DRAM 04 chip 6 is offset to the left relative to DRAM 03 chip 5. The offset is understood as follows: when pasting, DRAM 02 chip 4 cannot completely cover DRAM 01 chip 3, and the other chips are the same. In order to better explain the direction, "left" and "right" are introduced. This direction is based on Figure 2 The description expresses that the pasting direction is different.

[0054] After stacking, a multi-layer stacked chip is obtained. Then, the multi-layer stacked chip is encapsulated as a whole using a molding material 7, and the molding material 7 can be a conventional EMC. In practice, there is no limit to the number of columns of the multi-layer stacked chip, but in this embodiment, two columns of multi-layer stacked chips are taken as an example for explanation, and reference is made to FIG. Figure 3 .

[0055] Optional step: Use grinding process to thin the front side of the stacked chip after plastic sealing. The purpose of grinding is to thin the plastic sealing layer and reduce the thickness of the stacked chip. If there are stains or contamination that is difficult to remove on the surface, it can also be cleaned by grinding. This step can be performed or not according to the actual situation.

[0056] Drilling: Reference Figure 4 , use femtosecond laser to perform precision drilling on the mold layer. The ultrashort pulse characteristics of femtosecond laser can accurately control the amount of material removal and avoid thermal effects on surrounding materials. Vertical laser vias are formed in the stacked chips after plastic encapsulation. It should be noted that when the processing time needs to be shortened, picosecond laser can be used instead of femtosecond laser to perform precision drilling on the mold layer.

[0057] refer to Figure 4 The left side of the front side of the DRAM 04 chip 6 is connected to a laser through-hole 8, the right side of the front side of the DRAM 03 chip 5 is connected to a laser through-hole 8, the left side of the front side of the DRAM 02 chip 4 is connected to a laser through-hole 8, and the left side of the front side of the DRAM 01 chip 3 is connected to a laser through-hole 8.

[0058] refer to Figure 5 , and then depositing metal in the laser through hole 8 to form a TMV structure 9, thereby obtaining a stacked chip after TMV.

[0059] In order to better explain the direction, "left" and "right" are introduced. This direction is based on Figure 4 and Figure 5 The description here means that the directions of the laser through holes 8 are different.

[0060] RDL: Reference Figure 5 , an insulating material is added to the front of the stacked chip after TMV to form insulation 10. The insulating material can be silicon oxide or silicon nitride. The corresponding additional method can be a deposition method, which includes chemical vapor deposition (CVD) or physical vapor deposition (PVD). The insulating material can also be a polymer material, which includes PI and PBO. The corresponding additional method can be coating, which includes spin coating or slit coating. Photolithography: Coating photoresist on the insulating layer. Coating can also be coating, which includes spin coating or slit coating. Expose the photoresist through a mask to define the area where RDL needs to be formed. Development: Use a developer to remove the unexposed photoresist, leaving a photoresist pattern. Metal deposition: Deposit a metal layer on the developed insulating layer, usually copper or aluminum. Electroplating, evaporation or sputtering can be used. Removal of photoresist: Use a suitable solvent to remove the photoresist, leaving a metal pattern. Etching: Remove excess metal by dry or wet etching, leaving only the designed circuits and contacts 11. After the above, a redistribution layer is formed on the stacked chip after the TMV, and the redistribution layer is connected to the TMV structure to obtain the stacked chip after the RDL.

[0061] refer to Figure 6 , a bump 12 is formed on the redistribution layer of the stacked chip after RDL by using a bump technology, and the bump can be a micro bump or a solder ball, which can be used as an electrical interconnection point for the chip to be finally connected to the substrate. The bump technology includes a C4 method.

[0062] refer to Figure 7 , then remove the temporary base 1 attached to the back of the stacked chip, and then perform a cutting process, so that the multi-column stacked chips can be cut into a single-column stacked chip to obtain an offset stacked DRAM packaging structure. Among them, the bump technology and the cutting process use conventional methods in the field, and the principles are known to those skilled in the art and will not be elaborated. Bump technology: micro-bumps or solder balls are formed at specific positions of the RDL. These bumps can be made of metal (such as tin, copper) materials to facilitate subsequent connections. The temporary base 1 can be removed by a stripper or a physical stripping method to ensure that no damage is caused to the chip. Use precision cutting tools (such as laser cutting or blade cutting) to cut the chip to form a single chip unit. During the cutting process, ensure that the cutting depth is well controlled to avoid damaging the internal circuit. Clean and inspect the cut chips to ensure that there is no residual adhesive or other impurities, and check the function and quality of each chip unit.

[0063] The offset stacked DRAM package structure is deformed below.

[0064] Example 2

[0065] Different from Example 1, in this example, the step of "then depositing metal in the laser through hole to form a TMV structure to obtain a stacked chip after TMV" in Example 1 is modified, and the remaining steps are the same as in Example 1.

[0066] The modified steps are as follows:

[0067] Then, a conductive material is filled in the laser through hole, and the conductive material is a conductive paste to form a TMV structure, thereby obtaining a stacked chip after TMV.

[0068] More specifically, the conductive paste can be a conductive silver paste, which can be filled by dispensing and then cured. The curing can be natural curing or heat curing, and the specific curing conditions are adjusted according to the properties of the conductive silver paste.

[0069] Conductive material is filled in the laser vias, changing “point contact” into “surface contact” and increasing the effective contact area of ​​the connection.

[0070] Silver materials are expensive, which is not conducive to the promotion and application of chips. Let’s try to make our own conductive materials.

[0071] Example 3

[0072] Different from Example 2, the conductive material is tried to be homemade:

[0073] 1. Add 10 g of copper nanoparticles to 50 mL of ethylene glycol under stirring conditions and mix by ultrasonic treatment at 20 kHz to obtain treated nanoparticles.

[0074] 2. At a low temperature of 50°C, add 20 g of epoxy resin to 100 mL of xylene and stir. While stirring, add 0.4 g of renewable plant oil-based plasticizer and stir evenly to obtain a resin solution.

[0075] 3. In a high shear mixer at 2500 rpm, slowly add half of the treated nanoparticles to the resin solution, stir for 5 minutes, add the remaining half of the treated nanoparticles again, increase the stirring speed to 3500 rpm, and continue stirring for 15 minutes to ensure uniform dispersion to obtain a standby conductive material.

[0076] 4. When the conductive material is used, take the spare conductive material, add 4g of curing agent while stirring, continue to stir evenly to obtain a usable conductive material, fill it into the laser through hole, and cure it at room temperature.

[0077] Further provide the purchase method of the above-mentioned raw materials:

[0078] Copper nanoparticles: nanopowder, 100 nm, 99.8%, Sigma-Aldrich;

[0079] Epoxy resin: 105 Epoxy Resin, West System;

[0080] Renewable vegetable oil-based plasticizers: epoxidized soybean oil, Cargill Vikoflex® 7170 epoxidizedsoybean oil;

[0081] Hardener: 205 Fast Hardener®, Huntsman.

[0082] In this embodiment, a low-viscosity epoxy resin is selected, which has a small curing shrinkage rate, is not easy to become brittle or crack after curing, and will not damage the chip. When needed, it is used with a curing agent that can be cured at room temperature. However, the prepared conductive material will not cure immediately at room temperature. Although a chemical reaction begins after the conductive material and the curing agent are mixed, it takes time to convert from liquid to solid, and the complete conversion takes several hours, thus providing the operator with sufficient filling time.

[0083] Copper has similar electrical and thermal conductivity properties to silver. Compared with copper, nano copper has a larger specific surface area, which can improve the conductivity of the material. Nano copper also has better mechanical properties and ductility. However, copper nanoparticles tend to agglomerate, so a variety of measures were taken to avoid this problem: 1) dispersing them in a solvent under ultrasonic conditions; 2) selecting low-viscosity epoxy resin with good fluidity; 3) adding them to the resin solution in batches under high shear agitator conditions.

[0084] Epoxidized soybean oil is selected as the renewable vegetable oil-based plasticizer. In order to avoid the poor solubility of epoxidized soybean oil, the following operations are performed: 1) xylene and low-viscosity epoxy resin are pre-mixed. Xylene, as an organic solvent, helps to improve the solubility of epoxidized soybean oil, and low-viscosity epoxy resin has good fluidity; 2) then the renewable vegetable oil-based plasticizer is added to the solution under low temperature and stirring, thereby enhancing the compatibility of the renewable vegetable oil-based plasticizer and the aforementioned components.

[0085] Renewable plant oil-based plasticizers have good biodegradability and can improve the brittleness of the material after curing. Epoxidized soybean oil has good chemical stability and can remain stable under certain temperature and pressure conditions. In addition, epoxidized soybean oil has low volatility and good adhesion, and can also give the material excellent coating performance and chemical corrosion resistance.

[0086] It was also found that in this example, the epoxidized soybean oil could improve the dispersion of the copper nanoparticles in the material.

[0087] Example 4

[0088] Different from Example 2, the conductive material is tried to be homemade:

[0089] 1. Add 10 g of copper nanoparticles to 50 mL of ethylene glycol under stirring conditions and mix by ultrasonic treatment at 20 kHz to obtain treated nanoparticles.

[0090] 2. At a low temperature of 50°C, add 20 g of epoxy resin to 100 mL of xylene and stir. While stirring, add 0.4 g of renewable plant oil-based plasticizer and stir evenly to obtain a resin solution.

[0091] 3. In a high shear mixer at 2500 rpm, slowly add half of the treated nanoparticles to the resin solution, stir for 5 minutes, add the remaining half of the treated nanoparticles again, increase the stirring speed to 3500 rpm, and continue stirring for 15 minutes to ensure uniform dispersion to obtain a standby conductive material.

[0092] 4. When the conductive material is used, take the spare conductive material, add 6g of polyetheramine while stirring, continue stirring for 5 minutes, heat and stir at 20°C until it is evenly dispersed to obtain a usable conductive material, fill it into the laser through-hole, and the curing temperature is 70°C.

[0093] Further provide the purchase method of the above-mentioned raw materials:

[0094] Polyetheramine: Jeffamine D-230, Huntsman. The purchase method of other raw materials is the same as that of Example 3.

[0095] In this embodiment, different from Example 3, polyetheramine is selected to replace the curing agent of Example 3. The selected polyetheramine has a lower molecular weight, better fluidity and permeability, and is mixed with the conductive material to improve the wettability and dispersibility of the component. In order to improve the solubility of the polyetheramine in the system, after stirring, heat and stir at 20°C until it is evenly dispersed. 20°C is lower than the curing temperature of the polyetheramine, which can ensure that it is evenly dispersed when not cured. The epoxy resin selected in this application can be cured within a wide temperature range, and then the curing temperature suitable for the formula of Example 4 is tested.

[0096] Example 5

[0097] Different from Example 2, the conductive material is tried to be homemade:

[0098] 1. Add 10 g of copper nanoparticles to 50 mL of ethylene glycol under stirring conditions and mix by ultrasonic treatment at 20 kHz to obtain treated nanoparticles.

[0099] 2. At a low temperature of 50°C, add 20g of epoxy resin to 100mL of xylene and stir. Add 0.4g of plasticizer while stirring and stir evenly to obtain a resin solution.

[0100] 3. In a high shear mixer at 2500 rpm, slowly add half of the treated nanoparticles to the resin solution, stir for 5 minutes, add the remaining half of the treated nanoparticles again, increase the stirring speed to 3500 rpm, and continue stirring for 15 minutes to ensure uniform dispersion to obtain a standby conductive material.

[0101] 4. When the conductive material is used, take the spare conductive material, add 4g of curing agent while stirring, continue to stir evenly to obtain a usable conductive material, fill it into the laser through hole, and cure it at room temperature.

[0102] Further provide the purchase method of the above-mentioned raw materials:

[0103] Plasticizer: glycerol, 99.8%, Sigma-Aldrich;

[0104] The rest is the same as that of Example 3.

[0105] In this example glycerol was used in place of the epoxidized soybean oil.

[0106] Comparative Example 1

[0107] Different from Example 2, the conductive material is tried to be homemade:

[0108] 1. Add 10 g of copper nanoparticles to 50 mL of ethylene glycol under stirring conditions and mix by ultrasonic treatment at 20 kHz to obtain treated nanoparticles.

[0109] 2. At a low temperature of 50°C, add 20 g of epoxy resin into 100 mL of xylene to obtain a resin solution.

[0110] 3. In a high shear mixer at 2500 rpm, slowly add half of the treated nanoparticles to the resin solution, stir for 5 minutes, add the remaining half of the treated nanoparticles again, increase the stirring speed to 3500 rpm, and continue stirring for 15 minutes to ensure uniform dispersion to obtain a standby conductive material.

[0111] 4. When the conductive material is used, take the spare conductive material, add 4g of curing agent while stirring, continue to stir evenly to obtain a usable conductive material, fill it into the laser through hole, and cure it at room temperature.

[0112] The purchase method of the raw materials used above is the same as that of Example 3.

[0113] Embodiment 3 to embodiment 5 and comparative example 1 were tested.

[0114] Do not fill the laser through-hole with the usable conductive material, and prepare the usable conductive material into a compression specimen: 50 mm long, 10 mm wide, and 1 mm thick. Place the specimen on the base of the compression tester, start the test, and record the data until the specimen is broken and stops automatically. Calculate the maximum compression strength. Maximum compression strength = maximum compression force (N) / compression cross-sectional area (mm²).

[0115] Mechanical properties test results:

[0116] Example 3: Maximum compressive strength: 50 MPa;

[0117] Example 4: Maximum compressive strength: 52 MPa;

[0118] Example 5: Maximum compressive strength: 48 MPa;

[0119] Comparative Example 1: Maximum compressive strength: 45 MPa;

[0120] By comparing the above results, adding a plasticizer in the preparation method of the present application can improve the material performance. For how to select a suitable plasticizer, an experiment is set up to explore a suitable formula. Through the improvement of the examples, it is further found that compared with glycerol, epoxy soybean oil has better dispersibility and compatibility for components, and epoxy soybean oil can improve the dispersibility of copper nanoparticles in the material.

[0121] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for packaging an offset stacked DRAM structure, characterized in that: The steps include: Glue the back of the first DRAM chip to the temporary base; Offset stacking: Paste the back of another DRAM chip offset from the front of the first DRAM chip; the remaining DRAM chips are also pasted on the back of the previous DRAM chip in this way to obtain multi-layer offset stacked DRAM chips, which are then plastic-sealed to obtain plastic-sealed stacked chips; A plurality of through holes are formed in the stacked chip after plastic encapsulation by drilling, and each through hole is connected to a DRAM chip; a conductive material is filled in each through hole to form a TMV structure, and a stacked chip after TMV is obtained; a redistribution layer is formed on the front of the stacked chip after TMV by RDL technology, and the redistribution layer is connected to the TMV structure, and a stacked chip after RDL is obtained; a bump is formed on the redistribution layer of the stacked chip after RDL by bump technology, and a temporary base attached to the back of the stacked chip is removed to obtain an offset stacked DRAM structure; When stacking with offset, the calculation is not started from the first DRAM chip, but from the second DRAM chip thereafter. The offset direction of every two DRAM chips is the same, and the offset direction is changed after every two DRAM chips are stacked. The conductive material includes conductive paste and self-made conductive material; the conductive paste includes conductive silver paste; The method for preparing the homemade conductive material comprises the following steps: adding copper nanoparticles to ethylene glycol under stirring conditions, and performing ultrasonic treatment to mix the mixture to obtain treated nanoparticles; Under heating conditions, epoxy resin is added to xylene, and the mixture is stirred. A plasticizer is added while stirring, and the mixture is stirred evenly to obtain a resin solution. Under stirring conditions, a portion of the treated nanoparticles are added to the resin solution and stirred, and the remaining treated nanoparticles are added again and stirred to ensure uniform dispersion, thereby obtaining a self-made conductive material.

2. The method for packaging an offset stacked DRAM structure as claimed in claim 1, wherein: When drilling, the direction of the through hole connected to the first DRAM chip is the same as the direction of the through hole connected to the second DRAM chip, and the direction of the through hole connected to each subsequent DRAM chip is different from the previous one.

3. The method for packaging an offset stacked DRAM structure as claimed in claim 1, wherein: The front side of the stacked chip after plastic encapsulation is thinned using a grinding process, and drilling is performed after the front side is thinned.

4. The method for packaging an offset stacked DRAM structure as claimed in claim 1, wherein: When the homemade conductive material is used, take the homemade conductive material, add the curing agent during stirring, continue to stir evenly, obtain the usable conductive material, fill it into the through hole, and solidify it.

5. The method for packaging an offset stacked DRAM structure as claimed in claim 1, wherein: The particle size of copper nanoparticles is 50~200 nm.

6. The method for packaging an offset stacked DRAM structure as claimed in claim 1, wherein: The viscosity of epoxy resin is 500~1500cP.

7. The method for packaging an offset stacked DRAM structure as claimed in claim 1, wherein: The plasticizer includes at least one of a renewable vegetable oil-based plasticizer and glycerol, and the renewable vegetable oil-based plasticizer includes epoxidized soybean oil.

8. The method for packaging an offset stacked DRAM structure as claimed in claim 1, wherein: When the homemade conductive material is used, take the homemade conductive material, add polyetheramine while stirring, continue to stir evenly, then heat and stir until it is evenly dispersed to obtain a usable conductive material, fill it into the through hole, and heat and cure it.

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