Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. A first recess in the substrate; the multiple stacked electrode layers are located in the first groove, the bottommost electrode layer covers all the surfaces of the first groove and extends to be located on the surface of the substrate, the other electrode layers are sequentially stacked on the surface of the bottommost electrode layer, and the topmost electrode layer defines a second groove in the first groove; the dielectric layers are located between the adjacent electrode layers; and the interconnection structure is positioned in the second groove. The performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Deep Trench Capacitor (DTC) is widely used in antenna matching, RF filtering and IC decoupling, especially in applications with height and volume restrictions. It has very high stability and extremely low leakage current under high bias voltage, and plays a vital role in some industrial fields.

[0003] Silicon-based capacitors are replacing ceramic capacitors in the smartphone AP and PMIC terminal markets with their irreplaceable advantages such as miniaturization, high stability, and low ESR / ESL. High-density DTCs increase the effective area of ​​capacitors through three-dimensional structural design, thereby increasing capacitance density.

[0004] With the rapid development of the information industry, the feature size (CD) of integrated circuits has been continuously reduced, and the manufacturing process of integrated circuit chips has also been continuously refined. The development of integrated circuit chip manufacturing technology has prompted integrated circuit packaging technology to continuously pursue the demand for higher performance, more functions, smaller size, lower power consumption and cost.

[0005] In the development of integrated circuit packaging technology, 3D Through-Silicon-Via (TSV) packaging technology is the latest technology to achieve interconnection between chips by making vertical conduction between chips and wafers. Compared with the previous IC packaging bonding and stacking technology using bumps, TSV can maximize the density of chip stacking in the three-dimensional direction and minimize the size, greatly improving the chip speed and low power consumption performance. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to improving the performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a first groove, located in the substrate; a plurality of stacked electrode layers, located in the first groove, the bottom electrode layer covers each surface of the first groove and extends to the surface of the substrate, and the remaining electrode layers are stacked in sequence on the surface of the bottom electrode layer, and the top electrode layer forms a second groove in the first groove; a dielectric layer, located between adjacent electrode layers; and an interconnect structure, located in the second groove.

[0008] Optionally, on the surface of the substrate, any electrode layer exposes another adjacent electrode layer thereunder.

[0009] Optionally, the semiconductor structure further includes: an interconnect plug, which is located on each electrode layer exposed on the surface and is electrically connected thereto.

[0010] Optionally, the semiconductor structure also includes: a first insulating layer located between the bottom electrode layer and the sidewall and bottom of the first groove, and between the bottom electrode layer and the substrate surface; and a second insulating layer located between the interconnect structure and the top electrode layer.

[0011] Optionally, the semiconductor structure further includes: protective sidewalls, which are located on the sidewalls of each electrode layer on the surface of the substrate.

[0012] Optionally, the capacitor structure formed by the multiple electrode layers is electrically connected to the interconnection structure.

[0013] Optionally, the first groove is a groove for forming a through-hole interconnection structure penetrating the substrate.

[0014] Optionally, the dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; the material of the electrode layer includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0015] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a first groove in the substrate; forming a plurality of stacked electrode layers in the first groove, and a dielectric layer located between adjacent electrode layers, wherein the bottom electrode layer covers each surface of the first groove and extends to the surface of the substrate, and the remaining electrode layers are stacked in sequence on the surface of the bottom electrode layer, and the top electrode layer forms a second groove in the first groove; and forming an interconnection structure in the second groove.

[0016] Optionally, the step of forming a multi-layer stacked electrode layer and a dielectric layer located between adjacent electrode layers in the first groove includes: alternately stacking electrode material layers and dielectric material layers on each surface of the first groove and the substrate surface until the topmost electrode material layer is formed; patterning the multi-layer electrode material layers and dielectric material layers on the substrate surface to form multiple electrode layers and a dielectric layer located between adjacent electrode layers.

[0017] Optionally, in the step of patterning the multiple electrode material layers and dielectric material layers on the substrate surface, on the substrate surface, any electrode layer exposes another adjacent electrode layer thereunder.

[0018] Optionally, after forming the interconnect structure in the second groove, the forming method further includes: forming an interconnect plug on each electrode layer exposed on the surface and electrically connected thereto.

[0019] Optionally, before forming a multi-layer stacked electrode layer in the first groove, the method further includes: forming a first insulating layer covering the surfaces of the first groove and the surface of the substrate; in the step of forming a multi-layer stacked electrode layer in the first groove, the bottom electrode layer is formed on the first insulating layer; before forming an interconnection structure in the second groove, the formation method further includes: forming a second insulating layer covering the surfaces of the second groove and the surface of the top electrode layer; in the step of forming an interconnection structure in the second groove, the interconnection structure is isolated from the top electrode layer by the second insulating layer.

[0020] Optionally, the step of forming a second insulating layer includes: before patterning the multiple electrode material layers and dielectric material layers on the surface of the substrate, forming an insulating material layer covering the topmost electrode material layer; patterning the insulating material layer and retaining the insulating material layer covering the topmost electrode layer as the second insulating layer.

[0021] Optionally, the insulating material layer and the topmost electrode material layer are patterned in the same step.

[0022] Optionally, the step of forming an interconnection structure in the second groove includes: forming an interconnection material layer filling the second groove and covering the multi-layer electrode layer; planarizing the interconnection material layer and retaining the interconnection material layer located in the second groove as the interconnection structure.

[0023] Optionally, after forming the interconnect structure in the second groove, the forming method further includes: forming a protective sidewall on the sidewall of each electrode layer on the surface of the substrate.

[0024] Optionally, after forming the interconnection structure in the second groove, the forming method further includes: electrically connecting the capacitor structure formed by the multi-layer electrode layer to the interconnection structure.

[0025] Optionally, after forming the interconnection structure in the second groove, the forming method further includes: performing a backside thinning process on the substrate until the interconnection structure at the bottom of the second groove is exposed.

[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0027] In the semiconductor structure provided by the embodiment of the present invention, a plurality of stacked electrode layers are located in a first groove, the bottom electrode layer covers various surfaces of the first groove and extends to the surface of the substrate, and the remaining electrode layers are stacked in sequence on the surface of the bottom electrode layer, and the top electrode layer forms a second groove in the first groove, and the interconnection structure is located in the second groove; the embodiment of the present invention integrates the capacitor structure and the interconnection structure composed of the plurality of electrode layers in a first groove, which is beneficial to reducing the occupied area of ​​the capacitor structure and the interconnection structure and improving the integration of the semiconductor structure. Moreover, the capacitor structure and the interconnection structure are close to each other, which is beneficial to reducing the transmission distance of the electrical signal between the capacitor structure and the interconnection structure, thereby reducing the signal loss and further improving the performance of the semiconductor structure.

[0028] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a multi-layer stacked electrode layer and a dielectric layer located between adjacent electrode layers are formed in a first groove, the bottom electrode layer covers each surface of the first groove and extends to the surface of the substrate, and the remaining electrode layers are stacked in sequence on the surface of the bottom electrode layer, and the top electrode layer surrounds a second groove in the first groove, and an interconnection structure is formed in the second groove; the embodiment of the present invention integrates the capacitor structure and the interconnection structure composed of multiple electrode layers in a first groove, which is beneficial to reducing the occupied area of ​​the capacitor structure and the interconnection structure, and improving the integration of the semiconductor structure. Moreover, the capacitor structure is close to the interconnection structure, which is beneficial to reducing the transmission distance of the electrical signal between the capacitor structure and the interconnection structure, thereby reducing the signal loss and further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0030] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0031] Figures 3 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0032] At present, the integration degree of semiconductor structures needs to be improved. Now, we analyze the reasons why the performance of a semiconductor structure needs to be improved by combining it with a semiconductor structure.

[0033] Figure 1 It is a structural diagram of a semiconductor structure.

[0034] refer to Figure 1The semiconductor structure includes: a substrate 10; a first groove located in the substrate 10; a multi-layer stacked electrode layer 32 located in the first groove, the bottom electrode layer 32 covers each surface of the first groove, and the remaining electrode layers 32 are stacked in sequence on the surface of the bottom electrode layer 32, and the multi-layer electrode layer 32 fills the first groove; a dielectric layer 33 is located between adjacent electrode layers 32; a second groove is located in the substrate 10; and an interconnection structure 41 fills the second groove.

[0035] The electrode layers 32 in the first trench are used to form a deep trench capacitor (DTC) structure, and the interconnection structure 41 in the second trench is a through-silicon via (TSV). The DTC structure and the TSV structure are integrated in the same substrate 10 to improve the performance of the semiconductor structure. However, the size of the TSV structure is generally large and deep, and the DTC structure is difficult to make deep. The capacitance can only be increased by increasing the planar area, and the TSV process and the DTC process need to be completed independently. Therefore, the process of integrating the DTC structure and the TSV structure in the same substrate 10 is relatively complicated and costly, and it is easy to reduce the yield of the semiconductor structure and affect the performance of the semiconductor structure.

[0036] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a first groove, located in the substrate; a plurality of stacked electrode layers, located in the first groove, the bottom electrode layer covers each surface of the first groove and extends to the surface of the substrate, and the remaining electrode layers are stacked in sequence on the surface of the bottom electrode layer, and the top electrode layer forms a second groove in the first groove; a dielectric layer, located between adjacent electrode layers; and an interconnect structure, located in the second groove.

[0037] The embodiment of the present invention integrates the capacitor structure composed of multiple electrode layers and the interconnection structure in a first groove, which is beneficial to reducing the occupied area of ​​the capacitor structure and the interconnection structure and improving the integration of the semiconductor structure. Moreover, the capacitor structure and the interconnection structure are close to each other, which is beneficial to reducing the transmission distance of the electrical signal between the capacitor structure and the interconnection structure, thereby reducing the signal loss and further improving the performance of the semiconductor structure.

[0038] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 2 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0039] refer to Figure 2The semiconductor structure includes: a substrate 100; a first groove 110, located in the substrate 100; a multi-layer stacked electrode layer 320, located in the first groove 110, the bottom electrode layer 320 covers each surface of the first groove 110, and extends to the surface of the substrate 100, and the remaining electrode layers 320 are stacked in sequence on the surface of the bottom electrode layer 320, and the top electrode layer 320 surrounds the second groove 120 in the first groove 110; a dielectric layer 330, located between adjacent electrode layers 320; an interconnection structure 410, located in the second groove 120.

[0040] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0041] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0042] The first groove 110 is used to provide a spatial position for forming the electrode layer 320 and the interconnection structure 410 .

[0043] In this embodiment, the first groove 110 is a groove for forming a through-hole interconnection structure penetrating the substrate 100 .

[0044] Specifically, the through-hole interconnect structure is a through-silicon-Via (TSV) structure. Usually in the semiconductor process, the through-hole of the TSV structure is deeper, which is used to form a deep trench capacitor (DTC) structure composed of multiple stacked electrode layers 320, which is beneficial to improve the capacitance density of the capacitor.

[0045] The multi-layer electrode layer 320 is used to form a capacitor structure. Specifically, the multi-layer electrode layer 320 stacked in the first groove 110 is used to form a deep trench capacitor (DTC) structure.

[0046] In this embodiment, on the surface of the substrate 100 , any electrode layer 320 exposes another adjacent electrode layer 320 thereunder.

[0047] The exposed surface of the electrode layer 320 is used to form an interconnect plug thereon for electrical connection with the outside. On the surface of the substrate 100, any electrode layer 320 exposes another adjacent electrode layer 320 thereunder, so that each electrode layer 320 can expose a portion of its surface, thereby enabling each electrode layer 320 to be electrically connected with the outside.

[0048] In this embodiment, the material of the electrode layer 320 includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0049] As an example, in this embodiment, the material of the electrode layer 320 is polysilicon. Using polysilicon to form the electrode layer 320 is beneficial to the operation of the patterning process of the electrode layer 320.

[0050] It should be noted that, in this embodiment, the number of electrode layers 320 is not limited, and a corresponding number of electrode layers 320 are formed according to actual process requirements.

[0051] The dielectric layer 330 serves as an insulating layer in the formed capacitor structure and is used to isolate adjacent electrode layers 320 .

[0052] In this embodiment, the material of the dielectric layer 330 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the capacitor structure and correspondingly increasing the capacitance density.

[0053] Specifically, the dielectric layer 330 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 330 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 330 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0054] In this embodiment, the dielectric layer 330 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, according to process requirements, the material of the dielectric layer can also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0055] In this embodiment, the semiconductor structure further includes: a protective sidewall 500 located on the sidewall of each electrode layer 320 on the surface of the substrate 100 .

[0056] The protective sidewall 500 is used to cover the exposed sidewall of each electrode layer 320 , so as to completely isolate adjacent electrode layers 320 , thereby facilitating reducing the probability of electrical leakage between the electrode layers 320 .

[0057] In this embodiment, the material of the protective spacer 500 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. In this embodiment, the material of the protective spacer 500 is silicon nitride.

[0058] In this embodiment, the semiconductor structure further includes: an interconnect plug 510, which is located on each electrode layer 320 exposed on the surface and is electrically connected thereto.

[0059] The interconnection plug 510 is used to realize the electrical connection between the electrode layer 320 and the outside, so as to load the electrical signal to the electrode layer 320 .

[0060] In this embodiment, the material of the interconnection plug 510 includes Cu, Co or W.

[0061] In this embodiment, the semiconductor structure further includes: a first insulating layer 210 located between the bottom electrode layer 320 and the sidewall and bottom of the first groove 110 , and between the bottom electrode layer 320 and the surface of the substrate 100 .

[0062] The first insulating layer 210 is used to isolate the bottom electrode layer 320 from the substrate 100 .

[0063] The material of the first insulating layer 210 is an insulating material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0064] The second groove 120 is used to provide a spatial location for forming the interconnection structure 410 .

[0065] In this embodiment, the second groove 120 is surrounded by the topmost electrode layer 320 in the first groove 110. That is, the multilayer electrode layers 320 stacked in the first groove 110 do not fill the first groove 110, but leave space for the second groove 120 to provide space for support for the formation of the interconnection structure 410.

[0066] It should be noted that, in this embodiment, the ratio of the opening size of the second groove 120 to the opening size of the first groove 110 should not be too large or too small. If the ratio of the opening size of the second groove 120 to the opening size of the first groove 110 is too large, it is easy to cause the space for forming the electrode layer 320 in the first groove 110 to be too small, and correspondingly cause the space for forming the capacitor structure to be too small, which makes it difficult to form the electrode layer 320; if the ratio of the opening size of the second groove 120 to the opening size of the first groove 110 is too small, it is easy to cause the space for forming the interconnection structure 410 to be too small, which makes it difficult to form the interconnection structure 410 and also easily affects the electrical connection performance of the interconnection structure 410. For this reason, in this embodiment, according to the actual number of layers required for the DTC structure, the appropriate ratio of the opening size of the second groove 120 to the opening size of the first groove 110 is selected.

[0067] The interconnect structure 410 is used to realize electrical connection in the vertical direction.

[0068] Specifically, the back side of the substrate 100 can be thinned later until the bottom of the interconnection structure 410 in the second groove 120 is exposed, thereby realizing vertical conduction of the upper and lower devices of the substrate 100 through the interconnection structure 410, making the wafer stacking density in the three-dimensional direction higher and the external dimensions smaller, and greatly improving the chip speed and reducing the chip power consumption.

[0069] In this embodiment, the capacitor structure composed of the multi-layer electrode layer 320 and the interconnection structure 410 are integrated in a first groove 110, which is beneficial to reducing the occupied area of ​​the capacitor structure and the interconnection structure and improving the integration of the semiconductor structure. Moreover, the capacitor structure and the interconnection structure are close to each other, which is beneficial to reducing the transmission distance of the electrical signal between the capacitor structure and the interconnection structure, thereby reducing the signal loss and further improving the performance of the semiconductor structure.

[0070] In this embodiment, the material of the interconnect structure 410 includes Cu, Co or W.

[0071] In this embodiment, the semiconductor structure further includes: a second insulating layer 230 located between the interconnect structure 410 and the topmost electrode layer 320 .

[0072] The second insulating layer 230 is used to isolate the topmost electrode layer 320 and the interconnection structure 410 , thereby isolating the capacitor structure and the interconnection structure 410 in the first groove 110 .

[0073] The material of the second insulating layer 230 is an insulating material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0074] In this embodiment, the capacitor structure formed by the multi-layer electrode layer 320 is electrically connected to the interconnection structure 410 .

[0075] The capacitor structure formed by the multi-layer electrode layer 320 is electrically connected to the interconnection structure 410 , that is, in this embodiment, the DTC structure is electrically connected to the TSV structure, thereby achieving the normal function of the semiconductor structure.

[0076] In this embodiment, the DTC structure and the TSV structure are integrated in the first groove 110, so the DTC structure and the TSV structure are close to each other, which is beneficial to reduce the transmission distance of the electrical signal between the DTC structure and the TSV structure, thereby reducing the signal loss and improving the performance of the semiconductor structure.

[0077] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 3 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0078] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0079] refer to Figure 3 , providing a substrate 100.

[0080] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0081] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0082] Continue to refer Figure 3 , a first groove 110 is formed in the substrate 100 .

[0083] The first groove 110 is used to provide a space for the subsequent formation of an electrode layer and an interconnection structure.

[0084] In this embodiment, the first groove 110 is a groove used for subsequently forming a through-hole interconnection structure penetrating the substrate 100 .

[0085] Specifically, the through-hole interconnect structure is a through-silicon-Via (TSV) structure. Usually in the semiconductor process, the through-hole of the TSV structure is deeper, which is subsequently used to form a deep trench capacitor (DTC) structure composed of multiple stacked electrode layers, which is beneficial to improve the capacitance density of the capacitor.

[0086] refer to Figure 4, before forming a multi-layer stacked electrode layer in the first groove 110 , the method further includes: forming a first insulating layer 210 covering each surface of the first groove 110 and the surface of the substrate 100 .

[0087] The first insulating layer 210 is used to isolate the bottommost electrode layer to be formed subsequently from the substrate 100 .

[0088] The material of the first insulating layer 210 is an insulating material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0089] Combined with reference Figures 5 to 9 A multi-layer stacked electrode layer 320 and a dielectric layer 330 located between adjacent electrode layers 320 are formed in the first groove 110, the bottom electrode layer 320 covers each surface of the first groove 110 and extends to the surface of the substrate 100, and the remaining electrode layers 320 are stacked in sequence on the surface of the bottom electrode layer 320, and the top electrode layer 320 surrounds the second groove 120 in the first groove 110.

[0090] The multi-layer electrode layer 320 is used to form a capacitor structure. Specifically, the multi-layer electrode layer 320 stacked in the first groove 110 is used to form a deep trench capacitor (DTC) structure.

[0091] Accordingly, in this embodiment, in the step of forming a multi-layer stacked electrode layer 320 in the first groove 110 , the bottom electrode layer 320 is formed on the first insulating layer 210 , so that the capacitor structure formed by the multi-layer electrode layer 320 is isolated from the substrate 100 .

[0092] In this embodiment, the material of the electrode layer 320 includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0093] As an example, in this embodiment, the material of the electrode layer 320 is polysilicon. Using polysilicon to form the electrode layer 320 is beneficial to the operation of the patterning process of the electrode layer 320.

[0094] It should be noted that, in this embodiment, the number of electrode layers 320 is not limited, and a corresponding number of electrode layers 320 are formed according to actual process requirements.

[0095] The dielectric layer 330 serves as an insulating layer in the formed capacitor structure and is used to isolate adjacent electrode layers 320 .

[0096] In this embodiment, the material of the dielectric layer 330 is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the capacitor structure and correspondingly increasing the capacitance density.

[0097] Specifically, the dielectric layer 330 is a high-k dielectric layer formed by stacking, that is, the dielectric layer 330 is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by adopting a high-k composite dielectric layer, the thickness of the dielectric layer 330 can meet the process requirements while having good formation quality. To this end, the high-k dielectric material includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

[0098] In this embodiment, the dielectric layer 330 is a ZAZ layer. The ZAZ layer includes a first ZrO2 layer, an Al2O3 layer, and a second ZrO2 layer formed by stacking. In other embodiments, according to process requirements, the material of the dielectric layer can also be one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0099] Specifically, refer to Figure 5 The step of forming a multi-layer stacked electrode layer 320 and a dielectric layer 330 located between adjacent electrode layers 320 in the first groove 110 includes: alternately stacking electrode material layers 300 and dielectric material layers 310 on each surface of the first groove 110 and the surface of the substrate 100 until the topmost electrode material layer 300 is formed.

[0100] The electrode material layer 300 is used to form an electrode layer 320 , and the dielectric material layer 310 is used to form a dielectric layer 330 .

[0101] In this embodiment, the electrode material layers 300 and the dielectric material layers 310 are alternately stacked on the surfaces of the first groove 110 and the surface of the substrate 100 by using an atomic layer deposition process.

[0102] The electrode material layer 300 and the dielectric material layer 310 formed by the atomic layer deposition process have good thickness uniformity and good step coverage capability, so that the electrode material layer 300 and the dielectric material layer 310 can conformally cover the bottom and side walls of the first groove 110 and the top of the substrate 100 well, and it is also beneficial to make the thickness uniformity of the electrode layer 320 and the dielectric layer 330 better.

[0103] Combined with reference Figures 6 to 9Before subsequently forming the interconnect structure 410 in the second groove 120 , the forming method further includes: forming a second insulating layer 230 covering each surface of the second groove 120 and the surface of the topmost electrode layer 320 .

[0104] The second insulating layer 230 is used to isolate the topmost electrode layer 320 and the interconnection structure 410 , thereby isolating the capacitor structure in the first groove 110 and the interconnection structure formed subsequently.

[0105] The material of the second insulating layer 230 is an insulating material, for example, one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride.

[0106] Specifically, refer to Figure 6 The step of forming the second insulating layer 230 includes: before subsequently patterning the multi-layer electrode material layer 300 and the dielectric material layer 310 on the surface of the substrate 100 , forming an insulating material layer 220 covering the topmost electrode material layer 300 .

[0107] The insulating material layer 220 is used to form the second insulating layer 230 .

[0108] Accordingly, in this embodiment, the material of the insulating material layer 220 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide.

[0109] Combined with reference Figures 7 to 9 , an interconnection structure 410 is formed in the second groove 120 .

[0110] The second groove 120 is used to provide a spatial location for forming the interconnection structure 410 .

[0111] In this embodiment, the second groove 120 is surrounded by the topmost electrode layer 320 in the first groove 110. That is, the multilayer electrode layers 320 stacked in the first groove 110 do not fill the first groove 110, but leave space for the second groove 120 to provide space for support for the formation of the interconnection structure 410.

[0112] It should be noted that, in the present embodiment, an insulating material layer 220 is formed between the capacitor structure and the interconnection structure 410 , and accordingly, the second groove 120 is surrounded by the insulating material layer 220 .

[0113] Accordingly, in this embodiment, in the step of forming the interconnection structure 410 in the second groove 120 , the interconnection structure 410 is isolated from the topmost electrode layer 320 by the second insulating layer 230 .

[0114] It should also be noted that, in this embodiment, the ratio of the opening size of the second groove 120 to the opening size of the first groove 110 should not be too large or too small. If the ratio of the opening size of the second groove 120 to the opening size of the first groove 110 is too large, it is easy to cause the space for forming the electrode layer 320 in the first groove 110 to be too small, which correspondingly causes the space for forming the capacitor structure to be too small, causing difficulties in forming the electrode layer 320; if the ratio of the opening size of the second groove 120 to the opening size of the first groove 110 is too small, it is easy to cause the space for forming the interconnection structure 410 to be too small, causing difficulties in forming the interconnection structure 410, and also easily affecting the electrical connection performance of the interconnection structure 410. For this reason, in this embodiment, according to the actual number of layers required for the DTC structure, the appropriate ratio of the opening size of the second groove 120 to the opening size of the first groove 110 is selected.

[0115] The interconnect structure 410 is used to realize electrical connection in the vertical direction.

[0116] Specifically, the back side of the substrate 100 can be thinned later until the bottom of the interconnection structure 410 in the second groove 120 is exposed, thereby realizing vertical conduction of the upper and lower devices of the substrate 100 through the interconnection structure 410, making the wafer stacking density in the three-dimensional direction higher and the external dimensions smaller, and greatly improving the chip speed and reducing the chip power consumption.

[0117] In this embodiment, the capacitor structure composed of the multi-layer electrode layer 320 and the interconnection structure 410 are integrated in a first groove 110, which is beneficial to reducing the occupied area of ​​the capacitor structure and the interconnection structure and improving the integration of the semiconductor structure. Moreover, the capacitor structure and the interconnection structure are close to each other, which is beneficial to reducing the transmission distance of the electrical signal between the capacitor structure and the interconnection structure, thereby reducing the signal loss and further improving the performance of the semiconductor structure.

[0118] In this embodiment, the material of the interconnect structure 410 includes Cu, Co or W.

[0119] refer to Figure 7 The step of forming the interconnection structure 410 in the second groove 120 includes: forming an interconnection material layer 400 filling the second groove 120 and covering the multi-layer electrode layer 320 .

[0120] The interconnect material layer 400 is used to form an interconnect structure 410 .

[0121] refer to Figure 8 , planarizing the interconnect material layer 400 , and retaining the interconnect material layer 400 located in the second groove 120 as the interconnect structure 410 .

[0122] refer to Fig. 9The multi-layer electrode material layer 300 and the dielectric material layer 310 on the surface of the patterned substrate 100 are formed to form a plurality of electrode layers 320 and a dielectric layer 330 located between adjacent electrode layers 320 .

[0123] In this embodiment, after forming the multi-layer electrode material layer 300 and the dielectric material layer 310 , a patterning process is performed at the same time, which is beneficial to improving the process efficiency.

[0124] In this embodiment, in the step of patterning the multiple electrode material layers 300 and the dielectric material layers 310 on the surface of the substrate 100 , on the surface of the substrate 100 , any electrode layer 320 exposes another adjacent electrode layer 320 thereunder.

[0125] The exposed surface of the electrode layer 320 is used to form an interconnect plug thereon for electrical connection with the outside. On the surface of the substrate 100, any electrode layer 320 exposes another adjacent electrode layer 320 thereunder, so that each electrode layer 320 can expose a portion of its surface, thereby enabling each electrode layer 320 to be electrically connected with the outside.

[0126] Continue to refer Fig. 9 , patterning the insulating material layer 220 , retaining the insulating material layer 220 covering the topmost electrode layer 320 as the second insulating layer 230 .

[0127] In this embodiment, the insulating material layer 220 and the topmost electrode material layer 300 are patterned in the same step.

[0128] Patterning the insulating material layer 220 and the topmost electrode material layer 300 in the same step is beneficial to improving process efficiency and improving the verticality of the sidewalls of the electrode layer 320 and the second insulating layer 230 .

[0129] In this embodiment, after forming the interconnect structure 410 in the second groove 120 , the forming method further includes: forming a protective spacer 500 on the sidewall of each electrode layer 320 on the surface of the substrate 100 .

[0130] The protective sidewall 500 is used to cover the exposed sidewall of each electrode layer 320 , so as to completely isolate adjacent electrode layers 320 , thereby facilitating reducing the probability of electrical leakage between the electrode layers 320 .

[0131] In this embodiment, the material of the protective spacer 500 includes one or more of titanium oxide, titanium nitride, silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. In this embodiment, the material of the protective spacer 500 is silicon nitride.

[0132] refer to Fig.11After forming the interconnection structure 410 in the second groove 120 , the forming method further includes: forming an interconnection plug 510 electrically connected to each electrode layer 320 exposed on the surface.

[0133] The interconnection plug 510 is used to realize the electrical connection between the electrode layer 320 and the outside, so as to load the electrical signal to the electrode layer 320 .

[0134] In this embodiment, the material of the interconnection plug 510 includes Cu, Co or W.

[0135] In this embodiment, after forming the interconnection structure 410 in the second groove 120 , the forming method further includes: electrically connecting the capacitor structure formed by the multi-layer electrode layer 320 to the interconnection structure 410 .

[0136] The capacitor structure formed by the multi-layer electrode layer 320 is electrically connected to the interconnection structure 410 , that is, in this embodiment, the DTC structure is electrically connected to the TSV structure, thereby achieving the normal function of the semiconductor structure.

[0137] In this embodiment, the DTC structure and the TSV structure are integrated in the first groove 110, so the DTC structure and the TSV structure are close to each other, which is beneficial to reduce the transmission distance of the electrical signal between the DTC structure and the TSV structure, thereby reducing the signal loss and improving the performance of the semiconductor structure.

[0138] In this embodiment, after the interconnection structure 410 is formed in the second groove 120 , the forming method further includes: performing a backside thinning process on the substrate 100 until the interconnection structure 410 at the bottom of the second groove 120 is exposed.

[0139] The back side of the substrate 100 is thinned until the interconnection structure 410 at the bottom of the second groove 120 is exposed, so that vertical conduction of the upper and lower devices of the substrate 100 is achieved through the interconnection structure 410, so that the wafer stacking density in the three-dimensional direction is higher and the external dimensions are smaller, and the chip speed is greatly improved and the chip power consumption is reduced.

[0140] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A first groove located in the base; A plurality of stacked electrode layers are located in the first groove, the bottom electrode layer covers each surface of the first groove and extends to the surface of the substrate, the remaining electrode layers are stacked in sequence on the surface of the bottom electrode layer, and the top electrode layer surrounds the second groove in the first groove; A dielectric layer, located between adjacent electrode layers; The interconnection structure is located in the second groove.

2. The semiconductor structure according to claim 1, wherein: On the surface of the substrate, any one of the electrode layers exposes another adjacent electrode layer thereunder.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises an interconnection plug, which is located on each of the electrode layers with the surface exposed and is electrically connected thereto.

4. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a first insulating layer, located between the bottom electrode layer and the sidewall and bottom of the first groove, and between the bottom electrode layer and the substrate surface; The second insulating layer is located between the interconnection structure and the topmost electrode layer.

5. The semiconductor structure according to claim 1, wherein: The semiconductor structure further comprises: a protective sidewall located on the sidewall of each electrode layer on the surface of the substrate.

6. The semiconductor structure according to claim 1, wherein: A capacitor structure formed by multiple electrode layers is electrically connected to the interconnection structure.

7. The semiconductor structure according to claim 1, wherein: The first groove is a groove used to form a through-hole interconnection structure penetrating the substrate.

8. The semiconductor structure according to claim 1, wherein: The dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN; The material of the electrode layer includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

9. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first groove in the substrate; A plurality of stacked electrode layers and a dielectric layer located between adjacent electrode layers are formed in the first groove, the bottom electrode layer covers each surface of the first groove and extends to the surface of the substrate, the remaining electrode layers are stacked in sequence on the surface of the bottom electrode layer, and the top electrode layer forms a second groove in the first groove; An interconnect structure is formed in the second groove.

10. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming a plurality of stacked electrode layers and a dielectric layer located between adjacent electrode layers in the first groove comprises: alternately stacking electrode material layers and dielectric material layers on each surface of the first groove and the surface of the substrate until the topmost electrode material layer is formed; The multiple electrode material layers and dielectric material layers on the surface of the substrate are patterned to form a plurality of electrode layers and dielectric layers between adjacent electrode layers.

11. The method for forming a semiconductor structure according to claim 10, wherein: In the step of patterning the multiple electrode material layers and dielectric material layers on the substrate surface, on the substrate surface, any electrode layer exposes another adjacent electrode layer underneath it.

12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the interconnection structure in the second groove, the forming method further comprises: forming an interconnection plug on each electrode layer exposed on the surface and electrically connected thereto.

13. The method for forming a semiconductor structure according to claim 10, wherein: Before forming a multi-layer stacked electrode layer in the first groove, the method further includes: forming a first insulating layer covering each surface of the first groove and a surface of the substrate; In the step of forming a plurality of stacked electrode layers in the first groove, the bottommost electrode layer is formed on the first insulating layer; Before forming the interconnect structure in the second groove, the forming method further includes: forming a second insulating layer covering each surface of the second groove and a surface of the topmost electrode layer; In the step of forming an interconnection structure in the second groove, the interconnection structure is isolated from the topmost electrode layer by the second insulating layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The step of forming the second insulating layer includes: before patterning the multiple electrode material layers and dielectric material layers on the surface of the substrate, forming an insulating material layer covering the topmost electrode material layer; The insulating material layer is patterned, and the insulating material layer covering the topmost electrode layer is retained as the second insulating layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The insulating material layer and the topmost electrode material layer are patterned in the same step.

16. The method for forming a semiconductor structure according to claim 9, wherein: The step of forming an interconnection structure in the second groove includes: forming an interconnection material layer filling the second groove and covering the plurality of electrode layers; The interconnect material layer is planarized, and the interconnect material layer located in the second groove is retained as the interconnect structure.

17. The method for forming a semiconductor structure according to claim 9, wherein: After forming the interconnection structure in the second groove, the forming method further comprises: forming a protective sidewall on the sidewall of each electrode layer on the surface of the substrate.

18. The method for forming a semiconductor structure according to claim 9, wherein: After forming an interconnection structure in the second groove, the forming method further includes: electrically connecting a capacitor structure formed by a plurality of electrode layers to the interconnection structure.

19. The method for forming a semiconductor structure according to claim 9, wherein: After forming the interconnection structure in the second groove, the forming method further includes: performing a backside thinning process on the substrate until the interconnection structure at the bottom of the second groove is exposed.

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