Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the overlapped first electrode layers are located on the substrate, the edge of each first electrode layer is provided with a plurality of first electrode layer openings, and the side walls of the first electrode layer openings are sunken relative to the side walls of the edges of the first electrode layers; each second electrode layer is located between every two adjacent first electrode layers, the second electrode layers are insulated from the first electrode layers, a plurality of second electrode layer openings are formed in the edges, opposite to the edges of the first electrode layers, of each second electrode layer, and the side walls of the second electrode layer openings are sunken towards the side walls of the edges of the second electrode layers; the plurality of first conductive plugs penetrate through the edge of the second electrode layer, and each first conductive plug passes through the first electrode layer openings in the plurality of first electrode layers; and the plurality of second conductive plugs penetrate through the edge of the first electrode layer, and each second conductive plug passes through the second electrode layer openings in the plurality of second electrode layers so as to improve the electrical performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Capacitors are passive components commonly used in VLSI. Capacitors mainly include polysilicon-insulator-polysilicon (PIP) capacitors, metal-insulator-silicon (MIS) capacitors, and metal-insulator-metal (MIM) capacitors.

[0003] With the rapid development of wireless communication technology, people strongly hope to implant high-performance decoupling and bypass capacitors suitable for chip systems (SoC) into the copper interconnect terminal process of integrated circuits to obtain powerful RF systems. This further requires that the implanted capacitors should have high capacitance density, ideal voltage linearity, precise capacitance value control, and high reliability. Traditional PIP structures, MIS structures, and MOS structures have been difficult to meet performance requirements. Since MIM capacitors cause little interference to transistors and can provide better linearity and symmetry, the use of MIM capacitors will be the development trend of RF and analog / mixed signal integrated circuits.

[0004] However, the electrical performance of the MIM capacitor formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate; a plurality of overlapping first electrode layers located on the substrate, the edges of each first electrode layer respectively having a plurality of first electrode layer openings, the projection patterns of the first electrode layer openings in different first electrode layers overlap, and the side walls of the first electrode layer openings are recessed relative to the side walls of the first electrode layer edges; at least one second electrode layer, each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer, the edge of each second electrode layer opposite to the edge of the first electrode layer has a plurality of second electrode layer openings, the projection patterns of the second electrode layer openings in different second electrode layers overlap, and the side walls of the second electrode layer openings are recessed toward the side walls of the second electrode layer edges; a plurality of first conductive plugs penetrating the edges of the second electrode layers, each first conductive plug passing through the first electrode layer openings in the plurality of first electrode layers, and the side walls of the first conductive plugs contacting the second electrode layers; a plurality of second conductive plugs penetrating the edges of the first electrode layers, each second conductive plug passing through the second electrode layer openings in the plurality of second electrode layers, and the side walls of the second conductive plugs contacting the first electrode layers.

[0007] Optionally, there is a first distance between the side wall of the first electrode layer opening and the side wall of the first conductive plug, and the first distance is greater than 0.

[0008] Optionally, there is a second distance between the side wall of the second electrode layer opening and the side wall of the second conductive plug, and the second distance is greater than 0.

[0009] Optionally, the first electrode layer opening includes first sides that are distributed parallel to each other along a first direction and second sides connected to the first sides, the second sides extend along a second direction, and the first direction is perpendicular to the second direction.

[0010] Optionally, the second electrode layer opening includes third sides that are distributed parallel to each other along the first direction and fourth sides connected to the third sides, and the fourth sides extend along the second direction.

[0011] Optionally, it also includes: a third electrode layer opening, the third electrode layer opening is located in each first electrode layer, and the projection patterns of the third electrode layer openings in different first electrode layers overlap.

[0012] Optionally, it also includes: a plurality of third conductive plugs penetrating the second electrode layer, each third conductive plug passing through a third electrode layer opening in a plurality of first electrode layers, a distance from a side wall of the third electrode layer opening to a side wall of the third conductive plug being greater than 0, and a side wall of the third conductive plug being in contact with the second electrode layer.

[0013] Optionally, it also includes: a fourth electrode layer opening, the fourth electrode layer opening is located in each second electrode layer, and the projection patterns of the fourth electrode layer openings in different second electrode layers overlap.

[0014] Optionally, it also includes: a plurality of fourth conductive plugs penetrating the first electrode layer, each second conductive plug passes through a fourth electrode layer opening in a plurality of second electrode layers, the distance from the side wall of the fourth electrode layer opening to the side wall of the fourth conductive plug is greater than 0, and the side wall of the fourth conductive plug is in contact with the first electrode layer.

[0015] Optionally, the material of the first electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride and tungsten.

[0016] Optionally, the material of the second electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride and tungsten.

[0017] Optionally, it also includes: a first conductive structure located on the first conductive plug, and a second conductive structure located on the second conductive plug.

[0018] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of overlapping first electrode layers on the substrate; forming a plurality of first electrode layer openings at the edge of each first electrode layer, the projection patterns of the first electrode layer openings in different first electrode layers overlap, and the side walls of the first electrode layer openings are recessed relative to the side walls of the edge of the first electrode layer; forming at least one second electrode layer, each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer; forming a plurality of second electrode layer openings at the edge of each second electrode layer opposite to the edge of the first electrode layer, the projection patterns of the second electrode layer openings in different second electrode layers overlap, and the side walls of the second electrode layer openings are recessed toward the side walls of the edge of the second electrode layer; forming a plurality of first conductive plugs penetrating the second electrode layer, each first conductive plug passes through the first electrode layer openings in the plurality of first electrode layers, and the side walls of the first conductive plugs are in contact with the second electrode layer; forming a plurality of second conductive plugs penetrating the first electrode layer, each second conductive plug passes through the second electrode layer openings in the plurality of second electrode layers, and the side walls of the second conductive plugs are in contact with the first electrode layer.

[0019] Optionally, there is a first distance between the side wall of the first electrode layer opening and the side wall of the first conductive plug, and the first distance is greater than 0.

[0020] Optionally, there is a second distance between the side wall of the second electrode layer opening and the side wall of the second conductive plug, and the second distance is greater than 0.

[0021] Optionally, the first electrode layer opening includes first sides that are distributed parallel to each other along a first direction and second sides connected to the first sides, the second sides extend along a second direction, and the first direction is perpendicular to the second direction.

[0022] Optionally, the second electrode layer opening includes third sides that are distributed parallel to each other along the first direction and fourth sides connected to the third sides, and the fourth sides extend along the second direction.

[0023] Optionally, the method further includes forming a third electrode layer opening in the first electrode layer, and the projection patterns of the third electrode layer openings in different first electrode layers overlap.

[0024] Optionally, a plurality of third conductive plugs are formed penetrating the second electrode layer, each third conductive plug passes through a third electrode layer opening in the plurality of first electrode layers, a distance from a side wall of the third electrode layer opening to a side wall of the third conductive plug is greater than 0, and a side wall of the third conductive plug contacts the second electrode layer.

[0025] Optionally, a fourth electrode layer opening is formed in each second electrode layer, and projection patterns of the fourth electrode layer openings in different second electrode layers overlap.

[0026] Optionally, a plurality of fourth conductive plugs are formed penetrating the first electrode layer, each of the fourth conductive plugs passes through a fourth electrode layer opening in a plurality of second electrode layers, a distance from a side wall of the fourth electrode layer opening to a side wall of the fourth conductive plug is greater than 0, and a side wall of the fourth conductive plug contacts the first electrode layer.

[0027] Optionally, the material of the first electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride and tungsten.

[0028] Optionally, the material of the second electrode layer includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride and tungsten.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the semiconductor structure of the technical solution of the present invention, the edges of several overlapping first electrode layers on the substrate respectively have several first electrode layer openings, the projection patterns of the first electrode layer openings in different first electrode layers overlap, and the side walls of the first electrode layer openings are recessed relative to the side walls of the first electrode layer edges; there is a second electrode layer between adjacent first electrode layers, and the edge of the second electrode layer opposite to the first electrode layer has several second electrode layer openings, and the side walls of the second electrode layer openings are recessed toward the side walls of the second electrode layer edges; there are several first conductive plugs penetrating the edges of the second electrode layers, and each of the first conductive plugs passes through the first electrode layer openings in several first electrode layers; there are several second conductive plugs penetrating the edges of the first electrode layers. Conductive plug, each second conductive plug passes through the second electrode layer opening in the plurality of second electrode layers; the side wall of the first electrode layer opening is recessed relative to the side wall of the edge of the first electrode layer, so forming a first conductive plug at the edge of the first electrode layer is equivalent to losing half of the equivalent capacitance area of ​​the first electrode layer opening; similarly, the side wall of the second electrode layer opening is recessed toward the side wall of the edge of the second electrode layer, and similarly forming a second conductive plug at the edge of the second electrode layer is equivalent to losing half of the equivalent capacitance area of ​​the second electrode layer opening, which helps to reduce the equivalent series resistance while reducing the effective area of ​​the first electrode layer and the second electrode layer to a relatively small extent, and improves the overall high-frequency characteristics of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of a semiconductor structure;

[0032] Figures 2 to 18 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0033] As the background technology, the electrical performance of the MIM capacitor formed by the prior art needs to be improved.

[0034] Figure 1 It is a structural diagram of a semiconductor structure, in which, in order to observe the internal structure more clearly, the electrode layer is made transparent and simply represented by different types of lines, and the insulating layers involved in the middle are omitted.

[0035] Please refer to Figure 1, a semiconductor structure, comprising: a substrate (not shown in the figure); a first electrode layer 101 overlapping the substrate, the first electrode layer 101 comprising first electrode layers 101a and 101b, the first electrode layer 101 having a first electrode layer opening 102, a second electrode layer 103 located between adjacent first electrode layers 101, the second electrode layer 103 having a second electrode layer opening 103a, a first conductive plug (not shown in the figure) penetrating the second electrode layer 103, the first conductive plug passing through the first electrode layer openings 102 in several layers of the first electrode layer 101; a first conductive structure 103b located on the first conductive plug; several second conductive plugs (not shown in the figure) penetrating the first electrode layer 101, the second conductive plug passing through the second electrode layer openings 103a in several layers of the second electrode layer 103; a second conductive structure 104 located on the second conductive plug; a first pin 105 located on the first conductive structure 103b; and a second pin 106 located on the second conductive structure 104.

[0036] The inventors discovered that the shape of the first electrode layer opening 102 projected onto the substrate is a square, and the shape of the second electrode layer opening 103a projected onto the substrate is also a square. Since a large part of the capacitor is occupied by the electrode layer opening, a reduction in the effective area of ​​the electrode layer will lead to a decrease in capacitance, thereby affecting the electrical performance of the semiconductor structure ultimately formed.

[0037] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein the edges of several overlapping first electrode layers on a substrate respectively have several first electrode layer openings, the projection patterns of the first electrode layer openings in different first electrode layers overlap, and the side walls of the first electrode layer openings are recessed relative to the side walls of the first electrode layer edges; a second electrode layer is provided between adjacent first electrode layers, the edge of the second electrode layer opposite to the first electrode layer has several second electrode layer openings, and the side walls of the second electrode layer openings are recessed toward the side walls of the second electrode layer edges; several first conductive plugs are provided through the edges of the second electrode layers, and each of the first conductive plugs passes through the first electrode layer openings in the several first electrode layers; and the first conductive plugs are provided through the edges of the first electrode layers. A plurality of second conductive plugs are provided, each of which passes through a second electrode layer opening in the plurality of second electrode layers; the side wall of the first electrode layer opening is recessed relative to the side wall of the edge of the first electrode layer, so forming a first conductive plug at the edge of the first electrode layer is equivalent to sacrificing an equivalent capacitance area of ​​half of the first electrode layer opening; similarly, the side wall of the second electrode layer opening is recessed toward the side wall of the edge of the second electrode layer, and similarly, forming a second conductive plug at the edge of the second electrode layer is equivalent to sacrificing an equivalent capacitance area of ​​half of the second electrode layer opening, which helps to reduce the equivalent series resistance while reducing the effective area of ​​the first electrode layer and the second electrode layer to a relatively small extent, and improves the overall high-frequency characteristics of the semiconductor structure.

[0038] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 18 It is a schematic structural diagram of each step of a method for forming a semiconductor structure in one embodiment of the present invention.

[0040] First, please refer to Figure 2 and Figure 3 , providing a substrate 200.

[0041] Figure 3 for Figure 2 Cross-section view at AA Figure 2 for Figure 3 Top view of the .

[0042] In this embodiment, the substrate 200 has a first conductive layer 201 and a second conductive layer 202 .

[0043] In this embodiment, the substrate 200 further has a plurality of device structures (not shown), and the first conductive layer 201 and the second conductive layer 202 are electrically connected to the plurality of device structures respectively.

[0044] Please refer to Figure 4 , a plurality of overlapping first electrode layers 203 are formed on the substrate 200 .

[0045] Figure 4 The viewing direction and Figure 2 The viewing direction is consistent.

[0046] exist Figure 5 First, a first electrode layer 203 is formed on the substrate 200 .

[0047] In this embodiment, the method for forming the first electrode layer 203 on the substrate 200 includes: forming a first electrode material layer (not shown) on the substrate 200 ; and performing a first patterning process on the first electrode material layer to form the first electrode layer 203 .

[0048] The formation process of the first electrode material layer includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.

[0049] In this embodiment, the first electrode material layer is formed by an atomic layer deposition process.

[0050] The material of the first electrode layer 203 includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride and tungsten.

[0051] In this embodiment, the material of the first electrode layer 203 is titanium nitride.

[0052] Please refer to Figure 5 A plurality of first electrode layer openings 203 a are formed at the edge of each first electrode layer, the projection patterns of the first electrode layer openings 203 a in different first electrode layers 203 overlap, and the side walls of the first electrode layer openings 203 a are recessed relative to the side walls of the edges of the first electrode layers 203 .

[0053] Figure 5 The viewing direction and Figure 4 The viewing direction is the same.

[0054] In this embodiment, a plurality of first electrode layer openings 203 a are formed at the edge of the first electrode layer 203 , and the sidewalls of the first electrode layer openings 203 a are recessed relative to the sidewalls of the edge of the first electrode layer 203 .

[0055] In this embodiment, the first electrode layer opening 203a includes first edges 203b parallel to each other along a first direction and second edges 203c connected to the first edges 203b. The second edges 203c extend along a second direction. The first direction is perpendicular to the second direction.

[0056] In this embodiment, the first direction is the X direction, and the second direction is the Y direction.

[0057] Please continue to refer to Figure 5 , further comprising forming a third electrode layer opening 203d in the first electrode layer 203, wherein projection patterns of the third electrode layer openings 203d in different first electrode layers 203 overlap.

[0058] In this embodiment, the projection of the third electrode layer opening 203d toward the substrate is square.

[0059] In other embodiments, the projection of the third electrode layer opening 203d toward the substrate may also be a non-square shape.

[0060] Please refer to Figure 6 , a first insulating layer 204 is formed on the substrate 200 , and the first insulating layer 204 covers the surface of the first electrode layer 203 and fills the first electrode layer opening 203 a and the third electrode layer opening 203 d .

[0061] The material of the first insulating layer 204 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide or aluminum oxide.

[0062] In this embodiment, the material of the first insulating layer 204 is hafnium oxide.

[0063] Please refer to Figure 7 , a second electrode layer 205 is formed on the first insulating layer 204 .

[0064] In this embodiment, the method for forming the second electrode layer 205 on the first insulating layer 204 includes: forming a second electrode material layer (not shown) on the first insulating layer 204 ; and performing a second patterning process on the second electrode material layer to form the second electrode layer 205 .

[0065] The formation process of the second electrode material layer includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.

[0066] In this embodiment, the second electrode material layer is formed by an atomic layer deposition process.

[0067] The material of the second electrode layer 205 includes one or more of nickel, tantalum, titanium, platinum, tantalum nitride, titanium oxide, titanium nitride and tungsten.

[0068] In this embodiment, the material of the second electrode layer 205 is titanium nitride.

[0069] Please refer to Figure 8 A plurality of second electrode layer openings 205 a are formed at the edge of each second electrode layer 205 opposite to the edge of the first electrode layer 203 , and the sidewalls of the second electrode layer openings 205 a are recessed toward the sidewalls of the edge of the second electrode layer 205 .

[0070] In this embodiment, the projection patterns of the openings 205a of each second electrode layer overlap.

[0071] In this embodiment, the second electrode layer opening 205a includes third sides 205b distributed parallel to each other along the first direction and fourth sides 205c connected to the third sides 205b, and the fourth sides 205c extend along the second direction.

[0072] In this embodiment, the first direction is the X direction, and the second direction is the Y direction.

[0073] Please continue to refer to Figure 8 , further comprising forming a fourth electrode layer opening in each second electrode layer 205, wherein projection patterns of the fourth electrode layer openings in different second electrode layers 205 overlap.

[0074] In this embodiment, the projection of the opening of the fourth electrode layer toward the substrate is square.

[0075] In other embodiments, the projection of the opening of the fourth electrode layer toward the substrate may also be non-square.

[0076] Please refer to Fig. 9 , a second insulating layer 206 is formed on the first insulating layer 204 , and the second insulating layer 206 covers the surface of the second electrode layer 205 .

[0077] The material of the second insulating layer 206 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide or aluminum oxide.

[0078] In this embodiment, the material of the second insulating layer 206 is hafnium oxide.

[0079] Please refer to Fig.10 , a first electrode layer 203 is further formed on the second insulating layer 206 .

[0080] In this embodiment, the semiconductor structure only shows two stacked first electrode layers 203 , and a second electrode layer 205 is formed between the two first electrode layers 203 .

[0081] In other embodiments, the second electrode layer 205 may be further formed on the first electrode layer 203 , and the first electrode layer 203 may be further stacked on the second electrode layer 205 . This process may be repeated according to this rule to form multiple layers of stacked first electrode layers 203 , and a second electrode layer 205 may be formed between adjacent first electrode layers 203 .

[0082] Please refer to Fig.11 A plurality of first electrode layer openings 203 a are formed at the edge of the first electrode layer 203 .

[0083] In this embodiment, the projection pattern of the first electrode layer opening 203 a in the first electrode layer 203 overlaps with the projection pattern of the first electrode layer opening 203 a in the first electrode layer 203 located at the bottom of the second electrode layer 205 .

[0084] Please refer to Fig.12 , a dielectric layer 207 is formed on the substrate 200 , and the dielectric layer 207 covers the first electrode layer 203 , the second electrode layer 205 , the first electrode layer 203 , the first insulating layer 204 and the second insulating layer 206 .

[0085] In this embodiment, the material of the dielectric layer 207 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0086] In this embodiment, after forming the dielectric layer 207, the process further includes: forming a first through hole and a second through hole in the dielectric layer 207. For details on the formation process of the first through hole and the second through hole, please refer to Figure 13 to Figure 14 .

[0087] Please refer to Figure 13 to Figure 14, a first through hole 208 and a second through hole 209 are respectively formed in the dielectric layer 207 .

[0088] Fig.13 for Fig.14 A top view of Fig.14 for Fig.13 Cross-sectional view at AA.

[0089] In this embodiment, the first through hole 208 passes through the first electrode layer opening 203a in the first electrode layer 203, penetrates the second insulating layer 206, the second electrode layer 205, and the first insulating layer 204, and then extends into the substrate to expose a portion of the top surface of the first conductive layer 201.

[0090] In this embodiment, each second through hole 209 passes through the second electrode layer opening 205a in the second electrode layer 205, penetrates the first electrode layer 203, the second insulating layer 206, the first electrode layer 203, the first insulating layer 204, and then extends into the substrate to expose a portion of the top surface of the second conductive layer 201.

[0091] In this embodiment, third through holes 210 are further formed in the dielectric layer 207. Each third through hole 210 passes through a third electrode layer opening 203d in the first electrode layer 203, penetrates the second insulating layer 206, the second electrode layer 205, and the first insulating layer 204, and then extends into the substrate to expose a portion of the top surface of the first conductive layer 201.

[0092] In this embodiment, fourth through holes 211 are further formed in the dielectric layer 207. Each fourth through hole 211 passes through a fourth electrode layer opening in the plurality of second electrode layers 205, penetrates the first electrode layer 203, the second insulating layer 206, the first electrode layer 203, the first insulating layer 204, and then extends into the substrate to expose a portion of the top surface of the second conductive layer 202.

[0093] Please refer to Figures 15 to 17 , a first conductive plug 212 is formed in the first through hole 208 ; and a second conductive plug 213 is formed in the second through hole 209 .

[0094] Fig.15 The view direction of the figure and Fig.14 The viewing direction is consistent with Fig.16 and Fig.13 The viewing direction is consistent with Fig.17 yes Fig.16 The relationship between the first electrode layer, the second electrode layer and the opening of the first electrode layer at the middle edge, Fig.17 The first electrode layer and the second electrode layer are made transparent, and the insulating layer and the dielectric layer are omitted.

[0095] In this embodiment, there is a first distance between the sidewall of the first electrode layer opening 203a and the sidewall of the first conductive plug 212, and the size of the first distance is greater than 0 (please refer to Fig.17 ), and the sidewall of the first conductive plug 212 is in contact with the second electrode layer 205.

[0096] In this embodiment, there is a second distance between the sidewall of the second electrode layer opening 205a and the sidewall of the second conductive plug 213, and the size of the second distance is greater than 0 (please refer to Fig.17 ), and the sidewall of the second conductive plug 213 is in contact with the first electrode layer 203.

[0097] In this embodiment, the first conductive plug 212 is equivalent to riding on the boundary of the entire first electrode layer 203. It is not surrounded by the first electrode layer opening 203a. Instead, the first conductive plug 212 is designed to be outside the edge of the first electrode layer 203 by being recessed toward the center of the first electrode layer 203 through the first electrode layer opening 203a. This first conductive plug 212 can help reduce the equivalent series resistance and improve the high-frequency characteristics of the entire semiconductor structure while slightly reducing the effective area of ​​the first electrode layer 203.

[0098] In the present embodiment, similarly, the second conductive plug 213 is equivalent to riding on the boundary of the entire second electrode layer 205. It is not surrounded by the second electrode layer opening 205a. Instead, the second conductive plug 213 is designed to be outside the edge of the second electrode layer 205 by being recessed toward the center of the second electrode layer 205 through the second electrode layer opening 205a. Such a second conductive plug 213 can help reduce the equivalent series resistance and enhance the high-frequency characteristics of the entire semiconductor structure while slightly reducing the effective area of ​​the second electrode layer 205.

[0099] In this embodiment, the first conductive plug 212 is electrically connected to the first conductive layer 201 ; and the second conductive plug 213 is electrically connected to the second conductive layer 202 .

[0100] In this embodiment, the method for forming the first conductive plug 212 and the second conductive plug 213 includes: forming a conductive plug material layer (not shown) in the first through hole 208, in the second through hole 209 and on the dielectric layer 207; and planarizing the conductive plug material layer until the top surface of the dielectric layer 207 is exposed, thereby forming the first conductive plug 212 and the second conductive plug 213.

[0101] The material of the first conductive plug 212 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum; the material of the second conductive plug 213 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.

[0102] In this embodiment, before forming the first conductive plug 212 , the method further includes: forming a first auxiliary layer on the bottom surface and sidewall of the first through hole 208 ; and the first conductive plug 212 is located on the first auxiliary layer.

[0103] In this embodiment, before forming the second conductive plug 213 , the method further includes: forming a second auxiliary layer on the bottom surface and sidewall of the second through hole; and the second conductive plug 213 is located on the second auxiliary layer.

[0104] It should be noted that, in the present embodiment, when the metal material selected for the first conductive plug 212 and the second conductive plug 213 has a strong metal activity, such as metal copper, the first auxiliary layer and the second auxiliary layer are barrier layers, and their function is to prevent the metal diffusion of the first conductive plug 212 and the second conductive plug 213, thereby causing metal contamination; when the metal material selected for the first conductive plug 212 and the second conductive plug 213 has poor adhesion, such as metal tungsten, the first auxiliary layer and the second auxiliary layer are adhesion layers, and their function is to increase the adhesion between the first conductive plug 212 and the second conductive plug 213 and the dielectric layer.

[0105] Please continue to refer to Fig.16 , a third conductive plug 214 is formed in the third through hole 210 ; and a fourth conductive plug 215 is formed in the fourth through hole 211 .

[0106] In this embodiment, the third conductive plug 214 is electrically connected to the first conductive layer 201 ; and the fourth conductive plug 215 is electrically connected to the second conductive layer 202 .

[0107] The material of the third conductive plug 214 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum; the material of the fourth conductive plug 215 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.

[0108] Please refer to Fig.18 , a first conductive structure 216 is formed on the first conductive plug 212 , and a second conductive structure 217 is formed on the second conductive plug 213 .

[0109] Fig.18 The viewing direction and Fig.16 The viewing direction is consistent.

[0110] In this embodiment, the first conductive structure 216 is further formed on the third conductive plug 216 , and the second conductive structure 217 is formed on the fourth conductive plug.

[0111] Please continue to refer to Fig.18 , a first pin 218 is formed on the first conductive structure 216 , and a second pin 219 is formed on the second conductive structure 217 .

[0112] Correspondingly, the present invention further provides a semiconductor structure, comprising a substrate; a plurality of overlapping first electrode layers 203 located on the substrate, the edges of each first electrode layer 203 respectively having a plurality of first electrode layer openings 203a, the projection patterns of the first electrode layer openings 203a in different first electrode layers 203 overlap, and the sidewalls of the first electrode layer openings 203a are recessed relative to the sidewalls of the edges of the first electrode layers 203; at least one second electrode layer 205, each second electrode layer 205 is located between two adjacent first electrode layers 203, and the second electrode layer 205 is insulated from the first electrode layer 203, and each second electrode layer 205 is insulated from the edges of the first electrode layer 203. The edges of the second electrode layer 205 are provided with a plurality of second electrode layer openings 205a, and the side walls of the second electrode layer openings 205a are recessed toward the side walls of the edges of the second electrode layer 205; a plurality of first conductive plugs 212 are passed through the edges of the second electrode layer 205, and each of the first conductive plugs 212 passes through the first electrode layer openings 203a in a plurality of layers of the first electrode layer 203, and the side walls of the first conductive plugs 212 are in contact with the second electrode layer 205; a plurality of second conductive plugs 213 are passed through the edges of the first electrode layer 203, and each of the second conductive plugs 213 passes through the second electrode layer openings 205a in a plurality of layers of the second electrode layer 205, and the side walls of the second conductive plugs 213 are in contact with the first electrode layer 203.

[0113] In this embodiment, the edges of several overlapping first electrode layers 203 on the substrate respectively have several first electrode layer openings 203a, the projection patterns of the first electrode layer openings 203a in the first electrode layers 203 of different layers overlap, and the side walls of the first electrode layer openings 203a are recessed relative to the side walls of the edges of the first electrode layers 203; there is a second electrode layer 205 between adjacent first electrode layers 203, and the edges of the second electrode layer 205 opposite to the first electrode layer 203 have several second electrode layer openings 205a, and the side walls of the second electrode layer openings 205a are recessed toward the side walls of the edges of the second electrode layer 205; there are several first conductive plugs 212 penetrating the edges of the second electrode layer 205, and each of the first conductive plugs 212 passes through the first electrode layer openings 203a in several first electrode layers 203; there are several first conductive plugs 212 penetrating the edges of the first electrode layer 203 Two conductive plugs 213, each second conductive plug 213 passes through a second electrode layer opening 205a in a plurality of second electrode layers 205; by utilizing the side wall of the first electrode layer opening 203a to be recessed relative to the side wall of the edge of the first electrode layer 203, forming a first conductive plug 212 at the edge of the first electrode layer 203 is equivalent to sacrificing an equivalent capacitance area of ​​half of the first electrode layer opening 203a; similarly, by utilizing the side wall of the second electrode layer opening 205a to be recessed toward the side wall of the edge of the second electrode layer 205, forming a second conductive plug 213 at the edge of the second electrode layer 205 is equivalent to sacrificing an equivalent capacitance area of ​​half of the second electrode layer opening 205a, which helps to reduce the equivalent series resistance while reducing the effective area of ​​the first electrode layer 203 and the second electrode layer 205 to a relatively small extent, and improves the overall high-frequency characteristics of the semiconductor structure.

[0114] In this embodiment, there is a first distance between the sidewall of the first electrode layer opening 203a and the sidewall of the first conductive plug 212, and the size of the first distance is greater than 0 (please refer to Fig.17 ), and the sidewall of the first conductive plug 212 is in contact with the second electrode layer 205.

[0115] In this embodiment, there is a second distance between the sidewall of the second electrode layer opening 205a and the sidewall of the second conductive plug 213, and the size of the second distance is greater than 0 (please refer to Fig.17 ), and the sidewall of the second conductive plug 213 is in contact with the first electrode layer 203.

[0116] In this embodiment, the first electrode layer opening 203a includes first edges 203b parallel to each other along a first direction and second edges 203c connected to the first edges 203b. The second edges 203c extend along a second direction. The first direction is perpendicular to the second direction.

[0117] In this embodiment, the second electrode layer opening 205a includes third sides 205b distributed parallel to each other along the first direction and fourth sides 205c connected to the third sides 205b, and the fourth sides 205c extend along the second direction.

[0118] In this embodiment, it further includes: a third electrode layer opening 203d, the third electrode layer opening 203d is located in each first electrode layer 203, and the projection patterns of the first electrode layer openings 203a in different first electrode layers 203 overlap.

[0119] In this embodiment, it also includes: a plurality of first conductive plugs 212 penetrating the second electrode layer 205, each first conductive plug 212 passes through a third electrode layer opening 203d in a plurality of first electrode layers 203, the distance from the side wall of the third electrode layer opening 203d to the side wall of the first conductive plug 212 is greater than 0, and the side wall of the first conductive plug 212 is in contact with the second electrode layer 205.

[0120] In this embodiment, it further includes: a fourth electrode layer opening, the fourth electrode layer opening is located in each second electrode layer 205, and the projection patterns of the fourth electrode layer openings in different second electrode layers 205 overlap.

[0121] In this embodiment, a plurality of second conductive plugs 213 are passed through the first electrode layer 203 , each second conductive plug 213 passes through a fourth electrode layer opening in a plurality of second electrode layers 205 , a distance from a side wall of the fourth electrode layer opening to a side wall of the second conductive plug 213 is greater than 0, and a side wall of the second conductive plug 213 is in contact with the first electrode layer 203 .

[0122] In this embodiment, the first conductive plug 212 and a first conductive structure 216 on the first conductive plug 212 , and a first pin 218 on the first conductive structure 216 are also included.

[0123] In this embodiment, the second conductive plug 213 and a second conductive structure 217 on the second conductive plug 213 and a second pin 219 on the second conductive structure 217 are also included.

[0124] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of overlapping first electrode layers located on the substrate, each first electrode layer having a plurality of first electrode layer openings at its edge, projection patterns of the first electrode layer openings in different first electrode layers overlapping, and side walls of the first electrode layer openings being recessed relative to side walls of the first electrode layer edges; at least one second electrode layer, each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer, and each second electrode layer has a plurality of second electrode layer openings at an edge opposite to an edge of the first electrode layer, projection patterns of the second electrode layer openings in different second electrode layers overlap, and side walls of the second electrode layer openings are recessed toward side walls of the edges of the second electrode layer; a plurality of first conductive plugs penetrating the edge of the second electrode layer, each of the first conductive plugs passing through the first electrode layer openings in the plurality of first electrode layers, and a side wall of the first conductive plug in contact with the second electrode layer; A plurality of second conductive plugs are passed through the edge of the first electrode layer, each of the second conductive plugs passes through a second electrode layer opening in the plurality of second electrode layers, and a side wall of the second conductive plug is in contact with the first electrode layer.

2. The semiconductor structure according to claim 1, wherein: There is a first distance between the sidewall of the first electrode layer opening and the sidewall of the first conductive plug, and the first distance is greater than 0.

3. The semiconductor structure according to claim 1, wherein: There is a second distance between the sidewall of the second electrode layer opening and the sidewall of the second conductive plug, and the second distance is greater than 0.

4. The semiconductor structure according to claim 1, wherein: The first electrode layer opening includes first sides parallel to each other along a first direction and second sides connected to the first sides, the second sides extend along a second direction, and the first direction is perpendicular to the second direction.

5. The semiconductor structure according to claim 1, wherein: The second electrode layer opening includes third sides that are parallel to each other along the first direction and fourth sides connected to the third sides, and the fourth sides extend along the second direction.

6. The semiconductor structure according to claim 1, wherein: Also includes: The third electrode layer opening is located in each of the first electrode layers, and projection patterns of the third electrode layer openings in different first electrode layers overlap.

7. The semiconductor structure according to claim 6, wherein: Also includes: A plurality of third conductive plugs are passed through the second electrode layer, each of the third conductive plugs passes through the third electrode layer openings in the plurality of first electrode layers, a distance from a side wall of the third electrode layer opening to a side wall of the third conductive plug is greater than 0, and a side wall of the third conductive plug is in contact with the second electrode layer.

8. The semiconductor structure according to claim 1, wherein: Also includes: The fourth electrode layer opening is located in each second electrode layer, and projection patterns of the fourth electrode layer opening in different second electrode layers overlap.

9. The semiconductor structure according to claim 8, characterized in that Also includes: A plurality of fourth conductive plugs are passed through the first electrode layer, each of the fourth conductive plugs passes through a fourth electrode layer opening in a plurality of second electrode layers, a distance from a side wall of the fourth electrode layer opening to a side wall of the fourth conductive plug is greater than 0, and a side wall of the fourth conductive plug is in contact with the first electrode layer.

10. The semiconductor structure according to claim 1, wherein: Also includes: A first conductive structure is located on the first conductive plug, and a second conductive structure is located on the second conductive plug.

11. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of overlapping first electrode layers on the substrate; A plurality of first electrode layer openings are respectively formed at the edge of each first electrode layer, the projection patterns of the first electrode layer openings in different first electrode layers overlap, and the sidewalls of the first electrode layer openings are recessed relative to the sidewalls of the edges of the first electrode layers; forming at least one second electrode layer, wherein each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer; A plurality of second electrode layer openings are formed at the edge of each second electrode layer opposite to the edge of the first electrode layer, the projection patterns of the second electrode layer openings in different second electrode layers overlap, and the sidewalls of the second electrode layer openings are recessed toward the sidewalls of the edge of the second electrode layer; forming a plurality of first conductive plugs penetrating the second electrode layer, each of the first conductive plugs passing through the first electrode layer openings in the plurality of first electrode layers, and a side wall of the first conductive plug in contact with the second electrode layer; A plurality of second conductive plugs penetrating the first electrode layer are formed, each of the second conductive plugs passes through a second electrode layer opening in the plurality of second electrode layers, and a side wall of the second conductive plug contacts the first electrode layer.

12. The method for forming a semiconductor structure according to claim 11, wherein: There is a first distance between the sidewall of the first electrode layer opening and the sidewall of the first conductive plug, and the first distance is greater than 0.

13. The method for forming a semiconductor structure according to claim 11, wherein: There is a second distance between the sidewall of the second electrode layer opening and the sidewall of the second conductive plug, and the second distance is greater than 0.

14. The method for forming a semiconductor structure according to claim 11, wherein: The first electrode layer opening includes first sides parallel to each other along a first direction and second sides connected to the first sides, the second sides extend along a second direction, and the first direction is perpendicular to the second direction.

15. The method for forming a semiconductor structure according to claim 11, wherein: The second electrode layer opening includes third sides that are parallel to each other along the first direction and fourth sides connected to the third sides, and the fourth sides extend along the second direction.

16. The method for forming a semiconductor structure according to claim 11, wherein: The method further includes forming a third electrode layer opening in the first electrode layer, wherein projection patterns of the third electrode layer openings in different layers of the first electrode layer overlap.

17. The method for forming a semiconductor structure according to claim 16, wherein: A plurality of third conductive plugs are formed penetrating the second electrode layer, each of the third conductive plugs passes through the third electrode layer openings in the plurality of first electrode layers, a distance from the side wall of the third electrode layer opening to the side wall of the third conductive plug is greater than 0, and the side wall of the third conductive plug is in contact with the second electrode layer.

18. The method for forming a semiconductor structure according to claim 11, wherein: A fourth electrode layer opening is formed in each second electrode layer, and projection patterns of the fourth electrode layer openings in different second electrode layers overlap.

19. The method for forming a semiconductor structure according to claim 18, wherein: A plurality of fourth conductive plugs are formed penetrating the first electrode layer, each of the fourth conductive plugs passes through a fourth electrode layer opening in a plurality of second electrode layers, a distance from a side wall of the fourth electrode layer opening to a side wall of the second conductive plug is greater than 0, and a side wall of the second conductive plug is in contact with the first electrode layer.

Images