Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method. The semiconductor structure comprises a substrate; the plurality of overlapped first electrode layers are located on the substrate, each first electrode layer is internally provided with a plurality of first electrode layer openings, each first electrode layer opening is internally provided with a plurality of first compensation parts, and the side wall of each first compensation part protrudes towards the central axis of the corresponding first electrode layer opening; at least one second electrode layer, each second electrode layer is located between two adjacent first electrode layers, and each second electrode layer is internally provided with a plurality of second electrode layer openings; the first conductive plugs penetrate through the second electrode layer, the first conductive plugs pass through the first electrode layer openings in the first electrode layers, and the side walls of the first conductive plugs make contact with the second electrode layer; the plurality of second conductive plugs penetrate through the first electrode layer, each second conductive plug passes through the second electrode layer openings in the plurality of second electrode layers, and the side walls of the second conductive plugs are in contact with the first electrode layer, so that the electrical performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Capacitors are passive components commonly used in VLSI. Capacitors mainly include polysilicon-insulator-polysilicon (PIP) capacitors, metal-insulator-silicon (MIS) capacitors, and metal-insulator-metal (MIM) capacitors.

[0003] With the rapid development of wireless communication technology, people strongly hope to implant high-performance decoupling and bypass capacitors suitable for chip systems (SoC) into the copper interconnect terminal process of integrated circuits to obtain powerful RF systems. This further requires that the implanted capacitors should have high capacitance density, ideal voltage linearity, precise capacitance value control, and high reliability. Traditional PIP structures, MIS structures, and MOS structures have been difficult to meet performance requirements. Since MIM capacitors cause little interference to transistors and can provide better linearity and symmetry, the use of MIM capacitors will be the development trend of RF and analog / mixed signal integrated circuits.

[0004] However, the electrical performance of the MIM capacitor formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure comprising: a substrate; a plurality of overlapping first electrode layers located on the substrate, each of the first electrode layers having a plurality of first electrode layer openings, the projection patterns of the first electrode layer openings in different first electrode layers overlapping, each of the first electrode layer openings having a plurality of first compensation parts, and the side walls of the first compensation parts protruding toward the central axis of the first electrode layer opening; at least one second electrode layer, each of the second electrode layers being located between two adjacent first electrode layers, and the second electrode layers being insulated from the first electrode layers, and each of the second electrode layers having a plurality of second electrode layer openings; a plurality of first conductive plugs penetrating the second electrode layers, each of the first conductive plugs passing through the first electrode layer openings in the plurality of first electrode layers, and the side walls of the first conductive plugs contacting the second electrode layer; a plurality of second conductive plugs penetrating the first electrode layer, each of the second conductive plugs passing through the second electrode layer openings in the plurality of second electrode layers, and the side walls of the second conductive plugs contacting the first electrode layer.

[0007] Optionally, there is a first distance between the first electrode layer opening and the side wall of the first conductive plug, and the first distance is greater than 0.

[0008] Optionally, there is a second distance between the second electrode layer opening and the side wall of the second conductive plug, and the second distance is greater than 0.

[0009] Optionally, the first electrode layer opening includes first edges parallel to each other along a first direction and second edges parallel to each other along a second direction, the first direction and the second direction are perpendicular, the side wall of the first compensation portion includes a first compensation edge and a second compensation edge connected to each other, the first compensation edge extends along the first direction and the other end is connected to the second edge, the second compensation edge extends along the second direction and the other end is connected to the first edge, the side wall of the first compensation portion protrudes toward the central axis of the first electrode layer opening, and a plurality of first compensation portions are symmetrically distributed along the center of the first electrode layer opening.

[0010] Optionally, the length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in a range of 0.05:1 to 0.25:1.

[0011] Optionally, a plurality of second compensation parts are provided in the second electrode layer opening, and side walls of the second compensation parts protrude toward a central axis of the second electrode layer opening.

[0012] Optionally, the second electrode layer opening includes a third side parallel to each other along the first direction and a fourth side parallel to each other along the second direction, the side wall of the second compensation portion includes a third compensation side and a fourth compensation side connected to each other, the third compensation side extends along the first direction and the other end is connected to the fourth side, the fourth compensation side extends along the second direction and the other end is connected to the third side, the side wall of the second compensation portion protrudes toward the central axis of the second electrode layer opening, and a plurality of second compensation portions are symmetrically distributed along the center of the second electrode layer opening.

[0013] Optionally, the length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in a range of 0.05:1 to 0.25:1.

[0014] Optionally, it also includes a first conductive structure located on the first conductive plug and a second conductive structure located on the second conductive plug.

[0015] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of overlapping first electrode layers on the substrate; forming a plurality of first electrode layer openings in each first electrode layer, wherein the projection patterns of the first electrode layer openings in different first electrode layers overlap; forming a plurality of first compensation portions in each first electrode layer opening, wherein the side walls of the first compensation portions protrude toward the central axis of the first electrode layer opening; forming at least one second electrode layer, wherein each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer, and each second electrode layer has a plurality of second electrode layer openings; forming a plurality of first conductive plugs penetrating the second electrode layer, wherein each first conductive plug passes through the first electrode layer opening in the plurality of first electrode layers, and the side walls of the first conductive plug are in contact with the second electrode layer; and forming a plurality of second conductive plugs penetrating the first electrode layer, wherein each second conductive plug passes through the second electrode layer opening in the plurality of second electrode layers, and the side walls of the second conductive plug are in contact with the first electrode layer.

[0016] Optionally, there is a first distance between the first electrode layer opening and the side wall of the first conductive plug, and the first distance is greater than 0.

[0017] Optionally, there is a second distance between the second electrode layer opening and the side wall of the second conductive plug, and the second distance is greater than 0.

[0018] Optionally, the first electrode layer opening includes first edges parallel to each other along a first direction and second edges parallel to each other along a second direction, the first direction and the second direction are perpendicular, the side wall of the first compensation portion includes a first compensation edge and a second compensation edge connected to each other, the first compensation edge extends along the first direction and the other end is connected to the second edge, the second compensation edge extends along the second direction and the other end is connected to the first edge, the side wall of the first compensation portion protrudes toward the central axis of the first electrode layer opening, and a plurality of first compensation portions are symmetrically distributed along the center of the first electrode layer opening.

[0019] Optionally, the length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in a range of 0.05:1 to 0.25:1.

[0020] Optionally, a plurality of second compensation parts are formed in the second electrode layer opening, and side walls of the second compensation parts protrude toward a central axis of the second electrode layer opening.

[0021] Optionally, the second electrode layer opening includes a third side parallel to each other along the first direction and a fourth side parallel to each other along the second direction, the side wall of the second compensation portion includes a third compensation side and a fourth compensation side connected to each other, the third compensation side extends along the first direction and the other end is connected to the fourth side, the fourth compensation side extends along the second direction and the other end is connected to the third side, the side wall of the second compensation portion protrudes toward the central axis of the second electrode layer opening, and a plurality of second compensation portions are symmetrically distributed along the center of the second electrode layer opening.

[0022] Optionally, the length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in a range of 0.05:1 to 0.25:1.

[0023] Optionally, the method further includes forming a first conductive structure on the first conductive plug, and forming a second conductive structure on the second conductive plug.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the semiconductor structure of the technical solution of the present invention, several overlapping first electrode layers on the substrate respectively have several first electrode layer openings, the projection patterns of the first electrode layer openings in different first electrode layers overlap, and each first electrode layer opening has multiple first compensation parts. The side walls of the first compensation parts protrude toward the central axis of the first electrode layer opening, thereby increasing the remaining area of ​​the first electrode layer, thereby increasing the effective capacitance of the semiconductor structure, thereby improving the electrical performance of the finally formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0027] Figures 2 to 16 is a schematic structural diagram of each step of a method for forming a semiconductor structure in a first embodiment of the present invention;

[0028] Fig.17 Schematic diagram of the structure of the second electrode layer opening in the second embodiment of the present invention. DETAILED DESCRIPTION

[0029] As the background technology, the electrical performance of the MIM capacitor formed by the prior art needs to be improved.

[0030] Figure 1 It is a structural diagram of a semiconductor structure, in which, in order to observe the internal structure more clearly, the electrode plate is made transparent and simply represented by different types of lines, and the insulating layers involved in the middle are omitted.

[0031] Please refer to Figure 1 A semiconductor structure includes: a substrate (not shown); a first electrode layer 101 located on the substrate, the first electrode layer 101 including a stacked first sub-electrode layer 101a and a second sub-electrode layer 101b, the first electrode layer 101 having a first electrode layer opening 102, the projection of the first electrode layer opening 102 in the first sub-electrode layer 101a toward the substrate and the projection of the first electrode layer opening 102 in the second sub-electrode layer 101b toward the substrate coincide with each other; a second electrode layer 103 located between the first sub-electrode layer 101a and the second sub-electrode layer 101b, the second electrode layer 103 having a second electrode layer opening 103a; a first conductive plug penetrating the second electrode layer 103; Plug (not shown in the figure), a first conductive plug passes through a first electrode layer opening 102 in several layers of first electrode layers 101 (first sub-electrode layer 101a and second sub-electrode layer 101b); a first conductive structure 103b located on the first conductive plug; several second conductive plugs (not shown in the figure) passing through the first electrode layer 101 (first sub-electrode layer 101a and second sub-electrode layer 101b), the second conductive plug passes through the second electrode layer opening 103a in several layers of second electrode layers 103; a second conductive structure 104 located on the second conductive plug; a first pin 105 located on the first conductive structure 103b; and a second pin 106 located on the second conductive structure 104.

[0032] The inventors discovered that the shape of the first electrode layer opening 102 projected onto the substrate is a square, and the shape of the second electrode layer opening 103a projected onto the substrate is also a square. Since a large part of the capacitor is occupied by the electrode layer opening, a reduction in the effective area of ​​the electrode layer will lead to a decrease in capacitance, thereby affecting the electrical performance of the semiconductor structure ultimately formed.

[0033] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein several overlapping first electrode layers on a substrate respectively have several first electrode layer openings, the projection patterns of the first electrode layer openings in different first electrode layers overlap, and each first electrode layer opening has a plurality of first compensation parts, and the side walls of the first compensation parts protrude toward the central axis of the first electrode layer opening, thereby increasing the remaining area of ​​the first electrode layer, thereby increasing the effective capacitance of the semiconductor structure, thereby improving the electrical performance of the semiconductor structure finally formed.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 2 to 16 is a schematic structural diagram of each step of a method for forming a semiconductor structure in a first embodiment of the present invention; Fig.17 Schematic diagram of the structure of the second electrode layer opening in the second embodiment of the present invention.

[0036] First embodiment

[0037] First, please refer to Figure 2 and Figure 3 , providing a substrate 200.

[0038] Figure 3 for Figure 2 In the cross-sectional view of AA, Figure 2 for Figure 3 Top view of the .

[0039] In this embodiment, the substrate 200 has a first conductive layer 201 and a second conductive layer 202 .

[0040] In this embodiment, the substrate 200 further has a plurality of device structures (not shown), and the first conductive layer 201 and the second conductive layer 202 are electrically connected to the plurality of device structures respectively.

[0041] Please refer to Figure 4 , a plurality of overlapping first electrode layers 203 are formed on the substrate 200 .

[0042] Figure 4 The viewing direction and Figure 2 The viewing direction is consistent.

[0043] exist Figure 4 First, a first electrode layer 203 is formed on the substrate 200 .

[0044] In this embodiment, the method for forming the first electrode layer 203 on the substrate 200 includes: forming a first electrode material layer (not shown) on the substrate 200 ; and performing a first patterning process on the first electrode material layer to form the first electrode layer 203 .

[0045] The formation process of the first electrode material layer includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.

[0046] In this embodiment, the first electrode material layer is formed by an atomic layer deposition process.

[0047] The material of the first electrode layer 203 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride and tungsten.

[0048] In this embodiment, the material of the first electrode layer 203 is titanium nitride.

[0049] Please refer to Figure 5 , a first electrode layer opening 203 a is formed in the first electrode layer 203 .

[0050] Figure 5 The viewing direction and Figure 4 The viewing direction is the same.

[0051] In this embodiment, the first electrode layer opening 203 a forms a plurality of first compensation portions 203 b , and the sidewalls of the first compensation portions 203 b protrude toward the central axis of the first electrode layer opening 203 a .

[0052] In this embodiment, the first electrode layer opening 203a includes first edges (not marked in the figure) parallel to each other along the first direction (X) and second edges (not marked in the figure) parallel to each other along the second direction (Y), the first direction (X) and the second direction (Y) are perpendicular, the side wall of the first compensation portion 203b includes a first compensation edge (not marked in the figure) and a second compensation edge (not marked in the figure) connected to each other, the first compensation edge extends along the first direction (X) and the other end is connected to the second edge, the second compensation edge extends along the second direction (Y) and the other end is connected to the first edge, the side wall of the first compensation portion 203b protrudes toward the central axis of the first electrode layer opening 203a, and multiple first compensation portions 203b are symmetrically distributed along the center of the first electrode layer opening 203a.

[0053] In this embodiment, the length of the first side length W1 is the same as the length of the second side length W1, the length of the first compensation side w2 is the same as the length of the second compensation side w2, and the ratio of the length of the first compensation side w2 to the length of the first side W1 is in the range of 0.05:1 to 0.25:1.

[0054] In this embodiment, the side wall of the first compensation portion 203b protrudes toward the central axis of the first electrode layer opening 203a, that is, the first compensation side is recessed toward the center of the first electrode layer opening 203a relative to the first side, and the second compensation side is recessed toward the center of the first electrode layer opening 203a relative to the second side.

[0055] In this embodiment, the first compensation portion 203 b is used to increase the remaining area of ​​the first electrode layer, so that the effective capacitance of the semiconductor structure is increased, thereby improving the electrical performance of the finally formed semiconductor structure.

[0056] In this embodiment, the number of the first compensation portions 203 b is four, which are respectively distributed at the four corners of the first electrode layer opening 203 a.

[0057] Please refer to Figure 6 , a first insulating layer 204 is formed on the substrate 200 , and the first insulating layer 204 covers the surface of the first electrode layer 203 and fills the first electrode layer opening 203 a .

[0058] The material of the first insulating layer 204 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide or aluminum oxide.

[0059] In this embodiment, the material of the first insulating layer 204 is hafnium oxide.

[0060] Please refer to Figure 7 , a second electrode layer 205 is formed on the first insulating layer 204 .

[0061] In this embodiment, the method for forming the second electrode layer 205 on the first insulating layer 204 includes: forming a second electrode material layer (not shown) on the first insulating layer 204 ; and performing a second patterning process on the second electrode material layer to form the second electrode layer 205 .

[0062] The formation process of the second electrode material layer includes: atomic layer deposition process, plasma chemical vapor deposition process, low pressure chemical vapor deposition process, sputtering deposition process, ion beam deposition process or ion beam assisted deposition process.

[0063] In this embodiment, the second electrode material layer is formed by an atomic layer deposition process.

[0064] The material of the second electrode layer 205 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride and tungsten.

[0065] In this embodiment, the material of the second electrode layer 205 is titanium nitride.

[0066] Please refer to Figure 8, a second electrode layer opening 205 a is formed in the second electrode layer 205 .

[0067] In this embodiment, the shape of the second electrode layer opening 205 a projected onto the substrate is a square.

[0068] In this embodiment, the second electrode layer opening 205 a exposes the surface of the first insulating layer 204 .

[0069] In this embodiment, the projection of the second electrode layer opening 205 a toward the substrate does not overlap with the projection of the first electrode layer opening 203 a toward the substrate.

[0070] Please refer to Fig. 9 , a second insulating layer 206 is formed on the first insulating layer 204 , and the second insulating layer 206 covers the surface of the second electrode layer 205 .

[0071] The material of the second insulating layer 206 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide or aluminum oxide.

[0072] In this embodiment, the material of the second insulating layer 206 is hafnium oxide.

[0073] Please refer to Fig.10 , a first electrode layer 203 is further formed on the second insulating layer 206 .

[0074] In this embodiment, the semiconductor structure only shows two stacked first electrode layers 203 , and a second electrode layer 205 is formed between the two first electrode layers 203 .

[0075] In other embodiments, the second electrode layer 205 may be further formed on the first electrode layer 203, and the first electrode layer 203 may be further stacked on the second electrode layer 205. This process may be repeated to form multiple stacked first electrode layers, and a second electrode layer may be formed between adjacent first electrode layers.

[0076] Please refer to Fig.11 , a plurality of first electrode layer openings 203 a are formed in the first electrode layer 203 .

[0077] In this embodiment, the projection pattern of the first electrode layer opening 203 a in the first electrode layer overlaps with the projection pattern of the first electrode layer opening 203 a in the first electrode layer located at the bottom of the second electrode layer 205 .

[0078] In this embodiment, the first compensation portion 203 b is used to increase the remaining area of ​​the first electrode layer 203 , so that the effective capacitance of the semiconductor structure is increased, thereby improving the electrical performance of the finally formed semiconductor structure.

[0079] Please refer to Fig.12 , a dielectric layer 207 is formed on the substrate 200 , and the dielectric layer 207 covers the first electrode layer 203 .

[0080] In this embodiment, the material of the dielectric layer 207 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0081] In this embodiment, the dielectric layer 207 covers the first electrode layer 203 on the second insulating layer 206 .

[0082] In this embodiment, after forming the dielectric layer 207, the process further includes: forming a first through hole and a second through hole in the dielectric layer 207. For details on the formation process of the first through hole and the second through hole, please refer to Figures 9 to 11 .

[0083] The process of forming the first conductive plug and the second conductive plug in the dielectric layer 207 is shown in FIG. Figures 13 to 15 .

[0084] Please refer to Figure 13 to Figure 14 , a first through hole 208 and a second through hole 209 are respectively formed in the dielectric layer 207 .

[0085] Fig.13 for Fig.14 A top view of Fig.14 for Fig.13 Cross-sectional view at AA.

[0086] In this embodiment, the first through hole 208 passes through the first electrode layer opening 203a in the first electrode layer 203, penetrates the second insulating layer 206, the second electrode layer 205, and the first insulating layer 204, and then extends into the substrate 200 to expose a portion of the top surface of the first conductive layer 201.

[0087] In this embodiment, the second through hole 209 passes through the second electrode layer opening 205a in the second electrode layer 205, penetrates the first electrode layer 203, the second insulating layer 206, the first electrode layer 203, the first insulating layer 204, and then extends into the substrate 200 to expose a portion of the top surface of the second conductive layer 202.

[0088] Please refer to Fig.15 , a first conductive plug 210 is formed in the first through hole 208 ; and a second conductive plug 211 is formed in the second through hole 209 .

[0089] Fig.15 The viewing direction and Fig.14 The viewing direction is the same.

[0090] In this embodiment, the distance between the first electrode layer opening 203 a and the sidewall of the first conductive plug 210 is greater than 0, and the sidewall of the first conductive plug 210 is in contact with the second electrode layer 205 .

[0091] In this embodiment, the distance between the second electrode layer opening 205 a and the sidewall of the second conductive plug 211 is greater than 0, and the sidewall of the second conductive plug 211 is in contact with the first electrode layer 203 .

[0092] In this embodiment, the first conductive plug 210 is electrically connected to the first conductive layer 201 ; and the second conductive plug 211 is electrically connected to the second conductive layer 202 .

[0093] In this embodiment, the method for forming the first conductive plug 210 and the second conductive plug 211 includes: forming a conductive plug material layer (not shown) in the first through hole 208, in the second through hole 209 and on the dielectric layer 207; and planarizing the conductive plug material layer until the top surface of the dielectric layer 207 is exposed, thereby forming the first conductive plug 210 and the second conductive plug 211.

[0094] In this embodiment, before forming the first conductive plug 210, the process further includes: forming a first auxiliary layer (not shown) on the bottom surface and sidewall of the first through hole 208; and the first conductive plug 210 is located on the first auxiliary layer (not shown).

[0095] In this embodiment, before forming the second conductive plug 211, it also includes: forming a second auxiliary layer (not shown in the figure) on the bottom surface and sidewall of the second through hole 209; and the second conductive plug 211 is located on the second auxiliary layer (not shown in the figure).

[0096] The material of the first conductive plug 210 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum; the material of the second conductive plug 211 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten or platinum.

[0097] It should be noted that, in the present embodiment, when the metal material selected for the first conductive plug 210 and the second conductive plug 211 has strong metal activity, such as metal copper, the first auxiliary layer and the second auxiliary layer are barrier layers, and their function is to prevent the metal diffusion of the first conductive plug 210 and the second conductive plug 211, thereby causing metal contamination; when the metal material selected for the first conductive plug 210 and the second conductive plug 211 has poor adhesion, such as metal tungsten, the first auxiliary layer and the second auxiliary layer are adhesion layers, and their function is to increase the adhesion between the first conductive plug 210 and the second conductive plug 211 and the dielectric layer.

[0098] Please refer to Fig.16, a first conductive structure 212 is formed on the first conductive plug 210 , and a second conductive structure 213 is formed on the second conductive plug 211 .

[0099] Fig.16 The viewing direction and Fig.13 The viewing direction is consistent.

[0100] Please continue to refer to Fig.16 , a first pin 214 is formed on the first conductive structure 212 , and a second pin 215 is formed on the second conductive structure 213 .

[0101] Correspondingly, the present invention also provides a semiconductor structure, including a substrate 200; a plurality of overlapping first electrode layers 203 located on the substrate 200, each of the first electrode layers 203 having a plurality of first electrode layer openings 203a, the projection patterns of the first electrode layer openings 203a in different first electrode layers 203 overlapping, each of the first electrode layer openings 203a having a plurality of first compensation portions 203b, the side walls of the first compensation portions 203b protruding toward the central axis of the first electrode layer opening 203a; at least one second electrode layer 205, each of the second electrode layers 205 being located between two adjacent first electrode layers 203, and the second electrode layer 205 being insulated from the first electrode layer 203, and each of the second electrode layers 205 having a plurality of first compensation portions 203b a plurality of first conductive plugs 210 penetrating the second electrode layer 205, each of the first conductive plugs 210 passing through the first electrode layer opening 203a in the plurality of first electrode layers 203, the side wall distance from the first electrode layer opening 203a to the first conductive plug 210 being greater than 0, and the side wall of the first conductive plug 210 being in contact with the second electrode layer 205; a plurality of second conductive plugs 211 penetrating the first electrode layer 203, each of the second conductive plugs 211 passing through the second electrode layer opening 205a in the plurality of second electrode layers 205, the side wall distance from the second electrode layer opening 205a to the second conductive plug 211 being greater than 0, and the side wall of the second conductive plug 211 being in contact with the first electrode layer 203.

[0102] In this embodiment, the first electrode layer opening 203a includes first edges parallel to each other along a first direction and second edges parallel to each other along a second direction, the first direction is perpendicular to the second direction, the side wall of the first compensation portion 203b includes a first compensation edge and a second compensation edge connected to each other, the first compensation edge extends along the first direction and the other end is connected to the second edge, the second compensation edge extends along the second direction and the other end is connected to the first edge, the side wall of the first compensation portion 203b protrudes toward the central axis of the first electrode layer opening 203a, and multiple first compensation portions 203b are symmetrically distributed along the center of the first electrode layer opening 203a.

[0103] In this embodiment, the length of the first side (W1) is the same as the length of the second side (W1), the length of the first compensation side (w2) is the same as the length of the second compensation side (w2), and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:1.

[0104] In this embodiment, the projection shape of the second electrode layer opening 205 a toward the substrate 200 is a square.

[0105] In this embodiment, the projection patterns of the first electrode layer openings 203a in different layers of the first electrode layers 203 overlap, and each first electrode layer opening 203a has a plurality of first compensation portions 203b. The side walls of the first compensation portions 203b protrude toward the central axis of the first electrode layer opening 203a. This increases the remaining area of ​​the first electrode layer 203, thereby increasing the effective capacitance of the semiconductor structure, thereby improving the electrical performance of the semiconductor structure finally formed.

[0106] In this embodiment, a first conductive structure 212 located on the first conductive plug 210 and a second conductive structure 213 located on the second conductive plug 211 are also included.

[0107] In this embodiment, a first pin 214 located on the first conductive structure 212 and a second pin 215 located on the second conductive structure 213 are also included.

[0108] Second embodiment

[0109] The difference between the second embodiment and the first embodiment is that in the second embodiment, the second electrode layer opening 205 a also has a second compensation portion 205 b .

[0110] Please refer to the process structure diagram from providing the substrate 200 to forming the second electrode layer opening 205a. Figures 2 to 7 .

[0111] Please refer to Fig.17 A second electrode layer opening 205 a is formed in the second electrode layer 205 , and the second electrode layer opening 205 a has a second compensation portion 205 b .

[0112] Fig.17 The viewing direction and Figure 8 The viewing direction is the same.

[0113] In this embodiment, the second electrode layer opening 205a includes a third side parallel to each other along the first direction (X) and a fourth side parallel to each other along the second direction (Y), the side wall of the second compensation portion 205b includes a third compensation side and a fourth compensation side connected to each other, the third compensation side extends along the first direction (X) and the other end is connected to the fourth side, the fourth compensation side extends along the second direction (Y) and the other end is connected to the third side, the side wall of the second compensation portion 205b protrudes toward the central axis of the second electrode layer opening 205a, and multiple second compensation portions are symmetrically distributed along the center of the second electrode layer opening 205a.

[0114] In this embodiment, the length of the third side (W1) is the same as the length of the fourth side (W1), the length of the third compensation side (w2) is the same as the length of the fourth compensation side (w2), and the ratio of the length of the third compensation side (w2) to the length of the third side (W1) is in the range of 0.05:1 to 0.25:1.

[0115] In this embodiment, the side wall of the second compensation portion 205b protrudes toward the central axis of the second electrode layer opening 205a, that is, the third compensation side is recessed toward the center of the second electrode layer opening 205a relative to the third side, and the fourth compensation side is recessed toward the center of the second electrode layer opening 205a relative to the fourth side.

[0116] In this embodiment, the second compensation portion 205 b is used to increase the remaining area of ​​the second electrode layer 205 , so that the effective capacitance of the semiconductor structure is increased, thereby improving the electrical performance of the finally formed semiconductor structure.

[0117] After forming the second electrode layer opening 205a, the process structure diagram from forming the second insulating layer 206 to forming the first lead 214 and the second lead 215 is shown in FIG. Figures 9 to 16 .

[0118] Correspondingly, the present invention also provides a semiconductor structure, comprising a substrate 200; a plurality of overlapping first electrode layers 203 located on the substrate 200, each of the first electrode layers 203 having a plurality of first electrode layer openings 203a, the projection patterns of the first electrode layer openings 203a in different first electrode layers 203 overlapping, each of the first electrode layer openings 203a having a plurality of first compensation portions 203b, the sidewalls of the first compensation portions 203b protruding toward the central axis of the first electrode layer opening 203a; at least one second electrode layer 205, each of the second electrode layers 205 being located between two adjacent first electrode layers 203, and the second electrode layer 205 being insulated from the first electrode layer 203, and each of the second electrode layers 205 having a plurality of first compensation portions 203b a second electrode layer opening 205a; a plurality of first conductive plugs 210 penetrating the second electrode layer 205, each of the first conductive plugs 210 passing through the first electrode layer opening 203a in the plurality of first electrode layers 203, a distance from the first electrode layer opening 203a to the side wall of the first conductive plug 210 being greater than 0, and a side wall of the first conductive plug 210 being in contact with the second electrode layer 205; a plurality of second conductive plugs 211 penetrating the first electrode layer 203, each of the second conductive plugs 211 passing through the second electrode layer opening 205a in the plurality of second electrode layers 205, a distance from the second electrode layer opening 205a to the side wall of the second conductive plug 211 being greater than 0, and a side wall of the second conductive plug 211 being in contact with the first electrode layer 203.

[0119] In this embodiment, the first electrode layer opening 203a includes first edges parallel to each other along a first direction and second edges parallel to each other along a second direction, the first direction is perpendicular to the second direction, the side wall of the first compensation portion 203b includes a first compensation edge and a second compensation edge connected to each other, the first compensation edge extends along the first direction and the other end is connected to the second edge, the second compensation edge extends along the second direction and the other end is connected to the first edge, the side wall of the first compensation portion 203b protrudes toward the central axis of the first electrode layer opening 203a, and multiple first compensation portions 203b are symmetrically distributed along the center of the first electrode layer opening 203a.

[0120] In this embodiment, the length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:1.

[0121] In this embodiment, the second electrode layer opening 205a includes a third side parallel to each other along the first direction and a fourth side parallel to each other along the second direction, the side wall of the second compensation portion includes a third compensation side and a fourth compensation side connected to each other, the third compensation side extends along the first direction and the other end is connected to the fourth side, the fourth compensation side extends along the second direction and the other end is connected to the third side, the side wall of the second compensation portion 205b protrudes toward the central axis of the second electrode layer opening 205a, and multiple second compensation portions 205b are symmetrically distributed along the center of the second electrode layer opening 205a.

[0122] In this embodiment, the length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in the range of 0.05:1 to 0.25:1.

[0123] In this embodiment, a first conductive structure 212 located on the first conductive plug 210 and a second conductive structure 213 located on the second conductive plug 211 are also included.

[0124] In this embodiment, a first pin 214 located on the first conductive structure 212 and a second pin 215 located on the second conductive structure 213 are also included.

[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of overlapping first electrode layers located on the substrate, each of the first electrode layers having a plurality of first electrode layer openings, the projection patterns of the first electrode layer openings in different first electrode layers overlapping, each of the first electrode layer openings having a plurality of first compensation portions, and the sidewalls of the first compensation portions protruding toward the central axis of the first electrode layer opening; at least one second electrode layer, each of the second electrode layers is located between two adjacent first electrode layers, the second electrode layer is insulated from the first electrode layer, and each of the second electrode layers has a plurality of second electrode layer openings; a plurality of first conductive plugs penetrating the second electrode layer, each of the first conductive plugs passing through a first electrode layer opening in a plurality of first electrode layers, and a side wall of the first conductive plug in contact with the second electrode layer; A plurality of second conductive plugs pass through the first electrode layer, each of the second conductive plugs passes through a second electrode layer opening in the plurality of second electrode layers, and a side wall of the second conductive plug contacts the first electrode layer.

2. The semiconductor structure according to claim 1, wherein: There is a first distance between the first electrode layer opening and the sidewall of the first conductive plug, and the first distance is greater than 0.

3. The semiconductor structure according to claim 1, wherein: There is a second distance between the second electrode layer opening and the side wall of the second conductive plug, and the second distance is greater than 0.

4. The semiconductor structure according to claim 1, wherein: The first electrode layer opening includes first edges parallel to each other along a first direction and second edges parallel to each other along a second direction, the first direction and the second direction are perpendicular, the side walls of the first compensation portion include first compensation edges and second compensation edges connected to each other, the first compensation edge extends along the first direction and the other end is connected to the second edge, the second compensation edge extends along the second direction and the other end is connected to the first edge, the side walls of the first compensation portion protrude toward the central axis of the first electrode layer opening, and a plurality of first compensation portions are symmetrically distributed along the center of the first electrode layer opening.

5. The semiconductor structure according to claim 4, characterized in that The length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in a range of 0.05:1 to 0.25:

1.

6. The semiconductor structure according to claim 1, wherein: A plurality of second compensation parts are provided in the second electrode layer opening, and side walls of the second compensation parts protrude toward the central axis of the second electrode layer opening.

7. The semiconductor structure according to claim 6, wherein: The second electrode layer opening includes third sides parallel to each other along the first direction and fourth sides parallel to each other along the second direction, the side walls of the second compensation portion include third compensation sides and fourth compensation sides connected to each other, the third compensation side extends along the first direction and the other end is connected to the fourth side, the fourth compensation side extends along the second direction and the other end is connected to the third side, the side walls of the second compensation portion protrude toward the central axis of the second electrode layer opening, and a plurality of second compensation portions are symmetrically distributed along the center of the second electrode layer opening.

8. The semiconductor structure according to claim 7, wherein: The length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in a range of 0.05:1 to 0.25:

1.

9. The semiconductor structure according to claim 1, wherein: The system also includes a first conductive structure located on the first conductive plug and a second conductive structure located on the second conductive plug.

10. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of overlapping first electrode layers on the substrate; A plurality of first electrode layer openings are formed in each of the first electrode layers, and projection patterns of the first electrode layer openings in different first electrode layers overlap; A plurality of first compensation parts are formed in each of the first electrode layer openings, and the side walls of the first compensation parts protrude toward the central axis of the first electrode layer opening; forming at least one second electrode layer, each of the second electrode layers being located between two adjacent first electrode layers, the second electrode layer being insulated from the first electrode layer, and each of the second electrode layers having a plurality of second electrode layer openings; forming a plurality of first conductive plugs penetrating the second electrode layer, each of the first conductive plugs passing through the first electrode layer openings in the plurality of first electrode layers, and a side wall of the first conductive plug in contact with the second electrode layer; A plurality of second conductive plugs pass through the first electrode layer, each of the second conductive plugs passes through a second electrode layer opening in the plurality of second electrode layers, and a side wall of the second conductive plug contacts the first electrode layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: There is a first distance between the first electrode layer opening and the sidewall of the first conductive plug, and the first distance is greater than 0.

12. The method for forming a semiconductor structure according to claim 10, wherein: There is a second distance between the second electrode layer opening and the side wall of the second conductive plug, and the second distance is greater than 0.

13. The method for forming a semiconductor structure according to claim 10, wherein: The first electrode layer opening includes first edges parallel to each other along a first direction and second edges parallel to each other along a second direction, the first direction and the second direction are perpendicular, the side walls of the first compensation portion include first compensation edges and second compensation edges connected to each other, the first compensation edge extends along the first direction and the other end is connected to the second edge, the second compensation edge extends along the second direction and the other end is connected to the first edge, the side walls of the first compensation portion protrude toward the central axis of the first electrode layer opening, and a plurality of first compensation portions are symmetrically distributed along the center of the first electrode layer opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in a range of 0.05:1 to 0.25:

1.

15. The method for forming a semiconductor structure according to claim 10, wherein: A plurality of second compensation parts are formed in the second electrode layer opening, and side walls of the second compensation parts protrude toward a central axis of the second electrode layer opening.

16. The method for forming a semiconductor structure according to claim 15, wherein: The second electrode layer opening includes third sides parallel to each other along the first direction and fourth sides parallel to each other along the second direction, the side walls of the second compensation portion include third compensation sides and fourth compensation sides connected to each other, the third compensation side extends along the first direction and the other end is connected to the fourth side, the fourth compensation side extends along the second direction and the other end is connected to the third side, the side walls of the second compensation portion protrude toward the central axis of the second electrode layer opening, and a plurality of second compensation portions are symmetrically distributed along the center of the second electrode layer opening.

17. The method for forming a semiconductor structure according to claim 16, wherein: The length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in a range of 0.05:1 to 0.25:

1.

18. The method for forming a semiconductor structure according to claim 10, wherein: The method further includes forming a first conductive structure on the first conductive plug and forming a second conductive structure on the second conductive plug.

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