Circuit and cascode amplifier with improved high frequency linearity and method of application thereof

Abstract

The invention relates to a circuit and a cascode amplifier with improved high-frequency linearity and a method for applying the same. A cascode amplifier includes an amplifier transistor (202), a cascode transistor (204), and a current injection circuit (220). The amplifier transistor has: a first current terminal that receives a first power supply voltage; a second current terminal; and a control terminal that receives an input signal. The cascode transistor has: a first current terminal coupled to the second current terminal of the amplifier transistor; a second current terminal coupled to the output terminal; and a control terminal that receives the bias voltage. The current injection circuit has: an input that receives the input signal; and a first output and a second output coupled to the first current terminal and the second current terminal of the cascode transistor, respectively. The current injection circuit is configured to present an out-of-phase current to the cascode transistor in response to the input signal.

Description

Technical Field

[0001] The present description relates to amplifier circuits, and more particularly, to cascode amplifier circuits. Background Art

[0002] Cascode amplifiers are a common type of electronic amplifier due to their favorable gain and impedance characteristics. Generally speaking, a cascode amplifier comprises an amplifier stage that receives an input signal, and a cascode stage that produces an output signal.

[0003] Figure 1A A prior art cascode amplifier 100 is shown, which is implemented in this example using metal oxide semiconductor (MOS) transistors, specifically n-channel MOS (NMOS) transistors 102, 104. NMOS transistor 102 provides an amplifier stage in cascode amplifier 100, and NMOS transistor 104 provides a cascode stage. NMOS transistor 102 is common-source connected, with its source terminal coupled to circuit ground and its gate terminal coupled to input terminal VIN. NMOS transistor 104 is common-gate connected, with its source terminal coupled to the drain terminal of NMOS transistor 102 and its gate terminal coupled to bias voltage terminal VBIAS. Load device 105 has one terminal coupled to power supply terminal VDD and another terminal coupled to the drain terminal of NMOS transistor 104. Output terminal VOUT from cascode amplifier 100 is located at the drain terminal of NMOS transistor 104.

[0004] Cascode amplifiers can similarly be constructed using p-channel MOS (PMOS) transistors arranged as a common-source amplifier stage and a common-gate cascode stage. Bipolar junction transistors (BJTs) can also implement cascode amplifiers using a common-emitter amplifier stage and a common-base cascode stage.

[0005] In both MOS and BJT implementations, the cascode amplifier eliminates direct coupling between the output and the input, thereby improving input-output isolation over a single transistor amplifier stage. In addition, the cascode arrangement provides high voltage gain and improved bandwidth and linearity compared to simpler amplifier stage designs such as common source amplifiers and common emitter amplifiers. Cascode amplifiers are often used in high frequency applications such as communications receivers, high frequency test and measurement equipment such as spectrum analyzers, and the like. Summary of the invention

[0006] According to one example, a circuit includes: a first transistor having a first current terminal coupled to a first power supply terminal, a second current terminal, and a control terminal coupled to an input terminal; a second transistor having a first current terminal coupled to a second current terminal of the first transistor, a second current terminal coupled to an output terminal, and a bias terminal coupled to a gate terminal; and a current injection circuit having an input coupled to the input terminal, a first output coupled to the second current terminal of the second transistor, and a second output coupled to the first current terminal of the second transistor.

[0007] According to another example, a cascode amplifier includes: an amplifier transistor having a first current terminal receiving a first power supply voltage, a second current terminal, and a control terminal receiving an input signal; a cascode transistor having a first current terminal coupled to the second current terminal of the amplifier transistor, a second current terminal coupled to an output terminal, and a control terminal receiving a bias voltage; and a current injection circuit having an input receiving the input signal, and first and second outputs coupled to the first and second current terminals of the cascode transistor, respectively, the current injection circuit being configured to present out-of-phase currents to its first and second outputs in response to the input signal.

[0008] According to another example, a method includes applying an input signal to an amplifier transistor of a cascode amplifier, the cascode amplifier further including a cascode transistor coupled to the input transistor; generating out-of-phase injection currents from first and second outputs of a current injection circuit in response to the input signal; applying the out-of-phase injection currents to first and second current terminals of the cascode transistor; and generating an output signal from an output of the cascode amplifier in response to the input signal.

[0009] Exemplary technical advantages achieved by one or more of these examples include reducing distortion of the output signal of the cascode amplifier due to the effects of nonlinear current conducted by the cascode transistors. Improved intermodulation distortion performance, especially at high frequencies, can be obtained with minimal increase in power consumption.

[0010] Other exemplary technical advantages achieved by the present disclosure will be apparent to those of ordinary skill in the art referring to the following description in conjunction with its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A is an electrical diagram in schematic form of a prior art cascode amplifier.

[0012] Figure 1B is an electrical diagram in schematic form of another prior art cascode amplifier.

[0013] Figure 2 is an electrical diagram in block and schematic form of an exemplary cascode amplifier.

[0014] Figure 3 is coupled to Figure 2 An electrical diagram in schematic form of an exemplary current injection circuit in an exemplary cascode amplifier.

[0015] Figure 4A It shows Figure 2 A flow chart of an exemplary operation of a cascode amplifier.

[0016] Figure 4B It shows Figure 3 Flowchart of exemplary operation of a current injection circuit in a cascode amplifier.

[0017] Figure 5A and Figure 5B It shows Figure 3 A plot of the third-order intermodulation distortion performance of an exemplary cascode amplifier.

[0018] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0019] As described above, due to the high voltage gain of the cascode amplifier, the decoupling of its output from its input, and its generally linear operation, the cascode amplifier is an attractive amplifier configuration for a wide range of electronic circuits and systems. However, there are some non-idealities in the cascode amplifier. For example, nonlinearity exists in the transistor drain-source or collector-emitter currents and may reduce the linearity of the amplifier transfer function, especially at higher frequencies. In many cases, especially in the MOS context, the overall linearity of the cascode amplifier has previously been considered to be primarily determined by the linearity of the common-source stage. Prior art methods have addressed the linearity of the common-source stage of the MOS cascode amplifier, treating the common-gate stage as an ideal current source.

[0020] However, it has been observed that the nonlinear conduction of the common-gate stage or cascode stage of a cascode amplifier limits the overall linearity of the amplifier, especially at higher frequencies now commonly encountered in applications such as communication receivers. The nonlinearity of the source-drain current conducted by the common-gate NMOS transistor 104 of the prior art MOS cascode amplifier 100 is Figure 1A In the schematic diagram, the nonlinear current I NL The current source 107 is modeled. This nonlinear current I NLThe output signal at the terminal VOUT may be affected by “leakage” via the parasitic capacitance of the transistors 102, 104, which may be, in particular, Figure 1A The parasitic gate-to-source capacitance 109 between the gate and source of the transistor 104 and the parasitic capacitance 111 between the drain and source of the transistor 102 are shown in FIG. As the frequency of the input signal at the terminal VIN increases, the nonlinear current I through the parasitic capacitances 109 and 111 increases. NL The leakage of VOUT increases, which in turn increases the injection of non-linear current through the load 105 and causes distortion of the output signal at the terminal VOUT.

[0021] Figure 1B Another exemplary prior art cascode amplifier 105 is shown. The prior art cascode amplifier 150 includes a common-source NMOS transistor 152, a common-gate NMOS transistor 154, a load 155, an NMOS transistor 156, and a current source 158. The NMOS transistor 152 has a source terminal at circuit ground, a gate terminal receiving an input signal VIN, and a drain terminal coupled to the source terminal of the NMOS transistor 154. The drain terminal of the NMOS transistor 154 is coupled to one terminal of a load device 155, the other terminal of which is coupled to a VDD power supply terminal. The output signal from the cascode amplifier 150 is presented from the drain terminal of the NMOS transistor 154 at the output terminal VOUT.

[0022] exist Figure 1B In the arrangement of , NMOS transistor 156 and current source 158 form a current buffer 160 at the gate terminal of common-gate transistor 154. The drain terminal of NMOS transistor 156 is coupled to the drain terminal of common-gate transistor 154 and to load device 155, and the source terminal of NMOS transistor 156 is coupled to the gate terminal of common-gate transistor 154 and to one terminal of current source 158. Therefore, the gate terminal of common-gate NMOS transistor 154 receives its bias voltage from the source of NMOS transistor 156 rather than directly. The gate terminal of NMOS transistor 156 receives the bias voltage at bias terminal VBIAS. The second terminal of current source 158 is coupled to a common potential (e.g., circuit ground). Current source 158 can be implemented as a MOS transistor that receives a controlled or regulated gate voltage, or can be implemented in a branch of a current mirror, or can be configured in other ways to conduct a selected fixed current.

[0023] In this circuit, the current buffer 160 establishes a buffer current that is fed to or conducted from the output of the cascode amplifier 150. Therefore, the nonlinear current I that leaks through the parasitic gate-to-source capacitance 109 during operation of the cascode amplifier 150 isNL Considering the small signal operation of the cascode amplifier 150, the current buffer 160 effectively forms a nonlinear current I conducted through the parasitic gate-to-source capacitance 109. NL This reduces the nonlinear current fed to the output and distorts the output signal. However, the nonlinear current I leaked through the parasitic drain-to-source capacitance 111 of the common-source transistor 152 NL The portion of I is not isolated from the output by the current buffer 160. In addition, given the relatively large capacitance of the gate-to-source capacitor 109, the current buffer 160 must conduct a significant bias current to effectively buffer the nonlinear current I from the amplifier output. NL .

[0024] This is within the context of the embodiments described herein.

[0025] Figure 2 An exemplary cascode amplifier 200 is shown. Cascode amplifier 200 includes transistors 202 and 204, a load device 205, and a current injection circuit 220. Figure 2 The current source 207 in FIG. 2 is not an actual current source or device, but rather a current source that is used to control the nonlinear current I conducted by the transistor 204 during the operation of the cascode amplifier 200. NL Modeling.

[0026] Figure 2 Transistors 202 and 204 are shown as general three-terminal devices. Transistor 202 has a first current terminal coupled to power supply terminal PS2, and a control terminal coupled to input terminal IN. Transistor 204 has a first current terminal coupled to a second current terminal of transistor 202, and a control terminal receiving bias voltage VBIAS. Load device 205 has a first terminal coupled to power supply terminal PS1, and a second terminal coupled to the second current terminal of transistor 204.

[0027] Transistors 202 and 204 may be implemented as metal oxide semiconductor (MOS) transistors of either p-channel (PMOS) or n-channel (NMOS) conductivity type, or may be implemented as npn or pnp type bipolar junction transistors (BJTs). In this description for the case where transistors 202 and 204 are implemented as MOS transistors, the first current terminal corresponds to the source terminal, the second current terminal corresponds to the drain terminal, and the control terminal corresponds to the gate terminal. For transistors 202 and 204 implemented as bipolar transistors, the first current terminal corresponds to the emitter terminal, the second current terminal corresponds to the collector terminal, and the control terminal corresponds to the base terminal.

[0028] Load device 205 may be a resistive load, a reactive load (eg, a resistor-capacitor network), an active load (eg, a PMOS or NMOS current source, a simple or cascode, etc.), or such other load device as is suitable for the particular application of cascode amplifier 200 .

[0029] Figure 2 The transistor 202 in the example of is connected in a common source (MOS) or common emitter (BJT) manner, in that its first current terminal receives a supply voltage or circuit ground, and its control terminal receives an input signal. The transistor 204 is connected in a common gate (MOS) or common base (BJT) manner, in that its control terminal receives a bias voltage, its first current terminal receives a signal from the second current terminal of the transistor 202, and its second current terminal is coupled to the load device 105 and presents an output signal at the output terminal VOUT. The transistor 202 in the cascode amplifier 200 can be referred to as an amplifier transistor or an amplifier stage, and the transistor 204 can be referred to as a cascode transistor or a cascode stage.

[0030] As described above Figure 1A and 1B In the example of , the current conducted by cascode transistor 204 in response to the input signal at input terminal VIN includes both a linear component and a nonlinear component. The nonlinear current conducted by cascode transistor 204 is Figure 2 2 is modeled by a current source 207 coupled between the first and second current terminals of transistor 204. As described above, "leakage" of this nonlinear current through the parasitic capacitances of transistors 202 and 204 may cause distortion of the signal at the output terminal VOUT.

[0031] In order to reduce the nonlinear cascode current I NL To prevent this distortion caused by this leakage of the common-source common-gate amplifier 200, in this example, includes a current injection circuit 220. The current injection circuit 220 has an input coupled to the input terminal VIN and is biased from the power supply terminals PS1 and PS2. The current injection circuit 220 has an output coupled to a first current terminal and a second current terminal of the common-source common-gate transistor 204. As described in further detail below, the current injection circuit 220 injects the out-of-phase current I NL_INJ is injected into the first current terminal and the second current terminal of the cascode transistor 204. The injected current I NL_INJ The magnitude and polarity of corresponds to the nonlinear current I conducted by cascode transistor 204. NL amplitude and polarity.

[0032] Based on the phase of the input signal at the input terminal VIN, the injection current I from the two outputs of the current injection circuit 220 is NL_INJ are “out of phase” with respect to each other. For example, if the nonlinear current I conducted by cascode transistor 204 NL During the positive half cycle of the input signal at the terminal VIN, the current injection circuit 220 injects the positive polarity current I NL_INJ is conducted to its output coupled to the first current terminal of the cascode transistor 204. In contrast, if the nonlinear current I conducted by the cascode transistor 204 NL During the negative half cycle of the input signal at the terminal VIN, the current injection circuit 220 injects the negative polarity current I NL_INJ is conducted into its output which is coupled to a second current terminal of cascode transistor 204 .

[0033] Therefore, the injected out-of-phase current applied to cascode transistor 204 from current injection circuit 220 is the nonlinear current component I conducted by cascode transistor 204. NL Provides a "local" current loop. This local loop provides a guide for the nonlinear current I NL The conduction path is free from parasitic capacitance leakage through both cascode transistor 204 and amplifier transistor 202, thereby limiting the impact on the output signal caused by nonlinear conduction at the cascode stage. Therefore, the distortion of the output signal under high frequency operation can be reduced.

[0034] Figure 3 It shows that according to the above Figure 2 The exemplary cascode amplifier 300 of the described architecture and implemented using n-channel MOS (NMOS) transistors, includes its current injection circuit 320. As mentioned above, the cascode amplifier 300 may alternatively be implemented using PMOS transistors or BJT transistors, with the supply voltage and bias voltage arranged accordingly.

[0035] Figure 3 The cascode amplifier 300 includes NMOS transistors 302 and 304, a load device 305, and a current injection circuit 320. The current injection circuit 320 includes a common source amplifier 330 and a differential amplifier 340. The common source amplifier 330 includes an NMOS transistor 332 and a resistor 334. The differential amplifier 340 includes NMOS transistors 342 and 344, a current source 346, a resistor 348, and a capacitor 349.

[0036] In which the cascode amplifier 300 is implemented with NMOS transistors Figure 3 In the example, the VDD power supply terminal corresponds to Figure 2The circuit ground terminal corresponds to the power supply terminal PS2. Figure 3 In the PMOS implementation of the cascode amplifier 300, the ground power supply terminal and the VDD power supply terminal will correspond to Figure 2 Power supply terminals PS1 and PS2.

[0037] The NMOS transistor 302 in the cascode amplifier 300 is connected in a common source manner, wherein its source terminal is coupled to the ground terminal and its gate terminal is coupled to the input terminal VIN. The NMOS transistor 304 is connected in a common gate manner, wherein its gate terminal is coupled to the bias terminal VBIAS, its source terminal is coupled to the drain terminal of the transistor 302, and its drain terminal is coupled to the output terminal VOUT and the terminal of the load device 305. In this example, the NMOS common source transistor 302 can be referred to as an amplifier transistor or an amplifier stage, and the NMOS common gate transistor 304 can be referred to as a cascode transistor or a cascode stage. The load device 205 can be a passive resistive or reactive load, an active load such as a current source, or such other load devices suitable for a particular application.

[0038] As in Figure 1A , 1B In the example of FIG. 2, the nonlinear current conducted by the NMOS cascode transistor 304 in response to the input signal at the input terminal VIN is Figure 3 304 is modeled by a current source 307 coupled across the drain and source terminals of the NMOS cascode transistor 304. The current injection circuit 320 is set at Figure 3 In the cascode amplifier 300, to offset this nonlinear current I NL distortion effect.

[0039] As mentioned above, the current injection circuit 320 includes a common source amplifier 330 and a differential amplifier 340. The common source amplifier 330 includes an NMOS transistor 332 having a source terminal coupled to a circuit ground terminal and a gate terminal coupled to an input terminal VIN. The drain terminal of the NMOS transistor 332 is coupled to one terminal of a resistor 334. The resistor 334 has a second terminal coupled to a VDD power supply terminal. The resistor 334 acts as a load in the common source amplifier 330. The voltage at the drain terminal of the NMOS transistor 332 is responsive to the input signal at the input terminal VIN, so that the common source amplifier 330 amplifies the signal at the input terminal VIN to a desired voltage swing at the drain of the NMOS transistor 332.

[0040] The source terminals of NMOS transistors 342 and 344 of differential amplifier 340 are commonly coupled to one terminal of current source 346. In this NMOS implementation, current source 346 has a second terminal coupled to a ground terminal. The gate terminal of NMOS transistor 342 is coupled to the drain terminal of NMOS transistor 332 at the output of common-source amplifier 330, and the drain terminal of NMOS transistor 342 is coupled to the drain terminal of NMOS cascode transistor 304. Resistor 348 has one terminal coupled to the gate terminal of NMOS transistor 342, and a second terminal coupled to the gate terminal of NMOS transistor 344. The drain terminal of NMOS transistor 344 is coupled to the source terminal of NMOS cascode transistor 304. Capacitor 349 has one terminal coupled to the gate terminal of NMOS transistor 344 and to resistor 348, and another terminal coupled to the ground terminal.

[0041] The differential amplifier 340 in this example is arranged in the form of an NMOS differential amplifier, wherein its differential inputs are coupled to the same input terminal, namely the output of the common source amplifier 330. Thus, Figure 3 The differential amplifier 340 can be considered a "pseudo differential amplifier". Resistor 348 establishes a differential voltage across the gate terminals of NMOS transistors 342 and 344. This differential voltage is reflected in the nonlinear current I conducted by NMOS transistors 342 and 344. NL_INJ Due to the differential voltage across their gates, NMOS transistors 342, 344 conduct currents I out of phase with respect to each other in response to the input signal at input terminal VIN. NL_INJ .

[0042] The differential amplifier 340 may be implemented in forms other than a "pseudo-differential" arrangement, such as as a differential amplifier having two inputs and two outputs, a differential amplifier having two inputs and a single output, a differential amplifier having a single input and a single output, and other forms of differential amplifiers.

[0043] In operation of current injection circuit 320, an input signal at input terminal VIN is amplified by common-source amplifier 330 to generate a differential voltage across the inputs of differential amplifier 340. In response, differential amplifier 340 generates out-of-phase injection currents I applied to the source and drain terminals of NMOS cascode transistor 304. NL_INJ The injected current I in a given phase of the input signal at terminal VIN NL_INJ The nonlinear current I conducted by the NMOS cascode transistor 304 in the same input signal phase NL The injected current I from the differential amplifier 340 is NL_INJThe magnitude of is determined by the gain of the common-source amplifier 330. Ideally, the gain of the common-source amplifier 330 is selected, for example by trimming the resistor 334, so that the injected nonlinear current I from the common-source amplifier 330 is NL_INJ The magnitude of the nonlinear current I conducted by the NMOS cascode transistor 304 is NL The amplitude matches.

[0044] For example, in small signal operation of the cascode amplifier 300, the positive half cycle of the input signal at the terminal VIN turns on both NMOS transistors 302 and 332 more strongly, thereby increasing their drain-to-source currents. The nonlinear conduction of the NMOS cascode transistor 304 increases with the higher conduction of the NMOS transistor 302 and can be modeled as a nonlinear current component I through the current source 307. NL The stronger on-state of NMOS transistor 332 pulls the gate terminal of NMOS transistor 342 toward ground. This pulls the gate terminal of NMOS transistor 344 to a higher voltage than the gate terminal of NMOS transistor 342, thereby turning on NMOS transistor 344 more strongly than NMOS transistor 342. Therefore, the positive injection current I NL_INJ (in a small signal sense) with the nonlinear current component I NL A similar magnitude to that of is conducted from the source terminal of NMOS cascode transistor 304 into the drain terminal of NMOS transistor 344 .

[0045] Conversely, the negative half-cycle of the input signal at terminal VIN tends to turn off NMOS transistors 302 and 332, thereby reducing their drain-to-source current. The nonlinear conduction of NMOS cascode transistor 304 is reduced and, in a small signal sense, can be modeled as a nonlinear current component I through current source 307. NL When NMOS transistor 332 is turned off, the gate terminal of NMOS transistor 342 is pulled toward the VDD power supply through resistor 334. Therefore, the gate terminal of NMOS transistor 342 is pulled to a higher voltage than the voltage of NMOS transistor 344, thereby turning on NMOS transistor 342 more strongly than NMOS transistor 344. Therefore, the negative injection current I NL_INJ (in a small signal sense) with the nonlinear current component I NL A similar magnitude to the magnitude of φ is conducted from the drain terminal of NMOS cascode transistor 304 into the drain terminal of NMOS transistor 342 .

[0046] Due to this operation of the current injection circuit 320, the nonlinear current I NLis directed into the differential amplifier 340 rather than leaking through the parasitic gate-to-source capacitance of the cascode transistor 304 and the parasitic drain-to-source capacitance of the amplifier transistor 302. Thus, intermodulation distortion of the cascode amplifier 300 is reduced.

[0047] Figure 4A Shows a reduction Figure 2 An exemplary method for detecting nonlinear effects of cascode transistors of a cascode amplifier 200 is provided. In process block 400, an input signal is received at a control terminal of an input transistor, such as a gate terminal or a base terminal of an amplifier transistor 202 in the cascode amplifier 200. During process block 400, appropriate supply voltages suitable for the particular type of transistors implementing the cascode amplifier 200 are applied at supply terminals PS1, PS2, and an appropriate bias voltage is applied to a bias terminal VBIAS.

[0048] In process block 402, cascode amplifier 200 generates an output signal from cascode transistor 204 in response to an input signal applied to amplifier transistor 202. Figure 2 In the example of , an output signal is generated at an output terminal VOUT, which is coupled to the second current terminal of the cascode transistor 204 and to the load device 205.

[0049] At the same time, in process block 410, the current injection circuit 220 generates an out-of-phase injection current I in response to the input signal at the input terminal VIN. NL_INJ In this example, in process block 410, an out-of-phase injection current I is generated from one of the two outputs of the current injection circuit 220 according to the input signal phase. NL_INJ , whose magnitude is similar to the nonlinear current I conducted by the cascode transistor 204 of the cascode amplifier 200 NL The amplitude corresponds to .

[0050] In process block 414, current injection circuit 220 injects out-of-phase current I according to the phase of the input signal at terminal VIN. NL_INJ is applied to one of the first current terminal and the second current terminal of the cascode transistor 204. For example, in which the nonlinear current I NL During the positive input signal phase (such as Figure 2 ), the current injection circuit 220 conducts the current I from the first current terminal of the cascode transistor 204 (at the node between the cascode transistor 204 and the amplifier transistor 202). NL_INJ In which the nonlinear current I of the cascode transistor 204 NL During the negative input signal phase (such as Figure 2), the current injection circuit 220 injects a current I at the second current terminal of the cascode transistor 204. NL_INJ (conducting negative current I from the second current terminal of cascode transistor 204 NL_INJ )(at the node between the cascode transistor 204 and the load device 205).

[0051] As in Figure 2 As will be apparent from FIG. 4 , process blocks 410 and 414 are performed simultaneously with process blocks 400 and 402 . In operation, the out-of-phase injection current I applied to cascode transistor 204 in process block 414 is NL_INJ In real time, the cascode amplifier 200 responds to an input signal at the input terminal VIN and an output signal generated at the output terminal VOUT.

[0052] Figure 4B Shows a reduction Figure 3 An exemplary method of nonlinear effects of a more specific example of a cascode amplifier 300 is shown. Figure 4B The process boxes shown in Figure 4A The process blocks shown in and described above.

[0053] refer to Figure 3 In the cascode amplifier 300 of the embodiment, in process block 450, an input signal is received at an input terminal VIN, and thus at a gate terminal of an NMOS common-source transistor 302. At process block 450, an appropriate power supply voltage is received at a power supply terminal VDD with reference to circuit ground and at a ground terminal coupled to a source terminal of the NMOS transistor 302. In addition, an appropriate bias voltage is received at a bias terminal VBIAS, and thus at a gate of an NMOS cascode transistor 304 coupled in a common-gate arrangement. In process block 452, the cascode amplifier 300 generates an output signal from the drain terminal of the cascode transistor 304 at an output terminal VOUT in response to the input signal applied in process block 450.

[0054] At the same time, in process block 460, the input signal at input terminal VIN is also received at the gate terminal of NMOS transistor 332 in common source amplifier 330 in current injection circuit 320. As mentioned above, common source amplifier 330 applies a gain (inverting gain in this example) to the input signal based on the gain of NMOS transistor 332 and the resistance of resistor 334. This gain can be selected to produce a voltage swing at the drain terminal of NMOS transistor 332, thereby setting the out-of-phase injection current I from differential amplifier 340. NL_INJ The amplitude.

[0055] In process block 462, the output signal from common source amplifier 330 in response to the input signal at input terminal VIN is applied to differential amplifier 340. Figure 3 In the example of differential amplifier 340, resistor 348 establishes a differential voltage signal across the gate terminals of NMOS transistors 342 and 344 based on the output signal from common source amplifier 330. In response to this differential voltage signal and in response to the phase of the input signal at input terminal VIN, NMOS transistors 342 and 344 conduct injection currents I out of phase with each other at their drain terminals. NL_INJ By setting the gain of the common-source amplifier 330 as described above, the out-of-phase injection current I NL_INJ The magnitude of may correspond to the nonlinear current I conducted by the cascode transistor 304 NL The amplitude.

[0056] In process block 464, current injection circuit 220 injects out-of-phase current I according to the phase of the input signal at terminal VIN. NL_INJ is applied to the drain terminal and the source terminal of the cascode transistor 304. For example, in which the nonlinear current I NL During the positive input signal phase (such as Figure 3 ), NMOS transistor 342 conducts injection current I from the source terminal of cascode transistor 304 NL_INJ In contrast, the nonlinear current I NL During the negative input signal phase, NMOS transistor 344 conducts current I from the drain terminal of cascode transistor 304. NL_INJ Therefore, the current injection circuit 320 is a nonlinear current I conducted by the cascode transistor 304 during the operation of the cascode amplifier 300. NL Provides a current path.

[0057] As in Figure 4A In the example of , process blocks 460 , 462 , and 464 are performed concurrently with process blocks 450 and 452 .

[0058] The examples described above enable a significant improvement in the linearity of the cascode amplifier. This improvement is evident in reducing intermodulation distortion that varies with frequency. A common measure of intermodulation distortion in a weakly nonlinear circuit (e.g., a cascode amplifier in which the current through the cascode transistor has a nonlinear component) is the output third-order intercept point (OIP3). OIP3 is a quality factor associated with third-order intermodulation distortion, and compares the distortion power caused by third-order nonlinear conduction with the output power of a linearly amplified input signal. OIP3 is mathematical in that it is based on extrapolating the output power to input power characteristics on a logarithmic scale for both the output power and the third-order nonlinear product to determine the crossover point.

[0059] Figure 5A and Figure 5B Will Figure 3 The variation of OIP3 of the exemplary cascode amplifier 300 with frequency is Figure 1B The OIP3 of the prior art cascode amplifier 150 is compared with the frequency. Figure 5A and 5B The exemplary plot of is based on a simulation of an amplifier in response to two input frequency tones with a fixed frequency offset (eg, a constant |f1-f2|) within a center frequency range of 1 GHz to 6.5 GHz. Figure 5A shows the OIP3 comparison of intermodulation frequency (2f2-f1), and Figure 5B A comparison of OIP3 at intermodulation frequency (2f1-f2) is shown.

[0060] Figure 5A Plot 501 and Figure 5B The plot 511 in FIG. 5 shows a prior art cascode amplifier (eg, Figure 1B The OIP3 behavior of the cascode amplifier) ​​in the frequency range of about 1.2 GHz to about 6.5 GHz is described. Figure 5A Plot 505 and Figure 5B Plot 515 in FIG. 5 shows a common-source common-gate amplifier (eg, as described above with respect to Figure 3 The OIP3 behavior of the cascode amplifier described in the previous section is shown in Figure 2 over the same frequency range. Figure 5A and 5B Clearly, the OIP3 improves by about 6.5dB at the high end frequency of 6.5GHz, making the overall OIP3 of the amplifier 38dBm or better over the entire frequency range.

[0061] Thus, the examples described above enable a significant improvement in the linearity of cascode amplifiers, particularly those operating at high frequencies. This improvement is achieved due to a reduction in the amount of nonlinear current conducted by the cascode device that is injected into the amplifier output. This improvement can be reflected by a significant improvement in metrics such as OIP3. In addition, from a power consumption perspective, the examples described above can be implemented in an efficient manner. For example, some implementations of these examples achieve these advantages while requiring as little as about 20% of the bias current of the cascode device.

[0062] Examples are described in this specification as being implemented into a common-source common-gate amplifier used, for example, in high-frequency applications (e.g., communications or spectrum analysis) because this embodiment may be advantageous in that context. However, aspects of these examples may be beneficially applied in a wide range of applications and with a variety of transistor technologies. Therefore, the above description is provided only as an example and is not intended to limit the true scope of what is claimed.

[0063] As used herein, the terms "terminal", "node", "interconnection" and "pin" are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their terminals.

[0064] Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. In the examples described, modifications may be made, and other examples are possible within the scope of the claims.

[0065] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0066] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually only include semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party. Although in some exemplary embodiments, certain elements are included in the integrated circuit and other elements are outside the integrated circuit, in other exemplary embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being outside the integrated circuit may be included in the integrated circuit, and / or some features shown as being inside the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0067] The circuits described herein can be reconfigured to include replaced components to provide functionality that is at least partially similar to the functionality available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements that are coupled in series and / or in parallel to provide the impedance amount represented by the displayed resistor. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0068] Use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0069] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A circuit comprising: a first transistor having a first terminal coupled to the first power supply terminal, a second terminal, and a control terminal coupled to the input terminal; a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the output terminal, and a bias terminal coupled to a gate terminal; as well as A current injection circuit has an input coupled to the input terminal, a first output coupled to the second terminal of the second transistor, and a second output coupled to the first terminal of the second transistor.

2. The circuit according to claim 1, further comprising: A load device has a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to a second power supply terminal of the circuit.

3. The circuit of claim 1 , wherein the current injection circuit comprises: a third transistor having a first terminal, a second current terminal coupled to the second terminal of the second transistor, and a control terminal coupled to the input terminal; a fourth transistor having a first terminal, a second terminal coupled to the first terminal of the second transistor, and a control terminal; a current source having a first terminal coupled to the first power supply terminal and a second terminal coupled to the first terminals of the third transistor and the fourth transistor; as well as A first resistor has a first terminal coupled to the control terminal of the third transistor and a second terminal coupled to the control terminal of the fourth transistor.

4. The circuit of claim 3, wherein the current injection circuit further comprises: a fifth transistor having a first terminal coupled to the first power terminal, a second terminal coupled to the control terminal of the third transistor and to the first terminal of the first resistor, and a control terminal coupled to the input terminal; a second resistor having a first terminal coupled to the second power supply terminal and a second terminal coupled to the second terminal of the fifth transistor; as well as A capacitor has a first terminal coupled to the control terminal of the fifth transistor and a second terminal coupled to the first power terminal.

5. The circuit according to claim 3, wherein the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are n-channel metal oxide semiconductor (MOS) transistors; wherein the first power terminal receives a common potential; And wherein the second power terminal receives a positive potential relative to the common potential.

6. The circuit of claim 3, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are p-channel MOS transistors; wherein the second power supply terminal receives a common potential; And wherein the first power terminal receives a positive potential relative to the common potential. 7 . The circuit of claim 3 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are bipolar junction transistors.

8. A common-source common-gate amplifier, comprising: an amplifier transistor having a first terminal receiving a first supply voltage, a second terminal, and a control terminal receiving an input signal; a cascode transistor having a first terminal coupled to the second terminal of the amplifier transistor, a second terminal coupled to an output terminal, and a control terminal receiving a bias voltage; as well as a current injection circuit having an input for receiving the input signal, and first and second outputs coupled to the first and second terminals of the cascode transistor, respectively, the current injection circuit being configured to present out-of-phase currents from its first and second outputs in response to the input signal.

9. The cascode amplifier according to claim 8, further comprising: A load device has a first terminal coupled to the second terminal of the cascode transistor and a second terminal coupled to a second power supply terminal of the circuit.

10. The cascode amplifier according to claim 9, wherein the current injection circuit comprises: an amplifier having an input coupled to the input terminal and having an output; as well as a differential amplifier having a first input and a second input coupled to the output of the amplifier to establish a differential voltage between the first input and the second input, and having a first output and a second output coupled to the second terminal and the first terminal of the cascode transistor, respectively.

11. The cascode amplifier of claim 10, wherein the differential amplifier comprises: a first transistor having a first terminal, a second terminal corresponding to the first output of the differential amplifier coupled to the second terminal of the cascode transistor, and a control terminal corresponding to the first input of the differential amplifier coupled to the output of the second amplifier; a second transistor having a first terminal, a second terminal corresponding to the second output of the differential amplifier coupled to the first terminal of the cascode transistor, and a control terminal corresponding to the second input of the differential amplifier; a current source receiving a first supply voltage and coupled to the first terminals of the first transistor and the second transistor; A first resistor is coupled between the control terminals of the first transistor and the second transistor.

12. The cascode amplifier of claim 11, wherein the amplifier comprises: a third transistor having a first terminal receiving the first supply voltage, a second terminal coupled to the control terminal of the first transistor, and a control terminal receiving the input signal; a second resistor receiving a second supply voltage and coupled to the second terminal of the third transistor; as well as A capacitor receives the first supply voltage and is coupled to the control terminal of the second transistor.

13. The cascode amplifier of claim 12, wherein the input transistor, the cascode transistor, the first transistor, the second transistor, and the third transistor are n-channel metal oxide semiconductor (MOS) transistors; wherein the first power terminal receives a common potential; And wherein the second power terminal receives a positive potential relative to the common potential.

14. The cascode amplifier of claim 12, wherein the input transistor, the cascode transistor, the first transistor, the second transistor, and the third transistor are p-channel MOS transistors; wherein the second power supply terminal receives a common potential; And wherein the first power terminal receives a positive potential relative to the common potential.

15. The cascode amplifier of claim 12, wherein the input transistor, the cascode transistor, the first transistor, the second transistor, and the third transistor are bipolar junction transistors.

16. A method comprising: receiving an input signal at an amplifier transistor in a cascode amplifier, the cascode amplifier further comprising a cascode transistor coupled to the input transistor; generating out-of-phase injection currents from first and second outputs of a current injection circuit in response to the input signal; applying the out-of-phase injection current to a first current terminal and a second current terminal of the cascode transistor; as well as An output signal is generated from an output of the cascode amplifier in response to the input signal.

17. The method of claim 16, wherein receiving an input signal at an amplifier transistor comprises: receiving the input signal at a gate terminal of a common-source transistor in the cascode amplifier; And wherein generating an output signal comprises: An output signal is generated at a drain terminal of the cascode transistor.

18. The method of claim 17, wherein generating out-of-phase injection currents comprises: receiving the input signal at a common-source amplifier; applying an output signal from the common-source amplifier as a differential voltage to gate terminals of a first differential amplifier transistor and a second differential amplifier transistor; And wherein applying the opposite phase compensation current comprises: Currents from drain terminals of the first differential amplifier transistor and the second differential amplifier transistor are applied to the source terminal and the drain terminal of the cascode transistor, respectively.

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