Analog delay adjusting circuit and method

Abstract

The invention provides an analog time-delay adjusting circuit and method, the analog time-delay adjusting circuit comprises a time-delay circuit, a time-delay control circuit and a driving circuit, the time-delay circuit comprises a plurality of cascaded time-delay modules, and each time-delay module comprises two stages of time-delay units, and the output end of the first-stage delay unit is electrically connected with the input end of the second-stage delay unit. The delay control circuit selects the delay modules in the delay circuit, the delay adjustment range can be increased by increasing the number of the delay modules and selecting and connecting different numbers of delay units according to the needed delay duration, and meanwhile delay coarse adjustment and delay fine adjustment can be achieved by selecting different delay units to be combined, so that the delay adjustment precision is improved. And finally, the signal is output to a post-stage circuit after being subjected to delay processing through the driving circuit, so that a synchronous signal can be provided for the post-stage circuit, and the requirement of data synchronous acquisition is met.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an analog delay adjustment circuit and method. Background Art

[0002] With the rapid development of modern society, higher and higher requirements are placed on the transmission rate and signal accuracy of communication technology. However, due to the shorter signal cycle, the synchronization between high-speed signals and data is particularly difficult. In a synchronous system, as the resolution and conversion rate of data converters increase, when there are multiple converter chips, the data throughput increases exponentially, and traditional CMOS and LVDS interfaces will not be able to meet the processing requirements of high-speed signals. In order to meet the higher-speed interface protocol, the JESD204 interface protocol came into being. Version A supports a data rate of up to 3.125Gbps, version B supports a serial data rate of up to 12.5Gbps, and version C supports a data rate of up to 32Gbps.

[0003] In order to obtain the optimal data acquisition solution, taking the JESD204B interface protocol as an example, key signals need to be designed and processed. Usually, the edge of the clock signal or data signal is shifted so that the clock flip occurs in the middle of the data logic level to correctly acquire the first bit of the data, thereby ensuring the correct synchronization between the clock and data. The specific timing diagram of the clock signal and the data signal is shown in the figure. Figure 1 As shown. Usually, the large-step delay adjustment of x cycles is achieved by periodic signal adjustment, and the coarse delay adjustment of y half cycles is achieved by digital coarse adjustment. However, high-speed signals are significantly affected by non-ideal factors such as transistor-level wiring, on-chip connections, off-chip PCB routing mismatch, and signal interference. When the data rate gradually increases to the Gbps level, the rise time, fall time, and signal skew are unstable states, and the proportion of the signal cycle increases, which will cause Figure 1 As the range of the "adjustable window" in is reduced, the limited accuracy of the above scheme will no longer meet the requirements of high-speed data synchronization. Summary of the invention

[0004] The main purpose of the present application is to provide an analog delay adjustment circuit and method, aiming to solve the problem that the delay adjustment scheme in the related art has limited adjustment accuracy and cannot meet the requirements of high-speed data synchronization.

[0005] To achieve the above-mentioned purpose, the first aspect of the present application provides an analog delay adjustment circuit, including: a delay circuit, a delay control circuit and a drive circuit, the delay circuit includes a plurality of cascaded delay modules, each delay module includes two-stage delay units, the output end of the first-stage delay unit is electrically connected to the input end of the second-stage delay unit, and the drive circuit is used to electrically connect to an external processing module; the delay control circuit is used to: output a corresponding selection control signal to the second-stage delay unit according to a preset delay time; wherein the selection control signal is used to select the corresponding delay module to be connected to the drive circuit; the first-stage delay unit is used to: perform a delay processing of a preset first time length on the input signal and then output it to the second-stage delay unit; the second-stage delay unit is used to: perform a delay processing of a preset second time length on the output signal of the first-stage delay unit, and when the delay module corresponding to the second-stage delay unit is connected to the drive circuit, the output signal of the second-stage delay unit is transmitted to the drive circuit; the drive circuit is used to: perform a delay processing of a preset third time length on the output signal of the delay circuit and then output it to the processing module.

[0006] The second aspect of the present application provides an analog delay adjustment method, which is applied to the analog delay adjustment circuit as described in the first aspect of the present application, and the analog delay adjustment method includes: the delay control circuit outputs a corresponding selection control signal to the second-level delay unit according to a preset delay time; wherein the selection control signal is used to select the corresponding delay module to be connected to the driving circuit; the first-level delay unit performs delay processing of a preset first time length on the input signal and transmits it to the second-level delay unit; the second-level delay unit performs delay processing of a preset second time length on the output signal of the first-level delay unit, and when the delay module corresponding to the second-level delay unit is connected to the driving circuit, the output signal of the second-level delay unit is transmitted to the driving circuit; the driving circuit performs delay processing of a preset third time length on the output signal of the delay circuit and outputs it to the processing module.

[0007] From the above description, it can be seen that in the present application, the delay control circuit selects the delay module in the delay circuit, and by increasing the number of delay modules and selecting different numbers of delay units to connect according to the required delay duration, the delay adjustment range can be increased. At the same time, by selecting different delay units for combination, asynchronous delays can be achieved, and coarse and fine delay adjustments can be achieved, effectively improving the flexibility and accuracy of delay adjustment. Finally, the delay is processed by the driving circuit and then output to the subsequent circuit, providing a synchronous signal for the subsequent circuit to meet the needs of high-speed data synchronization acquisition. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 It is a timing diagram of synchronization of a clock signal and a data signal provided in an embodiment of the present application; Figure 2 It is a structural schematic diagram of an analog delay adjustment circuit provided in an embodiment of the present application; Figure 3 is a circuit schematic diagram of a delay circuit provided in an embodiment of the present application; Figure 4 is a circuit schematic diagram of a driving circuit provided in an embodiment of the present application; Figure 5 is a structural schematic diagram of another analog delay adjustment circuit provided in an embodiment of the present application; Figure 6 It is a basic flow chart of a simulation delay adjustment method provided in an embodiment of the present application; Figure 7 It is a structural schematic diagram of a delay control circuit provided in an embodiment of the present application; Figure 8 It is a comparison diagram of input and output signals of a delay control circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0010] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0011] In the related art, due to the limited adjustment accuracy of the delay adjustment scheme, the requirement of high-speed data synchronization cannot be met well. Therefore, an embodiment of the present application provides an analog delay adjustment circuit.

[0012] like Figure 2As shown is a structural schematic diagram of an analog delay adjustment circuit provided in an embodiment of the present application, the analog delay adjustment circuit includes: a delay circuit 100, a delay control circuit 200 and a drive circuit 300, the delay circuit 100 includes a plurality of cascaded delay modules 110, each delay module 110 includes two-stage delay units, the output end of the first-stage delay unit 111 is electrically connected to the input end of the second-stage delay unit 112, and the drive circuit 300 is used to electrically connect to an external processing module 400.

[0013] Specifically, the delay control circuit 200 is used to: output a corresponding selection control signal to the second-stage delay unit 112 according to a preset delay time; wherein the selection control signal is used to select the corresponding delay module 110 to be connected to the driving circuit 300; the first-stage delay unit 111 is used to: perform a delay process of a preset first time length on the input signal and then output it to the second-stage delay unit 112; the second-stage delay unit 112 is used to: perform a delay process of a preset second time length on the output signal of the first-stage delay unit 111, and when the delay module 110 corresponding to the second-stage delay unit 112 is connected to the driving circuit 300, the output signal of the second-stage delay unit 112 is transmitted to the driving circuit 300; the driving circuit 300 is used to: perform a delay process of a preset third time length on the output signal of the delay circuit 100 and then output it to the processing module 400. Among them, the first-stage delay unit 111, the second-stage delay unit 112 and the driving circuit 300 all include CML (Current Mode Logic) circuits.

[0014] In this embodiment, the analog delay adjustment circuit realizes high-precision delay adjustment based on the CML structure, wherein the delay control circuit 200 can generate a corresponding selection control signal according to the required delay time, and transmit the selection control signal to the delay circuit 100 to select the output signal processed by different numbers of delay modules 110 to be transmitted to the driving circuit 300; wherein the first-stage delay unit 111 and the second-stage delay unit 112 are both used to delay the input differential signal, and each delay module 110 is cascaded. When different delay units are selected to be connected to the driving circuit 300 When the differential signal is input, it will be delayed by different numbers of delay modules 110, so that the range of delay adjustment can be improved by increasing the number of delay units, and by selecting different delay units for combined processing, it is possible to perform delay processing of the differential signal with different time lengths, thereby achieving coarse and fine adjustment of the signal, thereby improving the accuracy of delay adjustment and meeting the requirements of high-speed and high-precision synchronization protocols. Finally, the signal is output to an external processing module after delay and drive processing by the driving circuit 300, so that the processing module can perform effective data acquisition based on the signal after delay processing.

[0015] like Figure 3The circuit diagram of a delay circuit provided by this embodiment is shown in FIG. Figure 2 and Figure 3 The first-stage delay unit 111 includes a first resistor-capacitor circuit, a second resistor-capacitor circuit, a first transistor NM1, a second transistor NM2, and a third transistor NM3.

[0016] Specifically, the first ends of the first transistor NM1 and the second transistor NM2 of the first delay module 110 are used to be electrically connected to an external differential signal generator, the first ends of the first transistors and the second transistors of the remaining delay modules 110 are electrically connected to the second-stage delay unit 112 in the previous delay module 110, the second ends of the first transistor NM1 and the second transistor NM2 in all the first-stage delay units 111 are electrically connected to the first end of the third transistor NM3, the third end of the first transistor NM1 is electrically connected to the first resistor-capacitor circuit and the second-stage delay unit 112, the third end of the second transistor NM2 is electrically connected to the second resistor-capacitor circuit and the second-stage delay unit 112, the second end of the third transistor NM3 is used to be electrically connected to an external control signal generator, and the third end of the third transistor NM3 is grounded. Wherein, the first resistor-capacitor circuit and the second resistor-capacitor circuit both include a resistor R1 and a first capacitor C1, one end of the resistor R1 is electrically connected to the transistor, the other end of the resistor R1 is electrically connected to the power supply, and the two ends of the first capacitor C1 are electrically connected to the two ends of the resistor R1, respectively.

[0017] In this embodiment, the first-stage delay unit 111 is based on a fully differential CML structure. The load of the first-stage delay unit 111 is a fixed passive RC, which provides a fixed delay. The first-stage delay unit 111 can be set to one or more cascaded delay sub-units according to the delay time requirement. In this embodiment, the minimum unit is a delay sub-unit as an example. The first-stage delay unit 111 includes two resistor-capacitor circuits (i.e., RC circuits), three transistors such as Figure 3 The NMOS tube shown, wherein the first transistor NM1 and the second transistor NM2 of the first delay module 110 are used to receive the input high-speed differential signals VIP and VIN, and the first transistors NM1 and the second transistors NM2 of the remaining delay modules 110 receive the output signal of the second-stage delay unit 112 in the previous delay module 110, and the input differential signal can be selected as a high-speed clock signal and / or a data signal according to actual application requirements; the third transistor NM3 is enabled and controlled by the bias voltage signal VBIAS to provide a stable bias current for the CML circuit; the device parameters of the two RC circuits are the same and the structure is the same, providing a fixed delay for this level of link.

[0018] For further information, see Figures 2 to 3 The delay circuit 100 also includes a first load resistor and a second load resistor (ie Figure 3The second-stage delay unit 112 includes a first delay subunit 1120 and a second delay subunit 1121, and the first delay subunit 1120 and the second delay subunit 1121 both include a CML circuit; the first delay subunit 1120 is electrically connected to the first-stage delay unit 111 and the second delay subunit 1121, respectively, the second delay subunit 1121 is electrically connected to the first-stage delay unit 111 of the next delay module 110, one end of the first load resistor (i.e., the resistor RL connected to the signal VOP2) is electrically connected to the first delay subunit 1120 and the driving circuit 300, one end of the second load resistor (i.e., the resistor RL connected to the signal VON2) is electrically connected to the second delay subunit 1121 and the driving circuit 300, and the other ends of the first load resistor and the second load resistor are both electrically connected to the power supply.

[0019] Specifically, the first delay subunit 1120 and the second delay subunit 1121 each include a fourth transistor NM3 / NM5, a fifth transistor NM4 / NM6, a sixth transistor NM8 / NM9 and a switch device Sn. <0> / Sn <1> The first end of the fourth transistor NM3 / NM5 is electrically connected to the first-stage delay unit 111 or the first delay subunit 1120, the first end of the fifth transistor NM4 / NM6 is electrically connected to the first-stage delay unit 111 or the first delay subunit 1120, the second end of the fourth transistor NM3 / NM5 is electrically connected to the first load resistor and the drive circuit 300, the second end of the fifth transistor NM4 / NM6 is electrically connected to the second load resistor and the drive circuit 300, the third end of the fourth transistor NM3 / NM5 and the fifth transistor NM4 / NM6 are electrically connected to the first end of the sixth transistor NM8 / NM9, and the second end of the sixth transistor NM8 / NM9 is electrically connected to the first end of the sixth transistor NM8 / NM9 through the switch device Sn. <0> / Sn <1> The sixth transistor NM8 / NM9 is electrically connected to an external control signal generator, and a third terminal thereof is grounded.

[0020] In this embodiment, the second-stage delay unit 112 is an optional output stage. The second-stage delay unit 112 generally includes two cascaded delay sub-units. Each delay sub-unit has the same structure. Taking the first second-stage delay unit 112 as an example, the first and second delay sub-units each include three transistors, such as Figure 3 The NMOS tube in the <0> / Sn <1> (n≥0), two transistors of the first delay subunit 1120 are used to receive the signal transmitted by the first-stage delay unit 111 in the delay module 110, two transistors of the second delay subunit 1121 are used to receive the signal transmitted by the first delay subunit 1120, and both transistors of the first and second delay subunits are connected to the driving circuit 300, Figure 3The signals VOP1 and VON1 in the delay module 110 are transmitted to the input end of the next delay module 110 (that is, the input end of the first delay unit 111 in the next delay module 110) to form a cascade system, and the signals VOP2 and VON2 are transmitted to the drive circuit 300, and the VOP2 and VON2 of the plurality of second delay units 112 are connected to the drive circuit and the first load resistor and the second load resistor; another transistor is connected to the first load resistor and the second load resistor through the switch device Sn. <0> / Sn <1> Connected to the control signal generator, when the switching device Sn <0> / Sn <1> When connected, the transistor is turned on to provide a stable bias current for the CML circuit, and the delay control circuit 200 selects two adjacent switch devices Sn. <0> / Sn <1> Closed, different delay paths can be selected. In addition, since the delay of the link is determined by the load of the output node, the resistance and parasitic capacitance of the signal node are required to be small enough to meet the signal swing and delay adjustment accuracy requirements for transmitting high-frequency signals.

[0021] like Figure 4 The schematic diagram of a driving circuit provided in this embodiment is shown in FIG. Figure 4 The driving circuit 300 includes a second resistor and a third resistor (i.e. Figure 4 two resistors R2 in the circuit), a seventh transistor NM10, an eighth transistor NM11 and a ninth transistor NM12; the first ends of the seventh transistor NM10 and the eighth transistor NM11 are both electrically connected to the second-stage delay unit 112, the second ends of the seventh transistor NM10 and the eighth transistor NM11 are both electrically connected to the first end of the ninth transistor NM12, the third end of the seventh transistor NM10 is respectively electrically connected to one end of the second resistor and the processing module, the third end of the eighth transistor NM11 is respectively electrically connected to one end of the third resistor and the processing module, the other ends of the second resistor and the third resistor are electrically connected to the power supply, the second end of the ninth transistor NM12 is used to be electrically connected to an external control signal generator, and the third end of the ninth transistor NM12 is grounded.

[0022] Specifically, in this embodiment, the driving circuit 300 is also based on the CML circuit, which can delay the signal output by the delay circuit 100, and can isolate the subsequent circuit from the delay circuit 100, and provide sufficient driving capability to prevent the delay circuit 100 from being affected by the subsequent circuit. The driving circuit 300 includes three transistors and two resistors, two of which are used to receive the signal transmitted by the delay circuit 100 (i.e. Figure 4 The signals VIP and VIN in the circuit are output at the same time (i.e. Figure 4The output signals VOP and VON in the input / output circuit are sent to the external processing module, and the other transistor is enabled by the bias voltage signal VBIAS to provide a stable bias current for the CML circuit. In addition, the delay of the driving circuit 300 is also determined by the node load. The output signals VOP and VON are connected to the nodes of the subsequent circuit without the need to design additional capacitors. Due to the transmission of high-frequency signals, the parasitic resistance and parasitic capacitance of the input and output nodes need to be small enough to meet the signal swing and delay adjustment accuracy requirements of the high-frequency signal.

[0023] Therefore, the analog delay adjustment circuit provided in this embodiment can use fewer circuit modules and a simple system structure to achieve high-precision delay control of high-speed signals. At the same time, the circuit works in an open-loop state without oscillation risk; the delay adjustment is controlled by combinational logic without functional risk; the delay step can be additionally configured through the trimming bit to reduce the impact of the process angle of passive components; the delay adjustment of high-frequency signals greater than half a cycle can be achieved, and combined with the typical half-cycle digital delay, it can meet the data synchronization acquisition application requirements of multiple scenarios.

[0024] The present application also provides an analog delay adjustment method, which is applied to the above analog delay adjustment circuit. Figure 5 The structural diagram of the analog delay adjustment circuit shown in FIG. Figure 6 The basic flow chart of the analog delay adjustment method shown in FIG. 1 includes the following steps: Step 601: The delay control circuit outputs a corresponding selection control signal to the second-stage delay unit according to a preset delay time.

[0025] In some implementations of the present embodiment, the delay control circuit outputs a corresponding selection control signal to the second-stage delay unit according to a preset delay time, including: when the delay control circuit receives a binary control code corresponding to the preset delay time, the delay control circuit generates a corresponding selection control signal and transmits it to the corresponding switching device in the second-stage delay unit; wherein the selection control signal is used to control the switching device to enter the on state, and when the switching device is in the on state, the corresponding delay sub-unit is connected to the driving circuit.

[0026] Specifically, in this embodiment, the delay control circuit can output a corresponding selection control signal according to the required delay time, wherein the input of the delay control circuit can be a k-bit binary control code, and according to the relationship comparison table between the required delay time and the binary control code, the corresponding binary control code is input to the delay control circuit. The delay control circuit can be a logic control circuit such as an encoder and a decoder. The output of the delay control circuit is n groups, a total of 2n combinational logic signals. In this embodiment, the input is 5-bit as an example, and the structure of the delay control circuit is as follows: Figure 7 As shown, Figure 7TIBx in <0> 、TIBx <1> Corresponding to Figure 5 Switching device Sn of the medium delay subunit <0> and Sn <1> When the input is a 5-bit binary control code, the comparison table of input and output signals is as follows: Figure 8 As shown, the blank cells of the output signal represent that the signal is invalid, and only the second-stage delay unit that receives the signal 1 is connected to the driving circuit. Assume Sn <0> Controlled transistors NM8 and Sn <1> The tail currents of the controlled transistor NM9 are respectively a <n> 、b <n>From Table 1, it can be seen that no matter what input combination, there are only two valid output signals; no matter what input combination, the static current flowing through the resistor RL is a+b and remains unchanged; when the configuration bit (decimal) is greater than or equal to 24, the combination of output signals remains unchanged; the 5-bit input configuration can generate 24-step delay control logic combinations.

[0027] Further, in some implementations of this embodiment, generating a corresponding selection control signal and transmitting it to a corresponding switch device in the second-stage delay unit includes: upon receiving a delay time of t delay =t1+ t2+ t3 corresponding to the binary control code, a target selection control signal is generated and transmitted to the target switch device in the corresponding second-stage delay unit; wherein, t1 is the delay time introduced by the RC circuit, t2 is the delay time introduced by the load resistance and the parasitic capacitance of the output node of the second-stage delay unit, and t3 is the delay time introduced by the resistance in the drive circuit and the parasitic capacitance of the output node of the drive circuit; the target switch device is the switch device of the second-stage delay unit in the first delay module, and when the target switch device is in the on state, the first delay module is connected to the drive circuit.

[0028] Specifically, in this embodiment, the delay time length introduced by R1 and C1 in the resistor-capacitor circuit of the first-stage delay unit is defined as t1, the delay time length introduced by the load resistor RL of the delay module and the parasitic capacitor Cpar1 of the output node of the second-stage delay unit is defined as t2, and the delay time length introduced by the resistor R2 in the driving circuit and the parasitic capacitor Cpar2 of the output node of the circuit is defined as t3. By inputting different binary control codes, the signal transmission path can be updated. When the signal link needs to generate a delay time length of t delay = t1+ t2+ t3, the input can be configured as decimal 0, at which time the two switch devices S0 of the first second-stage delay unit <0> 、S0 <1> Connected, now Figure 5 The first delay module in is connected to the drive circuit; when the signal link needs to generate a delay of t delay = t1+ [a / (a+b)]t1+ t2+ t3, the input can be configured as decimal 1. At this time, the switch device S0 in the first second-stage delay unit <1> , the switch device S1 in the second second-stage delay unit <0> Connected, now Figure 5 The second delay module in the circuit is connected to the drive circuit and introduces a delay of a / (a+b)t1; when the signal link needs to generate a delay of t delay = t1+ [b / (a+b)]t1+ t2+ t3, the input can be configured as decimal 2. At this time, the switch device S0 in the first second-stage delay unit <0> , the switch device S1 in the second second-stage delay unit <1> Connected, now Figure 5 The second delay module in the circuit is connected to the drive circuit and introduces a delay of b / (a+b)t1; when the signal link needs to generate a delay of t delay = 2 t1+ t2+ t3, the input can be configured as decimal 3, at this time the switch device S1 in the second second-stage delay unit <0> 、S1 <1> Connected, now Figure 5 The second delay module in is connected to the driving circuit and introduces a delay of t1. At this time, the signal is connected to the driving circuit after passing through two delay modules. Therefore, when the input configuration of the delay control circuit in this embodiment is decimal 3(n-1), the signal link can generate a delay of t delay = nt1+ t2+ t3; when the delay control circuit input is configured as decimal 3(n-1)+1, the signal link can generate a delay of t delay = nt1+ [a / (a+b)]t2+ t3; when the input of the delay control circuit is configured as decimal 3(n-1)+2, the signal link can generate a delay of t delay = nt1+ [b / (a+b)]t2+ t3; through normalization, take a+b=1, where a=1 / 3, b=2 / 3, then we can get: the input configuration is decimal 3(n-1), the delay time is t delay = nt1+ t2+ t3; the input configuration is decimal 3(n-1)+1, and the delay time is t delay = nt1+(1 / 3)t1+t2+ t3; the input configuration is 3(n-1)+2 in decimal, and the delay time is t delay =nt1+(2 / 3)t1+t2+ t3; from this we can see that the simulation delay step is [(1 / 3)t1] / step.

[0029] Step 602: The first-stage delay unit performs a delay process on the input signal for a preset first time length and transmits the delay signal to the second-stage delay unit; Step 603: the second-stage delay unit performs a delay process of a preset second time length on the output signal of the first-stage delay unit, and when the delay module corresponding to the second-stage delay unit is connected to the driving circuit, the output signal of the second-stage delay unit is transmitted to the driving circuit; Step 604: The driving circuit performs a delay process of a preset third time length on the output signal of the delay circuit and outputs the delay signal to the processing module.

[0030] Specifically, in this embodiment, when the output end of the first delay module is directly connected to the driving circuit, the input signal can be delayed for a time length of t1+ t2+ t3; when the output end of the second delay module is directly connected to the driving circuit, the input signal can be delayed for a time length of t1+ (1 / 3) t1+ t2+ t3, t1+ (2 / 3) t1+ t2+ t3, 2t1+ t2+ t3; when the two switch devices in the delay module are all connected, large-step adjustment can be achieved; when one of the switch devices in two adjacent delay modules is connected, small-step adjustment can be achieved. Therefore, this embodiment can achieve multi-step delay adjustment for, for example, a 6.4GHz signal based on an RC delay chain, and the total delay adjustment range is greater than half a signal period. At the same time, high-precision fine-tuning steps can be achieved to meet the requirements of high-precision and high-speed synchronization protocols.

[0031] It should be noted that the various embodiments in the present application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0032] It should also be noted that, in the content of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may expressly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0033] The above description of the disclosed embodiments enables professionals and technicians in the field to implement or use the present application. Various modifications to these embodiments will be apparent to professionals and technicians in the field, and the general principles defined in the present application can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown in the present application, but will conform to the widest range consistent with the principles and novel features disclosed in the present application.< / n> < / n>

Claims

1. An analog delay adjustment circuit, characterized in that: include: A delay circuit, a delay control circuit and a drive circuit, wherein the delay circuit includes a plurality of cascaded delay modules, each of which includes two-stage delay units, the output end of the first-stage delay unit is electrically connected to the input end of the second-stage delay unit, and the drive circuit is used to electrically connect to an external processing module; The delay control circuit is used to: output a corresponding selection control signal to the second-stage delay unit according to a preset delay time; wherein the selection control signal is used to select the corresponding delay module to be connected to the driving circuit; The first-stage delay unit is used to: perform a delay process on the input signal for a preset first time length and then output the delay signal to the second-stage delay unit; The second-stage delay unit is used to: perform a delay process of a preset second time length on the output signal of the first-stage delay unit, and when the delay module corresponding to the second-stage delay unit is connected to the driving circuit, transmit the output signal of the second-stage delay unit to the driving circuit; The driving circuit is used for: performing delay processing of a preset third time length on the output signal of the delay circuit and then outputting the delay signal to the processing module.

2. The analog delay adjustment circuit according to claim 1, characterized in that: The first-stage delay unit, the second-stage delay unit and the driving circuit all include CML circuits.

3. The analog delay adjustment circuit according to claim 2, characterized in that: The first-stage delay unit includes a first resistor-capacitor circuit, a second resistor-capacitor circuit, a first transistor, a second transistor and a third transistor; The first ends of the first transistor and the second transistor of the first delay module are both used to be electrically connected to an external differential signal generator, the first ends of the first transistor and the second transistor of the remaining delay modules are both electrically connected to the second-stage delay unit in the previous delay module, the second ends of the first transistor and the second transistor are both electrically connected to the first end of the third transistor, the third end of the first transistor is respectively electrically connected to the first resistor-capacitor circuit and the second-stage delay unit, the third end of the second transistor is respectively electrically connected to the second resistor-capacitor circuit and the second-stage delay unit, the second end of the third transistor is used to be electrically connected to an external control signal generator, and the third end of the third transistor is grounded.

4. The analog delay adjustment circuit according to claim 3, characterized in that: The first RC circuit and the second RC circuit both include a first resistor and a first capacitor, one end of the first resistor is electrically connected to the transistor, the other end of the first resistor is electrically connected to a power supply, and both ends of the first capacitor are electrically connected to both ends of the first resistor, respectively.

5. The analog delay adjustment circuit according to claim 2, characterized in that: The delay circuit further includes a first load resistor and a second load resistor, the second-stage delay unit includes a first delay subunit and a second delay subunit, and the first delay subunit and the second delay subunit both include a CML circuit; The first delay sub-unit is electrically connected to the first-level delay unit and the second delay sub-unit respectively, the second delay sub-unit is electrically connected to the first-level delay unit of the next delay module, one end of the first load resistor is electrically connected to the first delay sub-unit and the drive circuit respectively, one end of the second load resistor is electrically connected to the second delay sub-unit and the drive circuit respectively, and the other ends of the first load resistor and the second load resistor are both electrically connected to a power supply.

6. The analog delay adjustment circuit according to claim 5, characterized in that: The first delay subunit and the second delay subunit both include a fourth transistor, a fifth transistor, a sixth transistor and a switch device; The first end of the fourth transistor is electrically connected to the first-stage delay unit or the first delay sub-unit, the first end of the fifth transistor is electrically connected to the first-stage delay unit or the first delay sub-unit, the second end of the fourth transistor is electrically connected to the first load resistor and the drive circuit respectively, the second end of the fifth transistor is electrically connected to the second load resistor and the drive circuit respectively, the third ends of the fourth transistor and the fifth transistor are both electrically connected to the first end of the sixth transistor, the second end of the sixth transistor is electrically connected to the external control signal generator through the switching device, the third end of the sixth transistor is grounded, and the switching device is also electrically connected to the delay control circuit.

7. The analog delay adjustment circuit according to claim 2, characterized in that: The driving circuit includes a second resistor, a third resistor, a seventh transistor, an eighth transistor and a ninth transistor; The first ends of the seventh transistor and the eighth transistor are both electrically connected to the second-stage delay unit, the second ends of the seventh transistor and the eighth transistor are both electrically connected to the first end of the ninth transistor, the third end of the seventh transistor is respectively electrically connected to one end of the second resistor and the processing module, the third end of the eighth transistor is respectively electrically connected to one end of the third resistor and the processing module, the other ends of the second resistor and the third resistor are electrically connected to a power supply, the second end of the ninth transistor is used to be electrically connected to an external control signal generator, and the third end of the ninth transistor is grounded.

8. A method for adjusting analog delay, characterized in that: Applied to the analog delay adjustment circuit according to any one of claims 1 to 7, the analog delay adjustment method comprises: The delay control circuit outputs a corresponding selection control signal to the second-stage delay unit according to a preset delay time; wherein the selection control signal is used to select a corresponding delay module to be connected to the drive circuit; The first-stage delay unit performs a delay process of a preset first time length on the input signal and transmits the delay to the second-stage delay unit; The second-stage delay unit performs a delay process of a preset second time length on the output signal of the first-stage delay unit, and when the delay module corresponding to the second-stage delay unit is connected to the driving circuit, the output signal of the second-stage delay unit is transmitted to the driving circuit; The driving circuit performs a delay process of a preset third time length on the output signal of the delay circuit and then outputs the delay signal to the processing module.

9. The analog delay adjustment method according to claim 8, characterized in that: The delay control circuit outputs a corresponding selection control signal to the second-stage delay unit according to a preset delay time, including: When the delay control circuit receives the binary control code corresponding to the preset delay time length, it generates a corresponding selection control signal and transmits it to the corresponding switch device in the second-stage delay unit; The selection control signal is used to control the switch device to enter the on state. When the switch device is in the on state, the corresponding delay subunit is connected to the drive circuit.

10. The analog delay adjustment method according to claim 9, characterized in that: The generating of the corresponding selection control signal and transmitting it to the corresponding switch device in the second-stage delay unit includes: The delay control circuit receives the delay time t delay When the corresponding binary control code is generated, a target selection control signal is generated and transmitted to the target switch device in the corresponding second-stage delay unit; Among them, t delay = t1 + t2 + t3, t1 is the delay time introduced by the RC circuit, t2 is the delay time introduced by the load resistance and the parasitic capacitance of the output node of the second-stage delay unit, and t3 is the delay time introduced by the resistance in the drive circuit and the parasitic capacitance of the output node of the drive circuit; the target switching device is the switching device of the second-stage delay unit in the first delay module, and when the target switching device is in the on state, the first delay module is connected to the drive circuit.

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