A circuit for improving LDO overshoot by switching the substrate of a driving tube

Abstract

The present invention belongs to the technical field of integrated circuits, and particularly relates to a circuit for improving LDO overshoot by switching the substrate of a driving tube. The circuit comprises an error amplifier EA, wherein the positive input terminal of the error amplifier EA is connected to a feedback voltage VFB, the negative input terminal is connected to a reference voltage VREF, and the output terminal is connected to the gate terminal of a power tube P1; the power tube P1, wherein the source terminal of the power tube P1 is connected to a power supply potential VDD, the drain terminal is connected to the upper end of a resistor R1 and an LDO output voltage LDO_OUT, and the substrate terminal is connected to a substrate potential V_bulk; a feedback resistor; an overshoot detection circuit, comprising inverters INV1~INV3, a trigger D, an AND gate AND, an OR gate OR1, a NOR gate NOR1, a delay unit T3~T6 and an edge detection circuit; the present invention controls the substrate potential of the power tube through digital logic to increase or decrease the threshold voltage of the power tube, and reduce or increase its leakage current to achieve suppression of output overshoot.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a circuit for driving tube substrate switching to improve LDO overshoot. Background Art

[0002] LDO low-dropout linear regulators are gradually replacing traditional switching regulators due to their simple structure, low dropout, high efficiency, and low cost. In recent years, due to the further reduction and reduction of chip area and cost, traditional LDOs, namely, off-chip capacitor LDOs, have been replaced by off-chip capacitor-free LDOs because they need to reserve load capacitor pins outside the chip, which increases costs and wastes a large amount of capacitor area. However, due to the significant reduction in the value of the load capacitor, the transient response capability of the LDO is deteriorated. When the LDO load jumps, if the instantaneous overshoot and undershoot of the LDO are too large, the parameters of the module being powered will be deteriorated or even the function will be abnormal. In order to ensure the stability of the off-chip capacitor-free LDO, it is necessary to effectively improve the transient response capability of the off-chip capacitor-free LDO to prevent the impact from being too high or too low, and the LDO cannot stably power other modules.

[0003] The overall circuit structure of the current LDO and auxiliary circuit for improving transient response is as follows Figure 1 As shown, the overall circuit structure is divided into five major structures, namely A, B, C, D, and E: Structure A is an error amplifier, with the negative input terminal connected to the VREF reference voltage, the positive input terminal connected to the feedback voltage VFB, and the output terminal connected to the gate terminal of the power tube; Structure B is a power tube, with its source terminal connected to the VIN input voltage and the drain terminal connected to the LDO output voltage LDO_OUT; Structure C is a feedback resistor, with the upper terminal of the resistor connected to the LDO output voltage, the lower terminal of the resistor grounded, and the middle of the resistor connected to the feedback node voltage VFB; Structure D is a detection circuit, which is composed of two comparators, and the detection points are located at the upper voltage dividing node and the lower voltage dividing node of the LDO feedback node VFB, namely VFB+ and VFB-, respectively. The comparator detects VFB- and compares it with the reference voltage VREF. When the LDO output has an upward impact, VFB- increases instantly and when VFB- is higher than VFB, the comparator flips; similarly, when VFB+ is detected and compared with the reference voltage VREF, when the LDO output voltage has a downward impact, VFB+ decreases instantly and when VFB- is lower than VFB, the comparator flips. Structure E is a slew rate enhancement circuit (generally a fast charging and discharging circuit), which is controlled by structure C and has its output connected to the gate of the power tube. It improves the transient response speed of the LDO by directly charging and discharging the gate of the power tube instead of adjusting the LDO output voltage through a feedback loop, thereby suppressing the instantaneous overshoot of the LDO.

[0004] However, the above existing circuit has the following technical defects:

[0005] 1. Using a comparator to detect output overshoot and slew rate enhancement circuit will introduce a lot of power consumption into the circuit, because the comparator needs a higher slew rate and faster speed, and its tail current needs to be larger. At the same time, the slew rate enhancement circuit also needs a higher current to increase the charging and discharging speed.

[0006] 2. The auxiliary circuit for improving LDO transient response takes up a large area and is not suitable for scenarios with high circuit area requirements.

[0007] 3. The characteristics of the comparator (such as slew rate, offset, open-loop gain, margin, etc.) have a great influence on the detection accuracy and speed, etc., and the design requirements of the comparator are high, which increases the design difficulty for designers.

[0008] 4. The method of improving LDO overshoot by directly dynamically controlling the gate voltage of the power tube may have the risk of affecting the stability of the loop and easily cause self-oscillation of the loop system. Summary of the invention

[0009] The object of the present invention is to provide a circuit for improving LDO overshoot by switching the substrate of a driving tube, by digitally detecting the overshoot of the LDO output voltage and controlling the substrate potential of the power tube by digital logic, so as to increase or decrease the threshold voltage of the power tube and reduce or increase its leakage current, so as to suppress the output overshoot.

[0010] In order to solve the above technical problems, the present invention provides a circuit for driving tube substrate switching to improve LDO overshoot, comprising:

[0011] An error amplifier EA, wherein the positive input terminal of the error amplifier EA is connected to the feedback voltage VFB, the negative input terminal is connected to the reference voltage VREF, and the output terminal is connected to the gate terminal of the power tube P1;

[0012] A power tube P1, wherein a source terminal of the power tube P1 is connected to a power supply potential VDD, a drain terminal is connected to an upper end of a resistor R1 and an LDO output voltage LDO_OUT, and a substrate terminal is connected to a substrate potential V_bulk;

[0013] The feedback resistor is composed of resistors R1 to R4 connected in series, and the lower end of the resistor R4 is grounded; the feedback voltage VFB is connected between the resistor R1 and the resistor R2, and the feedback network voltage divider VFL+ and VFL- are respectively connected between the resistor R2 and the resistor R3 and between the resistor R3 and the resistor R4;

[0014] The overshoot detection circuit includes inverters INV1~INV3, a trigger D, an AND gate AND, an OR gate OR1, a NOR gate NOR1, delay units T3~T6 and an edge detection circuit; the input ends of the inverter INV1 and the inverter INV2 are respectively connected to the feedback network voltage divider VFL+ and VFL-, and the inverter INV1 and the inverter INV2 output logic signals YN1 and YN2 respectively; the two input ends of the AND gate AND are respectively connected to the logic signal YN1 and the logic signal YN2, and the output end of the AND gate AND outputs the logic signal V_bulk_UNDERSHOOT and is connected to the input end 1 of the OR gate OR1 and the input end 2 of the delay unit T3. The input end and the input end one of the edge detection circuit, the output end of the delay unit T3 is connected to the input end of the delay unit T4, the output end of the NOR gate NOR1 outputs the logic signal V_bulk_OVERSHOOT, and is connected to the input end two of the OR gate OR1, the input end of the delay unit T5 and the input end two of the edge detection circuit, the output end of the delay unit T5 is connected to the input end of the delay unit T6, the two input ends of the NOR gate NOR1 are respectively connected to the logic signal YN1 and the logic signal YN2, the output end of the OR gate OR1 is connected to the CP end of the trigger D, the D end of the trigger D is connected to the power supply potential VDD, and the Q end of the trigger D is connected to the input end of the inverter INV3;

[0015] A substrate switching circuit comprises switches S1-S7, current sources I1-I2 and capacitors C1-C2; one end of the switch S1 is connected to a power supply potential VDD, and the other end is connected to one end of the current source I1, the other end of the current source I1 is connected to one end of the capacitor C1 and one end of the switch S2, the other end of the switch S2 is connected to one end of switches S3, S4, S6 and S7 and a substrate potential V_bulk, the other end of the switch S3 is connected to the other end of the capacitor C1 and the power supply potential VDD-, the other end of the switch S4 is connected to the power supply potential VDD, the other end of the switch S6 is connected to one end of the current source I2 and one end of the capacitor C2, the other end of the current source I2 is connected to one end of the switch S5, the other end of the switch S5 is connected to the power supply potential VDD, and the other end of the capacitor C2 is connected to the power supply potential VDD+ and the other end of the switch S7;

[0016] Among them, the output ends of the delay unit T4 and the delay unit T3 are respectively used to control the opening and closing of the switch S1 and the switch S2, the two output ends of the edge detection circuit are respectively used to control the opening and closing of the switch S3 and the switch S7, the output end of the inverter INV3 is used to control the opening and closing of the switch S4, and the output ends of the delay unit T6 and the delay unit T5 are respectively used to control the opening and closing of the switch S5 and the switch S6.

[0017] Preferably, the edge detection circuit includes: inverters INV4~INV5, delay units T1~T2 and NOR gates NOR2~NOR3; the input end of the inverter INV4 and the delay unit T1 is the input end one of the edge detection circuit, the output end of the inverter INV4 and the delay unit T1 is respectively connected to the two input ends of the NOR gate NOR2, and the output end of the NOR gate NOR2 is the output end one of the edge detection circuit; the input end of the inverter INV5 and the delay unit T2 is the input end two of the edge detection circuit, the output end of the inverter INV5 and the delay unit T2 is respectively connected to the two input ends of the NOR gate NOR3, and the output end of the NOR gate NOR3 is the output end two of the edge detection circuit.

[0018] Preferably, the inverters INV1 - INV5 are all digital inverters.

[0019] Preferably, the inverter INV1 and the inverter INV2 have the same structure and the same flip point VFL, wherein the feedback network divided voltage VFL+ is higher than the voltage of the flip point VFL, and the feedback network divided voltage VFL- is lower than the voltage of the flip point VFL.

[0020] Preferably, the power supply potential VDD+ is higher than the power supply potential VDD, and the power supply potential VDD- is lower than the power supply potential VDD.

[0021] Preferably, it also includes: when the circuit is in a normal state, the inverter INV1 outputs a logic signal YN1 of 1 and an output logic signal YN2 of 0, and at this time, the AND gate AND and the NOR gate NOR1 are controlled to output a logic signal V_bulk_OVERSHOOT and a logic signal V_bulk_UNDERSHOOT of 0, and the OR gate OR1 is used as the input of the trigger D1, and finally outputs 1 through the inverter INV3, and the control switch S4 is closed, and at this time the substrate potential V_bulk is connected to the power supply potential VDD.

[0022] Preferably, the method further includes: when an LDO instantaneous overshoot occurs in the circuit, the feedback network voltage VFL- instantly rises and exceeds the flip point VFL of the inverter INV2, and the inverter INV2 outputs a logic signal YN2 that flips to 0. Since the feedback network voltage VFL+ is greater than the feedback network voltage VFL, the logic signal YN1 is 0. At this time, the NOR gate NOR1 outputs a logic signal V_bulk_OVERSHOOT of 1, and the AND gate AND outputs a logic signal V_bulk_UNDERSHOOT of 0. The inverter INV3 outputs 0, and the control switch S4 is turned on. The logic signal V_bulk_OVERSHOOT controls the switch S7 through the edge detection circuit. First, at the instant of the overshoot, the switch S7 is closed to connect the substrate potential V_bulk to the power supply potential VDD+, and then the switches S6 and S5 are closed. Through the delayed discharge of the capacitor C2, the substrate potential V_bulk is gradually restored to the power supply potential VDD.

[0023] Preferably, the method further includes: when an LDO instantaneous undershoot occurs in the circuit, the feedback network voltage VFL+ is instantaneously reduced and is lower than the flip point VFL of the inverter INV1, and the inverter INV1 outputs a logic signal YN1 which is flipped to 1. Since the feedback network voltage VFL- is less than the flip point VFL, the logic signal YN2 is 1. At this time, the NOR gate NOR1 outputs a logic signal V_bulk_OVERSHOOT which is 0, and the AND gate AND outputs a logic signal V_bulk_UNDERSHOOT which is 1. The logic signal V_bulk_UNDERSHOOT controls the switch S3 through the edge detection circuit. First, at the moment of the undershoot, the switch S3 is closed to connect the substrate potential V_bulk to the power supply potential VDD-. Subsequently, the switches S2 and S1 are closed, and the substrate potential V_bulk is gradually restored to the power supply potential VDD through the delayed charging of the capacitor C1.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The present invention realizes the suppression of instantaneous overshoot by dynamically switching the substrate of the power tube. Compared with the traditional LDO overshoot improvement circuit, it can achieve almost the same improvement effect, and does not require additional auxiliary circuits, reduces the occupied area, and has a simple circuit design. The potential of the power tube substrate is quickly reduced or increased when the overshoot occurs, and is restored to the original potential through slow charging or slow discharging, so as to achieve the instantaneous suppression of the LDO voltage overshoot, and since the substrate is slowly restored, it will not affect the change of the LDO output voltage, so as to ensure the stability of the LDO system. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The main structural circuit diagram of the existing LDO transient response improvement circuit is shown in FIG.

[0027] Figure 2 The present invention is a circuit diagram of a circuit for driving tube substrate switching to improve LDO overshoot.

[0028] Figure 3 FIG. 4 is a circuit diagram of a substrate switching circuit of the present invention.

[0029] Figure 4 This is a diagram showing the gate circuit and digital switch signal changes of the present invention.

[0030] Figure 5 This is a waveform diagram of the substrate switching process of the present invention.

[0031] Figure 6 This is a waveform comparison diagram before and after the improvement of the present invention. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0033] like Figure 2 and Figure 3 As shown, an embodiment of the present invention provides a circuit for driving tube substrate switching to improve LDO overshoot, including:

[0034] An error amplifier EA, wherein the positive input terminal of the error amplifier EA is connected to the feedback voltage VFB, the negative input terminal is connected to the reference voltage VREF, and the output terminal is connected to the gate terminal of the power tube P1;

[0035] A power tube P1, wherein a source terminal of the power tube P1 is connected to a power supply potential VDD, a drain terminal is connected to an upper end of a resistor R1 and an LDO output voltage LDO_OUT, and a substrate terminal is connected to a substrate potential V_bulk;

[0036] The feedback resistor is composed of resistors R1 to R4 connected in series, and the lower end of the resistor R4 is grounded; the feedback voltage VFB is connected between the resistor R1 and the resistor R2, and the feedback network voltage divider VFL+ and VFL- are respectively connected between the resistor R2 and the resistor R3 and between the resistor R3 and the resistor R4;

[0037] The overshoot detection circuit includes inverters INV1~INV3, a trigger D, an AND gate AND, an OR gate OR1, a NOR gate NOR1, delay units T3~T6 and an edge detection circuit; the input ends of the inverter INV1 and the inverter INV2 are respectively connected to the feedback network voltage divider VFL+ and VFL-, and the inverter INV1 and the inverter INV2 output logic signals YN1 and YN2 respectively; the two input ends of the AND gate AND are respectively connected to the logic signal YN1 and the logic signal YN2, and the output end of the AND gate AND outputs the logic signal V_bulk_UNDERSHOOT and is connected to the input end 1 of the OR gate OR1 and the input end 2 of the delay unit T3. The input end and the input end one of the edge detection circuit, the output end of the delay unit T3 is connected to the input end of the delay unit T4, the output end of the NOR gate NOR1 outputs the logic signal V_bulk_OVERSHOOT, and is connected to the input end two of the OR gate OR1, the input end of the delay unit T5 and the input end two of the edge detection circuit, the output end of the delay unit T5 is connected to the input end of the delay unit T6, the two input ends of the NOR gate NOR1 are respectively connected to the logic signal YN1 and the logic signal YN2, the output end of the OR gate OR1 is connected to the CP end of the trigger D, the D end of the trigger D is connected to the power supply potential VDD, and the Q end of the trigger D is connected to the input end of the inverter INV3;

[0038] A substrate switching circuit comprises switches S1-S7, current sources I1-I2 and capacitors C1-C2; one end of the switch S1 is connected to a power supply potential VDD, and the other end is connected to one end of the current source I1, the other end of the current source I1 is connected to one end of the capacitor C1 and one end of the switch S2, the other end of the switch S2 is connected to one end of switches S3, S4, S6 and S7 and a substrate potential V_bulk, the other end of the switch S3 is connected to the other end of the capacitor C1 and the power supply potential VDD-, the other end of the switch S4 is connected to the power supply potential VDD, the other end of the switch S6 is connected to one end of the current source I2 and one end of the capacitor C2, the other end of the current source I2 is connected to one end of the switch S5, the other end of the switch S5 is connected to the power supply potential VDD, and the other end of the capacitor C2 is connected to the power supply potential VDD+ and the other end of the switch S7;

[0039] Among them, the output ends of the delay unit T4 and the delay unit T3 are respectively used to control the opening and closing of the switch S1 and the switch S2, the two output ends of the edge detection circuit are respectively used to control the opening and closing of the switch S3 and the switch S7, the output end of the inverter INV3 is used to control the opening and closing of the switch S4, and the output ends of the delay unit T6 and the delay unit T5 are respectively used to control the opening and closing of the switch S5 and the switch S6.

[0040] The edge detection circuit includes: inverters INV4~INV5, delay units T1~T2 and NOR gates NOR2~NOR3; the input end of the inverter INV4 and the delay unit T1 is the input end one of the edge detection circuit, the output end of the inverter INV4 and the delay unit T1 is respectively connected to the two input ends of the NOR gate NOR2, and the output end of the NOR gate NOR2 is the output end one of the edge detection circuit; the input end of the inverter INV5 and the delay unit T2 is the input end two of the edge detection circuit, the output end of the inverter INV5 and the delay unit T2 is respectively connected to the two input ends of the NOR gate NOR3, and the output end of the NOR gate NOR3 is the output end two of the edge detection circuit.

[0041] Inverters INV1~INV5 are all digital inverters. Digital inverters are used to detect the output voltage, which has fast detection speed, simple design and low power consumption.

[0042] The inverter INV1 and the inverter INV2 have the same structure and the same flip point VFL, wherein the feedback network divided voltage VFL+ is higher than the voltage of the flip point VFL, and the feedback network divided voltage VFL- is lower than the voltage of the flip point VFL.

[0043] The power supply potential VDD+ is higher than the power supply potential VDD, and the power supply potential VDD- is lower than the power supply potential VDD.

[0044] like Figure 2 and Figure 3 As shown, first, for the power tube P1, its substrate potential is improved from a fixed high potential VDD to a dynamically changing V_bulk potential, and the LDO output voltage is suppressed by dynamically controlling the change of its substrate voltage. The overshoot detection circuit is different from the traditional circuit structure. The detection of LDO output overshoot is realized by inverter INV1 and inverter INV2. The two inverters are exactly the same inverters with the same flip point VFL, where VFL+ is a voltage higher than the inverter flip point of the feedback network voltage divider, and similarly, VFL- is a voltage lower than the inverter flip point of the feedback network voltage divider. The substrate switching circuit is composed of a switch, a current source and a capacitor, and is controlled by the overshoot detection circuit to realize dynamic switching of the substrate.

[0045] like Figure 3The figure shows a substrate switching circuit. Different from the common substrate switching circuit, this circuit switches the substrate potential from VDD to VDD- and VDD by instantaneously closing switches S3 and S7. When the substrate potential is restored from VDD- and VDD+ to VDD, the potential is slowly restored by slow discharge or charging of the capacitor. When the substrate potential is restored from VDD- to VDD, the digital logic first controls the switch S2 to close, and then the switch S1 is closed after a short delay, so that the upper plate of the capacitor is VDD and the lower plate is VDD-. After the charging delay, the substrate potential is restored from VDD- to VDD. Similarly, when the substrate potential is restored from VDD+ to VDD, the digital logic first controls the switch S6 to close, and then the switch S5 is closed after a short delay, so that the upper plate of the capacitor is VDD and the lower plate is VDD+. After the discharge delay, the substrate potential is restored from VDD+ to VDD.

[0046] The switch controls the potential change during the whole process. Figure 4 As shown, when the circuit is in a normal state, the inverter INV1 outputs a logic signal YN1 of 1 and an output logic signal YN2 of 0. At this time, the AND gate AND and the NOR gate NOR1 are controlled to output a logic signal V_bulk_OVERSHOOT and a logic signal V_bulk_UNDERSHOOT of 0, which are used as the input of the trigger D1 through the OR gate OR1 and finally output 1 through the inverter INV3, and the control switch S4 is closed. At this time, the substrate potential V_bulk is connected to the power supply potential VDD.

[0047] When the circuit has an LDO instantaneous overshoot, the feedback network voltage VFL- rises instantaneously and exceeds the flip point VFL of the inverter INV2. The inverter INV2 outputs the logic signal YN2 which flips to 0. Since the feedback network voltage VFL+ is greater than the feedback network voltage VFL, the logic signal YN1 is 0. At this time, the NOR gate NOR1 outputs the logic signal V_bulk_OVERSHOOT which is 1, and the AND gate AND outputs the logic signal V_bulk_UNDERSHOOT which is 0. The inverter INV3 outputs 0, and the control switch S4 is turned on. The logic signal V_bulk_OVERSHOOT controls the switch S7 through the edge detection circuit. First, at the moment of the overshoot, the switch S7 is closed to connect the substrate potential V_bulk to the power supply potential VDD+ (higher than the VDD potential). Then, the switches S6 and S5 are closed. Through the delayed discharge of the capacitor C2, the substrate potential V_bulk is gradually restored to the power supply potential VDD.

[0048] Similarly, when the LDO undershoot occurs in the circuit, the feedback network voltage VFL+ decreases instantaneously and is lower than the flip point VFL of the inverter INV1. The inverter INV1 outputs the logic signal YN1 which flips to 1. Since the feedback network voltage VFL- is less than the flip point VFL, the logic signal YN2 is 1. At this time, the NOR gate NOR1 outputs the logic signal V_bulk_OVERSHOOT which is 0, and the AND gate AND outputs the logic signal V_bulk_UNDERSHOOT which is 1. The logic signal V_bulk_UNDERSHOOT controls the switch S3 through the edge detection circuit. First, at the undershoot moment, the switch S3 is closed to connect the substrate potential V_bulk to the power supply potential VDD- (lower than VDD). Then, the switches S2 and S1 are closed. Through the delayed charging of the capacitor C1, the substrate potential V_bulk is gradually restored to the power supply potential VDD.

[0049] When the LDO output overshoots or undershoots, the substrate potential changes as follows Figure 5 As shown: It is assumed that the LDO load current changes instantaneously at time t1. At this time, the circuit detects the instantaneous overshoot of the LDO and instantly increases or decreases the V_bulk potential to V_bulk+ or V_bulk-. This process is used to instantly suppress the output overshoot voltage of the LDO and restore it to the original substrate potential VDD at time t2 through the charge and discharge circuit (taking the driving power tube P1 as an example). The entire process greatly suppresses the instantaneous overshoot of the LDO at time t1. From t1 to t2, due to the slow recovery of the substrate potential, the LDO output voltage remains smooth. The entire LDO recovery time occurs from t1 to (t1+Δt). From (t1+Δt) to t2, the substrate gradually recovers and the LDO output voltage remains unchanged. Δt is a very small time interval.

[0050] The suppression of LDO instantaneous overshoot is achieved by instantaneously switching the substrate potential as follows Figure 6 As shown: When the load current changes instantaneously Figure 6 In (a), the instantaneous overshoot of the LDO output voltage at t1 and t2 is reflected: due to the instantaneous switching of the substrate, the instantaneous change of the power tube current is used to adjust the load current, so that the LDO does not need to adjust through the negative feedback mechanism. Therefore, the adjustment time Δt is greatly reduced, and the corresponding impact of the LDO overshoot is as follows (1):

[0051] (1)

[0052] Where ΔI L is the load current change, C L is the load capacitance, which is the fixed value of the design target. By improving the Δt recovery time, the LDO overshoot voltage V SHOOT of a substantial reduction.

[0053] By comparing the LDO overshoot improvement without substrate switching, Figure 6 Middle (b): When the typical LDO outputs 1.5V, the load current changes instantly from 100uA to 100mA. The overshoot voltage is about 350mV and the undershoot voltage is about 350mV. At this time, the surge voltage is too high and there is a risk of abnormal function of the powered circuit. Using substrate switching to improve LDO overshoot Figure 6 Middle (c): After improvement, the overshoot voltage is about 200mV and the undershoot voltage is about 150mV. Using the power tube substrate switching method improves the overshoot voltage by about 150mV and the undershoot by about 200mV. Compared with the traditional LDO overshoot suppression circuit, the improvement effect is roughly the same.

[0054] In summary, the present invention suppresses output overshoot by dynamically changing the substrate potential of the power tube, wherein the substrate potential is quickly switched by a digital detection circuit, and then slowly charged or discharged to restore to the original substrate potential to achieve smooth recovery of the LDO output voltage, thereby ensuring that there will be no large amount of back gate leakage. Specifically: the detection circuit detects the overshoot voltage of the LDO output voltage, and controls the substrate of the power tube through digital logic to perform instantaneous switching and delayed recovery, thereby effectively improving the instantaneous impact voltage of the LDO and ensuring the stability of the system during load switching; the auxiliary circuit for improving the LDO overshoot does not introduce a large amount of additional power consumption, reducing the overall power consumption of the circuit; the method for improving the LDO overshoot directly affects the power tube through the digital gate circuit, which is faster and has a more obvious improvement effect than the analog slew rate enhancement circuit, and saves a lot of chip area compared to the traditional analog LDO overshoot improvement circuit.

[0055] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A circuit for improving LDO overshoot by switching the substrate of a driving tube, characterized in that: include: An error amplifier EA, wherein the positive input terminal of the error amplifier EA is connected to the feedback voltage VFB, the negative input terminal is connected to the reference voltage VREF, and the output terminal is connected to the gate terminal of the power tube P1; A power tube P1, wherein a source terminal of the power tube P1 is connected to a power supply potential VDD, a drain terminal is connected to an upper end of a resistor R1 and an LDO output voltage LDO_OUT, and a substrate terminal is connected to a substrate potential V_bulk; The feedback resistor is composed of resistors R1 to R4 connected in series, and the lower end of the resistor R4 is grounded; the feedback voltage VFB is connected between the resistor R1 and the resistor R2, and the feedback network voltage divider VFL+ and VFL- are respectively connected between the resistor R2 and the resistor R3 and between the resistor R3 and the resistor R4; The overshoot detection circuit includes inverters INV1~INV3, a trigger D, an AND gate AND, an OR gate OR1, a NOR gate NOR1, delay units T3~T6 and an edge detection circuit; the input ends of the inverter INV1 and the inverter INV2 are respectively connected to the feedback network voltage divider VFL+ and VFL-, and the inverter INV1 and the inverter INV2 output logic signals YN1 and YN2 respectively; the two input ends of the AND gate AND are respectively connected to the logic signal YN1 and the logic signal YN2, and the output end of the AND gate AND outputs the logic signal V_bulk_UNDERSHOOT and is connected to the input end 1 of the OR gate OR1 and the input end 2 of the delay unit T3. The input end and the input end one of the edge detection circuit, the output end of the delay unit T3 is connected to the input end of the delay unit T4, the output end of the NOR gate NOR1 outputs the logic signal V_bulk_OVERSHOOT, and is connected to the input end two of the OR gate OR1, the input end of the delay unit T5 and the input end two of the edge detection circuit, the output end of the delay unit T5 is connected to the input end of the delay unit T6, the two input ends of the NOR gate NOR1 are respectively connected to the logic signal YN1 and the logic signal YN2, the output end of the OR gate OR1 is connected to the CP end of the trigger D, the D end of the trigger D is connected to the power supply potential VDD, and the Q end of the trigger D is connected to the input end of the inverter INV3; A substrate switching circuit comprises switches S1-S7, current sources I1-I2 and capacitors C1-C2; one end of the switch S1 is connected to a power supply potential VDD, and the other end is connected to one end of the current source I1, the other end of the current source I1 is connected to one end of the capacitor C1 and one end of the switch S2, the other end of the switch S2 is connected to one end of switches S3, S4, S6 and S7 and a substrate potential V_bulk, the other end of the switch S3 is connected to the other end of the capacitor C1 and the power supply potential VDD-, the other end of the switch S4 is connected to the power supply potential VDD, the other end of the switch S6 is connected to one end of the current source I2 and one end of the capacitor C2, the other end of the current source I2 is connected to one end of the switch S5, the other end of the switch S5 is connected to the power supply potential VDD, and the other end of the capacitor C2 is connected to the power supply potential VDD+ and the other end of the switch S7; Among them, the output ends of the delay unit T4 and the delay unit T3 are respectively used to control the opening and closing of the switch S1 and the switch S2, the two output ends of the edge detection circuit are respectively used to control the opening and closing of the switch S3 and the switch S7, the output end of the inverter INV3 is used to control the opening and closing of the switch S4, and the output ends of the delay unit T6 and the delay unit T5 are respectively used to control the opening and closing of the switch S5 and the switch S6; the substrate of the power tube is controlled by digital logic to perform instantaneous switching and delayed recovery.

2. A circuit for improving LDO overshoot by switching the substrate of a driving tube as claimed in claim 1, characterized in that: The edge detection circuit includes: inverters INV4~INV5, delay units T1~T2 and NOR gates NOR2~NOR3; the input end of the inverter INV4 and the delay unit T1 is the input end one of the edge detection circuit, the output end of the inverter INV4 and the delay unit T1 is respectively connected to the two input ends of the NOR gate NOR2, and the output end of the NOR gate NOR2 is the output end one of the edge detection circuit; the input end of the inverter INV5 and the delay unit T2 is the input end two of the edge detection circuit, the output end of the inverter INV5 and the delay unit T2 is respectively connected to the two input ends of the NOR gate NOR3, and the output end of the NOR gate NOR3 is the output end two of the edge detection circuit.

3. A circuit for improving LDO overshoot by switching the substrate of a driving tube as claimed in claim 1, characterized in that: Inverters INV1~INV5 are all digital inverters.

4. A circuit for improving LDO overshoot by switching the substrate of a driving tube as claimed in claim 1, characterized in that: The inverter INV1 and the inverter INV2 have the same structure and the same flip point VFL, wherein the feedback network divided voltage VFL+ is higher than the voltage of the flip point VFL, and the feedback network divided voltage VFL- is lower than the voltage of the flip point VFL.

5. A circuit for improving LDO overshoot by switching the substrate of a driving tube as claimed in claim 1, characterized in that: The power supply potential VDD+ is higher than the power supply potential VDD, and the power supply potential VDD- is lower than the power supply potential VDD.

6. A circuit for improving LDO overshoot by switching the substrate of a driving tube as claimed in claim 1, characterized in that: Also includes: When the circuit is in a normal state, the inverter INV1 outputs a logic signal YN1 of 1 and an output logic signal YN2 of 0. At this time, the AND gate AND and the NOR gate NOR1 are controlled to output a logic signal V_bulk_OVERSHOOT and a logic signal V_bulk_UNDERSHOOT of 0. The OR gate OR1 is used as the input of the trigger D1, and finally outputs 1 through the inverter INV3, and the control switch S4 is closed. At this time, the substrate potential V_bulk is connected to the power supply potential VDD.

7. A circuit for improving LDO overshoot by switching the substrate of a driving tube as claimed in claim 6, characterized in that: Also includes: When the circuit has an LDO instantaneous overshoot, the feedback network voltage VFL- rises instantaneously and exceeds the flip point VFL of the inverter INV2. The inverter INV2 outputs the logic signal YN2 which flips to 0. Since the feedback network voltage VFL+ is greater than the feedback network voltage VFL, the logic signal YN1 is 0. At this time, the NOR gate NOR1 outputs the logic signal V_bulk_OVERSHOOT which is 1, and the AND gate AND outputs the logic signal V_bulk_UNDERSHOOT which is 0. The inverter INV3 outputs 0, and the control switch S4 is turned on. The logic signal V_bulk_OVERSHOOT controls the switch S7 through the edge detection circuit. First, at the moment of the overshoot, the switch S7 is closed to connect the substrate potential V_bulk to the power supply potential VDD+. Then, the switches S6 and S5 are closed. Through the delayed discharge of the capacitor C2, the substrate potential V_bulk is gradually restored to the power supply potential VDD.

8. A circuit for improving LDO overshoot by switching the substrate of a driving tube as claimed in claim 7, characterized in that: Also includes: When the LDO undershoot occurs in the circuit, the feedback network voltage VFL+ decreases instantaneously and is lower than the flip point VFL of the inverter INV1. The inverter INV1 outputs the logic signal YN1 which flips to 1. Since the feedback network voltage VFL- is less than the flip point VFL, the logic signal YN2 is 1. At this time, the NOR gate NOR1 outputs the logic signal V_bulk_OVERSHOOT which is 0, and the AND gate AND outputs the logic signal V_bulk_UNDERSHOOT which is 1. The logic signal V_bulk_UNDERSHOOT controls the switch S3 through the edge detection circuit. First, at the undershoot moment, the switch S3 is closed to connect the substrate potential V_bulk to the power supply potential VDD-. Then, the switches S2 and S1 are closed. Through the delayed charging of the capacitor C1, the substrate potential V_bulk is gradually restored to the power supply potential VDD.

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