Dark current eliminating circuit
By designing the combination of dynamic comparators, narrow pulse circuit and charge pump circuit in the read -out circuit of infrared devices, the rapid and accurate removal of dark currents are realized, and the problem of poor dark current elimination effect in existing technologies has been solved. , To improve the quality and dynamic range of the signal.
Patent Information
- Application Number
- CN202411193053.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-28
- Publication Date
- 2025-01-21
AI Technical Summary
There are large and non-uniform dark currents in infrared devices, which affect the signal read quality and reduce the dynamic range. It is difficult for the prior art to achieve accurate dark current removal.
A dark current removal circuit is designed. The circuit of the dynamic comparator and narrow pulse, combined with the charge pump circuit to achieve the copy and elimination of dark current, and have adaptive regulation functions.
The rapid and accurate removal of dark currents have been achieved, reaching the effect of 100PA level, which improves the quality and dynamic range of signal reading out, and has adaptive regulatory functions.
Smart Images
Figure CN119341543A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of readout circuits, and in particular to a dark current rejection circuit. Background Art
[0002] In optoelectronic devices, dark current is mainly caused by factors such as impurity ions, reverse leakage barriers, intrinsic defects and grain boundaries in the device. For infrared devices, especially medium and long-wave infrared devices, there is a large and highly non-uniform dark current. When reading out the signal, it is very easy for the signal of each element to be high or low or some signals are difficult to read, which significantly reduces the dynamic range of the infrared imaging system. The dark current signal is an important factor affecting the imaging quality of the image sensor. To improve the pixel imaging quality, the dark current must be weakened or eliminated. The dark current is temperature-dependent and voltage-dependent, but in the case of short-term use, it is considered to have no time dependence and its mean value is considered to change little over time.
[0003] There are currently three main methods for reducing dark current: the first is to improve the manufacturing process and structure of optoelectronic materials from the front end of pixel detection, reduce the absolute value of dark current of pixels, and improve the uniformity of dark current of pixel arrays, but methods of improving processes or adopting new device structures are usually more complicated and have long iteration cycles; the second is to use image processing methods to reduce the impact of dark current on image quality in the image processing stage. This is the focus of most dark current processing work, but because the data is subjected to dark current denoising externally, the dark current calculated after readout in the readout circuit is still relatively large; the third is to perform dark current rejection on the readout circuit. The methods that have been reported are: ① Add a row (or column) of black-shielded pixels next to the array to only detect dark current, which plays a role in precise correction. This method requires accurate shielding of the black-shielded pixels at the device end, has high process requirements, and cannot solve the uniformity problem. ② Add a bias current source to the input photocurrent input node to generate a replica current opposite to the dark current, thereby eliminating the dark current from the total input current. This method can independently eliminate the dark current in each pixel without improving the device. However, in order to accurately obtain the reverse replica of the dark current, the gate voltage of the bias current source MOS tube needs to be accurately controlled. When accurately replicating the dark current, the bias current source tube usually operates in the subthreshold region, and a small fluctuation in its gate voltage will cause a large fluctuation in the current, making it difficult to achieve precise control. Summary of the invention
[0004] The purpose of the present invention is to provide a dark current rejection circuit, which can copy and reject the dark current at the input end of the readout circuit, is suitable for the field of infrared readout circuits, and can quickly and accurately reject the dark current.
[0005] The purpose of the present invention can be achieved by the following technical solutions:
[0006] A dark current elimination circuit is used to copy and eliminate the dark current in a photodetector, comprising:
[0007] A dynamic comparator compares and judges the output result of CTIA in the readout circuit, wherein the reference voltage of the dynamic comparator is set to the reset level of CTIA, and when the output result of CTIA is greater than the reset level, the dynamic comparator outputs a high level to enable the narrow pulse generating circuit to apply the generated pulse to the discharge switch of the charge pump circuit, and when the output result of CTIA is less than the reset level, the dynamic comparator outputs a high level to enable the narrow pulse generating circuit to apply the generated pulse to the charge switch of the charge pump circuit;
[0008] A narrow pulse generating circuit, wherein a control signal of the narrow pulse generating circuit is generated according to the gate voltage of the first PMOS tube in the charge pump circuit, and when the clock rising edge of the dynamic comparator arrives, the narrow pulse generating circuit is controlled based on the control signal to generate a narrow pulse with adjustable width, which is applied to the charge pump charge and discharge switch of the charge pump circuit;
[0009] The charge pump circuit comprises a first PMOS tube for generating reverse replication of dark current and a charge pump charge and discharge switch connected to the gate of the first PMOS tube.
[0010] The narrow pulse generating circuit comprises a D latch and two cascaded inverters, wherein the output of the D latch is connected to the input of the first-stage inverter, the output of the first-stage inverter is connected to the input of the second-stage inverter, the output of the second-stage inverter is connected to the asynchronous reset end of the D latch, and the D input end of the D latch is grounded; the driving capability of the first-stage inverter is regulated by the control signal of the narrow pulse generating circuit, and a narrow pulse with adjustable width is output through the output end of the D latch; the node where the output of the first-stage inverter is connected to the input of the second-stage inverter is connected to a ground MOS tube capacitor.
[0011] The inverter is composed of a pull-up NMOS tube and a pull-down PMOS tube, wherein the gates of the pull-up NMOS tube and the pull-down PMOS tube are connected, the sources are connected, the drain of the PMOS tube is grounded, and the drain of the NMOS tube is connected to the driving current.
[0012] The driving capability of the first-stage inverter is regulated by a second PMOS tube, the gate of the second PMOS tube is connected to the control signal of the narrow pulse generating circuit, the source is connected to the drain of the NMOS tube pulled up by the inverter, and the channel current of the second PMOS tube is regulated.
[0013] The control signal of the narrow pulse generating circuit is generated by the gate voltage of the first PMOS tube through a source follower. The driving capability of the first-stage inverter is regulated by changing the control signal, and the speed at which the second PMOS tube charges the capacitor of the MOS tube to the ground is changed, thereby changing the time to reach the threshold of the second-stage inverter. The higher the control signal, the smaller the driving current of the first-stage inverter, the faster the speed of charging the capacitor of the MOS tube to the ground, the longer the time interval of the reverse phase of the second-stage inverter, and the wider the pulse width generated by the narrow pulse generating circuit.
[0014] The D latch has two reset input ports, both of which are global resets and are used for resetting at the beginning of dark current elimination and for resetting each time a pulse signal is generated.
[0015] The first PMOS tube operates in a subthreshold region.
[0016] The charge pump circuit includes a charging switch circuit, a discharging switch circuit, a first PMOS tube and a node capacitor, wherein the gate of the first PMOS tube is connected to one end of the node capacitor and the outputs of the charging switch circuit and the discharging switch circuit, and the other end of the node capacitor is grounded; when the gate voltage of the first PMOS tube is cyclically charged and discharged by the charging and discharging circuit to a certain stable level, the source-drain current of the first PMOS tube is the dark current.
[0017] The charging switch circuit controls the charging current through an NMOS tube. The smaller the gate voltage is, the larger the channel current is, and the larger the charging current is. The discharging switch circuit controls the discharging current through a PMOS tube. The larger the gate voltage is, the larger the channel current is, and the larger the discharging current is.
[0018] The node capacitance of the gate node of the first PMOS tube is composed of MOS tube parasitic capacitance, MIM capacitance and MOS tube capacitance.
[0019] Compared with the prior art, the present invention has the following beneficial effects:
[0020] In order to accurately obtain the gate voltage of the bias current source tube, the present invention designs a dynamic comparator and an automatic charging and discharging charge pump structure to achieve a dark current rejection effect of 100pA level. The circuit has an adaptive control function, which can adaptively control the speed of copying the dark current, thereby achieving a balance between the dark current replication accuracy and the rejection speed. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 It is a schematic diagram of the structure of the dark current rejection circuit of the present invention;
[0022] Figure 2 It is a schematic diagram of the structure of the narrow pulse generating circuit of the present invention;
[0023] Figure 3 It is a schematic diagram of the structure of the charge pump circuit of the present invention;
[0024] Figure 4 A schematic diagram of a process in which the gate voltage of M210 approaches a certain level during the dark current elimination process in an embodiment;
[0025] Figure 5 FIG. 1 is a schematic diagram of a process in which the CTIA input current approaches 0 during the dark current rejection process in an embodiment. DETAILED DESCRIPTION
[0026] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.
[0027] The present invention relates to a dark current rejection circuit, which is mainly used to reject the dark current of a photoelectric device in a pixel of a readout circuit of a photodetector. The circuit includes a dynamic comparator for judging the rejection result, a narrow pulse generating circuit, and a charge pump circuit including a PMOS tube for generating a reverse copy of the dark current. The present invention utilizes a charge pump and an adaptive charge and discharge time to achieve fast and accurate replication and rejection of the dark current, is suitable for photodetectors with large dark current, has the advantages of large dynamic range, adaptive rejection, etc., and provides a new way to reduce the dark current.
[0028] like Figure 1 As shown, the present invention adds a dark current rejection circuit to the standard CTIA type readout circuit, the standard CTIA type readout circuit includes a CTIA input stage, a CDS (correlated double sampling) sample-and-hold circuit and a SF (source follower) output stage, and the dark current rejection circuit includes:
[0029] A dynamic comparator compares and judges the output result of CTIA in the readout circuit, wherein the reference voltage of the dynamic comparator is set to the reset level of CTIA. When the output result of CTIA is greater than the reset level, the dynamic comparator outputs a high level to enable the narrow pulse generating circuit to apply the generated pulse to the discharge switch of the charge pump circuit. When the output result of CTIA is less than the reset level, the dynamic comparator outputs a high level to enable the narrow pulse generating circuit to apply the generated pulse to the charge switch of the charge pump circuit.
[0030] A narrow pulse generating circuit, wherein a control signal of the narrow pulse generating circuit is generated according to the gate voltage of the first PMOS tube M210 in the charge pump circuit, and when the clock rising edge of the dynamic comparator arrives, the narrow pulse generating circuit is controlled based on the control signal to generate a narrow pulse with adjustable width, which is applied to the charge pump charge and discharge switch of the charge pump circuit;
[0031] The charge pump circuit includes a first PMOS tube M210 for generating reverse replication of dark current and a charge pump charge and discharge switch connected to the gate of the first PMOS tube M210.
[0032] like Figure 2 As shown, the narrow pulse generating circuit includes a D latch and two sets of cascaded inverters, wherein the output of the D latch is connected to the input of the first-stage inverter (M12 & M13), the output of the first-stage inverter is connected to the input of the second-stage inverter (M15 & M16), the output of the second-stage inverter is connected to the asynchronous reset terminal of the D latch, and the D input terminal of the D latch is grounded. The driving capability of the first-stage inverter is regulated by the control signal of the narrow pulse generating circuit, and a narrow pulse with adjustable width is output through the output terminal of the D latch; the node where the output of the first-stage inverter is connected to the input of the second-stage inverter is connected to a ground MOS tube capacitor M14.
[0033] In this embodiment, the inverter is composed of a pull-up NMOS tube (M12 or M15) and a pull-down PMOS tube (M13 or M14), wherein the gates of the pull-up NMOS tube and the pull-down PMOS tube are connected, the sources are connected, the drain of the PMOS tube is grounded, and the drain of the NMOS tube is connected to the driving current.
[0034] The driving capability of the first-stage inverter is regulated by the second PMOS tube M11. The gate of the second PMOS tube M11 is connected to the control signal of the narrow pulse generating circuit, and the source is connected to the drain of the NMOS tube pulled up by the inverter to regulate the channel current of the second PMOS tube M11.
[0035] In this embodiment, the D latch has two reset input ports. The latch outputs a high level of the clock and latches a low level input. Both reset inputs are global resets, which are used for resetting at the beginning of dark current rejection and for resetting each time a pulse signal is generated.
[0036] By adding a MOS tube capacitor M14 to the output of the first-stage inverter (M12 & M13), the total capacitance of the output node of the first-stage inverter, i.e., the gate node of M14, is artificially increased, and the first-stage inverter drive current, i.e., the channel current of M11, is controlled by the control signal to control the output flip time of the first-stage inverter. After the rising edge of the clock arrives, the Q output changes from a high level to a low level, and the output of the first-stage inverter is slowly charged. After a certain period of time, the output of the first-stage inverter reaches the input threshold of the second-stage inverter (M15 & M16), and the output of the second-stage inverter flips, generating an RST signal. The RST signal resets Q to a high level through the asynchronous reset port RST of the latch. In this way, a pulse signal of a certain width is generated on Q. Changing CTRL can change the driving capability of the first-stage inverter, change the speed at which M11 charges M14, and change the slope of the inverter output ramp, thereby reaching the second-stage inversion threshold faster or slower. In the case of Figure 4 In the circuit, the higher the control signal CTRL is, the smaller the driving current of the first-stage inverter is, the slower the charging speed of the first-stage inverter is, the longer the time interval of the second-stage inverter flipping is, and the wider the pulse width generated by the narrow pulse generating circuit is.
[0037] In order to accurately replicate the dark current, M210 needs to work in the subthreshold region and its gate voltage needs to be accurately controlled. Therefore, this embodiment designs the following Figure 3 The charge pump circuit shown in FIG. The charge pump circuit includes a charging switch circuit, a discharging switch circuit, a first PMOS tube M210 and a node capacitor, wherein the gate of the first PMOS tube M210 is connected to one end of the node capacitor and the output of the charging switch circuit and the discharging switch circuit, and the other end of the node capacitor is grounded; the charging pulse and the discharging pulse respectively control the charging and discharging circuits of the charge pump. The control signal CTRL of the narrow pulse generating circuit is generated by the gate voltage of the first PMOS tube M210 through a source follower M27, and the control signal in turn controls the width of the charging and discharging narrow pulses, thereby realizing adaptive control of the entire charge pump system.
[0038] When only background dark current is input, reverse dark current is replicated by M210. When the channel current of M210 is of dark current magnitude, M210 operates in the subthreshold region, and its current changes exponentially with voltage. In order to accurately replicate the dark current, the gate voltage of M210 needs to be accurately obtained. Figure 3 As shown, at M210, according to the charge conservation formula, there is:
[0039]
[0040] V GThe total charge change of the gate node of M210 is divided by the total node capacitance, where the total charge change is equal to the charging current multiplied by the charging time minus the discharge current multiplied by the discharge time minus the leakage current multiplied by the leakage time, that is, I charge t charge -I discharge t discharge -I leak t leak The total node capacitance includes MIM capacitance, node MOS capacitance and parasitic capacitance. Precisely control V G That is, improve its resolution. This embodiment adopts the following methods to improve its resolution: ① Increase the node capacitance. The node capacitance is composed of MOS tube parasitic capacitance, MIM capacitance and MOS tube capacitance. When the area allows, MIM capacitance and MOS tube capacitance are used in parallel. ② Reduce the charge and discharge current and charge and discharge time. The charge and discharge current can be controlled by controlling the gate voltage of the current tube of the charge and discharge loop, and the charge and discharge time is controlled by a narrow pulse generating circuit.
[0041] Then, the overall dark current replication and elimination process is:
[0042] At the start-up stage, the charge pump is reset and the gate voltage of M210 is reset to 3.3V.
[0043] This embodiment assumes that the input photocurrent is 0, and only dark current is input at this time. The dark current input causes the CTIA feedback capacitor to integrate, generating an upward slope at the output node. The dynamic comparator reference voltage is set to the CTIA reset level, and the CTIA output slopes upward to generate a value higher than the reset level, and the comparator outputs a comparison result of 1. At the same time, as the dynamic comparator clock rising edge arrives, the narrow pulse generation circuit generates a pulse of a specific width according to the current gate voltage of M210, and applies this pulse to the discharge switch M23&M26 of the charge pump according to the comparator output result 1, causing the M210 gate voltage to release part of the charge. Since the M210 gate voltage is higher at the beginning, CTRL is higher, thereby generating a relatively wider pulse, and the number of discharged charges on the M210 gate is larger. As the cycle continues to advance, the discharge of the M210 gate slows down until the M210 source-drain current is greater than the dark current. At this time, the CTIA is reversely charged, the output node level is less than the reset level, and the comparison result 0 is output, resulting in a narrow pulse being applied to the charge switch M22&M25 of the charge pump. In addition, the charging switch circuit controls the charging current through an NMOS tube M21. The smaller the gate voltage of M21, the larger the channel current and the larger the charging current; the discharging switch circuit controls the discharging current through a PMOS tube M24. The larger the gate voltage of M24, the larger the channel current and the larger the discharging current.
[0044] This cycle continues until the gate voltage of M210 is continuously and finely charged and discharged to a certain level, at which point its source-drain current is close to the dark current and the input current of CTIA is approximately 0. Figure 4 It is the process that the gate voltage of M210 approaches a certain level during the dark current elimination process. Figure 5 As the gate voltage of M210 approaches a certain level and its source-drain current approaches the dark current, the input current of CTIA approaches 0. The simulation gives a dark current of 10nA, and after 40ms, the dark current drops to 10pA. The dynamic comparator period is 500us.
[0045] The present invention can not only replicate and eliminate dark current more accurately, but also has an adaptive control function within the pixel, and has excellent performance in both speed and accuracy.
[0046] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning, or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.
Claims
1. A dark current rejection circuit, characterized in that: Used to copy and remove the dark current in the photodetector. The dark current rejection circuit comprises: A dynamic comparator compares and judges the output result of CTIA in the readout circuit, wherein the reference voltage of the dynamic comparator is set to the reset level of CTIA, and when the output result of CTIA is greater than the reset level, a high level is output to enable the narrow pulse generating circuit, and the generated pulse is applied to the discharge switch of the charge pump circuit; when the output result of CTIA is less than the reset level, a high level is output to enable the narrow pulse generating circuit, and the generated pulse is applied to the charging switch of the charge pump circuit; A narrow pulse generating circuit, wherein a control signal of the narrow pulse generating circuit is generated according to the gate voltage of the first PMOS tube in the charge pump circuit, and when the clock rising edge of the dynamic comparator arrives, the narrow pulse generating circuit is controlled based on the control signal to generate a narrow pulse with adjustable width, which is applied to the charge pump charge and discharge switch of the charge pump circuit; The charge pump circuit comprises a first PMOS tube for generating reverse replication of dark current and a charge pump charge and discharge switch connected to the gate of the first PMOS tube.
2. A dark current elimination circuit according to claim 1, characterized in that: The narrow pulse generating circuit comprises a D latch and two cascaded inverters, wherein the output of the D latch is connected to the input of the first-stage inverter, the output of the first-stage inverter is connected to the input of the second-stage inverter, the output of the second-stage inverter is connected to the asynchronous reset end of the D latch, and the D input end of the D latch is grounded; the driving capability of the first-stage inverter is regulated by the control signal of the narrow pulse generating circuit, and a narrow pulse with adjustable width is output through the output end of the D latch; the node where the output of the first-stage inverter is connected to the input of the second-stage inverter is connected to a ground MOS tube capacitor.
3. A dark current elimination circuit according to claim 2, characterized in that: The inverter is composed of a pull-up NMOS tube and a pull-down PMOS tube, wherein the gates of the pull-up NMOS tube and the pull-down PMOS tube are connected, the sources are connected, the drain of the PMOS tube is grounded, and the drain of the NMOS tube is connected to the driving current.
4. A dark current elimination circuit according to claim 2, characterized in that: The driving capability of the first-stage inverter is regulated by a second PMOS tube, the gate of the second PMOS tube is connected to the control signal of the narrow pulse generating circuit, the source is connected to the drain of the NMOS tube pulled up by the inverter, and the channel current of the second PMOS tube is regulated.
5. A dark current elimination circuit according to claim 2, characterized in that: The control signal of the narrow pulse generating circuit is generated by the gate voltage of the first PMOS tube through a source follower. The driving capability of the first-stage inverter is regulated by changing the control signal, and the speed at which the second PMOS tube charges the capacitor of the MOS tube to the ground is changed, thereby changing the time to reach the threshold of the second-stage inverter. The higher the control signal, the smaller the driving current of the first-stage inverter, the faster the speed of charging the capacitor of the MOS tube to the ground, the longer the time interval of the reverse phase of the second-stage inverter, and the wider the pulse width generated by the narrow pulse generating circuit.
6. A dark current elimination circuit according to claim 2, characterized in that: The D latch has two reset input ports, both of which are global resets and are used for resetting at the beginning of dark current elimination and for resetting each time a pulse signal is generated.
7. The dark current elimination circuit according to claim 1, characterized in that: The first PMOS tube operates in a subthreshold region.
8. The dark current elimination circuit according to claim 1, characterized in that: The charge pump circuit includes a charging switch circuit, a discharging switch circuit, a first PMOS tube and a node capacitor, wherein the gate of the first PMOS tube is connected to one end of the node capacitor and the outputs of the charging switch circuit and the discharging switch circuit, and the other end of the node capacitor is grounded; when the gate voltage of the first PMOS tube is cyclically charged and discharged by the charging and discharging circuit to a certain stable level, the source-drain current of the first PMOS tube is the dark current.
9. A dark current elimination circuit according to claim 8, characterized in that: The charging switch circuit controls the charging current through an NMOS tube, and the smaller the gate voltage is, the larger the channel current is, and the larger the charging current is; The discharge switch circuit controls the discharge current through a PMOS tube. The larger the gate voltage is, the larger the channel current is, and the larger the discharge current is.
10. The dark current elimination circuit according to claim 8, characterized in that: The node capacitance of the gate node of the first PMOS tube is composed of MOS tube parasitic capacitance, MIM capacitance and MOS tube capacitance.