DLL Circuit

Abstract

The present invention discloses a DLL circuit. To reduce the static phase error, the DLL circuit of the present invention includes a phase detector, a filter and a delay line, and the DLL circuit also includes a pulse generator; the phase detector receives a reference clock and a second clock, and inputs the phase detection result to the filter, and the filter outputs a control code to the delay line; the pulse generator receives the reference clock, and when the pulse generator is enabled, generates an injection pulse and transmits it to the delay line; the delay line receives a first clock, and the output node of the delay line outputs a second clock; when the second clock is at a high level, the injection pulse is used to pull up the voltage of the output node of the delay line; or / and, when the second clock is at a low level, the injection pulse is used to pull down the voltage of the output node of the delay line. The present invention can eliminate the static phase error and improve the sampling margin of the sampling circuit. The present invention is suitable for the field of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a DLL circuit. Background Art

[0002] In communication systems, due to the influence of the propagation path, there will be a certain phase error between the data sampling clock and the system local clock. If this phase difference is not processed, data transmission may have bit errors, which will affect the quality of the system.

[0003] In order to reduce this phase error, a delay locked loop (DLL) circuit is usually introduced between the system local clock and the sampling clock to adjust the phase of the sampling clock in real time to align it with the system local clock. Although the DLL circuit can effectively reduce the phase error, due to the limited accuracy of the phase detector in the DLL circuit, even after the DLL circuit output clock is locked with the reference clock, there may still be a static phase difference between the system local clock and the sampling clock.

[0004] Figure 1 The architecture diagram of the digital DLL circuit in the prior art is shown. The DLL circuit adjusts the delay of the pha2 clock through a delay line to obtain an adjusted pha2' clock, so that the adjusted pha2' clock is finally aligned with the pha1 clock as the reference clock.

[0005] Figure 2 The schematic diagram of the static phase error in the DLL circuit in the prior art is shown. There is a static phase error between the rising pulse edge of pha1 and the rising pulse edge of pha2', which is a system error caused by the circuit itself.

[0006] In order to reduce the static phase error caused by the detection accuracy of the phase detector (PD), it is often necessary to design a high-precision phase detector to compensate for this error. However, this not only increases the complexity of circuit design and silicon cost, but also increases the corresponding power consumption.

[0007] In addition, in order to suppress the delay line delay variation caused by power supply ripple, the power supply module of the delay line needs to have a strong ripple suppression capability to reduce the impact of power supply noise on the phase imbalance of the DLL circuit. Summary of the invention

[0008] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0009] A DLL circuit comprises a phase detector, a filter and a delay line, wherein the DLL circuit further comprises a pulse generator; the phase detector receives a reference clock and a second clock, and inputs the phase detection result to the filter, and the filter outputs a control code to the delay line; the pulse generator receives the reference clock, and when the pulse generator is enabled, generates an injection pulse and transmits it to the delay line; the delay line receives a first clock, and an output node of the delay line outputs a second clock; and when the second clock is at a high level, the injection pulse is used to pull up the voltage of the output node of the delay line; or / and when the second clock is at a low level, the injection pulse is used to pull down the voltage of the output node of the delay line.

[0010] Furthermore, the pulse width of the injected pulse is lower than the pulse width of the reference clock.

[0011] Further, when the rising edge of the reference clock and the rising edge of the second clock appear, the injection pulses are both at a high level.

[0012] Further, after the control code is applied to the delay line, the injection pulse is applied to the delay line.

[0013] Furthermore, the filter also outputs an enabling signal for enabling the pulse generator.

[0014] Furthermore, the pulse generator receives a reference clock and generates the injection pulse according to the inverted reference clock.

[0015] Furthermore, the reference clock is derived from a system local clock.

[0016] Further, the delay line is a current starving inverter.

[0017] Furthermore, the filter is a digital filter.

[0018] Further, the enable signal is a periodic enable signal, or the enable signal is a signal that is always valid, or the enable signal is turned off or blocked after the static phase error is eliminated.

[0019] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0020] (1) Effectively reduce the static phase error of the DLL circuit.

[0021] (2) The present invention can be applied to a clock distribution network with low phase misalignment to provide a clock with low static phase error for a data sampling path.

[0022] (3) Improve the sampling margin of the sampling circuit, increase the eye width of the output data, and reduce the bit error rate.

[0023] (4) Suppress the delay line delay variation caused by power supply ripple.

[0024] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of a digital DLL circuit in the prior art;

[0026] Figure 2 It is a schematic diagram of the static phase error existing in the DLL circuit in the prior art;

[0027] Figure 3 is a schematic diagram of the DLL circuit of the present invention;

[0028] Figure 4 is a signal timing diagram of the present invention;

[0029] Figure 5 It is the signal timing diagram where the static phase error gradually disappears. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0032] Figure 3 The DLL circuit of the present invention is a schematic diagram. A DLL circuit includes a phase detector, a filter, a delay line and a pulse generator.

[0033] The phase detector receives the reference clock and the second clock as input signals. After the output signal of the phase detector is filtered by the filter, the control code is output to the delay line to control the delay length of the delay line to the input first clock and obtain the second clock.

[0034] Illustratively, the filter is a digital filter.

[0035] The reference clock may be derived from a system local clock. For example, the system local clock is transmitted through a signal line to obtain a reference clock.

[0036] In the present invention, the filter further outputs an enabling signal for enabling a pulse generator. The pulse generator receives a reference clock as an input signal and generates an injection pulse, which is applied to the delay line.

[0037] The injection pulse of the present invention is not always generated and applied to the delay line, but is generated only when necessary after the pulse generator is enabled by an enabling signal.

[0038] After the control code is applied to control the delay length of the delay line, an active high injection pulse is applied to the delay line.

[0039] The delay line in the present invention may be a current-starved inverter, wherein the second clock is pulled high by a P-channel Metal Oxide Semiconductor (PMOS) and the second clock is pulled low by an N-channel Metal Oxide Semiconductor (NMOS).

[0040] The delay line receives a first clock, and an output node of the delay line outputs a second clock; and when the second clock is at a high level, the injection pulse is used to pull up the voltage of the output node of the delay line; or / and, when the second clock is at a low level, the injection pulse is used to pull down the voltage of the output node of the delay line.

[0041] In the present invention, by injecting pulses into the delay line, additional charge is injected into the delay line to achieve a greater delay change. When the second clock is at a high level, the second clock output by the delay line is pulled up by the injected pulse; when the second clock is at a low level, the second clock output by the delay line is pulled down by the injected pulse.

[0042] Furthermore, by controlling the width of the injected pulse, a very small delay between the reference clock and the second clock can be achieved.

[0043] For example, when the phase detector detects that there is a large error between the second clock and the reference clock, the filter adjusts the delay of the delay line through the control code. Since the control code adjustment method cannot completely eliminate the static phase error, the filter can send an enable signal to the pulse generator at this time. The pulse generator injects additional charge into the delay line to eliminate the static phase error.

[0044] For example, if the static phase error is eliminated, the maintaining or sending of the enable signal may be turned off or stopped.

[0045] In one embodiment, the enable signal is turned off or blocked after the static phase error is eliminated.

[0046] Alternatively, the enable signal may be sent at regular intervals, that is, the enable signal has periodicity. Furthermore, the enable signal is a signal that is always valid and is always maintained in the background to ensure that the DLL circuit can maintain a minimum static phase error under non-ideal factors such as temperature, voltage and process.

[0047] In the present invention, the injection pulse can be generated by a reference clock. For example, the reference clock is inverted to obtain an inverted reference clock, and then the injection pulse is obtained after delay and pulse width adjustment.

[0048] Furthermore, the pulse width of the injected pulse is smaller than the pulse width of the reference clock.

[0049] Figure 4 The signal timing diagram of the present invention is shown. There is a static phase error between the reference clock and the second clock before the injection pulse, which is just as Figure 2 As shown.

[0050] After a certain time, the pulse generator starts to send an injection pulse to the delay line, and the pulse width (high level period) of the injection pulse covers the rising edge of the reference clock and the rising edge of the second clock before the injection pulse.

[0051] Further, when the rising edge of the reference clock and the rising edge of the second clock appear, the injection pulses are both at a high level.

[0052] By injecting pulses, the rising edge of the second clock output by the delay line in the present invention is substantially consistent with the rising edge of the reference clock, thereby substantially eliminating the static phase error.

[0053] Figure 5 Signal timing diagram showing the static phase error disappearing gradually. Figure 5 In , with the presence of the enable signal, an injection clock is generated and applied to the delay line.

[0054] Before the injection pulse is applied, there is a static phase error D2 between the reference clock and the second clock. After the injection pulse is applied, the static phase error gradually decreases to D1 until the static phase error D0 eventually approaches 0.

[0055] The present invention is applicable to scenarios requiring lower phase misalignment, such as double data rate synchronous dynamic random access memory (DDR SDRAM) and serializer / deserializer (SerDes) circuits.

[0056] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0057] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A DLL circuit, comprising a phase detector, a filter and a delay line, characterized in that: The DLL circuit also includes a pulse generator; The phase detector receives a reference clock and a second clock, and inputs a phase detection result to the filter, and the filter outputs a control code to the delay line; The pulse generator receives a reference clock and generates an injection pulse and transmits it to the delay line when the pulse generator is enabled; The delay line receives a first clock, and an output node of the delay line outputs a second clock; and when the second clock is at a high level, the injection pulse is used to pull up a voltage of the output node of the delay line; or / and when the second clock is at a low level, the injection pulse is used to pull down a voltage of the output node of the delay line; When the rising edge of the reference clock and the rising edge of the second clock appear, the injection pulses are both at a high level.

2. The DLL circuit according to claim 1, characterized in that: The pulse width of the injection pulse is lower than the pulse width of the reference clock.

3. The DLL circuit according to claim 2, characterized in that: The injection pulse is applied to the delay line after the control code is applied to the delay line.

4. The DLL circuit according to claim 3, characterized in that: The filter also outputs an enable signal for enabling the pulse generator.

5. The DLL circuit according to claim 4, characterized in that: The pulse generator receives a reference clock and generates the injection pulse according to the inverted reference clock.

6. The DLL circuit according to claim 5, characterized in that: The reference clock is derived from the system local clock.

7. The DLL circuit according to claim 6, characterized in that: The delay line is a current starving inverter.

8. The DLL circuit according to claim 7, characterized in that: The filter is a digital filter.

9. The DLL circuit according to claim 8, characterized in that: The enable signal is a periodic enable signal, or the enable signal is a signal that is always maintained valid, or the enable signal is turned off or blocked after the static phase error is eliminated.

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