Signal processing circuit and device

Abstract

The invention discloses a signal processing circuit and equipment. The circuit comprises a signal offset module, a first input end of the signal offset module is used for receiving an input signal, a second input end of the signal offset module is used for receiving an offset reference signal, and the signal offset module is used for superposing the offset reference signal on the input signal; the input end of the signal amplification module is connected with the output end of the signal offset module; the signal amplification module is used for performing gain amplification on the superposed input signal; the input end of the amplitude limiting module is connected with the output end of the signal amplification module, and the output end of the amplitude limiting module is used for outputting the adjusted input signal; the amplitude limiting module is used for limiting the signal amplitude of the gained input signal within an amplitude interval. According to the embodiment of the invention, the input signal can be adjusted to be matched with the acquisition interval, so that the normal acquisition of the input signal is realized.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a signal processing circuit and device. Background Art

[0002] At present, with the continuous development of semiconductor technology, various technologies involved in the design and manufacturing of integrated circuits have increasingly wider application space. Taking electron beam defect detection as an example, in electron beam defect detection equipment (EBI), after converting the electron beam signal or light signal into a voltage signal, the voltage signal can be converted into the final target image signal through ADC sampling.

[0003] After the detection unit generates a corresponding current signal based on the detected electron beam current, if the signal is directly output to the collection end, the signal voltage may be too large, too small, or other abnormal conditions may occur, causing the input signal to not match the collection interval of the collection end, resulting in the collection end being unable to normally collect the input signal.

[0004] In order to improve the accuracy of signal acquisition, the input signal needs to be processed to improve the signal quality. Therefore, it is necessary to propose a signal processing circuit to adjust and process the input signal to meet the actual acquisition requirements of the back end. Summary of the invention

[0005] The embodiments of the present application provide a signal processing circuit and device, which can improve the technical problem that the signal cannot be normally collected due to the mismatch between the input signal and the collection interval of the collection end.

[0006] In a first aspect, an embodiment of the present application provides a signal processing circuit, the signal processing circuit comprising:

[0007] A signal offset module, wherein a first input end of the signal offset module is used to receive an input signal, a second input end of the signal offset module is used to receive an offset reference signal, and the signal offset module is used to superimpose the offset reference signal on the input signal;

[0008] A signal amplification module, the input end of the signal amplification module is connected to the output end of the signal offset module; the signal amplification module is used to perform gain amplification on the superimposed input signal;

[0009] A limiting module, the input end of the limiting module is connected to the output end of the signal amplification module, and the output end of the limiting module is used to output the adjusted input signal; the limiting module is used to limit the signal amplitude of the input signal after gain within the amplitude range.

[0010] Optionally, the signal processing circuit further includes:

[0011] A reference voltage generating unit, the input end of the reference voltage generating unit is used to receive the offset control signal, the output end of the reference voltage generating unit is connected to the second input end of the signal offset module; the reference voltage generating unit is used to generate a corresponding offset reference signal according to the offset control signal.

[0012] Optionally, the signal offset module includes an analog subtractor, and the reference voltage generating unit includes a digital-to-analog converter.

[0013] Optionally, the signal amplification module includes:

[0014] A first operational amplifier, wherein two input terminals of the first operational amplifier are respectively connected to the output terminal of the signal offset module and the reference ground, and the output terminal of the first operational amplifier is connected to the input terminal of the amplitude limiting module;

[0015] A gain adjustment module is connected between one of the input terminals of the first operational amplifier and the output terminal of the first operational amplifier; the gain adjustment module is used to adjust the total resistance of the gain adjustment module according to the received gain control signal.

[0016] Optionally, the gain adjustment module includes at least two gain units, each gain unit is connected between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier;

[0017] The gain unit includes:

[0018] The gain resistor and the gain switch are connected in series, and the gain switch is used to be turned on or off according to a received gain control signal.

[0019] Optionally, the signal processing circuit further includes:

[0020] The first logic unit is connected to the control end of the gain switch; the first logic unit is used to send a gain control signal to the gain switch.

[0021] Optionally, the inverting input terminal of the first operational amplifier is connected to the output terminal of the signal offset module, and the gain adjustment module is connected between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; the signal amplification module further includes:

[0022] The inverting unit comprises a second operational amplifier, the inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, the non-inverting input terminal of the second operational amplifier is connected to the reference ground, and the output terminal of the second operational amplifier is connected to the input terminal of the limiting module.

[0023] Optionally, the signal processing circuit further includes:

[0024] A channel selection unit, wherein the first channel input terminal of the channel selection unit is connected to the output terminal of the signal amplification module, the second channel input terminal of the channel selection unit is connected to the reference ground, and the channel output terminal of the channel selection unit is connected to the input terminal of the limiting module; the channel selection unit is used to connect one of the first channel input terminal and the second channel input terminal to the channel output terminal.

[0025] Optionally, the limiting module includes:

[0026] A voltage follower, wherein the non-inverting input terminal of the voltage follower is connected to the channel selection unit, and the inverting input terminal of the voltage follower is connected to the output terminal of the voltage follower.

[0027] In a second aspect, an embodiment of the present application provides a signal processing device, and the signal processing device includes the signal processing circuit of the first aspect.

[0028] Compared with the prior art, the signal processing circuit and device provided in the embodiment of the present application can perform signal superposition, gain amplification and limit adjustment on the input signal in sequence by setting a signal offset module, a signal amplification module and a limiter module. By superimposing with the offset reference signal, the signal median of the input signal can be adjusted to match the acquisition interval of the back end. By gain amplifying the input signal, the signal amplitude of the input signal can be increased or reduced to a range that can be effectively collected. For the amplified input signal, the detection capability of the slight input signal change can be improved and the error and uncertainty introduced in the subsequent processing due to the small signal can be reduced. The signal quality can also be improved, and the accuracy of the back-end signal analysis and processing can be improved; for the reduced input signal, the signal can be prevented from exceeding the acquisition interval, so that the input signal can be correctly collected. The input signal after gain amplification is limited, which can prevent the signal exceeding the amplitude interval from flowing into the acquisition end, and play a protective role for the equipment at the acquisition end. The above signal processing process can adjust the input signal to match the acquisition interval of the acquisition end, thereby realizing the normal acquisition of the input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 is a schematic diagram of the module structure of a signal processing circuit provided in an embodiment of the present application;

[0031] Figure 2 is a schematic diagram of a module structure of a signal processing circuit provided in another embodiment of the present application;

[0032] Figure 3 is a circuit structure diagram of a signal processing circuit provided in an embodiment of the present application;

[0033] Figure 4 is a circuit structure diagram of a signal processing circuit provided in another embodiment of the present application;

[0034] Figure 5 is a circuit structure diagram of a signal processing circuit provided in yet another embodiment of the present application;

[0035] Figure 6 is a circuit structure diagram of a signal processing circuit provided in yet another embodiment of the present application;

[0036] Figure 7 is a circuit structure diagram of a signal processing circuit provided in yet another embodiment of the present application;

[0037] Figure 8 3 is a circuit structure diagram of a signal processing circuit provided in yet another embodiment of the present application.

[0038] In the attached figure:

[0039] 10. Signal offset module; 20. Signal amplification module; 30. Limiting module; 40. Reference voltage generating unit; 11. Analog subtractor; U1. First operational amplifier; 21. Gain adjustment module; 211. Gain unit; Rg. Gain resistor; Sg. Gain switch; 22. Inverting unit; 50. First logic unit; 60. Second logic unit; 70. Channel selection unit; IN. Input signal terminal; OUT. Output signal terminal. DETAILED DESCRIPTION

[0040] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0041] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The embodiments will be described in detail below in conjunction with the accompanying drawings.

[0043] At present, with the continuous development of semiconductor technology, various technologies involved in the design and manufacturing of integrated circuits have increasingly wider application space. Taking electron beam defect detection as an example, in electron beam defect detection equipment (EBI), after converting the electron beam signal or light signal into a voltage signal, the voltage signal can be converted into the final target image signal through ADC sampling.

[0044] After the detection unit generates a corresponding current signal based on the detected electron beam current, if the signal is directly output to the collection end, the signal voltage may be too large, too small, or other abnormal conditions may occur, causing the input signal to not match the collection interval of the collection end, resulting in the collection end being unable to normally collect the input signal.

[0045] In order to improve the accuracy of signal acquisition, the input signal needs to be processed to improve the signal quality. Therefore, it is necessary to propose a signal processing circuit to adjust and process the input signal to meet the actual acquisition requirements of the back end.

[0046] In order to solve the above technical problems, the embodiments of the present application provide a signal processing circuit and device. The signal processing circuit provided by the embodiments of the present application is first introduced below.

[0047] Figure 1 The structure diagram of a signal processing circuit provided by an embodiment of the present application is shown. The signal processing circuit comprises a signal offset module 10 , a signal amplification module 20 and a limiting module 30 .

[0048] The first input terminal of the signal offset module 10 can receive an input signal. For example, when the first input terminal of the signal offset module 10 is connected to an external detection unit, the detection unit can use the detected signal as an input signal and provide it to the signal offset module 10 through the input signal terminal IN. In addition, the first input terminal of the signal offset module 10 can also be connected to the input signal terminal IN of other devices or modules, and the signal output by other devices or modules can be used as the received input signal.

[0049] The second input end of the signal offset module 10 can receive an offset reference signal. When the two input ends of the signal offset module 10 receive the input signal and the offset reference signal respectively, the signal offset module 10 can superimpose the two signals and output them. That is, the signal offset module 10 can superimpose the offset reference signal on the input signal and output it as the superimposed input signal.

[0050] The input end of the signal amplification module 20 is connected to the output end of the signal shift module 10 . After receiving the superimposed input signal, the signal amplification module 20 may perform gain amplification on the superimposed input signal.

[0051] The input end of the limiting module 30 is connected to the output end of the signal amplification module 20. The limiting module 30 can limit the signal amplitude of the input signal after gain within the amplitude range. That is, the limiting module 30 can adjust the input signal after gain and output the adjusted input signal through the output signal terminal OUT. For example, it can be output to the acquisition end through the output signal terminal OUT. Compared with the input signal after gain, the signal voltage of the adjusted input signal higher than the amplitude range is limited to the upper limit of the range, and the signal voltage lower than the amplitude range is limited to the lower limit of the range.

[0052] In the above signal processing process, the input signal may be subjected to signal superposition, signal gain amplification and signal limiting in sequence.

[0053] It is understandable that the input signal is superimposed with the offset reference signal. When the offset reference signal is a DC stable voltage, the signal superposition process is equivalent to adjusting the signal median of the input signal. When the initial signal median of the input signal does not match the acquisition interval of the acquisition end, it is easy to affect the accuracy of signal acquisition and may also cause damage to the equipment at the acquisition end. Therefore, by offset adjusting the input signal, the signal median of the input signal can be matched with the acquisition interval of the acquisition end, thereby improving the accuracy of signal acquisition.

[0054] Similarly, the signal fluctuation amplitude of the input signal may not match the collection interval of the collection end. For example, the signal fluctuation amplitude of the input signal is small, and the collection interval of the collection end is large, so the signal change amplitude of the input signal cannot be accurately collected. Or the signal fluctuation amplitude of the input signal is large, exceeding the collection interval of the collection end, resulting in collection anomalies and even damage to the equipment at the collection end. Therefore, by amplifying the gain of the input signal, the signal fluctuation amplitude of the input signal can be adjusted to match the collection interval of the collection end, thereby improving the accuracy of signal collection.

[0055] After the input signal is amplified, the signal amplitude of the adjusted input signal can be limited within the amplitude range through the limiting module 30. For example, there may be high-frequency signals or interference signals exceeding the amplitude range in the input signal, and the limiting adjustment can prevent the signal exceeding the amplitude range from flowing into the acquisition end, thereby protecting the equipment at the acquisition end.

[0056] In this embodiment, by setting a signal offset module 10, a signal amplification module 20 and a limiting module 30, the input signal can be sequentially superimposed, gain amplified and limited. By superimposing with the offset reference signal, the signal median of the input signal can be adjusted to match the acquisition interval of the acquisition end of the back end. By gain amplifying the input signal, the signal amplitude of the input signal can be increased or reduced to a range that can be effectively collected. For the amplified input signal, the detection capability of the slight input signal change can be improved and the error and uncertainty introduced in the subsequent processing due to the small signal can be reduced. The signal quality can also be improved, and the accuracy of the back-end signal analysis and processing can be improved; for the reduced input signal, the signal can be prevented from exceeding the acquisition interval, so that the input signal can be correctly collected. The input signal after gain amplification is limited, which can prevent the signal exceeding the amplitude interval from flowing into the acquisition end, and play a protective role for the equipment of the acquisition end. The above signal processing process can adjust the input signal to match the acquisition interval of the acquisition end, thereby realizing the normal acquisition of the input signal.

[0057] Please refer to Figure 2 In some embodiments, the signal processing circuit may further include a reference voltage generating unit 40 .

[0058] The input terminal of the reference voltage generating unit 40 can receive the offset control signal, and the output terminal of the reference voltage generating unit 40 can be connected to the second input terminal of the signal offset module 10. The reference voltage generating unit 40 can generate a corresponding offset reference signal according to the received offset control signal.

[0059] The above-mentioned offset control signal can be generated by a control unit (not shown). The control unit can be an MCU (Microcontroller Unit), a SoC (System on Chip) or other types of processing modules. For example, the control unit can be connected to the reference voltage generating unit 40 via an SPI (Serial Peripheral Interface) to provide the offset control signal to the reference voltage generating unit 40.

[0060] Please refer to Figure 3 As an optional implementation, the signal offset module 10 may include an analog subtractor 11, and the reference voltage generating unit 40 may include a digital-to-analog converter DAC.

[0061] The offset control signal received by the digital-to-analog converter DAC may be a digital signal. The digital-to-analog converter DAC may generate a DC signal with a fixed voltage as an offset reference signal according to the digital signal.

[0062] The two input terminals of the analog subtractor 11 receive the input signal and the offset reference signal respectively. When the offset reference signal is a fixed DC voltage signal, superimposing the input signal with the offset reference signal is equivalent to adjusting the DC component of the input signal.

[0063] It is understandable that if Figure 3 As shown, the analog subtractor 11 includes an operational amplifier and resistors R1 to R4. By setting the resistance values ​​of the resistors R1 and R3 to be equal, and the resistance values ​​of the resistors R2 and R4 to be equal, the voltage gain of the analog subtractor 11 can be:

[0064] Vout = R4 / R3*(V2-V1);

[0065] Wherein, V2 is the signal voltage of the input signal provided by the input signal terminal IN, and V1 is the signal voltage of the offset reference signal.

[0066] Furthermore, when the resistance values ​​of the resistor R3 and the resistor R4 are equal, the voltage gain of the analog subtractor 11 is:

[0067] Vout = (V2 - V1);

[0068] That is, the output voltage of the analog subtractor 11 is the voltage difference between the input signal and the offset reference signal.

[0069] In another optional embodiment, the reference voltage generating unit 40 may be other modules or devices capable of generating a stable DC voltage, and the signal offset module 10 may be an analog adder or other modules or devices capable of realizing a signal superposition function, which is not limited here.

[0070] Please refer to Figure 4 In some embodiments, the signal amplification module 20 may include a first operational amplifier U1 and a gain adjustment module 21 .

[0071] Two input terminals of the first operational amplifier U1 can be connected to the output terminal of the signal offset module 10 and the reference ground respectively. The output terminal of the first operational amplifier U1 is connected to the input terminal of the amplitude limiting module 30 .

[0072] The gain adjustment module 21 is connected between one of the input terminals of the first operational amplifier U1 and the output terminal of the first operational amplifier U1. The gain adjustment module 21 can adjust the total resistance of the gain adjustment module 21 according to the received gain control signal.

[0073] When the gain adjustment module 21 is connected to the inverting input terminal of the first operational amplifier U1, an inverting operational amplifier circuit is formed; when the gain adjustment module 21 is connected to the non-inverting input terminal of the first operational amplifier U1, a non-inverting operational amplifier circuit is formed.

[0074] Whether it is a common-mode operational amplifier circuit or an inverting operational amplifier circuit, the gain multiple of the operational amplifier is associated with the resistance value of the feedback resistor connected in series between the input and output ends of the operational amplifier. The gain adjustment module 21 can be used as a feedback resistor, and the gain multiple can be adjusted by adjusting the total resistance value of the gain adjustment module 21.

[0075] It should be noted that Figure 4 The schematic diagram of the circuit structure of the inverting operational amplifier circuit is shown in FIG. 1 , and the gain formula of the inverting operational amplifier circuit is:

[0076] Av = -(R / R5);

[0077] Wherein, Av is the gain multiple, and R is the equivalent resistance of the gain adjustment module 21 .

[0078] When the voltage amplitude of the input signal changes greatly, adjust the signal median of the input signal to match the collection interval of the collection end. If the voltage amplitude change exceeds the collection interval, the gain multiple can be adjusted so that the voltage amplitude change is within the collection interval so that it can be normally collected by the equipment at the collection end.

[0079] Correspondingly, when the voltage amplitude change of the input signal is small, the gain multiple can be adjusted to amplify the input signal with a relatively weak amplitude change, thereby reducing the acquisition error caused by the small amplitude change during the acquisition process and improving the accuracy of signal acquisition.

[0080] Please refer to Figure 5In some embodiments, the gain adjustment module 21 may include at least two gain units 211 .

[0081] Each gain unit 211 may be connected between the inverting input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1, that is, the gain adjustment module 21 and the first operational amplifier U1 form an inverting amplifier circuit.

[0082] When the gain adjustment module 21 includes multiple gain units 211, the multiple gain units 211 are connected in parallel. The gain control signal can adjust the on / off state of each gain unit 211. That is, the gain control signal can control one or more of the multiple gain units 211 to be turned on.

[0083] Since each gain unit 211 is connected in parallel with each other, the total resistance of the gain adjustment module 21 is the parallel resistance of the gain units 211 in the on state. For example, when the gain adjustment module 21 includes 8 gain units 211, if there are 3 gain units 211 in the on state at a certain moment, the total resistance of the gain adjustment module 21 is the parallel resistance of the 3 gain units 211.

[0084] In some embodiments, each gain unit 211 may include a gain resistor Rg and a gain switch Sg connected in series, and the gain switch Sg may be turned on or off according to a received gain control signal.

[0085] Since the gain resistor and the gain switch are both discrete devices, the combination of the discrete devices and the first operational amplifier U1 can realize flexible adjustment of the gain amplification factor and reduce the cost of circuit devices.

[0086] In some embodiments, among the multiple gain units 211 of the gain adjustment module 21 , the resistance values ​​of the gain resistors Rg of any two gain units 211 are different.

[0087] Please refer to Figure 6 When the gain adjustment module 21 includes n gain units 211, the first gain unit 211 includes a gain resistor Rg1 and a gain switch Sg1, ..., and the nth gain unit 211 includes a gain resistor Rgn and a gain switch Sgn.

[0088] By setting the resistance of each gain resistor Rg to be different, when there are n gain units 211 in the gain adjustment module 21, by turning on n gain units 211 separately, the gain adjustment module 21 can support n different resistance values, thereby providing n different gain multiples. By turning on 2, 3, ..., n of the n gain units 211, more different gain multiples can be provided, thereby improving the range of signal amplification. In addition, since the selectable gain multiples are greatly increased, the output voltage signal can be close to the upper limit of the voltage sampling interval by selecting a suitable gain multiple, avoiding a large error ratio caused by a small output voltage signal, thereby improving the accuracy of signal amplification.

[0089] In some embodiments, among the multiple gain units 211 of the gain adjustment module 21 , the gain resistors Rg of at least two gain units 211 have the same resistance value.

[0090] By setting the gain resistors Rg of at least two gain units 211 to have the same resistance value, when the number of gain units 211 is large, each gain unit 211 can select the same gain resistor Rg, thereby avoiding too many types of required resistor elements. It is understandable that if the resistance values ​​and types of the gain resistors Rg are too many, the difficulty of device management during the production process will be greatly increased. If a certain type of gain resistor Rg is in short supply, production efficiency may be affected. Therefore, when some gain units 211 can select gain resistors Rg with the same resistance value, the number of component types can be reduced and production management efficiency can be improved.

[0091] As an optional implementation, in the multiple gain units 211, the number of gain resistors Rg of each resistance value is at least 2. That is, for any gain unit 211, there must be another gain unit 211, and the resistance value of the gain resistors Rg of the two is the same. Since the gain resistors Rg of any resistance value are not unique, the adaptability of each type of resistance value can be improved.

[0092] Please continue to refer to Figure 6 In some embodiments, the signal processing circuit may further include a first logic unit 50 .

[0093] The first logic unit 50 may be connected to the control end of the gain switch Sg of each gain unit 211 , and the first logic unit 50 may send a gain control signal to each gain switch Sg to adjust the conduction state of each gain switch Sg.

[0094] The first logic unit 50 may be connected to the control unit. The control unit may be an MCU (Microcontroller Unit), a SoC (System on Chip) or other types of processing modules. The control unit may send a digital signal to the first logic unit 50, and the digital signal may indicate the conduction state of each gain switch Sg. After receiving the digital signal, the first logic unit 50 may parse the digital signal to obtain the target state of each gain switch Sg, and based on the target state of each gain switch Sg, send a gain control signal corresponding to the target state to the corresponding gain switch Sg.

[0095] The first logic unit 50 can realize independent on-off control of each gain switch Sg. By selecting some gain switches Sg, the corresponding gain resistors Rg can be connected in parallel, so that the total resistance of the gain adjustment module 21 is adjusted to the resistance corresponding to the target gain amplification factor.

[0096] Please refer to Figure 7 In some embodiments, the inverting input terminal of the first operational amplifier U1 is connected to the output terminal of the signal offset module 10, and the gain adjustment module 21 is connected between the inverting input terminal of the first operational amplifier U1 and the output terminal of the first operational amplifier U1. The signal amplification module 20 may further include an inverting unit 22.

[0097] The inverting unit 22 may include a second operational amplifier U2 , whose inverting input terminal is connected to the output terminal of the first operational amplifier U1 , whose non-inverting input terminal is connected to the reference ground, and whose output terminal is connected to the input terminal of the limiting module 30 .

[0098] It is understandable that when the gain adjustment module 21 is connected to the inverting input terminal of the first operational amplifier U1, an inverting operational amplifier circuit is formed, which will invert and amplify the input signal. In order to avoid acquisition abnormalities caused by signal inversion, the signal can be inverted twice by setting an inverting unit 22 so that the output signal has the same polarity as the input signal.

[0099] As an optional implementation, the gain magnification of the inverting unit 22 may be -1. In this case, the inverting unit 22 does not perform operational amplification on the signal, but only plays a role of polarity reversal.

[0100] As another optional implementation, the gain magnification of the inverting unit 22 may not be -1. In this case, the inverting unit 22 has a certain gain characteristic, and can re-amplify the signal after the inverting operation amplification, thereby providing an additional gain magnification and enhancing the amplitude of the signal.

[0101] like Figure 7 As shown, the gain formula of the inverting unit 22 is:

[0102] Av=-R7 / R6;

[0103] That is, when the resistance values ​​of the resistor R6 and the resistor R7 are the same, the gain magnification of the inverting unit 22 is -1; when the resistance values ​​of the resistor R6 and the resistor R7 are different, the gain magnification of the inverting unit 22 is not -1.

[0104] Please refer to Figure 8 In some embodiments, the signal processing circuit may further include a channel selection unit 70 .

[0105] A first channel input terminal of the channel selection unit 70 is connected to the output terminal of the signal amplification module 20 , a second channel input terminal of the channel selection unit 70 is connected to the reference ground, and a channel output terminal of the channel selection unit 70 is connected to the input terminal of the limiter module 30 .

[0106] The channel selection unit 70 may connect one of the first channel input terminal and the second channel input terminal to the channel output terminal.

[0107] When the first channel input terminal is connected to the channel output terminal, the processed input signal can be output to the limiting module 30. When the second channel input terminal is connected to the channel output terminal, the limiting module 30 will not receive the processed input signal. Therefore, at the initial stage of powering on the signal processing circuit, the second channel input terminal can be connected to the channel output terminal to prevent the initial input signal from affecting the equipment at the acquisition end.

[0108] like Figure 8 As shown, the channel selection unit 70 may include two switches, and the control ends of the two switches may be connected to the second logic unit 60. The second logic unit 60 may control one of the two switches to be in an on state and the other to be in an off state.

[0109] Similarly, the second logic unit 60 can be connected to the control unit. The control unit can be an MCU (Microcontroller Unit), a SoC (System on Chip) or other types of processing modules. The control unit can send a digital signal to the second logic unit 60. After receiving the digital signal, the second logic unit 60 can control one of the switches of the channel selection unit 70 to turn on.

[0110] Please refer to Figure 8In some embodiments, the above-mentioned limiter module 30 may include a voltage follower. The non-inverting input terminal of the voltage follower is connected to the channel selection unit 70, and the inverting input terminal of the voltage follower is connected to the output terminal of the voltage follower.

[0111] like Figure 8 As shown, the voltage follower may include an operational amplifier, the output of which is connected to the inverting input. The two power input terminals of the voltage follower are respectively connected to the two power supply voltage terminals. For example, the voltage follower can be connected to the first power supply voltage V+ and the second power supply voltage V-, respectively. After determining the voltage magnitude of the first power supply voltage V+, the voltage upper limit value of the output voltage can be made slightly lower than the first power supply voltage V+ according to the output characteristics of the voltage follower. For example, the output voltage upper limit of some voltage followers is usually the difference between the first power supply voltage and 1.5 volts. Correspondingly, according to the second power supply voltage V-, the voltage lower limit value of the output voltage of the voltage follower can also be obtained. The amplitude range of the limiting module 30 can be determined according to the upper limit value and the lower limit value.

[0112] As an optional implementation, the above-mentioned limiting module 30 can also be formed by two voltage-stabilizing diodes connected in reverse parallel, and the reverse breakdown voltages of the two voltage-stabilizing diodes are respectively the upper limit and the lower limit of the amplitude range.

[0113] The embodiment of the present application also provides a signal processing device, which may include a detection unit, a processing unit, and a signal processing circuit. The signal processing circuit may include the signal processing circuit provided by the above embodiment of the present application. The detection unit is connected to the input end of the amplifier of the signal processing circuit, and the processing unit is connected to the output end of the amplifier of the signal processing circuit.

[0114] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0115] It should be noted that, in this article, the terms "comprises", "includes" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus.

[0116] This article uses specific examples to illustrate the principles and implementation methods of this application. The above examples are only used to help understand the methods and core ideas of this application. The above are only preferred implementation methods of this application. It should be pointed out that due to the limitations of textual expression and the objective existence of infinite specific structures, ordinary technicians in this technical field can make several improvements, modifications or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes or combinations, or the direct application of the concepts and technical solutions of this application to other occasions without improvement, should be regarded as the scope of protection of this application.

Claims

1. A signal processing circuit, characterized in that: The signal processing circuit comprises: A signal offset module, wherein a first input end of the signal offset module is used to receive an input signal, a second input end of the signal offset module is used to receive an offset reference signal, and the signal offset module is used to superimpose the offset reference signal on the input signal; A signal amplification module, the input end of which is connected to the output end of the signal offset module; the signal amplification module is used to perform gain amplification on the superimposed input signal; A limiting module, wherein the input end of the limiting module is connected to the output end of the signal amplification module, and the output end of the limiting module is used to output the adjusted input signal; the limiting module is used to limit the signal amplitude of the input signal after gain within an amplitude range.

2. The signal processing circuit according to claim 1, characterized in that: The signal processing circuit further includes: A reference voltage generating unit, wherein the input end of the reference voltage generating unit is used to receive an offset control signal, and the output end of the reference voltage generating unit is connected to the second input end of the signal offset module; the reference voltage generating unit is used to generate a corresponding offset reference signal according to the offset control signal.

3. The signal processing circuit according to claim 2, characterized in that: The signal offset module includes an analog subtractor, and the reference voltage generating unit includes a digital-to-analog converter.

4. The signal processing circuit according to claim 1, characterized in that: The signal amplification module comprises: A first operational amplifier, wherein two input terminals of the first operational amplifier are respectively connected to the output terminal of the signal offset module and a reference ground, and the output terminal of the first operational amplifier is connected to the input terminal of the limiting module; A gain adjustment module, the gain adjustment module is connected between one of the input terminals of the first operational amplifier and the output terminal of the first operational amplifier; the gain adjustment module is used to adjust the total resistance of the gain adjustment module according to a received gain control signal.

5. The signal processing circuit according to claim 4, characterized in that: The gain adjustment module comprises at least two gain units, each of which is connected between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; The gain unit comprises: A gain resistor and a gain switch are connected in series, and the gain switch is used to be turned on or off according to a received gain control signal.

6. The signal processing circuit according to claim 5, characterized in that: The signal processing circuit further includes: A first logic unit, wherein the first logic unit is connected to the control end of the gain switch; the first logic unit is used to send a gain control signal to the gain switch.

7. The signal processing circuit according to claim 4, characterized in that: The inverting input terminal of the first operational amplifier is connected to the output terminal of the signal offset module, and the gain adjustment module is connected between the inverting input terminal of the first operational amplifier and the output terminal of the first operational amplifier; The signal amplification module also includes: The inverting unit comprises a second operational amplifier, the inverting input terminal of the second operational amplifier is connected to the output terminal of the first operational amplifier, the non-inverting input terminal of the second operational amplifier is connected to the reference ground, and the output terminal of the second operational amplifier is connected to the input terminal of the limiting module.

8. The signal processing circuit according to claim 1, characterized in that: The signal processing circuit further includes: A channel selection unit, wherein a first channel input terminal of the channel selection unit is connected to an output terminal of the signal amplification module, a second channel input terminal of the channel selection unit is connected to a reference ground, and a channel output terminal of the channel selection unit is connected to an input terminal of the limiting module; the channel selection unit is used to connect one of the first channel input terminal and the second channel input terminal to the channel output terminal.

9. The signal processing circuit according to claim 8, characterized in that: The limiting module comprises: A voltage follower, wherein the non-inverting input terminal of the voltage follower is connected to the channel selection unit, and the inverting input terminal of the voltage follower is connected to the output terminal of the voltage follower.

10. A signal processing device, characterized in that: The signal processing device comprises the signal processing circuit according to any one of claims 1 to 9.

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