A processing circuit for signal acquisition

Abstract

A processing circuit for signal acquisition includes: an antenna, a radio frequency front-end module, an analog-to-digital converter, a signal detection module, a control module, a first signal conditioning circuit, a first radio frequency switch, a second signal conditioning circuit and a second radio frequency switch, wherein the antenna receives a wireless signal and outputs it to the radio frequency front-end module, the radio frequency front-end module outputs the processed signal to the input port of the analog-to-digital converter, the analog-to-digital converter is connected to the signal detection module, the signal detection module is connected to the control module, the control module is connected to the first signal conditioning circuit via the first radio frequency switch, and the control module is connected to the second signal conditioning circuit via the second radio frequency switch. Two signal conditioning circuits can be switched according to the requirements of the signal-to-noise ratio and the output swing, and the size of the inverter is set so that the signal conditioning circuit can be flexibly controlled and a larger output swing can be obtained under a low power supply voltage.

Description

Technical Field

[0001] The present application relates to the field of wireless signal technology, and more specifically, to a processing circuit for signal acquisition. Background Art

[0002] With the ever-expanding technical needs of integrated circuits and their application scenarios, there are many scenarios that need to be applied in low power supply voltage environments, and the signal changes in actual applications are complex. Currently, in wireless energy signal acquisition, there is a lack of adaptive adjustment under different signal-to-noise ratio conditions, and the signal cannot be flexibly inverted according to actual conditions. At the same time, ordinary inverters can only work normally under high power supply voltages. If switched to low power supply voltages, the ratio of the on-resistance of NMOSFET to the off-resistance of PMOSFET or the ratio of the off-resistance of NMOSFET to the on-resistance of PMOSFET will become smaller, resulting in the signal conditioning circuit not being able to work properly. For example, a cached wireless signal collector with publication number CN106097693A, for which the signal acquisition and processing device includes a circuit board and a digital-to-analog conversion circuit, an amplification circuit and a signal filtering circuit arranged on the circuit board and connected in sequence. Another example is a wireless signal acquisition and transmission system based on a node controller for coal preparation with publication number CN116824824B, which includes a data acquisition module, a data processing module, a storage module, a wireless signal communication module and a remote server, wherein the data processing module is used to perform calculations on the digital signal of the signal receiving unit. Another example is a wireless self-powered controller device based on a friction nanogenerator with publication number CN116700080A, which discloses that the control end generates a wireless signal, and the host end implements tasks such as signal reception, signal conversion, signal processing, and signal recognition based on a high-speed A / D converter circuit and an embedded MCU chip. Another example is a wireless signal acquisition and transmission system based on a node controller for coal preparation with publication number CN116824824B, which includes a data acquisition module, a data processing module, a storage module, a wireless signal communication module and a remote server, wherein the data processing module is used to perform calculations on the digital signal of the signal receiving unit. A is an AC / DC high-voltage voltage divider secondary signal wireless transmission system, including a wirelessly connected voltage divider bottom measuring device and a remote display device, the voltage divider bottom measuring device includes a signal processing module, a control module, a wireless transmission module and a power module, and a power on / off control circuit and control method for a remote control system with announcement number CN110570642B, including a wireless data transmission module, a main control module, a manual switch, a drive module and a system power supply circuit; the on / off of the system power supply circuit is controlled according to the manual switch and the wireless signal respectively, wherein the main control module includes an inverter, but the above five patents do not design a more suitable signal conditioning circuit that can be flexibly switched according to different actual signal-to-noise ratios, and design a corresponding signal conditioning circuit that can work normally under low power supply voltage, which may result in the inability to effectively process signals in some cases, and may also result in the signal conditioning circuit not working normally under low power supply voltage. Summary of the invention

[0003] In view of the above problems, the purpose of the present invention is to provide a processing circuit for signal acquisition, which ensures that the inverter can still work normally even at a low power supply voltage and obtain a larger output swing, and flexibly switches the signal conditioning circuit according to different signal-to-noise ratios. To achieve the above purpose, the present application adopts the following technical solutions:

[0004] A processing circuit for signal acquisition, comprising: an antenna, a radio frequency front-end module, an analog-to-digital converter, a signal detection module, a control module, a first signal conditioning circuit, a first radio frequency switch, a second signal conditioning circuit and a second radio frequency switch, wherein the antenna receives a wireless signal and outputs it to the radio frequency front-end module, the radio frequency front-end module outputs the processed signal to an input port of the analog-to-digital converter, the analog-to-digital converter is connected to the signal detection module, the signal detection module is connected to the control module, the control module is connected to the first signal conditioning circuit via a first radio frequency switch, and the control module is connected to the second signal conditioning circuit via a second radio frequency switch;

[0005] The signal detection module detects the power of the signal and the power of the noise, samples the signal within a period of time, calculates the average power of the signal and the average power of the noise, and calculates the signal-to-noise ratio; the control module is set with a signal-to-noise ratio threshold, compares the signal-to-noise ratio input by the signal detection module with the set signal-to-noise ratio threshold, and outputs a control signal by the MCU. When the signal-to-noise ratio is greater than the signal-to-noise ratio threshold, the second RF switch is turned on and the first RF switch is turned off to switch to the output route of the second signal conditioning circuit; when the signal-to-noise ratio is less than the signal-to-noise ratio threshold, the first RF switch is turned on and the second RF switch is turned off to switch to the output route of the first signal conditioning circuit;

[0006] The second signal conditioning circuit comprises: a first inverter group, a second inverter group and a seventh inverter; the input end of the first inverter group, the input end of the second inverter group and the input end of the seventh inverter are connected, the output end of the first inverter group is connected to the PMOSFET source of the seventh inverter, the output end of the second inverter group is connected to the NMOSFET source of the seventh inverter, and the second signal conditioning circuit is output through the output end of the seventh inverter;

[0007] The first signal conditioning circuit includes: an eighth inverter, a ninth inverter and a tenth inverter, the PMOSFET source of the tenth inverter is connected to the output end of the eighth inverter, the NMOSFET source of the tenth inverter is connected to the output end of the ninth inverter, the input ends of the eighth inverter, the ninth inverter and the tenth inverter are connected, and the first signal conditioning circuit is output through the output end of the tenth inverter.

[0008] Preferably, the width-to-length ratio of the PMOSFET of the eighth inverter is greater than that of the PMOSFET of the ninth inverter, the width-to-length ratio of the NMOSFET of the ninth inverter is greater than that of the NMOSFET of the eighth inverter, the width-to-length ratio of the NMOSFET of the tenth inverter is the same as that of the NMOSFET of the ninth inverter, and the width-to-length ratio of the PMOSFET of the tenth inverter is the same as that of the PMOSFET of the eighth inverter. By setting different width-to-length ratios for each field effect transistor, the first signal conditioning circuit is more adapted, the conversion speed is improved, the power consumption is reduced, and the signal output is optimized under a low signal-to-noise ratio.

[0009] Preferably, the first inverter group includes: a first inverter, a second inverter and a third inverter, the PMOSFET source of the third inverter is connected to the output end of the first inverter, and the NMOSFET source of the third inverter is connected to the output end of the second inverter; the second inverter group includes: a fourth inverter, a fifth inverter and a sixth inverter, the PMOSFET source of the sixth inverter is connected to the output end of the fourth inverter, and the NMOSFET source of the sixth inverter is connected to the output end of the fifth inverter; the input end of the first inverter, the input end of the second inverter, the input end of the third inverter, the input end of the fourth inverter, the input end of the fifth inverter, the input end of the sixth inverter and the input end of the seventh inverter are connected.

[0010] Further preferably, the width-to-length ratio of the NMOSFET of the first inverter is smaller than the width-to-length ratio of the NMOSFET of the second inverter, and the width-to-length ratio of the PMOSFET of the first inverter is larger than the width-to-length ratio of the PMOSFET of the second inverter; the width-to-length ratio of the NMOSFET of the fourth inverter is smaller than the width-to-length ratio of the NMOSFET of the fifth inverter, and the width-to-length ratio of the PMOSFET of the fourth inverter is larger than the width-to-length ratio of the PMOSFET of the fifth inverter. The width-to-length ratio of the NMOSFET of the inverter and the width-to-length ratio of the PMOSFET are set so that the inverter group has a stronger pull-up or pull-down path, so that the inverter can maintain good performance under low power supply voltage, improve certain anti-interference ability, and optimize signal output under high signal-to-noise ratio.

[0011] Further preferably, the width-to-length ratio of the NMOSFET of the third inverter is the same as that of the NMOSFET of the second inverter, and the width-to-length ratio of the PMOSFET of the third inverter is the same as that of the PMOSFET of the first inverter; the width-to-length ratio of the NMOSFET of the sixth inverter is the same as that of the NMOSFET of the fifth inverter, and the width-to-length ratio of the PMOSFET of the sixth inverter is the same as that of the PMOSFET of the fourth inverter.

[0012] Further preferably, the width-to-length ratio of the NMOSFET of the third inverter is smaller than the width-to-length ratio of the NMOSFET of the sixth inverter, the width-to-length ratio of the PMOSFET of the third inverter is larger than the width-to-length ratio of the PMOSFET of the sixth inverter, the width-to-length ratio of the NMOSFET of the seventh inverter is the same as the width-to-length ratio of the NMOSFET of the sixth inverter, and the width-to-length ratio of the PMOSFET of the seventh inverter is the same as the width-to-length ratio of the PMOSFET of the third inverter. By setting the width-to-length ratio of the NMOSFET of the inverter and the width-to-length ratio of the PMOSFET, the inverter group has a stronger pull-up or pull-down path, so that the inverter can maintain good performance under low power supply voltage, improve certain anti-interference capabilities, and optimize signal output under high signal-to-noise ratio.

[0013] Preferably, the RF front-end module includes an amplifier and a filter. The amplifier amplifies the input signal to increase the signal strength. The amplified signal enters the filter to improve the anti-interference capability of the system.

[0014] Compared with the prior art, the beneficial results of the present invention are: by controlling two RF switches through an MCU, two signal conditioning circuits can be switched according to the requirements of the signal-to-noise ratio and the output swing, thereby realizing flexible control of the signal conditioning circuit and targeted functional expansion, and by designing the first signal conditioning circuit and the second signal conditioning circuit, and setting the width-to-length ratio of the inverter NMOSFET and the width-to-length ratio of the PMOSFET, the inverter group has a stronger pull-up or pull-down path, and the inverter can work normally under a low power supply voltage and obtain a larger output swing, thereby realizing optimized processing of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and are used together with the description to explain the principles of the present application. It will be easy to recognize other embodiments and many expected advantages of the embodiments because they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with each other. The same reference numerals refer to corresponding similar parts.

[0016] In the description of the present invention, it should be noted that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Directional terms are used with reference to the orientation of the described figures, such as "top", "bottom", "left", "right", "upper", "lower", etc. Because the components of the embodiments can be positioned in several different orientations, directional terms are used for the purpose of illustration and the directional terms are by no means restrictive. The terms "installed", "provided with", "set / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection through an intermediate medium, or a communication between the two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0017] Figure 1 is a module block diagram of a processing circuit for signal acquisition according to a specific embodiment of the present application;

[0018] Figure 2 is a circuit diagram of a first signal conditioning circuit according to a specific embodiment of the present application;

[0019] Figure 3 is a circuit diagram of a second signal conditioning circuit according to a specific embodiment of the present application;

[0020] Figure 4 It is a circuit diagram of a processing circuit for signal acquisition according to a specific embodiment of the present application.

[0021] The meaning of the numbers in the figure are: 01, first inverter; 02, second inverter; 03, third inverter; 04, fourth inverter; 05, fifth inverter; 06, sixth inverter; 07, seventh inverter; 08, eighth inverter; 09, ninth inverter; 10, tenth inverter; 11, amplifier; 12, filter; 13, analog-to-digital converter. DETAILED DESCRIPTION

[0022] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It should also be noted that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0023] In the description of this proposal, it should be noted that the terms "include", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. The terms "installed", "provided with", "set / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection through an intermediate medium, or a communication between the two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] It should be noted that the NMOSFET described in this application refers to an N-type metal oxide semiconductor field effect transistor, the PMOSFET refers to a P-type metal oxide semiconductor field effect transistor, and if the connection method is not specifically specified, the inverter of this application is that the PMOSFET source (S) is connected to the power supply terminal (VDD), the NMOSFET source (S) is grounded, the PMOSFET and the NMOSFET gate (G) are connected as the input terminal of the inverter, the PMOSFET and the NMOSFET drain (D) are connected as the output terminal of the inverter, and MCU refers to a micro control unit.

[0025] It should be noted that the "0" and "1" described in this application refer to logic levels, and the strong "0" refers to a lower logic low level than the weak "0", and the strong "1" refers to a higher logic high level than the weak "1".

[0026] To facilitate understanding by those skilled in the art, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0027] Figure 1 It is a block diagram of a processing circuit for signal acquisition, such as Figure 1As shown, it includes: an antenna, a radio frequency front-end module, an analog-to-digital converter 13, a signal detection module, a control module, a first signal conditioning circuit, a first radio frequency switch, a second signal conditioning circuit and a second radio frequency switch. The antenna receives a wireless signal and outputs it to the radio frequency front-end module. The radio frequency front-end module outputs the processed signal to the input port of the analog-to-digital converter 13. The analog-to-digital converter 13 is connected to the signal detection module, and the signal detection module is connected to the control module. The control module is connected to the first signal conditioning circuit through the first radio frequency switch, and the control module is connected to the second signal conditioning circuit through the second radio frequency switch. In wireless energy signal acquisition, a high signal-to-noise ratio means that the useful energy in the signal is stronger than the noise. By monitoring the signal-to-noise ratio, the quality of the currently received signal can be judged, thereby selecting different signal processing paths.

[0028] In a specific embodiment, the signal detection module detects the power of the signal and the power of the noise, samples the signal within a period of time, calculates the average power of the signal and the average power of the noise, and calculates the signal-to-noise ratio; the control module is set with a signal-to-noise ratio threshold, compares the signal-to-noise ratio input by the signal detection module with the set signal-to-noise ratio threshold, and outputs a control signal by the MCU. When the signal-to-noise ratio is greater than the signal-to-noise ratio threshold, the second RF switch is turned on and the first RF switch is turned off to switch to the output route of the second signal conditioning circuit; when the signal-to-noise ratio is less than the signal-to-noise ratio threshold, the first RF switch is turned on and the second RF switch is turned off to switch to the output route of the first signal conditioning circuit;

[0029] In a specific embodiment, the wireless signal received by the antenna is preliminarily processed by the RF front-end module, and the processed signal is connected to the analog-to-digital converter 13, and is connected to the MCU after being processed into a digital signal. The signal detection module continuously monitors the input signal and samples the signal multiple times within a period of time to ensure that the dynamic changes of the signal and the fluctuations of the noise can be accurately captured. For the collected signal samples, the signal detection module detects the average power of the signal and the average power of the noise, and then accurately calculates the signal-to-noise ratio of the current signal according to the definition of the signal-to-noise ratio, that is, the ratio of the average signal power to the average noise power.

[0030] In a specific embodiment, a signal-to-noise ratio threshold is pre-set in the control module. This threshold is determined based on the system's performance requirements and actual application scenarios. When the signal detection module inputs the calculated signal-to-noise ratio into the control module, the control module will quickly compare it with the set signal-to-noise ratio threshold. If the signal-to-noise ratio is greater than this threshold, it means that the current signal quality is good and is suitable for the second signal conditioning circuit. The control module will send a corresponding instruction to the MCU. After receiving the instruction, the MCU will output a control signal to turn on the second RF switch and turn off the first RF switch. In this way, the output route of the second signal conditioning circuit is switched, which is usually optimized and inverted for signals with high signal-to-noise ratios, which can further improve the quality and stability of the signal, while outputting a larger output swing.

[0031] On the contrary, if the signal-to-noise ratio is less than the signal-to-noise ratio threshold, it indicates that the current signal is subject to greater noise interference or poor quality. In this case, the first signal conditioning circuit is suitable, and the delay is small. The control module will instruct the MCU to output different control signals, turn on the first RF switch and turn off the second RF switch, and switch to the output route of the first signal conditioning circuit. The first signal conditioning circuit focuses more on enhanced denoising and inversion processing of low signal-to-noise ratio signals to try to restore the signal's recognizability and reliability. By automatically switching the RF switch and signal conditioning circuit according to the signal-to-noise ratio, the entire signal acquisition processing circuit can adaptively respond to different signal quality conditions, and consider different output swing requirements, using different signal conditioning circuits to switch lines according to the signal-to-noise ratio, to maximize the signal processing effect and stability.

[0032] Optionally, the first RF switch and the second RF switch may be one of a PIN diode switch, a microwave switch, and a transistor switch.

[0033] Optionally, the RF front-end module includes an amplifier 11 and a filter. The amplifier 11 amplifies the input signal to increase the signal strength. The amplified signal enters the filter to improve the anti-interference capability of the system.

[0034] Figure 2 A circuit diagram of a first signal conditioning circuit according to a specific embodiment of the present application is shown. Figure 2As shown, it includes: an eighth inverter 08, a ninth inverter 09 and a tenth inverter 10, the PMOSFET source of the tenth inverter 10 is connected to the output end of the eighth inverter 08, the NMOSFET source of the tenth inverter 10 is connected to the output end of the ninth inverter 09, the input ends of the eighth inverter 08, the ninth inverter 09 and the tenth inverter 10 are connected, and the first signal conditioning circuit outputs through the output end of the tenth inverter 10. The first signal conditioning circuit is suitable for wireless signals with low signal-to-noise ratio, low delay and power consumption, maintains signal linearity, and avoids signal distortion.

[0035] Optionally, the width-to-length ratio of the PMOSFET of the eighth inverter 08 is greater than the width-to-length ratio of the PMOSFET of the ninth inverter 09, the width-to-length ratio of the NMOSFET of the ninth inverter 09 is greater than the width-to-length ratio of the NMOSFET of the eighth inverter 08, the width-to-length ratio of the NMOSFET of the tenth inverter 10 is the same as the width-to-length ratio of the NMOSFET of the ninth inverter 09, and the width-to-length ratio of the PMOSFET of the tenth inverter 10 is the same as the width-to-length ratio of the PMOSFET of the eighth inverter 08. By setting different width-to-length ratios for each field effect transistor, the first signal conditioning circuit is more adapted, the conversion speed is increased and the power consumption is reduced, a larger output swing is obtained, and the output of the signal is optimized under the condition of a low signal-to-noise ratio.

[0036] The following takes the example that the width-to-length ratio of the NMOSFET of the eighth inverter 08 is 1.2μm / 80nm, the width-to-length ratio of the PMOSFET of the eighth inverter 08 is 4.8μm / 80nm, the width-to-length ratio of the NMOSFET of the ninth inverter 09 is 2.5μm / 80nm, and the width-to-length ratio of the PMOSFET of the ninth inverter 09 is 1μm / 80nm, that is, the ratio of the width-to-length ratio of the NMOSFET of the ninth inverter 09 to the width-to-length ratio of the PMOSFET is 10 times the ratio of the width-to-length ratio of the NMOSFET of the eighth inverter 08 to the width-to-length ratio of the PMOSFET, to describe the principle of the first signal conditioning circuit of the present application:

[0037] In a specific embodiment, the width-to-length ratio of the NMOSFET of the tenth inverter 10 is the same as that of the NMOSFET of the ninth inverter 09, and the width-to-length ratio of the PMOSFET of the tenth inverter 10 is the same as that of the PMOSFET of the eighth inverter 08, that is, the width-to-length ratio of the NMOSFET of the tenth inverter 10 is 2.5μm / 80nm, and the width-to-length ratio of the PMOSFET of the tenth inverter 10 is 4.8μm / 80nm.

[0038] In a specific embodiment, when the input I1 is "1", the eighth inverter 08 and the ninth inverter 09 will have a "0" output. Since the eighth inverter 08 and the ninth inverter 09 have different NMOSFET width-to-length ratios or PMOSFET width-to-length ratios, the outputs of the eighth inverter 08 and the ninth inverter 09 have weak "0" and strong "0" respectively, and the tenth inverter 10 will have a larger ratio of the on-resistance of NMOSFET to the off-resistance of PMOSFET or a larger ratio of the off-resistance of NMOSFET to the on-resistance of PMOSFET, to ensure that the strong "0" is transmitted to the output O1 even at a low voltage. When the input I1 is "0", the eighth inverter 08 and the ninth inverter 09 will have a "1" output. Since the eighth inverter 08 and the ninth inverter 09 have different NMOSFET width-to-length ratios or PMOSFET width-to-length ratios, the eighth inverter 08 and the ninth inverter 09 will have a strong "1" and a weak "1" respectively. Through the tenth inverter 10, there is a larger ratio of the on-resistance of the NMOSFET to the off-resistance of the PMOSFET or a larger ratio of the off-resistance of the NMOSFET to the on-resistance of the PMOSFET. Compared with the input I1 being "1", a similar large resistance ratio is observed in an opposite manner to ensure that a strong "1" is propagated to the output O1 at a low voltage. In this way, at a lower power supply voltage, the first signal conditioning circuit can obtain a larger output swing, and this arrangement is more suitable for inverting signals with a low signal-to-noise ratio.

[0039] Figure 3 A circuit diagram of a second signal conditioning circuit according to a specific embodiment of the present application is shown. Figure 3 As shown, it includes: a first inverter group, a second inverter group and a seventh inverter 07; the input end of the first inverter group, the input end of the second inverter group and the input end of the seventh inverter 07 are connected, the output end of the first inverter group is connected to the PMOSFET source in the seventh inverter 07, the output end of the second inverter group is connected to the NMOSFET source in the seventh inverter 07, and the second signal conditioning circuit is output through the output end of the seventh inverter 07.

[0040] Optionally, the first inverter group includes: a first inverter 01, a second inverter 02 and a third inverter 03, the PMOSFET source of the third inverter 03 is connected to the output end of the first inverter 01, and the NMOSFET source of the third inverter 03 is connected to the output end of the second inverter 02; the second inverter group includes: a fourth inverter 04, a fifth inverter 05 and a sixth inverter 06, the PMOSFET source of the sixth inverter 06 is connected to the output end of the fourth inverter 04, and the NMOSFET source of the sixth inverter 06 is connected to the output end of the fifth inverter 05; the input end of the first inverter 01, the input end of the second inverter 02, the input end of the third inverter 03, the input end of the fourth inverter 04, the input end of the fifth inverter 05, the input end of the sixth inverter 06 and the input end of the seventh inverter 07 are connected.

[0041] Optionally, the width-to-length ratio of the NMOSFET of the first inverter 01 is smaller than the width-to-length ratio of the NMOSFET of the second inverter 02, and the width-to-length ratio of the PMOSFET of the first inverter 01 is greater than the width-to-length ratio of the PMOSFET of the second inverter 02; the width-to-length ratio of the NMOSFET of the fourth inverter 04 is smaller than the width-to-length ratio of the NMOSFET of the fifth inverter 05, and the width of the PMOSFET of the fourth inverter 04 is greater than the width-to-length ratio of the PMOSFET of the fifth inverter 05; the width-to-length ratio of the NMOSFET of the third inverter 03 is smaller than the width-to-length ratio of the NMOSFET of the sixth inverter 06, and the width-to-length ratio of the PMOSFET of the third inverter 03 is greater than the width-to-length ratio of the PMOSFET of the sixth inverter 06.

[0042] The following takes the case where the width-to-length ratio of the PMOSFET of the first inverter 01 is 4.6μm / 80nm, and the width-to-length ratio of the NMOSFET of the first inverter 01 is 0.6μm / 80nm; the width-to-length ratio of the NMOSFET of the second inverter 02 is 1.8μm / 80nm, and the width-to-length ratio of the PMOSFET of the second inverter 02 is 1.2μm / 80nm; the width-to-length ratio of the NMOSFET of the fourth inverter 04 is 0.8μm / 80nm, and the width-to-length ratio of the PMOSFET of the fourth inverter 04 is 2.3μm / 80nm; the width-to-length ratio of the NMOSFET of the fifth inverter 05 is 2.8μm / 80nm, and the width-to-length ratio of the PMOSFET of the fifth inverter 05 is 0.9μm / 80nm as an example to describe the working principle of the second signal conditioning circuit according to a specific embodiment of the present application:

[0043] In a specific embodiment, the width-to-length ratio of the NMOSFET of the third inverter 03 is the same as the width-to-length ratio of the NMOSFET of the second inverter 02, and the width-to-length ratio of the PMOSFET of the third inverter 03 is the same as the width-to-length ratio of the PMOSFET of the first inverter 01; the width-to-length ratio of the NMOSFET of the sixth inverter 06 is the same as the width-to-length ratio of the NMOSFET of the fifth inverter 05, the width-to-length ratio of the PMOSFET of the sixth inverter 06 is the same as the width-to-length ratio of the PMOSFET of the fourth inverter 04, the width-to-length ratio of the NMOSFET of the seventh inverter 07 is the same as the width-to-length ratio of the NMOSFET of the sixth inverter 06, and the width-to-length ratio of the PMOSFET of the sixth inverter 06 is the same as the width-to-length ratio of the PMOSFET of the fourth inverter 04. The width-to-length ratio of the PMOSFET of the seventh inverter 07 is the same as that of the PMOSFET of the third inverter 03. Therefore, in a specific embodiment, the width-to-length ratio of the NMOSFET of the third inverter 03 is 1.8μm / 80nm, and the width-to-length ratio of the PMOSFET of the third inverter 03 is 4.6μm / 80nm; the width-to-length ratio of the NMOSFET of the sixth inverter 06 is 2.8μm / 80nm, and the width-to-length ratio of the PMOSFET of the sixth inverter 06 is 2.3μm / 80nm; the width-to-length ratio of the NMOSFET of the seventh inverter 07 is 2.8μm / 80nm, and the width-to-length ratio of the PMOSFET of the seventh inverter 07 is 4.6μm / 80nm.

[0044] In a specific embodiment, when the input I2 is “1”, for the first inverter group, the first inverter 01 and the second inverter 02 will have a “0” output. Since the first inverter 01 and the second inverter 02 have different NMOSFET width-to-length ratios, the outputs of the first inverter 01 and the second inverter 02 output the first weak "0" and the first strong "0" respectively, and the third inverter 03 will have a larger ratio of the off-resistance of PMOSFET to the on-resistance of NMOSFET, so as to ensure that the first strong "0" is transmitted to the output A even at a low voltage; for the second inverter group, when the input I2 is "1", the fourth inverter 04 and the fifth inverter 05 will have a "0" output, and since the fourth inverter 04 and the fifth inverter 05 have different NMOSFET width-to-length ratios, the outputs of the fourth inverter 04 and the fifth inverter 05 output the second weak "0" and the second strong "0" respectively, and the sixth inverter 06 will have a larger ratio of the off-resistance of PMOSFET to the on-resistance of NMOSFET, so as to ensure that the second strong "0" is transmitted to the output B even at a low voltage.

[0045] Optionally, in the first inverter group and the second inverter group, the sizes of the six inverters are different, and the seventh inverter 07 has an enhanced large resistance ratio, which is used to ensure that even at low voltage, the stronger "0" between the first strong "0" and the second strong "0" is output to O2. The above-mentioned second signal conditioning circuit is suitable for processing signals with a higher signal-to-noise ratio. While the performance of the second signal conditioning circuit is more stable at low power supply voltage, it can obtain a larger output swing than the first signal conditioning circuit.

[0046] In a specific embodiment, when the input I2 is "0", for the first inverter group, the first inverter 01 and the second inverter 02 will have a "1" output. Since the first inverter 01 and the second inverter 02 have different NMOSFET width-to-length ratios or PMOSFET width-to-length ratios, the first inverter 01 and the second inverter 02 will have a first strong "1" and a first weak "1" respectively. The third inverter 03 implements a larger ratio of the off-resistance of the NMOSFET to the on-resistance of the PMOSFET, which is used to ensure that the first strong "1" is transmitted to the output A even at a low voltage. ; For the second inverter group, the fourth inverter 04 and the fifth inverter 05 will have a "1" output. Since the fourth inverter 04 and the fifth inverter 05 have different PMOSFET width-to-length ratios, the fourth inverter 04 and the fifth inverter 05 will have the second strongest "1" and the second weakest "1", respectively. The sixth inverter 06 implements a larger ratio of the off-resistance of the NMOSFET and the on-resistance of the PMOSFET, which is used to ensure that the second strongest "1" is transmitted to the output B even at a low voltage. Compared with the input I2 being "1", a similar large resistance ratio is observed in the opposite way.

[0047] Optionally, in the first inverter group and the second inverter group, the sizes of the six inverters are different, and the seventh inverter 07 has an enhanced large resistance ratio to ensure that a stronger "1" is output to O2 even at a low voltage. The above-mentioned second signal conditioning circuit has more stable performance at a low power supply voltage and can obtain a larger output swing than the first signal conditioning circuit.

[0048] Figure 4 A circuit diagram of a processing circuit for signal acquisition in a specific embodiment of the present application is shown. In a specific embodiment, Figure 4As shown, it includes: an antenna, an amplifier 11, a filter 12, an analog-to-digital converter 13, a signal detection module, a control module, a first signal conditioning circuit, a first radio frequency switch SPST1, a second signal conditioning circuit and a second radio frequency switch SPST2. The antenna receives a wireless signal and outputs it to the amplifier 11. After amplifying the signal, the signal enters the filter 12 for filtering, and then the processed signal is output to the input port of the analog-to-digital converter 13. The analog-to-digital converter 13 is connected to the signal detection module, and the signal detection module is connected to the control module. The control module is connected to the first signal conditioning circuit through the first radio frequency switch, and the control module is connected to the second signal conditioning circuit through the second radio frequency switch. Combined with the above Figure 2 The first signal conditioning circuit and the above Figure 3 The second signal conditioning circuit determines the quality of the current received signal by monitoring the signal-to-noise ratio, thereby selecting a different signal processing path.

[0049] The above describes the specific implementation of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A processing circuit for signal acquisition, characterized in that: include: An antenna, a radio frequency front-end module, an analog-to-digital converter, a signal detection module, a control module, a first signal conditioning circuit, a first radio frequency switch, a second signal conditioning circuit and a second radio frequency switch, wherein the antenna receives a wireless signal and outputs it to the radio frequency front-end module, the radio frequency front-end module outputs the processed signal to the input port of the analog-to-digital converter, the analog-to-digital converter is connected to the signal detection module, the signal detection module is connected to the control module, the control module is connected to the first signal conditioning circuit via the first radio frequency switch, and the control module is connected to the second signal conditioning circuit via the second radio frequency switch; The signal detection module detects the power of the signal and the power of the noise, samples the signal within a period of time, calculates the average power of the signal and the average power of the noise, and calculates the signal-to-noise ratio; the control module is set with a signal-to-noise ratio threshold, compares the signal-to-noise ratio input by the signal detection module with the set signal-to-noise ratio threshold, and outputs a control signal by the MCU. When the signal-to-noise ratio is greater than the signal-to-noise ratio threshold, the second RF switch is turned on and the first RF switch is turned off to switch to the output route of the second signal conditioning circuit; when the signal-to-noise ratio is less than the signal-to-noise ratio threshold, the first RF switch is turned on and the second RF switch is turned off to switch to the output route of the first signal conditioning circuit; The second signal conditioning circuit comprises: a first inverter group, a second inverter group and a seventh inverter; the input end of the first inverter group, the input end of the second inverter group and the input end of the seventh inverter are connected, the output end of the first inverter group is connected to the PMOSFET source of the seventh inverter, the output end of the second inverter group is connected to the NMOSFET source of the seventh inverter, and the second signal conditioning circuit is output through the output end of the seventh inverter; The first signal conditioning circuit includes: an eighth inverter, a ninth inverter and a tenth inverter, the PMOSFET source of the tenth inverter is connected to the output end of the eighth inverter, the NMOSFET source of the tenth inverter is connected to the output end of the ninth inverter, the input ends of the eighth inverter, the ninth inverter and the tenth inverter are connected, and the first signal conditioning circuit is output through the output end of the tenth inverter.

2. The processing circuit according to claim 1, characterized in that: The width-to-length ratio of the PMOSFET of the eighth inverter is greater than that of the PMOSFET of the ninth inverter, the width-to-length ratio of the NMOSFET of the ninth inverter is greater than that of the NMOSFET of the eighth inverter, the width-to-length ratio of the NMOSFET of the tenth inverter is the same as that of the NMOSFET of the ninth inverter, and the width-to-length ratio of the PMOSFET of the tenth inverter is the same as that of the PMOSFET of the eighth inverter.

3. The processing circuit according to claim 1, characterized in that: The first inverter group includes: a first inverter, a second inverter and a third inverter, the PMOSFET source of the third inverter is connected to the output end of the first inverter, and the NMOSFET source of the third inverter is connected to the output end of the second inverter; the second inverter group includes: a fourth inverter, a fifth inverter and a sixth inverter, the PMOSFET source of the sixth inverter is connected to the output end of the fourth inverter, and the NMOSFET source of the sixth inverter is connected to the output end of the fifth inverter; the input end of the first inverter, the input end of the second inverter, the input end of the third inverter, the input end of the fourth inverter, the input end of the fifth inverter, the input end of the sixth inverter and the input end of the seventh inverter are connected.

4. The processing circuit according to claim 3, characterized in that: The width-to-length ratio of the NMOSFET of the first inverter is smaller than that of the NMOSFET of the second inverter, and the width-to-length ratio of the PMOSFET of the first inverter is larger than that of the PMOSFET of the second inverter; the width-to-length ratio of the NMOSFET of the fourth inverter is smaller than that of the NMOSFET of the fifth inverter, and the width of the PMOSFET of the fourth inverter is larger than that of the PMOSFET of the fifth inverter.

5. The processing circuit according to claim 4, characterized in that: The width-to-length ratio of the NMOSFET of the third inverter is the same as that of the NMOSFET of the second inverter, and the width-to-length ratio of the PMOSFET of the third inverter is the same as that of the PMOSFET of the first inverter; the width-to-length ratio of the NMOSFET of the sixth inverter is the same as that of the NMOSFET of the fifth inverter, and the width-to-length ratio of the PMOSFET of the sixth inverter is the same as that of the PMOSFET of the fourth inverter.

6. The processing circuit according to claim 5, characterized in that: The width-to-length ratio of the NMOSFET of the third inverter is smaller than that of the NMOSFET of the sixth inverter, the width-to-length ratio of the PMOSFET of the third inverter is larger than that of the PMOSFET of the sixth inverter, the width-to-length ratio of the NMOSFET of the seventh inverter is the same as that of the NMOSFET of the sixth inverter, and the width-to-length ratio of the PMOSFET of the seventh inverter is the same as that of the PMOSFET of the third inverter.

7. The processing circuit according to claim 1, characterized in that: The RF front-end module includes an amplifier and a filter. The amplifier amplifies the input signal, and the amplified signal enters the filter.

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