A low-power UWB despreader implementation device

Abstract

The present invention provides a low-power UWB despreader implementation device, which comprises: a spread spectrum code sequence shift processing unit is electrically connected to a read-only memory and a multiplier group respectively, and reads a local spread spectrum code sequence from the read-only memory before the despreading work starts; after the despreading work starts, the spread spectrum code sequence shift processing unit performs a two-bit circular right shift on the local spread spectrum code sequence to cover the previous local spread spectrum code sequence; a multiplexer is electrically connected to an address pointer generation unit and a data cache register group respectively; the multiplexer outputs ADC data to the data cache register group according to the control of the address pointer generation unit; in each sampling period, the data cache register group only receives one group of ADC data; the spread spectrum code sequence shift processing unit and the data cache register group are electrically connected to the multiplier group as two inputs respectively; after the multiplication operation is performed, the result is used as the input of a multi-stage adder, and a multi-stage addition operation is performed to obtain a final despreading result.

Description

Technical Field

[0001] The invention relates to the technical field of ultra-wideband technology, and in particular to a low-power UWB despreader implementation device. Background Art

[0002] UWB (Ultra-Wideband) is a communication technology with a bandwidth exceeding 500MHz. It was first used in radar and remote sensing systems and was allowed to be used in the commercial field in 2002. UWB can not only transmit at a high data rate, but is also good at high-precision positioning and ranging. With the release of the 802.15.4z standard, safe, real, centimeter-level ranging and positioning make it widely used in high-precision positioning scenarios required by other IoTs such as automobiles, mobile phones, homes, smart buildings, etc. UWB has the advantages of low power consumption, high-speed transmission, strong anti-multipath capability, and high security. Among them, low power consumption is one of its biggest advantages. The extremely short pulse signal sent by UWB has a transmission power of no more than -41.3dBm / MHz. The signal is submerged in noise, which also brings difficulties to reception.

[0003] At present, UWB uses spread spectrum technology to solve the above problems. Taking direct sequence spread spectrum (DS-SS) as an example, the ultra-wideband pulse signal is modulated by a pseudo-random noise sequence (PN) to expand the signal spectrum, which can improve the spectrum smoothness, reduce the transmission power, and provide multiple access technology. The receiver needs to use the same spread spectrum code as the sender to demodulate the received signal, that is, despreading technology, to restore the original information. The maximum length of the UWB spread spectrum code is 127, and the duty cycle is 1 / 4. When the oversampling rate Fs=2, it is necessary to cache 1016 sample data and perform 1016 multiplication and accumulation operations. The power consumption of the despreader reaches tens of mW.

[0004] Therefore, it is necessary to provide a low-power UWB despreader implementation device to effectively solve the above problems. Summary of the invention

[0005] The present invention aims at solving the problems and shortcomings of the prior art and provides a low-power UWB despreader implementation device, so as to reduce the power consumption in the UWB despreading process.

[0006] The embodiment of the present invention provides a low-power UWB despreader implementation device, including:

[0007] Read-only memory, spread spectrum code sequence shift processing unit, address pointer generation unit, multi-way data selector, data cache register group, multiplier group, multi-stage adder;

[0008] The read-only memory is electrically connected to the spread spectrum code sequence shift processing unit, and the spread spectrum code sequence shift processing unit is electrically connected to the multiplier group. The read-only memory is used to store the spread spectrum code sequence used by the ultra-wideband. The spread spectrum code sequence shift processing unit includes a spread spectrum code sequence shift register and a first trigger. Before the despreading work starts, the spread spectrum code sequence shift register reads the specified spread spectrum code sequence from the read-only memory as the local spread spectrum code sequence. After the despreading work starts, the local spread spectrum code sequence is delayed by one clock cycle by the first trigger, and then a two-bit cyclic shift is performed to cover the previous local spread spectrum code sequence.

[0009] The address pointer generating unit is electrically connected to the multiplexer, and the multiplexer is electrically connected to the data buffer register group. The address pointer generating unit includes an address pointer generator and a second trigger. After the despreading work starts, the address pointer generator performs address pointer counting with a step length of 1 after a clock cycle delay of the second trigger. The multiplexer selects a control switch according to the address pointer selection to output the ADC data to one of the data buffer registers. The data buffer register only receives one group of the ADC data in each sampling cycle.

[0010] The spread spectrum code sequence shift processing unit and the data buffer register group are electrically connected to the multiplier group respectively, and the data of the spread spectrum code sequence shift register and the data of the data buffer register are used as inputs of the multiplier group for multiplication operation, and the result is used as the output result of the multiplier group;

[0011] The multi-stage adder is electrically connected to the multiplier group, and the output result of the multiplier group is used as the input of the multi-stage adder for addition operation. The multi-stage adder adopts a multi-stage algorithm to perform multi-stage segmented accumulation calculation on the output result of the multiplier group to obtain the final despreading result.

[0012] Preferably, the storage space of the read-only memory is 32*L*Fs, wherein L is the maximum length of the spread spectrum code sequence, and Fs is the ADC oversampling rate.

[0013] Preferably, the two-bit cyclic shift is performed to supplement the lowest bit to the highest bit, and the obtained result is stored in the spread spectrum code sequence shift register, waiting for the first trigger to be triggered again to perform the next cyclic right shift.

[0014] Preferably, the storage space of the spread spectrum code sequence shift register is L*Fs, wherein L is the maximum length of the spread spectrum code sequence, and Fs is the ADC oversampling rate.

[0015] Preferably, the number of the data cache register groups is N, the N data cache registers are all electrically connected to the multiplexer, the nth data cache register is electrically connected to the nth multiplier, wherein n is an integer between 0 and (N-1).

[0016] Preferably, the length of the address pointer generator is L*Fs. After the second trigger is triggered, the data in the next address pointer generator is read, and the data is the address of the data cache register group to be used. After this operation is completed, wait for the next second trigger to be triggered.

[0017] Preferably, each of the data cache register groups adopts a circular addressing structure, and each data cache register in the data cache register group can work independently without being affected by other data cache registers. In one clock cycle, only one data cache register has circuit flip power consumption.

[0018] Preferably, the multiplier group includes N 2bit*W multipliers, W is the sampling bit width of the ADC, and the two inputs of the nth multiplier come from the spread spectrum code shift sequence shift processing unit and the nth data cache register respectively. After the data of the spread spectrum code shift sequence shift processing unit and the data of the nth data cache register are multiplied by the nth multiplier, the output result of the nth multiplier is the input of the multi-stage adder, wherein n is an integer between 0 and (N-1).

[0019] Preferably, the adder group includes a first-level adder, a second-level adder and a third-level adder, the first-level adder is electrically connected to the multiplier group, the first-level adder is electrically connected to the second-level adder, the second-level adder is electrically connected to the third-level adder, the output of the multiplier group is the input of the first-level adder, every sixteen data are subjected to the first segmented accumulation, the calculation result of the first-level adder is output to the second-level adder, the second-level adder performs the second segmented accumulation, the calculation result of the second adder is output to the third-level adder, the third-level adder performs the final accumulation, and the result is the final despreading result.

[0020] Preferably, the final despreading result is calculated by the following formula:

[0021] ,

[0022] in, is the final despreading result, is the spreading code period, is the pulse repetition period, For the ADC data, is the spreading code.

[0023] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0024] An embodiment of the present invention provides a low-power UWB despreader implementation device, comprising: a read-only memory, a spread spectrum code sequence shift processing unit, an address pointer generating unit, a multi-way data selector, a data cache register group, a multiplier group, and a multi-stage adder; the read-only memory is electrically connected to the spread spectrum code sequence shift processing unit, the spread spectrum code sequence shift processing unit is electrically connected to the multiplier group, the read-only memory is used to store the spread spectrum code sequence used by ultra-wideband, the spread spectrum code sequence shift processing unit comprises a spread spectrum code sequence shift register and a first trigger, and the spread spectrum code sequence is shifted before the despreading work starts. The sequence shift register reads the designated spread spectrum code sequence from the read-only memory as the local spread spectrum code sequence. After the despreading work starts, the local spread spectrum code sequence is delayed by one clock cycle by the first trigger and then cyclically shifted by two bits to cover the previous local spread spectrum code sequence. The address pointer generating unit is electrically connected to the multiplexer, and the multiplexer is electrically connected to the data buffer register group. The address pointer generating unit includes an address pointer generator and a second trigger. After the despreading work starts, the address pointer generator performs address pointer counting with a step length of 1 after a clock cycle delay by the second trigger. The multiplexer selects a control switch according to the address pointer selection to output the ADC data to one of the data buffer registers. The data buffer register receives only one group of the ADC data in each sampling cycle. The spread spectrum code sequence shift processing unit and the data buffer register group are electrically connected to the multiplier group respectively. The data of the spread spectrum code sequence shift register and the data of the data buffer register are used as the input of the multiplier group for multiplication operation, and the result is used as the output result of the multiplier group. The multiplier is electrically connected to the multiplier group, the output result of the multiplier group is used as the input of the multi-stage adder for addition operation, the multi-stage adder adopts a multi-stage algorithm to perform multi-stage segmented accumulation calculation on the output result of the multiplier group to obtain the final despreading result, through the coordinated work of the read-only memory, the spread spectrum code sequence shift processing unit, the address pointer generation unit, the multi-way data selector, the data cache register group, the multiplier group, and the multi-stage adder, when the despreader starts to work, the multi-way data selector only selects one data cache register, thereby simplifying the hardware structure of the despreader and reducing the power consumption of the despreader;

[0025] Furthermore, each of the data cache registers in the data cache register group adopts a circular addressing structure, and each data cache register in the data cache register group can work independently without being affected by other data cache registers. In one clock cycle, only one data cache register has circuit flip power consumption, thereby further reducing the power consumption of the despreader;

[0026] Further, the adder group includes a first-stage adder, a second-stage adder and a third-stage adder, the first-stage adder is electrically connected to the multiplier group, the first-stage adder is electrically connected to the second-stage adder, the second-stage adder is electrically connected to the third-stage adder, the output of the multiplier group is the input of the first-stage adder, every sixteen data are subjected to the first segmented accumulation, the calculation result of the first-stage adder is output to the second-stage adder, the second-stage adder performs the second segmented accumulation, the calculation result of the second adder is output to the third-stage adder, the third-stage adder performs the final accumulation, and the result is the final despreading result. By using the addition tree structure, the circuit timing can be significantly improved, which is convenient for inserting the sequential logic unit;

[0027] Furthermore, compared with conventional despreader hardware, the despreader provided by the present invention reduces average power consumption from 39 mW to 20 mW, achieving a power consumption reduction of approximately 50%, while the hardware cost remains unchanged and the despreading function remains stable. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are some embodiments of the present invention, not all embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0029] Figure 1 A schematic diagram of the structure of a low-power UWB despreader implementation device according to a preferred embodiment of the present invention;

[0030] Figure 2 The present invention is a schematic diagram of the structure of a multi-stage adder of a low-power UWB despreader implementation device according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The technical solution of the present invention is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0033] Based on the problem that the hardware implementation of the despreading function in the UWB ultra-wideband chip in the prior art is complex and the power consumption is high, the embodiment of the present invention provides a low-power UWB despreader implementation device, which can significantly reduce the power consumption in the UWB despreading process.

[0034] Figure 1 FIG. 1 is a schematic structural diagram of a low-power UWB despreader implementation device according to a preferred embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of a multi-stage adder of a low-power UWB despreader implementation device of a preferred embodiment of the present invention. Figure 1 and Figure 2 , a low-power UWB despreader implementation device, comprising: a read-only memory, a spread spectrum code sequence shift processing unit, an address pointer generation unit, a multi-way data selector, a data cache register group, a multiplier group, and a multi-stage adder;

[0035] The read-only memory is electrically connected to the spread spectrum code sequence shift processing unit, and the spread spectrum code sequence shift processing unit is electrically connected to the multiplier group. The read-only memory is used to store the spread spectrum code sequence used by the ultra-wideband. The spread spectrum code sequence shift processing unit includes a spread spectrum code sequence shift register and a first trigger. Before the despreading work starts, the spread spectrum code sequence shift register reads the specified spread spectrum code sequence from the read-only memory as the local spread spectrum code sequence. After the despreading work starts, the local spread spectrum code sequence is delayed by one clock cycle by the first trigger, and then a two-bit cyclic shift is performed to cover the previous local spread spectrum code sequence.

[0036] The address pointer generating unit is electrically connected to the multiplexer, and the multiplexer is electrically connected to the data buffer register group. The address pointer generating unit includes an address pointer generator and a second trigger. After the despreading work starts, the address pointer generator performs address pointer counting with a step length of 1 after a clock cycle delay of the second trigger. The multiplexer selects a control switch according to the address pointer selection to output the ADC data to one of the data buffer registers. The data buffer register only receives one group of the ADC data in each sampling cycle.

[0037] The spread spectrum code sequence shift processing unit and the data buffer register group are electrically connected to the multiplier group respectively, and the data of the spread spectrum code sequence shift register and the data of the data buffer register are used as inputs of the multiplier group for multiplication operation, and the result is used as the output result of the multiplier group;

[0038] The multi-stage adder is electrically connected to the multiplier group, and the output result of the multiplier group is used as the input of the multi-stage adder for addition operation. The multi-stage adder adopts a multi-stage algorithm to perform multi-stage segmented accumulation calculation on the output result of the multiplier group to obtain the final despreading result.

[0039] In a specific implementation, the storage space of the read-only memory is 32*L*Fs, where L is the maximum length of the spread spectrum code sequence and Fs is the ADC oversampling rate.

[0040] In a specific implementation, the two-bit cyclic shift is performed to supplement the lowest bit to the highest bit, and the obtained result is stored in the spread spectrum code sequence shift register, waiting for the first trigger to be triggered again to perform the next cyclic right shift.

[0041] The least significant bit is supplemented to the most significant bit by specifically supplementing the least significant 2 bits to the most significant 2 bits.

[0042] In a specific implementation, the storage space of the spread spectrum code sequence shift register is L*Fs, where L is the maximum length of the spread spectrum code sequence and Fs is the ADC oversampling rate.

[0043] In a specific implementation, the number of the data cache register groups is N, the N data cache registers are all electrically connected to the multiplexer, the nth data cache register is electrically connected to the nth multiplier, where n is an integer between 0 and (N-1).

[0044] In a specific implementation, the length of the address pointer generator is L*Fs. After the second trigger is triggered, the data in the next address pointer generator is read. The data is the address of the data cache register group to be used. After this operation is completed, the next second trigger is triggered. The step length of the address pointer count is 1. When it exceeds the maximum address limit, it starts counting from address 0.

[0045] In a specific implementation, each of the data cache registers adopts a circular addressing structure, and each data cache register in the data cache register group can work independently without being affected by other data cache registers. In one clock cycle, only one data cache register has circuit flip power consumption. That is to say, only one group of data cache registers is updated in each clock cycle, and the values ​​of other data cache registers remain unchanged. When the last address is cached, the next group of data will return to the first data cache register in the cache and overwrite the previous data.

[0046] In a specific implementation, the multiplier group includes N 2bit*W multipliers, W is the sampling bit width of the ADC, and the two inputs of the nth multiplier come from the spread spectrum code shift sequence shift processing unit and the nth data cache register respectively. After the data of the spread spectrum code shift sequence shift processing unit and the data of the nth data cache register are multiplied by the nth multiplier, the output result of the nth multiplier is the input of the multi-stage adder, wherein n is an integer between 0 and (N-1).

[0047] In a specific implementation, the adder group includes a first-level adder, a second-level adder and a third-level adder, the first-level adder is electrically connected to the multiplier group, the first-level adder is electrically connected to the second-level adder, the second-level adder is electrically connected to the third-level adder, the output of the multiplier group is the input of the first-level adder, every sixteen data are first segmented and accumulated, the calculation result of the first-level adder is output to the second-level adder, the second-level adder performs a second segmented accumulation, the calculation result of the second adder is output to the third-level adder, the third-level adder performs the final accumulation, and the result is the final despreading result.

[0048] Among them, the second-stage adder performs the second segmented accumulation. The second-stage adder is also a multi-input adder. Similar to the first-stage adder, it divides every 16 data into one segment. The first stage requires N / 16 adders, and the second stage requires N / 16 / 16 adders.

[0049] In a specific implementation, the final despreading result is calculated by the following formula:

[0050] ,

[0051] in, is the final despreading result, is the spreading code period, is the pulse repetition period, For the ADC data, is the spreading code.

[0052] In summary, an embodiment of the present invention provides a low-power UWB despreader implementation device, comprising: a read-only memory, a spread spectrum code sequence shift processing unit, an address pointer generating unit, a multi-way data selector, a data cache register group, a multiplier group, and a multi-stage adder; the read-only memory is electrically connected to the spread spectrum code sequence shift processing unit, the spread spectrum code sequence shift processing unit is electrically connected to the multiplier group, the read-only memory is used to store the spread spectrum code sequence used by ultra-wideband, the spread spectrum code sequence shift processing unit includes a spread spectrum code sequence shift register and a first trigger, and before the despreading work starts, the first trigger is used to store the spread spectrum code sequence used by ultra-wideband. The spread spectrum code sequence shift register reads a designated spread spectrum code sequence from the read-only memory as a local spread spectrum code sequence. After the despreading work starts, the local spread spectrum code sequence is delayed by one clock cycle through the first trigger, and then a two-bit cyclic shift is performed to cover the previous local spread spectrum code sequence. The address pointer generation unit is electrically connected to the multiplexer, and the multiplexer is electrically connected to the data cache register group. The address pointer generation unit includes an address pointer generator and a second trigger. After the despreading work starts, the address pointer generator is delayed by one clock cycle through the second trigger. After the clock cycle delay, the address pointer count is performed with a step length of 1. The multi-way data selector selects the control switch according to the address pointer to output the ADC data to one of the data buffer registers. The data buffer register only receives one group of the ADC data in each sampling cycle. The spread spectrum code sequence shift processing unit and the data buffer register group are electrically connected to the multiplier group respectively. The data of the spread spectrum code sequence shift register and the data of the data buffer area register are used as the input of the multiplier group for multiplication operation, and the result is used as the output result of the multiplier group. The adder is electrically connected to the multiplier group, the output result of the multiplier group is used as the input of the multi-stage adder for addition operation, the multi-stage adder adopts a multi-stage algorithm to perform multi-stage segmented accumulation calculation on the output result of the multiplier group to obtain the final despreading result, through the coordinated work of the read-only memory, the spread spectrum code sequence shift processing unit, the address pointer generation unit, the multi-way data selector, the data cache register group, the multiplier group, and the multi-stage adder, when the despreader starts to work, the multi-way data selector only selects one data cache register, thereby simplifying the hardware structure of the despreader and reducing the power consumption of the despreader;

[0053] Furthermore, each of the data cache registers in the data cache register group adopts a circular addressing structure, and each data cache register in the data cache register group can work independently without being affected by other data cache registers. In one clock cycle, only one data cache register has circuit flip power consumption, thereby further reducing the power consumption of the despreader;

[0054] Further, the adder group includes a first-stage adder, a second-stage adder and a third-stage adder, the first-stage adder is electrically connected to the multiplier group, the first-stage adder is electrically connected to the second-stage adder, the second-stage adder is electrically connected to the third-stage adder, the output of the multiplier group is the input of the first-stage adder, every sixteen data are subjected to the first segmented accumulation, the calculation result of the first-stage adder is output to the second-stage adder, the second-stage adder performs the second segmented accumulation, the calculation result of the second adder is output to the third-stage adder, the third-stage adder performs the final accumulation, and the result is the final despreading result. By using the addition tree structure, the circuit timing can be significantly improved, which is convenient for inserting the sequential logic unit;

[0055] Furthermore, compared with conventional despreader hardware, the despreader provided by the present invention reduces average power consumption from 39 mW to 20 mW, achieving a power consumption reduction of approximately 50%, while the hardware cost remains unchanged and the despreading function remains stable.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-power UWB despreader implementation device, characterized in that: It includes: Read-only Memory, spread spectrum code sequence shift processing unit, address pointer generation unit, multi-way data selector, data cache register group, multiplier group, multi-stage adder; The read-only memory is electrically connected to the spread spectrum code sequence shift processing unit, and the spread spectrum code sequence shift processing unit is electrically connected to the multiplier group. The read-only memory is used to store the spread spectrum code sequence used by the ultra-wideband. The spread spectrum code sequence shift processing unit includes a spread spectrum code sequence shift register and a first trigger. Before the despreading work starts, the spread spectrum code sequence shift register reads the specified spread spectrum code sequence from the read-only memory as the local spread spectrum code sequence. After the despreading work starts, the local spread spectrum code sequence is delayed by one clock cycle by the first trigger, and then a two-bit cyclic shift is performed to cover the previous local spread spectrum code sequence. The address pointer generating unit is electrically connected to the multiplexer, and the multiplexer is electrically connected to the data buffer register group. The address pointer generating unit includes an address pointer generator and a second trigger. After the despreading work starts, the address pointer generator performs address pointer counting with a step length of 1 after a clock cycle delay of the second trigger. The multiplexer selects a control switch according to the address pointer selection to output the ADC data to one of the data buffer registers. The data buffer register only receives one group of the ADC data in each sampling cycle. The spread spectrum code sequence shift processing unit and the data buffer register group are electrically connected to the multiplier group respectively, and the data of the spread spectrum code sequence shift register and the data of the data buffer register are used as inputs of the multiplier group for multiplication operation, and the result is used as the output result of the multiplier group; The multi-stage adder is electrically connected to the multiplier group, and the output result of the multiplier group is used as the input of the multi-stage adder for addition operation. The multi-stage adder adopts a multi-stage algorithm to perform multi-stage segmented accumulation calculation on the output result of the multiplier group to obtain the final despreading result.

2. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: The storage space of the read-only memory is 32*L*Fs, where L is the maximum length of the spread spectrum code sequence and Fs is the ADC oversampling rate.

3. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: The two-bit circular shift is performed to supplement the lowest bit to the highest bit, and the obtained result is stored in the spread spectrum code sequence shift register, waiting for the first trigger to be triggered again to perform the next circular right shift.

4. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: The storage space of the spread spectrum code sequence shift register is L*Fs, where L is the maximum length of the spread spectrum code sequence and Fs is the ADC oversampling rate.

5. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: The number of the data cache register groups is N, the N data cache registers are all electrically connected to the multi-way data selector, the nth data cache register is electrically connected to the nth multiplier, wherein n is an integer between 0 and (N-1).

6. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: The length of the address pointer generator is L*Fs. After the second trigger is triggered, the data in the next address pointer generator is read. The data is the address of the data cache register group to be used. After this operation is completed, wait for the next second trigger to be triggered.

7. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: Each of the data cache registers adopts a circular addressing structure, and each data cache register in the data cache register group can work independently without being affected by other data cache registers. In one clock cycle, only one data cache register has circuit flip power consumption.

8. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: The multiplier group includes N 2bit*W multipliers, W is the sampling bit width of the ADC, and the two inputs of the nth multiplier come from the spread spectrum code shift sequence shift processing unit and the nth data cache register respectively. After the data of the spread spectrum code shift sequence shift processing unit and the data of the nth data cache register are multiplied by the nth multiplier, the output result of the nth multiplier is the input of the multi-stage adder, wherein n is an integer between 0 and (N-1).

9. A low-power UWB despreader implementation device as claimed in claim 1, characterized in that: The adder group includes a first-level adder, a second-level adder and a third-level adder, the first-level adder is electrically connected to the multiplier group, the first-level adder is electrically connected to the second-level adder, the second-level adder is electrically connected to the third-level adder, the output of the multiplier group is the input of the first-level adder, every sixteen data are first segmented and accumulated, the calculation result of the first-level adder is output to the second-level adder, the second-level adder performs a second segmented accumulation, the calculation result of the second adder is output to the third-level adder, the third-level adder performs the final accumulation, and the result is the final despreading result.

10. The low-power UWB despreader implementation device according to claim 1, characterized in that: The final despreading result is calculated by the following formula: ， in, is the final despreading result, is the spreading code period, is the pulse repetition period, For the ADC data, is the spreading code.

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