Semiconductor structure and preparation method thereof, and three-dimensional memory

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a three-dimensional memory, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims at solving the problem that a grid electrode induces drain electrode leakage in the memory. The semiconductor structure includes a substrate, an active pillar, and a gate structure. The active columns are located on the substrate and extend in the direction perpendicular to the substrate. The gate structure surrounds a portion of the side of the active pillar. The gate structure is provided with a first surface and a second surface which are oppositely arranged, the first surface and the second surface are arranged at intervals in the direction perpendicular to the substrate, and the first surface is farther away from the substrate relative to the second surface. The work function of the gate structure is gradually increased in the direction from the first surface to the second surface. The gate structure with a higher work function can maintain enough threshold voltage, the gate structure with a low work function can improve the problem of drain leakage induced by the gate, and the semiconductor structure is applied to a three-dimensional memory to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, a three-dimensional memory, a storage system and an electronic device. Background Art

[0002] As the size of dynamic random access memory (DRAM) continues to shrink, gate-all-around vertical channel transistors have become a promising approach to achieve 4F 2 The key technology of DRAM memory cells can reduce the need for advanced lithography technology, thereby achieving higher density integration of DRAM. However, the performance and process of DRAM need to be further improved. Summary of the invention

[0003] Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, a three-dimensional memory, a storage system, and an electronic device, aiming to improve the problem of gate induced drain leakage.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a semiconductor structure is provided. The semiconductor structure includes a substrate, an active column and a gate structure. The active column is located on the substrate and extends in a direction perpendicular to the substrate. The gate structure surrounds a part of the side surface of the active column. The gate structure has a first surface and a second surface that are arranged opposite to each other, the first surface and the second surface are arranged at intervals in a direction perpendicular to the substrate, and the first surface is farther away from the substrate than the second surface. Along the direction from the first surface to the second surface, the work function of the gate structure gradually increases.

[0006] It should be noted that "gradually increasing" means: the work function of the gate structure increases discontinuously, for example, the gate structure may be formed by stacking multiple film layers with different work functions, and the work functions of the different film layers increase along the direction from the first surface to the second surface. Alternatively, the work function of the gate structure increases continuously, and the gate structure may be a whole film layer, and the work function of the film layer gradually increases from small to large along the direction from the first surface to the second surface.

[0007] The semiconductor structure provided by the above-mentioned embodiment of the present disclosure enables the gate structure to have a lower work function at the portion close to the source than at the portion close to the drain. Since the gate structure with a low work function can carry a higher voltage, the electric field strength in the channel close to the drain can be reduced, which is beneficial to improving the problem of gate-induced drain leakage.

[0008] Furthermore, through the above arrangement, the portion of the gate structure close to the drain has a higher work function than the portion of the gate structure close to the source. Since the main parameter that determines the threshold voltage is the work function of the gate structure, the higher the work function of the gate structure, the higher the threshold voltage. The higher the threshold voltage, the less leakage is generated when the device is in the cut-off state. The gate structure of the present application can improve the problem of gate-induced drain leakage while ensuring a higher threshold voltage.

[0009] In some embodiments, the semiconductor structure further includes a storage capacitor and a bit line. The storage capacitor is located on a side of the active column close to the first surface. The bit line is located on a side of the active column close to the second surface. The gate structure includes a first sublayer and a second sublayer stacked in sequence in a direction close to the substrate, and the work function of the first sublayer is smaller than the work function of the second sublayer.

[0010] In some embodiments, the material of the first sub-layer includes titanium nitride, the material of the second sub-layer includes titanium nitride, and a nitrogen content in the first sub-layer is lower than a nitrogen content in the second sub-layer.

[0011] In some embodiments, in the extension direction of the active pillar, the thickness of the first sub-layer is less than the thickness of the second sub-layer.

[0012] In some embodiments, the work function of the first sub-layer has a value range of 4 eV to 5 eV, and the work function of the second sub-layer has a value range of 4.16 eV to 5.16 eV.

[0013] On the other hand, a method for preparing a semiconductor structure is provided, comprising: forming an active column on a substrate, the active column extending in a direction perpendicular to the substrate; forming a gate structure, the gate structure surrounding a portion of the side surface of the active column; the gate structure having a first surface and a second surface arranged opposite to each other, the first surface and the second surface being arranged at intervals in a direction perpendicular to the substrate, and the first surface being farther away from the substrate than the second surface; and the work function of the gate structure gradually increases in a direction from the first surface to the second surface.

[0014] In some embodiments, the substrate includes a first sub-portion close to the active pillar; before forming the gate structure, the preparation method further includes: doping the first sub-portion so that the first sub-portion forms a first conductive layer. Etching the first conductive layer to form a bit line. Forming a first insulating layer, the first insulating layer covers the bit line, and the first insulating layer also surrounds a portion of the active pillar, and the portion of the active pillar surrounded by the first insulating layer is a first pole.

[0015] In some embodiments, the forming of the gate structure includes: sequentially forming a third conductive layer and a second conductive layer on the first insulating layer, etching the second conductive layer and the third conductive layer to form a first sublayer and a second sublayer, wherein the first sublayer and the second sublayer constitute the gate structure.

[0016] In some embodiments, after forming the gate structure, the preparation method further includes: forming a second insulating layer, the second insulating layer covers the gate structure, and the second insulating layer also surrounds part of the active column, and the part of the active column surrounded by the second insulating layer is the second pole. Doping the exposed end of the active column away from the third conductive layer to form a conductive contact portion. Forming a storage capacitor, the storage capacitor is electrically connected to the conductive contact portion.

[0017] In another aspect, a three-dimensional memory is provided, wherein the three-dimensional memory comprises the semiconductor structure as described in some embodiments above, or the semiconductor structure is prepared by the method for preparing the semiconductor structure as described above, and a peripheral device electrically connected to the semiconductor structure.

[0018] In yet another aspect, a storage system is provided, comprising: the three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0019] On the other hand, an electronic device is provided, comprising a circuit board and the storage system as described above, wherein the circuit board is electrically connected to the storage system.

[0020] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, three-dimensional memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure or the actual process of the methods.

[0022] Figure 1 is a block diagram of an electronic device according to some embodiments;

[0023] Figure 2 is a block diagram of a storage system according to some embodiments;

[0024] Figure 3 is a block diagram of a storage system according to some other embodiments;

[0025] Figure 4 is a block diagram of a three-dimensional memory according to some embodiments;

[0026] Figure 5 is a schematic diagram of a gate induced drain leakage effect according to some embodiments;

[0027] Figure 6 is a schematic structural diagram of a semiconductor structure according to some embodiments;

[0028] Figure 7 is a schematic structural diagram of a semiconductor structure according to some other embodiments;

[0029] Figure 8 is a flow chart of a method for manufacturing a semiconductor structure according to some embodiments;

[0030] Fig. 9 is a schematic diagram of a method for manufacturing a semiconductor structure according to some embodiments;

[0031] Fig.10 is a schematic diagram of a method for manufacturing a semiconductor structure according to some embodiments;

[0032] Fig.11 is a schematic diagram of a method for manufacturing a semiconductor structure according to some embodiments;

[0033] Fig.12 is a schematic diagram of a method for manufacturing a semiconductor structure according to some embodiments;

[0034] Fig.13 is a schematic diagram of a method for manufacturing a semiconductor structure according to some embodiments;

[0035] Fig.14 is a schematic diagram of a method for manufacturing a semiconductor structure according to some embodiments;

[0036] Fig.15 is a flow chart of a method for manufacturing a semiconductor structure according to some embodiments;

[0037] Fig.16 is a flow chart of a method for manufacturing a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0039] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0040] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0041] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0042] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0043] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0044] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0045] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0046] As used in the present disclosure, whether a component (e.g., layer, structure, or device) is "on," "above," or "below" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate of the semiconductor structure in a direction perpendicular to the substrate when the substrate is located in the lowest plane of the semiconductor structure in a direction perpendicular to the substrate. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0047] The transistors provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or a portion may be N-type transistors and the other portion may be P-type transistors.

[0048] Some embodiments of the present disclosure provide an electronic device. Figure 1 FIG. 6 is a block diagram of an electronic device 6000 provided in some embodiments of the present disclosure. Figure 1 As shown, the electronic device 6000 includes a storage system 4000 and a circuit board 7000. The storage system 4000 is electrically connected to the circuit board 7000. In addition, the electronic device 6000 may also include at least one of a central processing unit (CPU) and a cache.

[0049] Exemplarily, the electronic device 6000 can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0050] Some embodiments of the present disclosure further provide a storage system 4000. The storage system 4000 can be applied to the above-mentioned electronic device 6000. Of course, the storage system 4000 can also be applied to other electronic devices, and the present disclosure does not limit this.

[0051] Figure 2 4 is a block diagram of a storage system 4000 provided in some embodiments of the present disclosure. Figure 2 As shown, the storage system 4000 includes a controller 5000 and a three-dimensional memory 2000. The controller 5000 is coupled to the three-dimensional memory 2000 and is configured to control the three-dimensional memory 2000 to store data. The storage system 4000 can be integrated into various types of storage devices, for example, included in the same package (for example, a universal flash storage (Universal Flash Storage, referred to as UFS) package or an embedded multimedia card (Embedded Multi Media Card, referred to as eMMC) package). That is, the storage system 4000 can be applied to and packaged into different types of electronic products, for example, mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (Virtual Reality, referred to as VR) devices, augmented reality (AugmentedReality, referred to as AR) devices, or any other suitable electronic devices having storage therein.

[0052] In some embodiments, Figure 2 As shown, the storage system 4000 includes a controller 5000 and a three-dimensional memory 2000, and the storage system 4000 can be integrated into a memory card.

[0053] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0054] In other embodiments, Figure 3 As shown, the storage system 4000 includes a controller 5000 and a plurality of three-dimensional memories 2000, and the storage system 4000 is integrated into a solid state drive (SSD).

[0055] In the storage system 4000, in some embodiments, the controller 5000 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices 6000 such as personal computers, digital cameras, mobile phones, etc.

[0056] In other embodiments, the controller 5000 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0057] In some embodiments, the controller 5000 may be configured to manage data stored in the three-dimensional memory 2000 and communicate with an external device (e.g., a host). In some embodiments, the controller 5000 may also be configured to control operations of the three-dimensional memory 2000, such as read, erase, and program operations. In some embodiments, the controller 5000 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 2000, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 5000 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 2000.

[0058] Of course, the controller 5000 may also perform any other suitable functions, such as formatting the three-dimensional memory 2000; for example, the controller 5000 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0059] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Interface (SCSI) protocol, Enhanced Minidisk Interface (ESDI) protocol, Integrated Drive Electronics 6000 (IDE) protocol, and Firewire protocol.

[0060] The above-mentioned controller can be, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.

[0061] Some embodiments of the present disclosure provide a three-dimensional memory 2000. The three-dimensional memory 2000 can be applied to the above-mentioned storage system 4000. Of course, the three-dimensional memory 2000 can be applied to other storage systems, and the present disclosure does not limit this.

[0062] Figure 4 FIG. 2 is a block diagram of a three-dimensional memory 2000 provided according to some embodiments of the present disclosure. Figure 4 As shown, the present disclosure also provides a three-dimensional memory 2000, including a semiconductor structure 1000 and a peripheral device 3000. The peripheral device 3000 is electrically connected to the semiconductor structure 1000. The peripheral device 3000 may include a peripheral circuit. The peripheral circuit is configured to control and sense the array device. The peripheral circuit may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array device, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (e.g., a processor and a programmable logic device (PLD)) or a storage circuit (e.g., a static random access memory (SRAM)).

[0063] Figure 5 Schematic diagram of gate induced drain leakage effect provided by some embodiments of the present disclosure. Figure 5 As shown, the inventors of the present disclosure have found through research that: from the analysis of the device structure, in the transistor, the edge of the gate structure should be aligned with the edge of the source and the drain. However, in the actual production process of the device, the edge of the gate structure cannot be completely aligned with the edge of the source and the drain. Therefore, there is an overlap between the source and the gate structure, and an external electric field is generated in the overlap area, that is, Figure 5Position A in the middle is affected by the external electric field. When the device is turned off, the holes generated by the gate induced drain leakage (GIDL) effect caused by the external electric field move and accumulate in the channel ( Figure 5 In position B), the channel potential is gradually increased. Figure 5 Figure (1) is a schematic diagram of the transistor structure before the GIDL effect occurs, Figure (2) is a schematic diagram of the transistor structure after the GIDL effect occurs, Figure (3) is a schematic diagram of the potential of the transistor before the GIDL effect occurs, and Figure (4) is a schematic diagram of the potential of the transistor after the GIDL effect occurs. Figure 5 The solid line in represents the initial potential of the transistor. Figure 5 The dotted line in represents the transistor potential after the hole moves. After the GIDL effect occurs, the bit line voltage drops from 1V to 0V. After the channel potential increases, the energy barrier between the channel and the bit line decreases, and the continuously decreasing barrier induces drain leakage, electrons flow to the gate structure and storage node, and the leakage current flows to the gate structure and storage node. The leakage current flows from the bit line to the storage node, reducing the potential level of the storage node.

[0064] Therefore, in Figure 5 The stronger the electric field at position A, the stronger the gate induced drain leakage effect (hereinafter referred to as GIDL effect for ease of description) is.

[0065] Based on this, in order to weaken the GIDL effect, some embodiments of the present disclosure provide a semiconductor structure 1000 . Figure 6 and Figure 7 A schematic structural diagram of a semiconductor structure 1000 provided in some embodiments of the present disclosure.

[0066] like Figure 6 and Figure 7 As shown, the semiconductor structure 1000 provided by the present disclosure includes a substrate 100, an active pillar 200 and a gate structure 300. The active pillar 200 is located on the substrate 100 and extends in a direction perpendicular to the substrate 100. The gate structure 300 surrounds a portion of the side surface of the active pillar 200. For example, Figure 6 As shown, the gate structure 300 surrounds the side of the middle section of the active pillar 200, exposing the first pole 210 and the second pole 220 of the active pillar 200. The second pole 220 is the source of the transistor, located at the end of the active pillar 200 away from the substrate 100, and the second pole 220 may include a conductive contact portion 240; the first pole 210 is the drain of the transistor, located at the end of the active pillar 200 close to the substrate 100.

[0067] In this embodiment, the gate structure 300 has a first surface 301 and a second surface 302 that are oppositely disposed. The first surface 301 and the second surface 302 are spaced apart in a direction perpendicular to the substrate 100, and the first surface 301 is farther away from the substrate 100 than the second surface 302. Figure 6 As shown, the first surface 301 can be understood as the top surface of the gate structure 300, and the second surface 302 can be understood as the bottom surface of the gate structure 300. Along the direction from the first surface 301 to the second surface 302, the work function of the gate structure 300 gradually increases. It should be noted that "gradually increase" means that the work function of the gate structure 300 increases discontinuously. For example, the gate structure 300 can be composed of a plurality of film layers with different work functions, and the work functions of different film layers increase along the direction from the first surface 301 to the second surface 302. Alternatively, the work function of the gate structure 300 increases continuously, and the gate structure 300 can be a whole film layer, and along the direction from the first surface 301 to the second surface 302, the work function of the film layer gradually increases from small to large.

[0068] Through the above arrangement, the gate structure 300 has a lower work function at the portion close to the second electrode 220 than at the portion close to the first electrode 210. Since the gate structure 300 with a low work function can carry a higher voltage, the electric field strength in the channel close to the first electrode 210 can be reduced, that is, the gate structure 300 with a low work function can be reduced. Figure 5 The electric field intensity at position A is beneficial to weaken the GIDL effect.

[0069] Furthermore, through the above arrangement, the portion of the gate structure 300 close to the first pole 210 has a higher work function than the portion of the gate structure 300 close to the second pole 220. Since the main parameter that determines the threshold voltage is the work function of the gate structure 300, the higher the work function of the gate structure 300, the higher the threshold voltage. The higher the threshold voltage, the less leakage is generated when the device is in the off state, and the gate structure 300 of the present application can reduce the GIDL effect while ensuring a higher threshold voltage.

[0070] In some embodiments, Figure 6 and Figure 7 As shown, the semiconductor structure 1000 further includes a storage capacitor 400 and a bit line 500. The storage capacitor 400 is located on a side of the active pillar 200 close to the first surface 301. The bit line 500 is located on a side of the active pillar 200 close to the second surface 302.

[0071] In this embodiment, Figure 6As shown, the gate structure 300 includes a first sublayer 310 and a second sublayer 320 stacked in sequence in a direction close to the substrate 100, and the work function of the first sublayer 310 is smaller than the work function of the second sublayer 320. The first sublayer 310 is close to the storage capacitor 400, and the second sublayer 320 is close to the bit line 500. The first sublayer 310 is close to the second electrode 220, and the second sublayer 320 is close to the first electrode 210.

[0072] Compared with the second sublayer 320, the first sublayer 310 has a lower work function, so the first sublayer 310 can carry a higher voltage, thereby reducing the electric field strength in the channel, that is, reducing Figure 5 The electric field strength at position A is conducive to reducing the GIDL effect. Compared with the first sublayer 310, the second sublayer 320 has a higher work function, which is conducive to ensuring a higher threshold voltage. When the device is in the off state, it reduces leakage and helps to reduce the GIDL effect.

[0073] In other embodiments, Figure 7 As shown, the gate structure 300 may include a plurality of sublayers stacked in sequence along a direction close to the substrate 100, and the work functions of the plurality of sublayers increase in sequence along a direction close to the substrate 100. The present disclosure does not limit the number of the plurality of sublayers. For example, the gate structure 300 may include four sublayers, which may include a first sublayer, a second sublayer, a third sublayer and a fourth sublayer along a direction close to the substrate 100, and the work functions of the first sublayer, the second sublayer, the third sublayer and the fourth sublayer increase in sequence. The first sublayer with a relatively low work function is close to the second pole 220, and can carry a higher voltage, reducing the potential in the channel, that is, reducing Figure 5 The potential at position A in the middle is reduced, which is beneficial to weaken the GIDL effect. The second sublayer, the third sublayer and the fourth sublayer can maintain the threshold voltage of the device.

[0074] In some embodiments, Figure 6 As shown, the material of the first sublayer 310 includes titanium nitride. The material of the second sublayer 320 includes titanium nitride. The nitrogen content in the first sublayer 310 is lower than the nitrogen content in the second sublayer 320. The nitrogen content in titanium nitride is related to the work function. The higher the nitrogen content in titanium nitride, the higher the work function of the material composed of it. The embodiment of the present application adjusts the nitrogen content in the first sublayer 310 and the second sublayer 320, that is, adjusts the content ratio of nitrogen to titanium, which is conducive to making the work function of the first sublayer 310 smaller than the work function of the second sublayer 320.

[0075] In some embodiments, Figure 6 and Figure 7 As shown, along the extension direction of the active pillar 200 , the thickness of the first sub-layer 310 is less than the thickness of the second sub-layer 320 .

[0076] The first sublayer 310 is close to the second electrode 220, and the second sublayer 320 is close to the first electrode 210. The GIDL effect mentioned above only occurs in the overlapping area between the second electrode 220 and the gate structure 300, that is, Figure 5 Therefore, the thickness of the first sublayer 310 can meet the function of improving the GIDL effect.

[0077] In addition, the work function of the second sublayer 320 is larger than that of the first sublayer 310, and the second sublayer 320 plays a role in controlling the threshold voltage of the channel. The larger the area of ​​the channel covered by the second sublayer 320, the better the control of the threshold voltage of the channel. Therefore, the thickness of the second sublayer 320 is greater than the thickness of the first sublayer 310, and the area that can cover the channel is larger. In addition, the work function of the second sublayer 320 is higher, so that the threshold voltage of the channel is higher, which is conducive to reducing leakage.

[0078] In some embodiments, Figure 6 As shown, the work function of the first sublayer 310 ranges from 4eV to 5eV, and the work function of the second sublayer 320 ranges from 4.16eV to 5.16eV. The first sublayer 310 with a work function in the range of 4eV to 5eV can better reduce the electric field strength in the channel and improve the GIDL effect. Exemplarily, the work function of the first sublayer 310 can be 4eV, 4.16eV, 4.32eV or 5eV, and the work function of the first sublayer 310 can be in the range of 4eV to 5eV, and the present disclosure does not limit this. The second sublayer 320 with a work function in the range of 4.16eV to 5.16eV can ensure a sufficient threshold voltage, which is conducive to reducing leakage. Exemplarily, the work function of the second sublayer 320 may be 4.16 eV, 4.32 eV, 4.66 eV or 5.16 eV. The work function of the second sublayer 320 may be within the value range of 4.16 eV to 5.16 eV.

[0079] In some embodiments, Figure 7 As shown, the semiconductor structure 1000 has a plurality of bit lines 500, and the plurality of bit lines 500 are arranged along a first direction X and extend along a second direction Y. The first direction X and the second direction Y are both perpendicular to the extending direction of the active pillar 200, and the first direction X intersects the second direction Y. This article only takes the case where the first direction X is perpendicular to the second direction Y as an example for description.

[0080] In this embodiment, there may be multiple active pillars 200 , which are arranged in sequence along the second direction Y and spaced apart from each other, and multiple active pillars 200 are arranged in sequence along the first direction X and a row of active pillars 200 arranged in the second direction Y is connected to a bit line 500 .

[0081] In this embodiment, the number of gate structures 300 may be multiple, and one gate structure 300 surrounds one active pillar 200. The gate structures 300 are sequentially arranged at intervals along the second direction Y, and a row of gate structures 300 along the first direction X are connected to form a word line 303. The number of word lines 303 is multiple, and the multiple word lines 303 are arranged at intervals along the second direction Y and extend along the first direction X. One word line 303 is connected to a row of active pillars 200 arranged along the first direction X.

[0082] In this embodiment, there are multiple storage capacitors 400 , and one storage capacitor 400 is connected to one active pillar 200 .

[0083] refer to Figure 7 , a first electrode 210, a second electrode 220 and a gate structure 300 constitute a transistor. Figure 7 For example, the semiconductor structure 1000 includes a plurality of transistors, the gate structures 300 of the plurality of transistors arranged along the first direction X can be electrically connected to form a word line 303; and the first electrodes 210 of the plurality of active pillars 200 arranged along the second direction Y are electrically connected to the same bit line 500. The word line 303 is used to receive a word line control signal to turn on the transistor, and the bit line 500 is used to receive a bit line control signal to read information from the storage capacitor 400 or write information into the storage capacitor 400.

[0084] In some embodiments, Figure 8 As shown, the present application also provides a method for preparing a semiconductor structure 1000, including: S100-S500.

[0085] S100 , forming an active pillar on a substrate, wherein the active pillar extends in a direction perpendicular to the substrate.

[0086] By way of example, the material of the substrate 100 may be single crystal silicon, polycrystalline silicon, amorphous silicon, or germanium, silicon germanium, gallium arsenide, or other semiconductor materials.

[0087] S200, forming a gate structure, the gate structure surrounding a portion of the side surface of the active column. The gate structure has a first surface and a second surface arranged opposite to each other, the first surface and the second surface are arranged in a direction perpendicular to the substrate, and the first surface is farther away from the substrate than the second surface. Along the direction from the first surface to the second surface, the work function of the gate structure gradually increases.

[0088] refer to Figure 7The portion of the gate structure 300 near the second electrode 220 after the formation has a lower work function than the portion of the gate structure 300 near the first electrode 210. Since the gate structure 300 with a low work function can carry a higher voltage, the electric field strength in the channel near the first electrode 210 can be reduced, that is, the Figure 5 The electric field intensity at position A is beneficial to weaken the GIDL effect.

[0089] Furthermore, through the above arrangement, the portion of the gate structure 300 close to the first pole 210 has a higher work function than the portion of the gate structure 300 close to the second pole 220. Since the main parameter that determines the threshold voltage is the work function of the gate structure 300, the higher the work function of the gate structure 300, the higher the threshold voltage. The higher the threshold voltage, the less leakage is generated when the device is in the off state, and the gate structure 300 of the present application can reduce the GIDL effect while ensuring a higher threshold voltage.

[0090] In some embodiments, Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 As shown, the substrate 100 includes a first sub-portion close to the active pillar 200; before forming the gate structure 300, the preparation method further includes:

[0091] S300 , doping the first sub-portion to form a first conductive layer in the first sub-portion.

[0092] In this step, an ion implantation process may be used to perform doping on the upper surface of the substrate 100 near the active pillar, so that the first sub-portion forms the first conductive layer 330 .

[0093] S400 , etching the first conductive layer to form a bit line.

[0094] In this step, the first conductive layer 330 is etched to be formed into a plurality of parts. The plurality of parts are arranged at intervals along the first direction X and extend along the second direction Y to form the bit line 500 .

[0095] S500, forming a first insulating layer, wherein the first insulating layer covers the bit line and also surrounds a portion of the active column, and a portion of the active column surrounded by the first insulating layer is a first electrode.

[0096] In this step, the first insulating layer 600 covers the bit line 500 and surrounds the first electrode 210, which is beneficial to protecting the reliability of the semiconductor structure 1000. The first electrode 210 is the drain of the transistor.

[0097] In some embodiments, Fig.13 , Fig.14 and Fig.15 As shown, a gate structure 300 is formed, including:

[0098] S201, sequentially forming a third conductive layer and a second conductive layer on the first insulating layer;

[0099] S202 , etching the second conductive layer and the third conductive layer to form a first sublayer and a second sublayer, wherein the first sublayer and the second sublayer constitute a gate structure.

[0100] In this embodiment, Fig.14 As shown, the third conductive layer 350 and the second conductive layer 340 are a whole layer structure, and the third conductive layer 350 is etched to form the second sub-layer 320. The second conductive layer 340 is etched to form the first sub-layer 310. Figure 7 After etching the second conductive layer 340 and the third conductive layer 350, a plurality of first sublayers 310 and second sublayers 320 are formed, which are stacked in sequence in a direction close to the substrate 100. The first sublayers 310 and the second sublayers 320 together constitute a plurality of gate structures. The work function of the first sublayer 310 is smaller than that of the second sublayer 320. The first sublayer 310 has a lower work function than the second sublayer 320, so the first sublayer 310 can carry a higher voltage, thereby reducing the electric field strength in the channel, that is, reducing Figure 5 The electric field strength at position A is conducive to reducing the GIDL effect. Compared with the first sublayer 310, the second sublayer 320 has a higher work function, which is conducive to ensuring a higher threshold voltage. When the device is in the off state, it reduces leakage and helps to reduce the GIDL effect.

[0101] In addition, illustratively, since the titanium nitride material can change the work function of the material by adjusting the content of nitrogen, the first sub-layer 310 and the second sub-layer 320 can be formed by using the titanium nitride material.

[0102] In some embodiments, Figure 7 , Fig.13 , Fig.14 and Fig.16 As shown, after forming the gate structure, the preparation method further includes:

[0103] S701, forming a second insulating layer, wherein the second insulating layer covers the gate structure and also surrounds a portion of the active column, and the portion of the active column surrounded by the second insulating layer is a second electrode.

[0104] In this step, a second insulating layer 700 is formed to cover the gate structure 300, which is beneficial to protecting the reliability of the gate structure 300. The portion of the active pillar surrounded by the second insulating layer is the second electrode, and the second electrode 220 is the source of the transistor.

[0105] S702 , doping the end of the exposed active pillar away from the third conductive layer to form a conductive contact portion. In this step, the end of the exposed active pillar 200 away from the third conductive layer 350 may be doped by ion implantation to form a conductive contact portion 240 .

[0106] S703 , forming a storage capacitor, wherein the storage capacitor is electrically connected to the conductive contact portion.

[0107] In this step, a storage capacitor 400 is formed at one end of the second electrode 220 away from the substrate 100 , and the storage capacitor 400 is electrically connected to the conductive contact portion 240 , so that operations such as reading and writing are performed on the storage capacitor 400 using a transistor structure.

[0108] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; An active pillar, located on the substrate and extending in a direction perpendicular to the substrate; A gate structure surrounding a portion of a side surface of the active pillar; The gate structure has a first surface and a second surface that are arranged opposite to each other, the first surface and the second surface are spaced apart in a direction perpendicular to the substrate, and the first surface is farther away from the substrate than the second surface; along the direction from the first surface to the second surface, the work function of the gate structure gradually increases.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: a storage capacitor, the storage capacitor being located on a side of the active column close to the first surface; a bit line, the bit line being located on a side of the active pillar close to the second surface; The gate structure includes a first sublayer and a second sublayer sequentially stacked in a direction close to the substrate, and a work function of the first sublayer is smaller than a work function of the second sublayer.

3. The semiconductor structure according to claim 2, characterized in that: The material of the first sub-layer includes titanium nitride, the material of the second sub-layer includes titanium nitride, and the nitrogen content in the first sub-layer is lower than the nitrogen content in the second sub-layer.

4. The semiconductor structure according to claim 2, characterized in that: In an extension direction of the active pillar, a thickness of the first sublayer is smaller than a thickness of the second sublayer.

5. The semiconductor structure according to claim 2, characterized in that: The work function of the first sub-layer has a value range of 4 eV to 5 eV, and the work function of the second sub-layer has a value range of 4.16 eV to 5.16 eV.

6. A method for preparing a semiconductor structure, characterized in that: include: forming an active pillar on a substrate, wherein the active pillar extends in a direction perpendicular to the substrate; A gate structure is formed, the gate structure surrounds a portion of the side surface of the active column; the gate structure has a first surface and a second surface that are arranged opposite to each other, the first surface and the second surface are arranged at intervals in a direction perpendicular to the substrate, and the first surface is farther away from the substrate than the second surface; along the direction from the first surface to the second surface, the work function of the gate structure gradually increases.

7. The preparation method according to claim 6, characterized in that: The substrate includes a first sub-portion close to the active pillar; before forming the gate structure, the preparation method further includes: doping the first sub-portion so that the first sub-portion forms a first conductive layer; Etching the first conductive layer to form a bit line; A first insulating layer is formed, wherein the first insulating layer covers the bit line and also surrounds a portion of the active pillar, and a portion of the active pillar surrounded by the first insulating layer is a first electrode.

8. The preparation method according to claim 7, characterized in that: The forming of the gate structure comprises: forming a third conductive layer and a second conductive layer in sequence on the first insulating layer; The second conductive layer and the third conductive layer are etched to form a first sublayer and a second sublayer, wherein the first sublayer and the second sublayer constitute the gate structure.

9. The preparation method according to claim 8, characterized in that: After forming the gate structure, the preparation method further includes: forming a second insulating layer, wherein the second insulating layer covers the gate structure and the second insulating layer also surrounds a portion of the active column, and the portion of the active column surrounded by the second insulating layer is a second electrode; Doping the exposed end of the active column away from the third conductive layer to form a conductive contact portion; A storage capacitor is formed, the storage capacitor being electrically connected to the conductive contact.

10. A three-dimensional memory, characterized in that: include: A semiconductor structure, wherein the semiconductor structure is the semiconductor structure according to any one of claims 1 to 5, or the semiconductor structure is prepared by the method for preparing a semiconductor structure according to any one of claims 6 to 9; The peripheral device is electrically connected to the semiconductor structure.

11. A storage system, characterized in that: include: A three-dimensional memory, wherein the three-dimensional memory is the three-dimensional memory according to claim 10; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

12. An electronic device, characterized in that: It comprises a circuit board and the storage system as claimed in claim 11, wherein the circuit board is electrically connected to the storage system.

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