Semiconductor structure, memory cell and preparation method thereof, memory and electronic equipment

Abstract

The invention relates to a semiconductor structure, a memory cell, a preparation method of the memory cell, a memory and electronic equipment. The semiconductor structure comprises an active column, a first grid electrode and a second grid electrode, the active columns are located in the substrate and extend in the direction perpendicular to the substrate; the top surface of the active column is provided with a first accommodating hole which extends towards the bottom surface of the active column along the axis direction of the active column; the first grid electrode fills the first accommodating hole; the second grid is located on the outer side wall of the active column. The grid control capability can be enhanced, and the storage density is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure, a storage unit and a preparation method thereof, a memory and an electronic device. Background Art

[0002] In the field of integrated circuit design and manufacturing technology, how to realize high-density storage units has always been a difficult problem in the development of dynamic random access memory (DRAM) technology.

[0003] In order to improve storage density, researchers have developed vertical channel transistor (VCT) technology. Since there are fewer restrictions on gate length and source-drain contact area in vertical channel transistors, it has an advantage in improving the density of DRAM storage cells. For vertical channel transistors, high switching ratio and low leakage current have a decisive influence on the operating speed, power consumption and life of DRAM storage cells. Therefore, how to optimize the switching ratio and leakage current of vertical channel transistors has become a problem that needs to be solved urgently. Summary of the invention

[0004] Based on this, the present disclosure provides a semiconductor structure, a memory cell and a method for manufacturing the same, a memory and an electronic device, which can at least enhance the gate control capability and improve the storage density.

[0005] In order to solve the above-mentioned technical problems and other problems, according to some embodiments, one aspect of the present disclosure provides a semiconductor structure, which includes an active column, a first gate and a second gate; the active column is located in a substrate and extends in a direction perpendicular to the substrate; the top surface of the active column has a first accommodating hole extending along its axial direction toward the bottom surface of the active column; the first gate fills the first accommodating hole; the top surface of the first gate is connected to the write transistor; the second gate is located on the outer side wall of the active column.

[0006] In the semiconductor structure of the above embodiment, a vertical active column is formed inside the substrate, and the semiconductor structure is arranged inside the substrate, which is different from the method of forming a transistor on the surface of the substrate through multiple film layers. In addition, by filling the first gate of the first receiving hole in the active column and the second gate arranged on the outer side wall of the active column, the semiconductor structure has a double-gate structure, which is conducive to increasing the contact area between the gate and the channel of the semiconductor structure, so that the gate control ability of the gate is enhanced, thereby reducing the subthreshold swing, improving the switching ratio of the semiconductor structure, and enhancing the electrical performance of the semiconductor structure in the above embodiment.

[0007] In some embodiments, the active pillars include single crystal silicon pillars.

[0008] In some embodiments, the first gate includes a first sub-gate located in the first receiving hole and a second sub-gate located on a top surface of the first sub-gate; a top surface of the first sub-gate is flush with a top surface of the active pillar.

[0009] According to some embodiments, another aspect of the present disclosure provides a memory cell, the memory cell comprising a read transistor and a write transistor; the read transistor comprises the semiconductor structure in the above embodiment; wherein the bottom surface of the active column is connected to the read bit line; the second gate is connected to the read word line; the top surface of the first gate is connected to the write transistor,

[0010] In the storage unit of the above embodiment, the write transistor is connected to the top surface of the first gate, which can realize the vertical stacking of the read transistor and the write transistor, thereby further improving the space utilization rate, which is beneficial to improving the device integration and storage density.

[0011] In some embodiments, the write transistor includes a third gate and a semiconductor layer; the semiconductor layer is located on the top surface of the first gate; a gate trench is provided in the semiconductor layer; the semiconductor layer on the side wall of the gate trench is connected to the write bit line; the third gate fills the gate trench; the top surface of the third gate is connected to the write word line; wherein the semiconductor layer and the third gate are insulated from each other; and the write bit line and the write word line are insulated from each other.

[0012] In some embodiments, the semiconductor layer has an extension portion, which is located on a top surface of the write bit line and extends in a direction away from the third gate.

[0013] In some embodiments, the extension direction of the write bit line is the same as the extension direction of the read word line; the extension direction of the write bit line is the same as or different from the extension direction of the write word line.

[0014] According to some embodiments, another aspect of the present disclosure provides a method for preparing a memory cell. In some embodiments, the method includes:

[0015] A patterned substrate is formed in which at least one active column is formed; the active column extends in a direction perpendicular to the substrate, and the top surface of the active column has a first receiving hole extending along the axis direction thereof toward the bottom surface of the active column;

[0016] forming a first gate in the first receiving hole;

[0017] forming a read bit line on the bottom surface of the active pillar;

[0018] forming a second gate and a read word line connected to the second gate on the outer sidewall of the active column;

[0019] forming a write transistor on a top surface of the first gate;

[0020] The storage unit includes a read transistor and a write transistor; the read transistor includes an active column, a first gate and a second gate.

[0021] In the preparation method of the storage unit of the above embodiment, the active column is prepared by patterning the substrate, so that the active column and the first receiving hole therein are formed inside the substrate. In this way, in the preparation process of the active column of the read transistor, it can be achieved only by patterning the substrate, without forming multiple film layers on the substrate, which can simplify the process flow and save production costs. In addition, by forming a first gate in the first receiving hole and forming a second gate on the outer wall of the active column, the read transistor including the active column, the first gate and the second gate has a dual-gate structure. At the same time, a write transistor is formed on the top surface of the first gate, which can realize the vertical stacking of the read transistor and the write transistor.

[0022] In some embodiments, patterning a substrate, forming at least one active pillar in the substrate, and forming a first gate in a first receiving hole includes:

[0023] Performing a first patterning on the substrate to form a plurality of first receiving holes distributed in an array in the substrate;

[0024] Sequentially forming a first gate dielectric layer and a first gate electrode in the first receiving hole;

[0025] The substrate is patterned for the second time to form a plurality of active pillars distributed in an array in the substrate, and each of the first receiving holes is located at the axis of the active pillar in a one-to-one correspondence.

[0026] In some embodiments, forming a first gate dielectric layer and a first gate in the first receiving hole in sequence includes:

[0027] A first gate dielectric layer and a first sub-gate are sequentially formed in the first receiving hole; the top surface of the first sub-gate is flush with the top surface of the active column;

[0028] After forming a second gate and a read word line connected to the second gate on the outer sidewall of the active pillar, forming a second sub-gate located on the top surface of the first sub-gate;

[0029] The first gate includes a first sub-gate and a second sub-gate.

[0030] In some embodiments, forming a read bit line on a bottom surface of an active pillar includes:

[0031] After the substrate is patterned for the second time, a metal silicidation process is performed on the substrate located at the bottom surface of the active pillars based on the interval between adjacent active pillars to form a read bit line extending along the first direction.

[0032] In some embodiments, forming a second gate and a read word line connected to the second gate on an outer sidewall of the active pillar includes:

[0033] After the substrate is patterned for the second time, a second gate dielectric layer covering the sidewalls of the active pillars and an isolation material layer covering the second gate dielectric layer and filling the spaces between adjacent active pillars are formed;

[0034] removing a portion of the isolation material layer between adjacent active pillars in the second direction to form an etching hole exposing the sidewall of the second gate dielectric layer; the second direction intersects the first direction;

[0035] Based on the etched hole, the isolation material layer on the outer side of the side wall of the corresponding active column in the first direction is etched back to form a second receiving hole on the outer side wall of the corresponding active column;

[0036] A second gate is formed in the second receiving hole, and a read word line connected to the second gate is formed in the etched hole.

[0037] In some embodiments, forming a write transistor on a top surface of the first gate includes:

[0038] forming an interlayer dielectric layer and a write bit line in sequence on the top surface of the first gate in a direction away from the substrate;

[0039] forming a third receiving hole penetrating the interlayer dielectric layer and the write bit line and exposing the top surface of the first gate;

[0040] A semiconductor layer is formed on the inner wall of the third receiving hole and the top surface of the write bit line; the bottom surface of the semiconductor layer is connected to the top surface of the first gate;

[0041] forming a third gate dielectric layer covering the semiconductor layer;

[0042] forming a third gate electrode covering the third gate dielectric layer and filling the third receiving hole, and a write word line connected to the third gate electrode;

[0043] The write transistor includes a semiconductor layer, a third gate dielectric layer and a third gate.

[0044] According to some embodiments, another aspect of the present disclosure provides a memory including the above-mentioned storage unit.

[0045] According to some embodiments, another aspect of the present disclosure provides an electronic device including the above-mentioned memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1A schematic diagram of the structure of a vertical gate-all-around transistor provided in the related art;

[0048] Figure 2 A schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0049] Figure 3 A curve diagram showing the relationship between the subthreshold swing amplitude and the first gate width in a semiconductor structure provided in an embodiment of the present disclosure;

[0050] Figure 4 A curve diagram showing the relationship between the switching ratio and the first gate width in a semiconductor structure provided in an embodiment of the present disclosure;

[0051] Figure 5 A schematic diagram of the structure of a storage unit provided in an embodiment of the present disclosure;

[0052] Figure 6 is an equivalent circuit diagram of a storage unit provided in an embodiment of the present disclosure;

[0053] Figure 7 A schematic diagram of a process for preparing a storage unit provided in an embodiment of the present disclosure;

[0054] Figure 8 A schematic diagram of a structure obtained in step S1111 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0055] Fig. 9 A schematic diagram of a structure obtained in step S1112 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0056] Fig.10 A schematic diagram of a structure obtained in step S1113 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0057] Fig.11 It is a schematic diagram of a structure obtained in step S1114 in the method for preparing a storage unit provided in one embodiment of the present disclosure;

[0058] Fig.12 A schematic diagram of a structure obtained in step S1115 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0059] Fig.13 A schematic diagram of a structure obtained in step S1116 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0060] Fig.14 A schematic diagram of a structure obtained in step S121 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0061] Fig.15 A schematic diagram of a structure obtained in step S1211 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0062] Fig.16 A schematic diagram of a structure obtained in step S1212 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0063] Fig.17 A schematic diagram of a structure obtained in step S1213 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0064] Fig.18 A schematic diagram of a structure obtained by forming a second mask stack in step S13 in a method for preparing a memory cell provided in an embodiment of the present disclosure;

[0065] Fig.19 A schematic diagram of a structure obtained by forming an active pillar in step S13 in a method for preparing a memory cell provided in an embodiment of the present disclosure;

[0066] Fig. 20 A schematic diagram of a structure obtained in step S411 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0067] Fig.21 A schematic diagram of a structure obtained in step S31 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0068] Fig. 22 A schematic diagram of a structure obtained in step S412 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0069] Fig.23 A schematic diagram of a structure obtained in step S413 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0070] Fig.24 Figure (a) is Fig.23 A local enlarged view of the middle Z region, (b) is a cross-sectional view of (a) along the AA' direction;

[0071] Fig.25 FIG. (a) is a schematic diagram of a structure obtained in step S42 in a method for preparing a memory cell provided in an embodiment of the present disclosure, and FIG. (b) is a cross-sectional view of FIG. (a) along the AA' direction;

[0072] Fig.26 FIG. (a) is a schematic diagram of a structure obtained in step S43 in a method for preparing a memory cell provided in an embodiment of the present disclosure, and FIG. (b) is a cross-sectional view of FIG. (a) along the AA' direction;

[0073] Fig. 27FIG. (a) is a schematic diagram of a structure obtained in step S44 in a method for preparing a memory cell provided in an embodiment of the present disclosure, and FIG. (b) is a cross-sectional view of FIG. (a) along the AA' direction;

[0074] Fig.28 A schematic diagram of a structure obtained in step S1221 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0075] Fig.29 A schematic diagram of a structure obtained in step S1222 of a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0076] Fig.30 A schematic diagram of a structure obtained by forming a dielectric material layer in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0077] Fig.31 A schematic diagram of a structure obtained by forming an isolation dielectric layer in a method for preparing a memory cell provided in an embodiment of the present disclosure;

[0078] Fig.32 A schematic diagram of a structure obtained in step S51 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0079] Fig.33 A schematic diagram of a structure obtained in step S52 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0080] Fig.34 A schematic diagram of a structure obtained in step S53 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0081] Fig.35 A schematic diagram of a structure obtained in step S54 in a method for preparing a storage unit provided in an embodiment of the present disclosure;

[0082] Fig.36 Schematic diagram of the structure obtained in step S55 of the method for preparing a storage unit provided in an embodiment of the present disclosure.

[0083] Description of reference numerals:

[0084] U, storage unit; T1, read transistor; T2, write transistor;

[0085] RBL, read bit line; RWL, read word line; WBL, write bit line; WWL, write word line; SN, storage node; H1, first accommodation hole; H2, second accommodation hole; H3, third accommodation hole; EH, etching hole;

[0086] 1. substrate; 2. active pillar; 3. first gate; 31. first sub-gate; 311. first conductive layer; 32. second sub-gate; 321. second conductive layer; 33. first gate dielectric layer; 331. first gate dielectric material layer; 4. second gate; 41. second gate dielectric layer; 411. second gate dielectric material layer; 5. third gate; 51. third gate dielectric layer; 6. semiconductor layer; 7. first mask stack; 71. first silicon oxide layer; 72. first polysilicon layer; 73, a first silicon oxynitride layer; 74, a first spin-coated hard mask layer; 75, a second silicon oxynitride layer; 76, a first patterned photoresist layer; 77, a second silicon oxide layer; 8, a second mask stack; 81, a third silicon oxide layer; 82, a second polysilicon layer; 83, a third silicon oxynitride layer; 84, a second spin-coated hard mask layer; 85, a fourth silicon oxynitride layer; 91, an isolation material layer; 92, an isolation dielectric layer; 921, a dielectric material layer; 93, an interlayer dielectric layer. DETAILED DESCRIPTION

[0087] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0089] The term "and / or" used herein includes any and all combinations of one or more of the related listed items. In the case of using "including", "having", and "comprising" described herein, another component may be added unless a clear limiting term such as "only", "consisting of", etc. is used. Unless mentioned to the contrary, a term in the singular form may include a plural form and is not to be understood as having one number.

[0090] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present disclosure.

[0091] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0092] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0093] Please refer to Figure 1 , due to the excellent gate control capability and high switching ratio of the vertical gate-all-around transistor, it has broad application prospects as the access transistor of DRAM. However, as the feature size continues to scale, the gate control capability and switching ratio of the vertical gate-all-around transistor decrease accordingly. In the traditional vertical gate-all-around transistor, an indium gallium zinc oxide (IGZO) material layer is usually formed in the active column 2 as a channel, which reduces the reading speed of the memory, and the compatibility between the IGZO material and the silicon-based semiconductor material of the peripheral device process is poor.

[0094] In view of the above-mentioned deficiencies in the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, the details of which will be described in subsequent embodiments.

[0095] According to some embodiments, the present disclosure provides a semiconductor structure.

[0096] As an example, the semiconductor structure can be used to form a semiconductor device (such as DRAM), and the DRAM may include a transistor structure and an equivalent capacitor connected to the transistor structure, the equivalent capacitor is used to store data, and the transistor structure is used to read data in the equivalent capacitor or write data into the equivalent capacitor. It can be understood that the semiconductor structure provided in the embodiment of the present application can be directly used as a transistor structure in a DRAM or as a component of a transistor structure, for example, it can be a transistor in a 2T0C structure, but it is not limited to this. The semiconductor structure provided in the embodiment of the present application can also be used as other structures.

[0097] Please refer to Figure 2 ,

[0098] The semiconductor structure includes an active column 2, a first gate 3 and a second gate 4; the active column 2 is located in the substrate and extends in a direction perpendicular to the substrate; the top surface of the active column 2 has a first accommodating hole H1 extending along its axial direction toward the bottom surface of the active column 2; the first gate 3 fills the first accommodating hole H1; the second gate 4 is located on the outer wall of the active column 2.

[0099] In the semiconductor structure of the above embodiment, a vertical active column 2 is formed inside the substrate, and the semiconductor structure is arranged inside the substrate, so as to be different from the method of forming a transistor on the surface of the substrate through multiple film layers. In addition, by filling the first gate 3 of the first receiving hole H1 in the active column 2, and the second gate 4 arranged on the outer wall of the active column 2, the semiconductor structure has a dual-gate structure, wherein the first gate 3 is used to store or release charges, and the second gate 4 is used to control the on and off of the semiconductor structure. The semiconductor structure with a dual-gate structure is conducive to increasing the contact area between the gate and the channel of the semiconductor structure, so that the gate control ability of the gate is enhanced, thereby reducing the subthreshold swing (SS), improving the switching ratio of the semiconductor structure, and enhancing the electrical performance of the semiconductor structure in the above embodiment.

[0100] It can be understood that the subthreshold swing is a performance indicator for measuring the conversion rate between the on and off states of a semiconductor device, which represents the change in gate voltage required for a tenfold change in source-drain current. In the above embodiment, the subthreshold swing can vary with the change in the width IGL of the first gate 3.

[0101] For example, the width IGL of the first gate 3 may be 1 nm to 3 nm; for example, the width IGL of the first gate 3 may be 1 nm, 1.5 nm, 2 nm, 2.5 nm or 3 nm.

[0102] For example, combined with Figure 2 and Figure 3 It is understood that the subthreshold swing can be reduced as the width IGL of the first gate 3 increases. For example, compared with the related art, the subthreshold swing of the semiconductor structure provided in the embodiment of the present application can be reduced by 15%.

[0103] Accordingly, combined Figure 2 and Figure 4 It is understood that a smaller subthreshold swing means a faster on / off ratio, that is, the on / off ratio can be improved as the width IGL of the first gate 3 increases. Therefore, the semiconductor structure provided in the above embodiment has a higher on / off ratio, which is beneficial to improving the electrical performance of the semiconductor device. For example, compared with the related art, the on / off ratio can be improved by an order of magnitude using the semiconductor structure provided in the embodiment of the present application.

[0104] Please continue to refer to Figure 2 An active column 2 perpendicular to the substrate and a second gate 4 located on the outer side wall of the active column 2 are formed in the substrate, so that the semiconductor structure has a vertical channel structure. Therefore, more active columns 2 can be arranged while occupying the same substrate area, thereby further improving space utilization and facilitating improving device integration and storage density.

[0105] In some embodiments, the active pillar 2 includes a single crystal silicon pillar. Compared with the related art using IGZO as the channel material, the use of a single crystal silicon pillar in this embodiment can improve the compatibility with the silicon-based semiconductor material of the peripheral device process. In addition, the semiconductor structure using a single crystal silicon pillar has a faster reading speed, which is conducive to improving the reading speed of the semiconductor structure.

[0106] In some embodiments, the first gate 3 includes a first sub-gate 31 located in the first receiving hole H1 and a second sub-gate 32 located on the top surface of the first sub-gate 31; the top surface of the first sub-gate 31 is flush with the top surface of the active pillar 2. An isolation dielectric layer is formed around the second sub-gate 32 to prevent the charge stored in the first gate 3 from leaking, thereby effectively reducing leakage current.

[0107] In some embodiments, Figure 2 As shown in FIG. (b), the second gate 4 can be arranged around the active pillar 2, that is, the second gate 4 is a surrounding gate structure (Gate-All-Around, referred to as GAA). This further increases the contact area between the gate and the active pillar 2 to further improve the gate control capability. In addition, the GAA structure is also conducive to saving structural size to further increase the distribution density of the semiconductor structure, thereby further improving the storage density of the device.

[0108] According to some embodiments, the present disclosure also provides a storage unit.

[0109] As an example, the above-mentioned memory cell can be used as a component of a transistor structure and an equivalent capacitor in a DRAM, for example, it can be a 2T0C structure, but it is not limited to this. The memory cell provided in the embodiment of the present application can also be used as other structures.

[0110] Please refer to Figure 5 In some embodiments, the memory cell U includes a read transistor T1 and a write transistor T2. The read transistor T1 includes the semiconductor structure in the above embodiment. In some embodiments, the memory cell U may be a 2T0C structure composed of the read transistor T1 and the write transistor T2.

[0111] In some embodiments, the bottom surface of the active pillar 2 is connected to the read bit line; the second gate 4 is connected to the read word line; and the top surface of the first gate 3 is connected to the write transistor T2.

[0112] In the storage unit of the above embodiment, the write transistor T2 is connected to the top surface of the first gate 3, which can realize the vertical stacking of the read transistor T1 and the write transistor T2, thereby further improving the space utilization rate and facilitating the improvement of device integration and storage density.

[0113] In some embodiments, the semiconductor structure further includes a first gate dielectric layer 33 , which covers the surface of the first receiving hole H1 and is located between the first sub-gate 31 and the active pillar 2 .

[0114] In some embodiments, the semiconductor structure further includes a second gate dielectric layer 41 , and the second gate dielectric layer 41 is located on the sidewall of the active pillar 2 and at least between the second gate 4 and the active pillar 2 .

[0115] In some embodiments, the write transistor T2 includes a third gate 5 and a semiconductor layer 6; the semiconductor layer 6 is located on the top surface of the first gate 3; the semiconductor layer 6 has a gate trench; the semiconductor layer 6 on the sidewall of the gate trench is connected to the write bit line WBL; the third gate 5 fills the gate trench; the top surface of the third gate 5 is connected to the write word line WWL; wherein the write bit line WBL and the write word line WWL are insulated from each other. The third gate 5 is connected to the write word line WWL to control the on and off of the write transistor T2; the write bit line WBL is used to write a level signal to the storage unit U to achieve data storage.

[0116] In some embodiments, the semiconductor structure further includes a third gate dielectric layer 51 , and the third gate dielectric layer 51 conformally covers the semiconductor layer 6 . The semiconductor layer 6 and the third gate 5 are insulated from each other by the third gate dielectric layer 51 .

[0117] Figure 6 The equivalent circuit of the semiconductor structure in this embodiment, the storage unit U can be equivalent to a 2T0C storage circuit composed of a read transistor T1 and a write transistor T2. Figure 5 and Figure 6 It is understood that the first gate 3 can be used to store charges. For example, the first gate 3 and the active pillar 2 and the first gate dielectric layer 33 therebetween can be equivalent to a capacitor. The connection between the first gate 3 and the semiconductor layer 6 corresponds to Figure 5 One end of the active pillar 2 is connected to the read bit line RBL, and the other end of the active pillar 2 is applied with a reference voltage Vref. For example, one end of the active pillar 2 away from the write transistor T2 is connected to the read bit line RBL as the source of the read transistor T1, and the other end of the active pillar 2 is applied with a reference voltage Vref as the drain of the read transistor T1.

[0118] For example, when the memory cell U of the present embodiment performs a write operation, the write word line WWL applies a control level through the third gate 5, so that the write transistor T2 is turned on. At the same time, the write bit line WBL is used to provide a data level to the memory cell U, which is written into the first gate 3 through the semiconductor layer 6, so that the charge is stored in the first gate 3 to realize the writing of data.

[0119] Accordingly, when the memory cell U of the present embodiment performs a read operation, the read word line RWL applies a control level through the second gate 4, so that the read transistor T1 is turned on. When the first gate 3 stores charges, due to the potential difference between the data level stored in the first gate 3 and the reference voltage Vref, the charges stored in the first gate 3 enter the active pillar 2 based on the tunneling effect and other related principles, causing a potential change at one end of the active pillar 2 connected to the read bit line RBL, and then the potential change is read through the read bit line RBL to realize data reading.

[0120] It can be understood that the write operation and the read operation of the storage unit U in the embodiment of the present disclosure can be performed separately.

[0121] Please continue to refer to Figure 5 In some embodiments, the semiconductor layer 6 has an extension portion, which is located on the top surface of the write bit line WBL and extends in a direction away from the third gate 5 to increase the contact area between the semiconductor layer 6 and the write bit line WBL, thereby reducing the contact resistance therebetween.

[0122] In some embodiments, the extending direction of the write bit line WBL is the same as the extending direction of the read word line RWL; the extending direction of the write bit line WBL is the same as or different from the extending direction of the write word line WWL.

[0123] For example, the material of the semiconductor layer 6 includes a metal oxide semiconductor of at least one of indium, gallium, zinc or tin, such as indium gallium zinc oxide (IGZO), so as to reduce the leakage current of the write transistor T2, thereby ensuring the reliability of the write transistor T2.

[0124] In some embodiments, the semiconductor layer 6 can be arranged around the third gate 5, that is, the write transistor T2 can adopt a channel-all-around (CAA) structure, which is beneficial to saving structure size to increase the distribution density of the storage unit U, thereby increasing the storage density of the device.

[0125] According to some embodiments, the present application also provides a method for preparing a storage unit, which is used to prepare the storage unit provided in some of the above embodiments.

[0126] Please refer to Figure 7In some embodiments, the method for preparing a storage unit may include the following steps:

[0127] S10: patterning the substrate to form at least one active column in the substrate; the active column extends in a direction perpendicular to the substrate, and the top surface of the active column has a first receiving hole extending along the axis direction thereof toward the bottom surface of the active column;

[0128] S20: forming a first gate in the first receiving hole;

[0129] S30: forming a read bit line on the bottom surface of the active pillar;

[0130] S40: forming a second gate and a read word line connected to the second gate on the outer sidewall of the active pillar;

[0131] S50: forming a write transistor on a top surface of the first gate;

[0132] The storage unit includes a read transistor and a write transistor; the read transistor includes an active column, a first gate and a second gate.

[0133] In the preparation method of the storage unit of the above embodiment, the active column is prepared by patterning the substrate, so that the active column and the first receiving hole therein are formed inside the substrate. In this way, in the preparation process of the active column in the read transistor, it can be achieved only by patterning the substrate, without forming multiple film layers on the substrate, which can simplify the process flow and save production costs. In addition, by forming a first gate in the first receiving hole and forming a second gate on the outer wall of the active column, the read transistor including the active column, the first gate and the second gate has a dual-gate structure. At the same time, a write transistor is formed on the top surface of the first gate, which can realize the vertical stacking of the read transistor and the write transistor.

[0134] In some embodiments, step S10, patterning the substrate, forming at least one active pillar in the substrate, and forming a first gate in the first receiving hole, includes:

[0135] S11: performing a first patterning on the substrate to form a plurality of first receiving holes distributed in an array in the substrate;

[0136] S12: forming a first gate dielectric layer and a first gate in the first receiving hole in sequence;

[0137] S13: performing a second patterning on the substrate to form a plurality of active pillars distributed in an array in the substrate, and making the first receiving holes correspondingly located at the axis of the active pillars.

[0138] In some embodiments, step S12, sequentially forming a first gate dielectric layer and a first gate in the first receiving hole, includes:

[0139] S121: forming a first gate dielectric layer and a first sub-gate in sequence in the first receiving hole; a top surface of the first sub-gate is flush with a top surface of the active pillar;

[0140] S122: after forming a second gate and a read word line connected to the second gate on an outer sidewall of the active pillar, forming a second sub-gate located on a top surface of the first sub-gate;

[0141] The first gate includes a first sub-gate and a second sub-gate.

[0142] In some embodiments, step S30, forming a read bit line on the bottom surface of the active pillar, includes:

[0143] S31: After the substrate is patterned for the second time, a metal silicidation process is performed on the substrate located at the bottom surface of the active pillars based on the interval between adjacent active pillars to form a read bit line extending along the first direction.

[0144] In some embodiments, step S40, forming a second gate and a read word line connected to the second gate on the outer sidewall of the active pillar, includes:

[0145] S41: after patterning the substrate for the second time, forming a second gate dielectric layer covering the sidewalls of the active pillars, and an isolation material layer covering the second gate dielectric layer and filling the spaces between adjacent active pillars;

[0146] S42: removing a portion of the isolation material layer between adjacent active pillars in the second direction to form an etching hole exposing the sidewall of the second gate dielectric layer; the second direction intersects the first direction;

[0147] S43: etching back the isolation material layer outside the sidewall of the corresponding active pillar in the first direction based on the etched hole to form a second receiving hole on the outer sidewall of the corresponding active pillar;

[0148] S44: forming a second gate in the second receiving hole, and forming a read word line connected to the second gate in the etched hole.

[0149] In some embodiments, step S50, forming a write transistor on the top surface of the first gate, includes:

[0150] S51: forming an interlayer dielectric layer and a write bit line in sequence on the top surface of the first gate in a direction away from the substrate;

[0151] S52: forming a third receiving hole penetrating the interlayer dielectric layer and the write bit line and exposing the top surface of the first gate;

[0152] S53: forming a semiconductor layer on the inner wall of the third receiving hole and the top surface of the write bit line; the bottom surface of the semiconductor layer is connected to the top surface of the first gate;

[0153] S54: forming a third gate dielectric layer covering the semiconductor layer;

[0154] S55: forming a third gate electrode covering the third gate dielectric layer and filling the third receiving hole, and a write word line connected to the third gate electrode;

[0155] The write transistor includes a semiconductor layer, a third gate dielectric layer and a third gate.

[0156] It should be understood that although Figure 7 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 7 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0157] In order to more clearly illustrate the preparation method of the memory cell provided by the above embodiments, Figures 8 to 36 Understand some embodiments of the present application.

[0158] The embodiments of the present application do not specifically limit the constituent materials of the substrate 1. As an example, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate 1, a silicon germanium (SiGe) substrate 1, a silicon germanium carbon (SiGeC) substrate 1, a silicon carbide (SiC) substrate 1, a gallium arsenide (GaAs) substrate 1, an indium arsenide (InAs) substrate 1, an indium phosphide (InP) substrate 1 or other III / V semiconductor substrates 1 or II / VI semiconductor substrates 1. Alternatively, for example, the substrate 1 can be a layered substrate 1 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator, etc.

[0159] Please refer to Figures 8 to 14 In step S11, the first patterning of the substrate 1 is not limited to a single patterning process, and the first patterning may include multiple patterning processes. In some embodiments, step S11 may include:

[0160] S111: forming a patterned mask stack on the substrate 1, wherein the position of the first receiving hole H1 is defined in the patterned mask stack;

[0161] S112 : performing a first patterning on the substrate 1 based on the patterned mask stack to form a plurality of first receiving holes H1 distributed in an array in the substrate 1 .

[0162] For example, a self-aligned double patterning (SADP) process may be used to form a patterned mask stack on the substrate 1, specifically comprising:

[0163] S1111: Figure 8 As shown, a first mask stack 7 is formed on the surface of the substrate 1; the first mask stack 7 may include a first silicon oxide layer 71, a first polysilicon layer 72, a first silicon oxynitride layer 73, a first spin-on hard mask layer 74 and a second silicon oxynitride layer 75 sequentially deposited on the surface of the substrate 1;

[0164] S1112: Fig. 9 As shown, a photoresist (PR) layer is formed on the surface of the first mask stack 7, and the photoresist layer is exposed and developed to form a first pattern in the photoresist layer, thereby forming a first patterned photoresist layer 76;

[0165] S1113: Fig.10 As shown, the first silicon oxynitride layer 73 and the first spin-on hard mask layer 74 are etched based on the first patterned photoresist layer 76 to transfer the first pattern to the first silicon oxynitride layer 73 and the first spin-on hard mask layer 74; the first patterned photoresist layer 76 is removed;

[0166] S1114: Fig.11 As shown, a second silicon oxide layer 77 is deposited on the sidewalls and top of the first silicon oxynitride layer 73 and the first spin-on hard mask layer 74;

[0167] S1115: Fig.12 As shown, the structure obtained by the back-etching step 114 is removed in order to remove the first silicon oxynitride layer 73, the first spin-coated hard mask layer 74, and a part of the second silicon oxide layer 77, and the remaining second silicon oxide layer 77 has a second pattern. For example, this step can be back-etched by anisotropic etching, which can selectively etch materials in a preset crystal direction or crystal plane direction, and leave only a few or almost no etching marks in other directions. In this step, the back-etching by anisotropic etching can make the morphology of the obtained structure more accurate and controllable;

[0168] S1116: Fig.13 As shown, the first polysilicon layer 72 and the first silicon oxynitride layer 73 are etched based on the second pattern to form a patterned mask stack;

[0169] like Fig.14 As shown, in step S112 , the substrate 1 is etched based on the patterned mask stack to form a plurality of first receiving holes H1 distributed in an array in the substrate 1 .

[0170] Here, in some embodiments, in combination Figure 13 to Figure 14 It can be understood that the first silicon oxide layer 71 is etched while the substrate 1 is etched based on the patterned mask stack; and the remaining first silicon oxide layer 71 is removed.

[0171] For example, in step S111, the first spin-coated hard mask layer 74 can be formed by a spin coating process; for example, the first spin-coated hard mask layer 74 can be an insulating layer of a carbon-hydrogen (CxHy) system, which can include silicon hard mask materials, carbon hard mask materials, and organic hard mask materials, etc.

[0172] Please refer to Figure 15 to Figure 16 In step S121, a first gate dielectric layer 33 and a first sub-gate 31 are sequentially formed in the first receiving hole H1, specifically including:

[0173] S1211: Fig.15 As shown, a first gate dielectric material layer 331 is formed, and the first gate dielectric material layer 331 conformally covers the outer surface of the active pillar 2;

[0174] S1212: Fig.16 As shown, a first conductive layer 311 is formed to cover the first gate dielectric material layer 331 and fill the first receiving hole H1;

[0175] S1213: Fig.17 As shown, the first conductive layer 311 and the first gate dielectric material layer 331 are etched back until the top surface of the active pillar 2 is exposed; the remaining first conductive layer 311 serves as the first sub-gate 31, and the top surface of the first sub-gate 31 is flush with the top surface of the active pillar 2; the remaining first gate dielectric material layer 331 serves as the first gate dielectric layer 33.

[0176] Please refer to Figure 18 to Figure 19 In step S13, the second patterning of the substrate 1 is not limited to a single patterning process, and the second patterning may also include multiple patterning processes.

[0177] For example, the substrate 1 can also be patterned for the second time using a self-aligned double patterning (SADP) process to form a plurality of active pillars 2 distributed in an array in the substrate 1 , and each first receiving hole H1 is located at the axis of the active pillar 2 in a one-to-one correspondence.

[0178] like Fig.18As shown, a second mask stack 8 may be formed on the surface of the substrate 1; the second mask stack 8 may include a third silicon oxide layer 81, a second polysilicon layer 82, a third silicon oxynitride layer 83, a second spin-on hard mask layer 84, and a fourth silicon oxynitride layer 85 sequentially deposited on the surface of the substrate 1. The substrate 1 may be patterned for the second time based on the second mask stack 8 by adopting steps that are the same as or similar to steps S111 to S117, so as to obtain a second patterned substrate 1. Fig.19 As shown, a plurality of active pillars 2 distributed in an array are formed in the substrate 1, which will not be described in detail here.

[0179] Please refer to Figure 20 to Figure 23 In step S41, after the substrate 1 is patterned for the second time, a second gate dielectric layer 41 covering the sidewalls of the active pillars 2 and an isolation material layer 91 covering the second gate dielectric layer 41 and filling the spaces between adjacent active pillars 2 are formed, which may include:

[0180] S411: Fig. 20 As shown, a second gate dielectric material layer 411 is formed to cover the sidewalls of the active pillar 2;

[0181] S412: Fig. 22 As shown, an isolation material layer 91 covers the second gate dielectric layer 41 and fills the intervals between adjacent active pillars 2;

[0182] S413: Fig.23 As shown, the structure obtained by the etching back step 412 is performed until the top surface of the active pillar 2 is exposed; the remaining second gate dielectric material layer 411 serves as the second gate dielectric layer 41 .

[0183] Please refer to Fig.21 For example, after step S411, step S31 may be performed, after the substrate 1 is patterned for the second time, based on the interval between adjacent active pillars 2, a metal silicide process is performed on the substrate 1 located at the bottom surface of the active pillar 2 to form a read bit line RBL extending along the first direction, specifically including:

[0184] S311: etching and removing the second gate dielectric layer 41 at the bottom to expose the substrate 1 below;

[0185] S312: forming a metal layer in the portion of the substrate 1 exposed at the bottom of the second gate dielectric layer 41;

[0186] S313: performing heat treatment on the metal layer to diffuse the metal layer along the first direction to connect with each other, so as to form a read bit line RBL extending along the first direction.

[0187] For example, the first direction may be Fig.21 The X direction shown in .

[0188] Fig.24Figure (a) is Fig.23 A partial enlarged view of the middle Z region. Fig.24 Figure (b) is a cross-sectional view of Figure (a) along the AA' direction. Figure 25 to Figure 27 The meaning of each figure and Fig.24 They are basically the same and will not be elaborated below.

[0189] Please refer to Figure 24 to Figure 25 In step S42, a portion of the isolation material layer 91 between adjacent active pillars 2 in the second direction is removed to form an etching hole EH exposing the sidewall of the second gate dielectric layer 41; the second direction intersects the first direction; for example, the second direction is Fig.25 Y direction shown in .

[0190] By way of example, the step of forming the etching hole EH may include:

[0191] S421: forming a receiving groove extending along the second direction between adjacent first gates 3, and forming an etching stop layer in the receiving groove; the material of the etching stop layer is different from the material of the isolation material layer 91;

[0192] S422 : etching a portion of the isolation material layer 91 between the active pillars 2 adjacent to each other in the second direction along the first direction to form an etching hole EH exposing the sidewall of the second gate dielectric layer 41 .

[0193] Please refer to Fig.26 In step S43 , the isolation material layer 91 on the outer sidewall of the corresponding active pillar 2 in the first direction is etched back based on the etching hole EH to form a second receiving hole H2 on the outer sidewall of the corresponding active pillar 2 .

[0194] It is worth noting that in step S42 and step S43 , the width of the etched hole EH along the first direction is greater than the width of the active pillar 2 along the first direction, so that the second receiving hole H2 can expose the sidewall of the second gate dielectric layer 41 along the first direction.

[0195] It should be noted that Fig.24 In FIG. 1( b ), the orthographic projection shape of the active pillar 2 is for illustration only, and the shape of the active pillar 2 is not limited here, and accordingly, the shape of the etched hole EH is also not limited.

[0196] Please refer to Fig. 27 In step S44, a second gate 4 is formed in the second receiving hole H2, and a read word line RWL connected to the second gate 4 is formed in the etched hole EH.

[0197] Here, it can be understood that the second gate 4 and the read word line RWL are an integrated structure and can be simultaneously formed in the etching hole EH and the second receiving hole H2 through a one-time deposition process.

[0198] Please refer to Figure 28 to Figure 29 After forming the second gate 4 and the read word line RWL connected to the second gate 4 on the outer wall of the active pillar 2, step S122 is performed to form the second sub-gate 32 located on the top surface of the first sub-gate 31, which specifically includes:

[0199] S1221: Fig.28 As shown, a second conductive layer 321 is formed covering the structure obtained in step 40 above;

[0200] S1222: Fig.29 As shown, part of the second conductive layer 321 is removed to form a second sub-gate 32 located on the top surface of the first sub-gate 31 .

[0201] For example, the material of the second sub-gate 32 may be the same as or similar to the material of the first sub-gate 31 , and the material of the second sub-gate 32 and the material of the first sub-gate 31 include metal, such as tungsten.

[0202] Please refer to Figure 30 to Figure 31 , forming a dielectric material layer 921 covering the second sub-gate 32 and the isolation material layer 91 ; etching back the dielectric material layer 921 until the top surface of the second sub-gate 32 is exposed, and the remaining dielectric material layer serves as the isolation dielectric layer 92 .

[0203] For example, the material of the isolation material layer 91 may include but is not limited to silicon nitride. The material of the isolation dielectric layer 92 may include but is not limited to silicon oxide.

[0204] Please refer to Fig.32 In step S51 , an interlayer dielectric layer 93 and a write bit line WBL are sequentially formed on the top surface of the first gate 3 in a direction away from the substrate 1 .

[0205] By way of example, the material of the write bit line WBL may include but is not limited to nickel and titanium.

[0206] Please refer to Fig.33 In step S52 , a third receiving hole H3 is formed which penetrates the interlayer dielectric layer 93 and the write bit line WBL and exposes the top surface of the first gate 3 .

[0207] By way of example, the material of the interlayer dielectric layer 93 may include but is not limited to silicon oxide.

[0208] Please refer to Fig.34 In step S53 , a semiconductor layer 6 is formed on the inner wall of the third receiving hole H3 and the top surface of the write bit line WBL; the bottom surface of the semiconductor layer 6 is connected to the top surface of the first gate 3 .

[0209] Please refer to Fig.35 In step S54, a third gate dielectric layer 51 covering the semiconductor layer 6 is formed.

[0210] By way of example, the material of the third gate dielectric layer 51 may be the same as or similar to the material of the first gate dielectric layer 33 and the material of the second gate dielectric layer 41. For example, the material of the first gate dielectric layer 33, the material of the second gate dielectric layer 41, and the material of the third gate dielectric layer 51 may include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0211] Please refer to Fig.36 In step S55 , a third gate 5 covering the third gate dielectric layer 51 and filling the third receiving hole H3 , and a write word line WWL connected to the third gate 5 are formed.

[0212] Illustratively, the material of the write word line WWL includes metal, such as tungsten.

[0213] In some embodiments, a memory is provided, comprising the above-mentioned storage unit.

[0214] In some embodiments, an electronic device is provided, comprising the above-mentioned memory. Since a memory with better performance and reliability is used, the electronic device of this embodiment has more beneficial performance and higher reliability.

[0215] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0216] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0217] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0218] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: An active column is located in the substrate and extends in a direction perpendicular to the substrate; the top surface of the active column has a first receiving hole extending toward the bottom surface along the axis direction thereof; A first gate, filling the first containing hole; The second gate is located on the outer side wall of the active column.

2. The semiconductor structure according to claim 1, characterized in that: The active pillars include single crystal silicon pillars.

3. The semiconductor structure according to claim 1, characterized in that: The first gate includes a first sub-gate located in the first containing hole and a second sub-gate located on the top surface of the first sub-gate; the top surface of the first sub-gate is flush with the top surface of the active pillar.

4. A storage unit, characterized in that: It comprises a read transistor and a write transistor; the read transistor comprises a semiconductor structure as described in any one of claims 1 to 3; wherein the bottom surface of the active column is connected to the read bit line; the second gate is connected to the read word line; and the top surface of the first gate is connected to the write transistor.

5. The storage unit according to claim 4, characterized in that The write transistor comprises: A semiconductor layer is located on the top surface of the first gate; a gate trench is provided in the semiconductor layer; and the semiconductor layer on the sidewall of the gate trench is connected to a write bit line; A third gate electrode fills the gate trench; a top surface of the third gate electrode is connected to a write word line; The semiconductor layer and the third gate are insulated from each other; the write bit line and the write word line are insulated from each other.

6. The storage unit according to claim 5, characterized in that The semiconductor layer has an extension portion, which is located on a top surface of the write bit line and extends in a direction away from the third gate.

7. The storage unit according to claim 5, characterized in that The extending direction of the write bit line is the same as the extending direction of the read word line; An extension direction of the write bit line is the same as or different from an extension direction of the write word line.

8. A method for preparing a storage unit, characterized in that: The method comprises: A patterned substrate, wherein at least one active column is formed in the substrate; the active column extends in a direction perpendicular to the substrate, and the top surface of the active column has a first receiving hole extending along the axis direction thereof toward the bottom surface of the active column; forming a first gate in the first receiving hole; forming a read bit line on the bottom surface of the active pillar; forming a second gate and a read word line connected to the second gate on an outer sidewall of the active column; forming a write transistor on a top surface of the first gate; Wherein, the storage unit includes a read transistor and the write transistor; the read transistor includes the active column, the first gate and the second gate.

9. The method for preparing a storage unit according to claim 8, characterized in that: The patterned substrate, forming at least one active pillar in the substrate, and the first gate formed in the first receiving hole, include: Performing a first patterning on the substrate to form a plurality of the first receiving holes distributed in an array in the substrate; forming a first gate dielectric layer and a first gate electrode in the first receiving hole in sequence; The substrate is patterned for the second time to form a plurality of active pillars distributed in an array in the substrate, and each of the first receiving holes is located at the axis of the active pillar in a one-to-one correspondence.

10. The method for preparing a storage unit according to claim 9, characterized in that: The step of sequentially forming a first gate dielectric layer and a first gate electrode in the first receiving hole comprises: The first gate dielectric layer and the first sub-gate are sequentially formed in the first receiving hole; the top surface of the first sub-gate is flush with the top surface of the active pillar; After forming a second gate and a read word line connected to the second gate on the outer sidewall of the active pillar, forming a second sub-gate located on the top surface of the first sub-gate; Wherein, the first gate includes the first sub-gate and the second sub-gate.

11. The method for preparing a storage unit according to claim 9, characterized in that: The forming of a read bit line on the bottom surface of the active pillar comprises: After the substrate is patterned for the second time, a metal silicidation process is performed on the substrate located at the bottom surface of the active pillars based on the interval between adjacent active pillars to form the read bit line extending along the first direction.

12. The method for preparing a storage unit according to claim 9, characterized in that: The second gate and the read word line connected to the second gate are formed on the outer sidewall of the active column, comprising: After patterning the substrate for the second time, forming a second gate dielectric layer covering the sidewalls of the active pillars, and an isolation material layer covering the second gate dielectric layer and filling the spaces between adjacent active pillars; removing a portion of the isolation material layer between adjacent active pillars in a second direction to form an etching hole exposing a sidewall of the second gate dielectric layer; the second direction intersects the first direction; Based on the etched hole, the isolation material layer corresponding to the outer side wall of the active column in the first direction is etched back to form a second receiving hole on the outer side wall corresponding to the active column; The second gate is formed in the second receiving hole, and the read word line connected to the second gate is formed in the etched hole.

13. The method for preparing a storage unit according to any one of claims 9 to 12, characterized in that: The step of forming a write transistor on the top surface of the first gate comprises: forming an interlayer dielectric layer and a write bit line in sequence on the top surface of the first gate in a direction away from the substrate; forming a third receiving hole penetrating the interlayer dielectric layer and the write bit line and exposing the top surface of the first gate; A semiconductor layer is formed on the inner wall of the third receiving hole and the top surface of the write bit line; the bottom surface of the semiconductor layer is connected to the top surface of the first gate; forming a third gate dielectric layer covering the semiconductor layer; forming a third gate electrode covering the third gate dielectric layer and filling the third receiving hole, and a write word line connected to the third gate electrode; Wherein, the write transistor includes the semiconductor layer, the third gate dielectric layer and the third gate.

14. A memory, characterized in that: include: A storage unit as claimed in any one of claims 4 to 6.

15. An electronic device, characterized in that: include: The memory as claimed in claim 14.

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