Semiconductor structure, memory system and preparation method of semiconductor structure

Abstract

The invention provides a semiconductor structure, a storage system and a preparation method of the semiconductor structure, relates to the technical field of semiconductor chips, and aims to solve the problems of collapse and electric leakage of a partial region of a laminated structure in the preparation process of the semiconductor structure. The semiconductor structure includes a stack structure and a first isolation structure. The stacked structure comprises a plurality of insulating layers and a plurality of gate layers, and the plurality of insulating layers and the plurality of gate layers are alternately stacked. The first isolation structure penetrates through the stacking structure, the first isolation structure extends in the first direction, the first isolation structure comprises a main structure and a plurality of sub-structures located on the two sides of the main structure in the second direction respectively, the sub-structures are connected with the side wall of the main structure, and each sub-structure is inserted between every two adjacent insulating layers. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, a storage system, and a method for preparing the semiconductor structure. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing technologies become challenging and costly, which causes the storage density of 2D (2-Dimension) or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate or source layer. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor structure, a storage system, and a method for preparing a semiconductor structure, which aim to solve the problem of partial collapse and leakage of a stacked structure during the preparation process of the semiconductor structure.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor structure is provided. The semiconductor structure includes a stacked structure and a first isolation structure. The stacked structure includes multiple insulating layers and multiple gate layers, and the multiple insulating layers and the multiple gate layers are alternately stacked. The first isolation structure runs through the stacked structure, and the first isolation structure extends along a first direction; the first isolation structure includes a main structure and a plurality of sub-structures respectively located on both sides of the main structure along a second direction, the sub-structures are connected to the side walls of the main structure, and each sub-structure is inserted between two adjacent insulating layers; the second direction intersects with the first direction.

[0007] The semiconductor structure provided by the above-mentioned embodiments of the present disclosure, the first isolation structure includes a main structure and multiple sub-structures, wherein each sub-structure is inserted between two adjacent insulating layers, which can enhance the binding force of the first isolation structure to the stacked structure, and at the same time enhance the supporting force to prevent collapse during the formation of the gate layer. It can be understood that the use of such a design improves the yield of the semiconductor structure product and ensures the storage performance of the semiconductor structure.

[0008] In some embodiments, the main structure and the plurality of substructures of the first isolation structure all include a first isolation material.

[0009] In some embodiments, the semiconductor structure further includes a dielectric layer, which is located at least between adjacent insulating layers and gate layers; the dielectric layer is also disposed between the substructure and the gate layer in the same layer.

[0010] In some embodiments, the semiconductor structure also includes a second isolation structure extending along a second direction; the second isolation structure penetrates the stacked structure, the stacked structure has a core area and a peripheral area located outside the core area, and the first isolation structure separates the core area and the peripheral area; the core area includes a connection area and a storage area, and the second isolation structure penetrates the connection area and the storage area; the orthographic projection of the second isolation structure on the first plane at least partially overlaps with the orthographic projection of the first isolation structure on the first plane; the first plane is parallel to the surface of the stacked structure.

[0011] In some embodiments, the second isolation structure passes through the first isolation structure and enters the peripheral area; the semiconductor structure also includes a plurality of virtual channel structures located in the peripheral area, the plurality of virtual channel structures include a first partial virtual channel structure and a second partial virtual channel structure, the first partial virtual channel structure and the second partial virtual channel structure are respectively located on both sides of the second isolation structure.

[0012] In some embodiments, the semiconductor structure further includes a support column located in the peripheral region, the support column penetrating the stacked structure; the support column is located between the first partial dummy channel structure and the second partial dummy channel structure.

[0013] In some embodiments, the semiconductor structure also includes a third isolation structure extending along the second direction, and the third isolation structure penetrates the stacked structure; the third isolation structure is located between two adjacent second isolation structures; the core area includes a storage area and a connection area, and the third isolation structure is at least located in the storage area; wherein the orthographic projection of the third isolation structure on the first plane at least partially overlaps with the orthographic projection of the first isolation structure on the first plane.

[0014] In some embodiments, the second isolation structure includes a dielectric structure and a filling structure; the dielectric structure is located at the bottom of the second isolation structure and between the second isolation structure and the plurality of insulating layers.

[0015] In some embodiments, a size of the first isolation structure in the second direction is larger than a size of the second isolation structure in the first direction.

[0016] In some embodiments, the stacking structure includes a first stacking structure and a second stacking structure, and the second stacking structure is arranged on the first stacking structure; wherein the first isolation structure includes a first sub-isolation structure and a second sub-isolation structure; the first sub-isolation structure runs through the first stacking structure, and the second sub-isolation structure runs through the second stacking structure; the size of one end of the first sub-isolation structure close to the second sub-isolation structure is larger than the size of one end of the second sub-isolation structure close to the first sub-isolation structure.

[0017] In some embodiments, the dimension of an end of the first sub-isolation structure close to the second sub-isolation structure in the second direction is larger than the dimension of an end of the first sub-isolation structure away from the second sub-isolation structure in the second direction; the dimension of an end of the second sub-isolation structure away from the first sub-isolation structure in the second direction is larger than the dimension of an end of the second sub-isolation structure close to the first sub-isolation structure in the second direction.

[0018] In some embodiments, the first sub-isolation structure includes a first main structure and a plurality of first sub-structures respectively located on both sides of the first main structure along the second direction, the first sub-structures are connected to the side walls of the first main structure, and each first sub-structure is inserted between two adjacent insulating layers; the second sub-isolation structure includes a second main structure and a plurality of second sub-structures respectively located on both sides of the second main structure along the second direction, the second sub-structures are connected to the side walls of the second main structure, and each second sub-structure is inserted between two adjacent insulating layers.

[0019] In some embodiments, along the direction from the first stacking structure away from the second stacking structure, the dimension of the end of the first main structure close to the second main structure in the second direction is larger than the dimension of the end of the first main structure away from the second main structure in the second direction; the dimension of the end of the second main structure away from the first main structure in the second direction is larger than the dimension of the end of the second main structure close to the first main structure in the second direction.

[0020] In some embodiments, the semiconductor structure also includes multiple channel structures located in the core area, and the multiple channel structures penetrate the stacking structure; the channel structure includes a first sub-channel structure and a second sub-channel structure, the first sub-channel structure penetrates the first stacking structure, and the second sub-channel structure penetrates the second stacking structure; the size of the first sub-channel structure near one end of the second sub-channel structure is larger than the size of the second sub-channel structure near one end of the first sub-channel structure.

[0021] On the other hand, a storage system is provided, comprising: a three-dimensional memory and a controller, wherein the three-dimensional memory comprises the semiconductor structure as described above, and the controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0022] It can be understood that the beneficial effects that can be achieved by the storage system provided by the above embodiments of the present disclosure can be referred to the beneficial effects of the semiconductor structure described above, and will not be repeated here.

[0023] On the other hand, a method for preparing a semiconductor structure is provided, comprising: forming an initial stacking structure, the initial stacking structure comprising multiple insulating layers and multiple sacrificial layers alternately stacked; forming a first partition groove and a plurality of channel holes; the first partition groove penetrates the initial stacking structure, and the plurality of channel holes penetrate the initial stacking structure; removing part of the sacrificial layer located around the first partition groove to form a first cavity located between two adjacent insulating layers; filling the first partition groove and the first cavity with a first isolation material to form a first isolation structure; and filling the plurality of channel holes with a channel material to form a plurality of channel structures.

[0024] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor structure provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here.

[0025] In some embodiments, after forming multiple channel structures, it also includes: forming a second partition groove, the second partition groove extends along the second direction and penetrates the initial stacking structure; the second partition groove extends along the second direction; through the second partition groove, at least part of the sacrificial layer is replaced with the gate layer to form a stacking structure; depositing a second isolation material in the second partition groove to form a second isolation structure.

[0026] In some embodiments, an initial stacking structure is formed, and a first groove and a plurality of channel holes are formed, including: forming an initial first stacking structure; forming a plurality of first sub-channel holes and a first sub-groove, wherein the plurality of first sub-channel holes penetrate the initial first stacking structure, and the first sub-groove penetrates the first stacking structure; the first sub-groove extends along a first direction; forming an initial second stacking structure on the first stacking structure; the initial second stacking structure and the initial first stacking structure constitute an initial stacking structure; forming a plurality of second sub-channel holes and a second sub-groove, wherein the plurality of second sub-channel holes penetrate the initial second stacking structure, and the second sub-groove penetrates the second stacking structure; the second sub-groove extends along the first direction; filling the first groove and the first cavity with a first isolation material to form a first isolation structure, including: filling the first sub-groove, the second sub-groove and the first cavity with a first isolation material to form a first isolation structure; filling a plurality of channel holes with a channel material to form a plurality of channel structures, including: filling a plurality of first sub-channel holes and a plurality of second sub-channel holes with a channel material to form a plurality of channel structures.

[0027] In some embodiments, the preparation method also includes: after forming a plurality of first sub-channel holes and first sub-grooves, and before forming an initial second stacking structure on the first stacking structure, it also includes: depositing a first sacrificial material in the plurality of first sub-channel holes and first sub-grooves; after forming a plurality of second sub-channel holes and second sub-grooves, and before filling the first sub-grooves and second sub-grooves with the first isolation material, it also includes: removing the first sacrificial material in the plurality of first sub-channel holes and first sub-grooves; depositing a second sacrificial material in the plurality of first sub-channel holes, first sub-grooves, and a plurality of second sub-channel holes and second sub-grooves; and removing the second sacrificial material in the second sub-grooves and first sub-grooves.

[0028] In some embodiments, at least a portion of the sacrificial layer is replaced with a gate layer via a second partition groove to form a stacked structure, including: removing at least the sacrificial layer located in the storage area via the second partition groove to form a second cavity; filling the second cavity with a dielectric material to form a dielectric layer attached to the cavity wall of the second cavity and the bottom and side walls of the second partition groove; and filling the second cavity with a conductive material to form a multi-layer gate layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0030] Figure 1A A top view of a semiconductor structure provided according to some embodiments;

[0031] Figure 1B Another top view of a semiconductor structure provided according to some embodiments;

[0032] Figure 2A is another top view of a semiconductor structure provided according to some embodiments;

[0033] Figure 2B Another top view of a semiconductor structure provided according to some embodiments;

[0034] Figure 2C is another top view of a semiconductor structure provided according to some embodiments;

[0035] Figure 3 is another top view of a semiconductor structure provided according to some embodiments;

[0036] Figure 4A According to some embodiments, a semiconductor structure is provided according to Figure 2A to Figure 2C The cross-sectional structure diagram obtained by making cross-sections along the cross-sectional lines CC' and DD';

[0037] Figure 4B According to some embodiments, a semiconductor structure is provided according to Figure 2A to Figure 2C Another cross-sectional structure diagram obtained by making cross-sectional correspondence along the cross-sectional lines CC' and DD';

[0038] Figure 4C According to some embodiments, a semiconductor structure is provided according to Figure 4A An enlarged structural diagram of the first isolation structure in FIG.

[0039] Figure 4D A flowchart of a method for preparing a semiconductor structure according to some embodiments;

[0040] Figure 4E A flowchart of step 2 in a method for preparing a semiconductor structure according to some embodiments;

[0041] Figure 4F A flowchart between step 241 and step 243 in a method for preparing a semiconductor structure according to some embodiments;

[0042] Figure 4G A flowchart of step 7 in a method for preparing a semiconductor structure according to some embodiments;

[0043] Figure 5 According to some embodiments, a semiconductor structure is provided according to Figure 4E The cross-sectional structure diagram corresponding to step S21;

[0044] Figure 6 According to some embodiments, a semiconductor structure is provided according to Figure 4E The cross-sectional structure diagram corresponding to step S22;

[0045] Figure 7 According to some embodiments, a semiconductor structure is provided according to Figure 4E The cross-sectional structure diagram corresponding to step S23;

[0046] Figure 8 According to some embodiments, a semiconductor structure is provided according to Figure 4E The cross-sectional structure diagram corresponding to step S24;

[0047] Fig. 9 According to some embodiments, a semiconductor structure is provided according to Figure 4F The cross-sectional structure diagram corresponding to step S241;

[0048] Fig.10 According to some embodiments, a semiconductor structure is provided according to Figure 4F The cross-sectional structure diagram corresponding to step S242;

[0049] Fig.11A A cross-sectional structural diagram of a semiconductor structure provided according to some embodiments corresponding to step S242 - 1 and step S242 - 2 ;

[0050] Fig. 11B A cross-sectional structural diagram corresponding to step S242 - 3 of a semiconductor structure provided according to some embodiments;

[0051] Fig.12 According to some embodiments, a semiconductor structure is provided according to Figure 4F The cross-sectional structure diagram corresponding to step S243;

[0052] Fig.13 According to some embodiments, a semiconductor structure is provided according to Figure 4D The cross-sectional structure diagram corresponding to step S3;

[0053] Fig.14 According to some embodiments, a semiconductor structure is provided according to Figure 4D The cross-sectional structure diagram corresponding to step S4;

[0054] Fig.15 A cross-sectional structural diagram corresponding to step S4-1 of a semiconductor structure provided according to some embodiments;

[0055] Fig.16 A cross-sectional structural diagram corresponding to step S4-2 of a semiconductor structure provided according to some embodiments;

[0056] Fig.17 According to some embodiments, a semiconductor structure is provided according to Figure 4D The cross-sectional structure diagram corresponding to step S5;

[0057] Fig.18A According to some embodiments, a semiconductor structure is provided according to Figure 4D The cross-sectional structure diagram corresponding to step S6;

[0058] Fig.18B According to some embodiments, a semiconductor structure is provided according to Figure 4G The cross-sectional structure diagram corresponding to step S71;

[0059] Fig.19 According to some embodiments, a semiconductor structure is provided according to Figure 4G The cross-sectional structure diagram corresponding to step S72;

[0060] Fig. 20 According to some embodiments, a semiconductor structure is provided according to Figure 4G The cross-sectional structure diagram corresponding to step S73;

[0061] Fig.21 According to some embodiments, a semiconductor structure is provided according to Figure 4D The cross-sectional structure diagram corresponding to step S8;

[0062] Fig. 22 is a structural diagram of a three-dimensional memory according to some embodiments;

[0063] Fig.23A is a structural diagram of a storage system according to some embodiments;

[0064] Fig. 23B is a structural diagram of a storage system according to some other embodiments;

[0065] Fig.24 is a structural diagram of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0066] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0067] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0068] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0069] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0070] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0071] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0072] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0073] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0074] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0075] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0076] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0077] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0078] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0079] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0080] At present, with the increasing number of stacked layers of 3D NAND memory, the preparation process of three-dimensional memory is becoming more and more difficult. In order to reduce the process difficulty and reduce the manufacturing cost, an SCT (Staircase Contact, abbreviated as SCT) architecture is proposed. That is to say, in the preparation process of the semiconductor structure in the three-dimensional memory, the SCT one-time molding process replaces the process of first forming SS (Staircase Structure) and then CT (Contact), thereby realizing the merger of SS process and CT process.

[0081] During the preparation process of semiconductor structures, there may be problems of collapse and collapse, which are described in detail below in combination with the structure and existing preparation process.

[0082] Figure 1A and Figure 1B A structural diagram of a semiconductor structure provided in some embodiments of the present disclosure, Figure 2A to Figure 4A Another structural diagram of a semiconductor structure provided in some embodiments of the present disclosure. It should be noted that Figure 1A and Figure 1B , the first direction Y and the second direction X intersect, and the first direction Y and the second direction X are, for example, two orthogonal directions in the plane where the semiconductor structure 50 is located: the first direction Y is, for example, the extension direction of the first isolation structure 2, and the second direction X is, for example, the extension direction of the second isolation structure 4. The third direction Z is perpendicular to the plane where the semiconductor structure 50 is located, that is, perpendicular to the XY plane. Exemplarily, the second direction X is the word line direction, and the first direction Y is the bit line direction.

[0083] It should be noted that the labels "A to B" appearing in the drawings mean that structure / region A belongs to structure / region B, that is, the structure referred to by the labels is both structure A and structure B. For example, Figure 1B “CN~AA” means that the area indicated by the label is the storage area CN, and the storage area CN belongs to the core area AA.

[0084] As used in the present disclosure, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate of the semiconductor device in a third direction Z when the substrate is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied throughout the present disclosure to describe spatial relationships.

[0085] In some embodiments, Figure 1A , Figure 1B , Figure 3 As shown in FIG. 5 , in a plan view of the semiconductor structure, the semiconductor structure 50 includes a core region AA and a peripheral region BB located outside the core region AA. Figure 4A and Figure 4BAs shown, the semiconductor structure 50 includes a stacked structure 1, and the stacked structure 1 includes an insulating layer 11 and a gate layer 12 alternately stacked. The semiconductor structure 50 also includes a first isolation structure 2 and a second isolation structure 4, and the first isolation structure 2 and the second isolation structure 4 both penetrate the stacked structure. Exemplarily, the first isolation structure 2 extends along a first direction Y, and the second isolation structure 4 extends along a second direction X. The first isolation structure 2 isolates the core array block of the stacked structure, that is, the first isolation structure 2 separates the core area AA and the peripheral area BB, and the second isolation structure 4 extends along the second direction X and passes through the core area AA, and the second isolation structure 4 separates the stacked structure 1 into a plurality of storage blocks P.

[0086] In addition, the semiconductor structure further includes a plurality of channel structures, and the plurality of channel structures penetrate the stack structure 1 .

[0087] In some embodiments, the preparation method of the semiconductor structure is as follows: first, an initial stacking structure including multiple insulating layers and multiple sacrificial layers is formed, and then the sacrificial layers are replaced with gate layers. In this process, it is necessary to first form a first partition groove and a second partition groove that penetrate the initial stacking structure, remove the sacrificial layer through the first partition groove and the second partition groove to form a cavity, and then fill the gate material to form a gate layer. Finally, the first partition groove and the second partition groove are filled to form a first isolation structure 2 and a second isolation structure 4. After the cavity is formed, the multiple insulating layers are supported only by the channel structure. If the supporting force is insufficient, the multiple insulating layers will collapse. Furthermore, after the first partition groove and the second partition groove are formed, the initial stacking structure is cut and separated into independent storage blocks. The storage blocks are isolated from the surrounding structures, which may collapse in subsequent processes. For example, Figure 1A As shown, the storage block P will shake in the second direction Y.

[0088] Based on this, some embodiments of the present disclosure provide a semiconductor structure, a storage system, and a method for preparing a semiconductor structure to overcome the above problems. The semiconductor structure, the storage system, and the method for preparing a semiconductor structure provided by some embodiments of the present disclosure are introduced below.

[0089] Some embodiments of the present disclosure provide a method for preparing a semiconductor structure, such as Figure 4D As shown, it includes steps S1 to S8.

[0090] S1. Reference Figure 5 to Figure 7 , forming an initial stacking structure 1a, the initial stacking structure 1a includes multiple insulating layers 11 and multiple sacrificial layers 13, and the multiple insulating layers 11 and the multiple sacrificial layers 13 are alternately stacked.

[0091] For example, Figure 5 to Figure 7 As shown, in step S1 , an initial stacking structure 1 a is formed, for example, on one side of a substrate 101 .

[0092] In some examples, the substrate 101 may be a single-layer substrate or a composite substrate having a multi-layer structure.

[0093] The substrate 101 is a single-layer structure, and the substrate 101 may include one or more semiconductor materials such as silicon (e.g., single crystal silicon), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc.; the substrate 101 may also be made of non-conductive materials such as glass, plastic or sapphire wafer.

[0094] The substrate 101 is a multi-layer structure, and the substrate 101 may include, for example, a base plate and a first sacrificial layer and a second sacrificial layer sequentially stacked on the base plate.

[0095] The material of the above-mentioned base plate may include, for example, one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials; the base plate may also be made of non-conductive materials such as glass, plastic, or sapphire wafers. The material of the first sacrificial layer may include, for example, silicon oxide and / or silicon nitride. The material of the second sacrificial layer may include, for example, one or more of amorphous silicon, polycrystalline silicon, single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0096] On this basis, a single etch stop layer may be formed on the substrate 101 , or multiple etch stop layers may be formed.

[0097] Exemplarily, in step S1, a thin film deposition process is used to form a plurality of insulating layers 11 and a plurality of sacrificial layers 13 that are alternately stacked. The thin film deposition process includes, but is not limited to, a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), an atomic layer deposition process (ALD), or an electroplating process.

[0098] The initial stacking structure 1a includes multiple insulating layers 11 and multiple sacrificial layers 13, and the multiple insulating layers 11 and the multiple sacrificial layers 13 are alternately stacked. Alternating stacking means that in the thickness direction of the semiconductor structure (for example, parallel to the Z-axis direction), the multiple insulating layers 11 and the multiple sacrificial layers 13 are stacked, and the arrangement adopts an alternating arrangement; for example, in the direction from the bottom to the top of the initial stacking structure 1a, a layer of insulating layer 11 is first arranged, and then a layer of sacrificial layer 13 is arranged on the insulating layer 11, and then another layer of insulating layer 11 is arranged on the sacrificial layer 13, and so on. The initial stacking structure 1a is formed by alternating cycles.

[0099] It should be noted that Figure 7 The number of insulating layers 11 and sacrificial layers 13 is only for illustration. The embodiments of the present disclosure do not limit the number of insulating layers 11 and sacrificial layers 13, and they can be set accordingly as needed.

[0100] For example, the thickness of the multi-layer insulation layer 11, for example, the thickness of the insulation layer 11 along the Figure 7 The dimensions in the Z direction shown in the figure may be the same or different. Figure 7 The dimensions in the Z direction shown in the figure may be the same or different and may be set according to specific process requirements.

[0101] Exemplarily, the material of the above-mentioned insulating layer is an insulating material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and their silicates, and a combination of one or more of organic insulating materials. In addition, the materials of each dielectric layer in the multilayer dielectric layer can be the same or different. In the case where the materials of the multilayer dielectric layers of the stacked structure are the same, when the multilayer dielectric layers are formed, the preparation process of the initial stacked structure can be simplified.

[0102] Exemplarily, the material of the sacrificial layer includes, but is not limited to, a combination of one or more of silicon nitride, silicon oxide, and silicon oxynitride. In addition, the materials of each sacrificial layer in the multi-layer sacrificial layer may be the same or different. When the materials of the multi-layer sacrificial layers of the stacked structure are the same, the preparation process of the initial stacked structure can be simplified when the multi-layer sacrificial layers are formed.

[0103] S2, reference Fig. 9 , forming a first partition groove 21 and a plurality of channel holes K; the first partition groove 21 penetrates the initial stacking structure 1a, and the plurality of channel holes K penetrates the initial stacking structure 1a.

[0104] Exemplarily, an etching process is used to form the first isolation groove 21 and a plurality of channel holes K in the initial stacking structure 1 a.

[0105] The first partition groove 21 separates the peripheral area BB and the core area AA of the initial stacking structure 1 a , and a plurality of channel holes K are located in the core area AA.

[0106] In some examples, such as Fig. 9 As shown, the initial stacking structure 1 a includes multiple insulating layers 11 and multiple sacrificial layers 13 , and the layer farthest from the substrate 101 is the insulating layer 11 .

[0107] In some other examples, among the multiple insulating layers 11 and the multiple sacrificial layers 13 included in the initial stacked structure 1 a , the layer farthest from the substrate 101 is the sacrificial layer 13 .

[0108] The side of the initial stacking structure 1a away from the substrate 101 further includes, for example, an insulating cover layer. The first isolation groove 21 and a plurality of channel holes K penetrate the insulating cover layer and the initial stacking structure 1a.

[0109] The material of the insulating cover layer is an insulating material, and the material of the insulating cover layer includes but is not limited to silicon oxide and / or silicon nitride.

[0110] S3. Reference Fig.13 , a portion of the sacrificial layer 13 around the first partition 21 is removed to form a first cavity Q1 between two adjacent insulating layers 11 .

[0111] For example, refer to Fig.13 For example, a wet etching process is adopted to remove a portion of the sacrificial layer 13 around the first partition 21 with an etching solution. The etching solution can only etch and remove the sacrificial layer without causing damage to other structures in the semiconductor structure.

[0112] In some examples, the etching depth of the etching solution on the portion of the sacrificial layer 13 around the first groove 21 is controlled by controlling the reaction time of the etching solution, so that the sizes of the first cavity Q1 between every two adjacent insulating layers in the second direction X are equal or approximately equal.

[0113] S4. Reference Fig.14 and Fig.15 , a first isolation material G1 is filled in the first isolation groove 21 and the first cavity Q1 to form a first isolation structure 2; the first isolation structure 2 extends along the first direction Y, and includes a main structure 2a and a plurality of substructures 2b respectively located on both sides of the main structure 2a along the second direction X, the substructures 2b are connected to the side walls of the main structure 2a, each substructure 2b is inserted between two adjacent insulating layers 11, and the second direction X and the first direction Y intersect.

[0114] Exemplarily, the first isolation material G1 is an insulating material.

[0115] In some embodiments, the first isolation material G1 includes, but is not limited to, a combination of one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0116] The process of filling the first isolation material G1 may be, for example, a chemical vapor deposition process, an atomic layer deposition process, a plasma deposition process, or the like.

[0117] In the process of filling the first isolation material, the first isolation material is filled in the first cavity Q1 to form a plurality of substructures 2b, and the first isolation material is filled in the first partition groove 21 to form a main structure 2a. The first isolation structure 2 includes a main structure 2a and a plurality of substructures 2b respectively located on both sides of the main structure 2a along the second direction X. The substructure 2b is connected to the side wall of the main structure 2a, and each substructure 2b is inserted between two adjacent insulating layers 11. By setting the main structure 2a and the substructure 2b, the bonding force between the first isolation structure 2 and the initial stacking structure 1a can be enhanced, thereby enhancing the supporting force and preventing collapse in subsequent processes.

[0118] S5. Reference Fig.17 , a channel material G2 is filled in a plurality of channel holes K to form a plurality of channel structures 3 .

[0119] For example, refer to Fig.17 A thin film deposition process is used to fill the channel hole K with a channel material G2, wherein the channel material G2 includes a functional layer material and a semiconductor layer material, wherein the functional layer surrounds the semiconductor layer, the functional layer serves as a storage film, for example, and the semiconductor layer serves as a semiconductor channel, for example.

[0120] In some embodiments, the functional layer is, for example, a composite layer including a tunneling layer, a storage layer (also referred to as a “charge trapping layer”), and a blocking layer which are sequentially stacked from the outer sidewall of the semiconductor layer.

[0121] In some examples, the tunneling layer includes, but is not limited to, silicon oxide, silicon oxynitride, or any combination thereof.

[0122] In some examples, the storage layer includes, but is not limited to, silicon nitride, silicon oxynitride, silicon, or any combination thereof.

[0123] In some examples, the barrier layer includes, but is not limited to, silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof.

[0124] In some examples, the storage film includes, but is not limited to, a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0125] In some examples, the material of the semiconductor layer includes, but is not limited to, silicon and polycrystalline silicon. The material of the semiconductor layer is, for example, amorphous silicon, polycrystalline silicon, or a combination of one or more of monocrystalline silicon.

[0126] Exemplarily, the shape of the channel structure 3 includes but is not limited to a columnar shape.

[0127] Exemplarily, after forming the functional layer and the semiconductor layer, the remaining space of the channel structure 3 (the remaining space within the channel hole K excluding the functional layer and the semiconductor layer) can be partially or completely filled with a capping layer and / or an air gap comprising a dielectric material (e.g., silicon oxide), wherein the capping layer is closer to the center of the column than the semiconductor layer.

[0128] S6. Reference Figure 18A to Figure 19 , forming a second partition groove 41, the second partition groove 41 extends along the second direction X and penetrates the initial stacking structure 1a; the second partition groove 41 extends along the second direction X.

[0129] Exemplarily, an etching process is used to form the second isolation groove 41 in the initial stacking structure 1 a.

[0130] Exemplarily, the side of the initial stacking structure away from the substrate further includes an insulating cover layer, for example. The gate line trench penetrates the insulating cover layer and the initial stacking structure.

[0131] The material and setting method of the insulating covering layer refer to the description in step S2 and will not be repeated here.

[0132] S7, reference Fig. 20 , at least part of the sacrificial layer 13 is replaced with the gate layer 12 via the second partition groove 41 to form a stacked structure 1 .

[0133] It should be noted that replacing at least part of the sacrificial layer 13 with the gate layer 12 means replacing at least the sacrificial layer 13 in the core area with the gate layer 12. At this time, the initial stacking structure becomes a stacking structure 1 after the gate replacement, and the stacking structure 1 includes insulating layers and gate layers alternately stacked, the first isolation structure penetrates the stacking structure and extends along the first direction Y, and the second isolation groove extends along the second direction X.

[0134] In some embodiments, during the gate replacement process, the sacrificial layer is replaced with the gate layer via the first partition groove and the second partition groove, and then the first partition groove and the second partition groove are filled to form the first isolation structure and the second isolation structure. That is, the first isolation structure 2 is not formed before the gate layer is formed. In the multi-layer insulation layer 11, the adjacent insulation layers 11 lose support, and the support force of the multiple channel structures 3 is insufficient, which easily causes the insulation layer 11 to be delaminated and bent. For example, the plane of the insulation layer 11 is parallel to the Figure 3 The plane where the X direction is and the plane where the Y direction is shown in the figure, when the insulating layer 11 has the problem of delamination and bending, there is an angle between the surface of the insulating layer 11 and the plane where the X direction is and the plane where the Y direction is.

[0135] It is understandable that when the insulating layer 11 has a delamination and bending problem, the adjacent insulating layers 11 are Figure 3The spacing in the Z direction shown in the figure will decrease or even become zero, resulting in that the sacrificial layer in some areas cannot be replaced during the formation of the gate layer, and the above-mentioned stacking structure 1 cannot be formed.

[0136] On the other hand, continue to refer to Figure 3 The storage block P is separated by the first partition groove and the second partition groove, and the storage block is isolated from the surrounding structures. This will cause the storage block to lack support, and the two ends of the storage block P are prone to shaking along the first direction Y, causing collapse. For example, a storage block P collapses toward one side of the first direction Y, which will cause the size of the second partition groove on the collapsed side to decrease, and the size of the second partition groove on the other side to increase, affecting the normal progress of the gate replacement process.

[0137] In some embodiments of the present disclosure, according to the foregoing introduction, since the first isolation structure 2 has been formed in step S4 and the channel structure 3 has been formed in step S5 before the gate replacement process, in the process of forming the gate layer 12, between adjacent insulating layers 11, the first isolation structure 2 and the channel structure 3 can both play a certain supporting role, which can prevent the problem of delamination and bending of the insulating layer 11, and since the two ends of the storage block P are fixed by the first isolation structure 2, the problem of shaking of the storage block P is improved, and the size of the second partition groove 41 will not be affected, so as to better form the gate layer 12, and then form the stacked structure 1.

[0138] In addition, since in steps S3 and S4, the first isolation structure 2 formed includes a main structure 2a and a plurality of substructures 2b respectively located on both sides of the main structure 2a along the second direction X, the substructure 2b is connected to the side wall of the main structure 2a, and each substructure 2b is inserted between two adjacent insulating layers 11, which is equivalent to the first isolation structure 2 having a plurality of branches inserted into the stacking structure. This can further enhance the bonding force between the first isolation structure 2 and the initial stacking structure 1a, so that in the gate replacement process, the first isolation structure has a stronger supporting effect on the insulating layer and a stronger fixing effect on the two ends of the storage block separated by the second partition groove 41, further improving the problem of storage block shaking and ensuring the smooth progress of the preparation process.

[0139] It should be noted that the sequence of the above-mentioned steps S4 and S5 is only used as an illustration of a possible method for preparing the semiconductor structure of the present application, and the present application does not limit the sequence of preparing steps S4 and S5.

[0140] S8. Reference Fig.21 , a second isolation material G3 is deposited in the second isolation groove 41 to form a second isolation structure 4.

[0141] Exemplarily, the second isolation material G3 is an insulating material.

[0142] In some embodiments, the second isolation material G3 includes, but is not limited to, a combination of one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0143] It should be noted that, refer to Figure 1B As shown, a plurality of storage blocks P are arranged in the storage area CN. In order to isolate different storage blocks P, the boundary of each storage block P needs to have a first isolation structure extending along the first direction Y and a second isolation structure extending along the second direction X.

[0144] In summary, the semiconductor structure obtained by the semiconductor structure preparation method provided by some embodiments of the present disclosure can simplify the preparation process because the first partition groove 21 and the multiple channel holes K are formed synchronously, and the first isolation structure 2 includes a main structure 2a and a substructure 2b, which can enhance the bonding force between the first isolation structure 2 and the initial stacking structure 1a, thereby enhancing the supporting force and preventing collapse in subsequent processes; further, the gate layer 12 is formed after the first isolation structure 2 and the channel structure 3, and the first isolation structure 2 and the channel structure 3 can both play a certain supporting role, which can prevent the problem of delamination and bending of the insulating layer 11 and the problem of shaking of the storage block P, so as to better form the gate layer 12.

[0145] The semiconductor structure obtained according to the above-mentioned preparation method is introduced below.

[0146] Some embodiments of the present disclosure also provide a semiconductor structure 50. Figure 4A As shown, the semiconductor structure 50 includes a stacked structure 1 and a first isolation structure 2. The stacked structure 1 includes a multi-layer insulation layer 11 and a multi-layer gate layer 12, and the multi-layer insulation layer 11 and the multi-layer gate layer 12 are alternately stacked. The first isolation structure 2 runs through the stacked structure 1, and the first isolation structure 2 extends along the first direction Y; the first isolation structure 2 includes a main structure 2a and a plurality of sub-structures 2b respectively located on both sides of the main structure 2a along the second direction X, the sub-structures 2b are connected to the side walls of the main structure 2a, and each sub-structure 2b is inserted between two adjacent insulation layers 11; the second direction X intersects with the first direction Y.

[0147] For example, refer to Figure 4A to Figure 4C , Figure 4C The figure shows an enlarged view of the first isolation structure 2, wherein the substructures 2b of the first isolation structure 2 are located on both sides of the main structure 2a along the second direction X. Since each substructure 2b is inserted between two adjacent insulating layers 11, the bonding force between the first isolation structure 2 and the initial stacking structure 1a can be enhanced, thereby enhancing the supporting force and preventing collapse in subsequent processes. Moreover, after the semiconductor structure is prepared, the bonding force between the first isolation structure 2 and the stacking structure 1 is enhanced, which can improve the stability of the semiconductor structure.

[0148] In some embodiments, reference Figure 4C , Fig.14 and Fig.15 As shown, the main structure 2a and the plurality of substructures 2b of the first isolation structure 2 all include a first isolation material G1.

[0149] Exemplarily, the first isolation material G1 is an insulating material.

[0150] In some embodiments, the first isolation material G1 includes, but is not limited to, a combination of one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0151] It should be noted that, according to the introduction of the aforementioned step S4, the main structure 2a and multiple substructures 2b of the first isolation structure 2 are formed at one time, and the first isolation material G1 is filled in the first isolation groove 21 to form the above-mentioned main structure 2a, and at the same time, the first isolation material G1 is filled in the first cavity Q1 to form multiple substructures 2b.

[0152] In some embodiments, reference Figure 4B and Fig.19 The semiconductor structure 50 further includes a dielectric layer 14 , which is located at least between the adjacent insulating layer 11 and the gate layer 12 ; the dielectric layer 14 is also disposed between the substructure 2 b and the gate layer 12 in the same layer.

[0153] It should be noted that the material of the dielectric layer 14 can be, for example, a material with a high dielectric constant (High-K) which has good stability and good insulation performance. It can play a good insulation role when arranged between adjacent insulating layers 11 and gate layers 12 and between the substructure 2b and the gate layer 12 in the same layer to prevent the generation of leakage current.

[0154] By way of example, the dielectric layer 14 may include, for example, a metal oxide or a metal nitride. The metal oxide may include, for example, aluminum oxide, and the metal nitride may include titanium nitride, tantalum nitride, or tungsten nitride.

[0155] The steps of forming the dielectric layer 14 are described below. As mentioned above, in some embodiments, S7: at least part of the sacrificial layer 13 is replaced with the gate layer 12 via the second partition 41 to form a stacked structure 1, such as Figure 4G As shown, the following steps S71 to S73 are also included:

[0156] S71, reference Fig.18B , at least the sacrificial layer 13 located in the storage area CN is removed through the second partition groove 41 to form a second cavity Q2.

[0157] For example, Fig.18BAs shown, the sacrificial layer 13 located in the storage area CN is completely removed to form a second cavity Q2. In order to form a gate layer in the storage area in the subsequent steps,

[0158] In some examples, the sacrificial layer located in the peripheral area BB is also removed in S71 .

[0159] In this step, the etching liquid contacts the multiple sacrificial layers through the second partition groove 41. The etching direction of the etching liquid is to diffuse from the second partition groove 41 to the surrounding areas, gradually removing the sacrificial layers. The etching liquid does not react with the insulating layer, the channel structure 3 and the first isolation structure 2. After the sacrificial layer 13 is etched, a second cavity Q2 is formed between adjacent insulating layers 11.

[0160] S72, such as Fig.19 and Fig. 20 As shown, a dielectric material is deposited in the second cavity Q2 to form a dielectric layer 14 attached to the cavity wall of the second cavity Q2 and the bottom and sidewall of the second partition groove 41 .

[0161] By way of example, the material of the dielectric layer 14 may include, for example, metal oxide or metal nitride. Please refer to the introduction in the above section for details.

[0162] Exemplarily, the material of the dielectric layer 14 can be a high dielectric constant (High-K) material with good stability and good insulation performance. It is arranged to be attached to the cavity wall of the second cavity Q2 and the bottom and side walls of the second partition 41 to play a good insulation role and prevent the generation of leakage current.

[0163] The dielectric material enters the initial stacking structure 1a through the second partition groove 41 and is deposited on the cavity wall of the second cavity Q2 and the bottom and sidewall of the second partition groove 41. Fig.19 As described above, the dielectric material is deposited on the upper and lower surfaces of the insulating layer 11, and on the side surface exposed in the second partition groove 41. At the same time, the dielectric material is also deposited on the surface of the first isolation structure 2 exposed in the second cavity Q2, and on the surface of the channel structure 3 exposed in the second cavity Q2. For example, the dielectric material is formed on the end surface 2bb (such as the side surface 2bb of the substructure 2b of the first isolation structure 2 facing the second cavity Q2) Figure 4C )superior.

[0164] S73, such as Fig. 20 As shown, a conductive material G4 is filled in the second cavity Q2 to form a multi-layer gate layer 12 .

[0165] Exemplarily, the conductive material G4 includes, but is not limited to, one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and metal silicide. In addition, the material of each gate layer 12 in the multi-layer gate layer 12 can be the same or different.

[0166] After the dielectric layer 14 is formed on the cavity wall of the second cavity Q2, the conductive material G4 is introduced into the second cavity Q2 through the second partition 41, thereby forming the gate layer 12. In this way, the dielectric layer 14 is formed between the adjacent insulating layers 11 and the gate layer 12, and the substructure 2b of the first isolation structure 2 inserted between the two adjacent insulating layers 11 will not directly contact the gate layer 12 of the same layer, and the dielectric layer 14 is arranged between the substructure 2b and the gate layer 12 of the same layer.

[0167] The process for forming the gate layer 12 may be, for example, a chemical vapor deposition process, an atomic layer deposition process, a plasma deposition process, or the like.

[0168] In other embodiments, the semiconductor structure does not include a dielectric layer, that is, the stacked structure 1 includes insulating layers 11 and gate layers 12 that are alternately arranged, that is, there is no step of filling the dielectric material in S72, and the surfaces of the substructure 2b and the gate layer 12 in the same layer are in direct contact with each other.

[0169] In some embodiments, reference Figure 2A to Figure 3 The semiconductor structure 50 also includes a second isolation structure 4 extending along the second direction X; the second isolation structure 4 runs through the stacking structure 1, the stacking structure 1 has a core area AA and a peripheral area BB located outside the core area AA, and the first isolation structure 2 separates the core area AA and the peripheral area BB; the core area AA includes a connection area LN and a storage area CN, and the second isolation structure 4 runs through the connection area LN and the storage area CN.

[0170] In some examples, such as Figure 4B and Fig.21 As shown, the second isolation structure 4 includes a dielectric structure 43 and a filling structure 42 ; the dielectric structure 43 is located at the bottom of the filling structure 42 and between the filling structure 42 and the plurality of insulating layers 11 .

[0171] Referring to the description of S72, it can be seen that Fig.19 and Fig. 20 As shown, a dielectric material is deposited in the second cavity Q2 to form a dielectric layer 14 attached to the cavity wall of the second cavity Q2 and the bottom and sidewalls of the second partition 41. The dielectric material enters the initial stacking structure 1a through the second partition 41 and is deposited on the cavity wall of the second cavity Q2 and the bottom and sidewalls of the second partition 41, wherein the sidewall of the second partition 41 is the side of the insulating layer 11 exposed in the second partition 41. In other words, the dielectric structure 43 is a portion of the dielectric layer 14 located in the second partition 41, and the material of the dielectric structure is a dielectric material. The specific material can refer to the description of the dielectric layer 14 in the aforementioned part, and will not be repeated here.

[0172] Referring to the description of step S8, a second isolation material G3 is deposited in the second isolation trench 41 to form a second isolation structure 4. After a dielectric material is deposited on the bottom and sidewalls of the second isolation trench 41 to form a dielectric structure 43, the second isolation material is deposited in the second isolation trench to form a filling structure 42, so that the dielectric structure 43 and the filling structure 42 in the second isolation trench form a second isolation structure, and the dielectric structure 43 is located at the bottom of the filling structure 42 and between the filling structure 42 and the plurality of insulating layers 11 (i.e., the dielectric structure 43 is located at the bottom and sidewalls of the second isolation trench).

[0173] In other examples, such as Figure 4A As shown, the semiconductor structure 50 does not include the dielectric layer 14 , and the second isolation structure includes a filling structure 42 .

[0174] In the step of forming the second isolation material, the second isolation material is filled in the second isolation groove, and the filling structure 42 is in contact with the side surfaces of the gate layer 12 and the insulating layer 11 exposed in the second isolation groove.

[0175] In some embodiments, the orthographic projection of the second isolation structure 4 on the first plane M1 at least partially overlaps with the orthographic projection of the first isolation structure 2 on the first plane M1 ; the first plane M1 is parallel to the surface of the stacked structure 1 .

[0176] It can be understood that the first plane M1 is parallel to the surface of the stacked structure 1 , that is, the first plane M1 is parallel to the plane where the second direction X is located and the plane where the first direction Y is located. Figure 2A to Figure 2C FIG. 1 is a structural diagram showing the positional relationship between the first isolation structure 2 and the second isolation structure 4 in the first plane M1 according to some embodiments.

[0177] In some examples, Figure 1A and Figure 1B In the structural diagram of the positional relationship between the first isolation structure 2 and the second isolation structure 4 in the first plane M1 in some embodiments, it can be seen that the orthographic projection of the second isolation structure 4 on the first plane M1 does not overlap with the orthographic projection of the first isolation structure 2 on the first plane M1, that is, the end of the second isolation structure 4 close to the first isolation structure 2 is in contact with the side wall of the first isolation structure 2. This is because the first partition groove and the second partition groove are formed simultaneously, and the sacrificial layer is removed through the first partition groove and the second partition groove to form a cavity, and then the gate material is filled to form a gate layer. Finally, the first partition groove and the second partition groove are filled, and the first isolation structure and the second isolation structure can be formed simultaneously without overlapping. Since the etching solution can enter the initial stacking structure through the first partition groove and the second partition groove, the sacrificial layer can be relatively fully removed.

[0178] In the method for preparing the semiconductor structure of the present application, a first partition groove is first formed, and then the first partition groove is filled to form a first isolation structure 2, and then a second partition groove is formed to perform a gate replacement process. In this way, when the second partition groove is formed to form the initial stacked structure into a plurality of independent storage blocks, the storage block P may be insufficiently isolated. Since the sacrificial layer can only be removed through the second partition groove, the sacrificial layer near the first isolation structure 2 cannot be fully removed, and some residues will remain, which affects the normal realization of the semiconductor storage function, and at the same time, the storage blocks cannot be guaranteed to be fully separated, and finally signal interference occurs between adjacent storage blocks P, affecting the performance of the memory.

[0179] It should be noted that the orthographic projection of the second isolation structure 4 on the first plane M1 overlaps at least partially with the orthographic projection of the first isolation structure 2 on the first plane M1, that is, the second isolation structure 4 at least partially penetrates the first isolation structure in the second direction X. For example, when the second isolation groove is formed in S6, the second isolation groove at least partially penetrates the first isolation structure 2. This arrangement can ensure that the storage blocks are fully separated, increase the reaction contact area between the sacrificial layer and the etching liquid near the first isolation structure 2, ensure that the sacrificial layer can be fully in contact with the etching liquid, and thus ensure that the sacrificial layer is completely replaced by the gate layer, thereby improving the reliability of the semiconductor structure. Moreover, with this arrangement, the first isolation structure 2 can still be tightly combined with the end (multi-layer insulation layer) of the storage block P, and the supporting function of the first isolation structure 2 on the initial stacking structure will not be affected.

[0180] Several examples in which the orthographic projections of the second isolation structure 4 and the first isolation structure 2 at least partially overlap are introduced below.

[0181] For example, refer to Figure 2A , the second isolation structure 4 passes through the first isolation structure 2 and enters the peripheral area BB. In other words, the second isolation structure 4 can penetrate from the inside of the first isolation structure 2 and extend to the peripheral area BB. This arrangement can ensure that adjacent storage blocks P are completely isolated. On the one hand, the first isolation structure can continue to play a supporting role to prevent collapse or shaking in the subsequent gate replacement process. On the other hand, the storage blocks can be fully isolated to ensure the smooth progress of the subsequent gate replacement process.

[0182] For example, refer to Figure 2B , the end of the second isolation structure 4 close to the first isolation structure penetrates the first isolation structure 2 and is flush with the side of the first isolation structure 2 close to the peripheral area BB, and the second isolation structure just penetrates the first isolation structure completely and does not extend to the peripheral area. Similarly, it can ensure that adjacent storage blocks P are completely isolated, with the above-mentioned beneficial effects, which will not be repeated here one by one.

[0183] For example, refer to Figure 2C The second isolation structure 4 enters the first isolation structure 2 near the end of the first isolation structure 2. For example, the second isolation structure 4 penetrates half of the first isolation structure 2, and also has the above-mentioned beneficial effects, which will not be elaborated here.

[0184] In some embodiments, continue to refer to Figure 2A to Figure 2C The semiconductor structure 50 further includes a plurality of virtual channel structures 6 located in the peripheral area BB, and a plurality of channel structures 3 located in the core area AA. Exemplarily, the plurality of virtual channel structures 6 and the channel structures 3 are formed synchronously and have the same film layer structure. The plurality of virtual channel structures 6 and the plurality of channel structures 3 all penetrate the pair structure 1, including a functional layer and a semiconductor layer, wherein the functional layer surrounds the semiconductor layer, the functional layer is used as a storage film, for example, and the semiconductor layer is used as a semiconductor channel, for example.

[0185] In some embodiments, the functional layer is, for example, a composite layer including a tunneling layer, a storage layer (also referred to as a “charge trapping layer”), and a blocking layer which are sequentially stacked from the outer sidewall of the semiconductor layer.

[0186] like Figure 2A As shown, when the second isolation structure 4 passes through the first isolation structure 2 and enters the peripheral area BB, the multiple virtual channel structures 6 include a first partial virtual channel structure 61 and a second partial virtual channel structure 62, and the first partial virtual channel structure 61 and the second partial virtual channel structure 62 are respectively located on both sides of the second isolation structure 4.

[0187] There is a first interval h1 between the first partial dummy channel structure 61 and the second isolation structure 4 , and there is a second interval h2 between the second partial dummy channel structure 62 and the second isolation structure 4 .

[0188] For example, Figure 2A As shown, the first isolation structure 2 separates the peripheral area BB from the storage area CN, wherein the peripheral area BB is provided with a plurality of virtual channel structures 6, and the storage area CN is provided with a plurality of channel structures 3. The arrangement of the plurality of virtual channel structures 6 and the plurality of channel structures 3 can provide a certain supporting force to avoid collapse caused by insufficient supporting force during the preparation process; the second isolation structure 4 passes through the first isolation structure 2 and enters the peripheral area BB to separate the plurality of virtual channel structures 6 into a first portion of virtual channel structures 61 and a second portion of virtual channel structures 62, wherein the first portion of virtual channel structures 61 and the second isolation structure 4 have a first spacing h1, and the second portion of virtual channel structures 62 and the second isolation structure 4 have a second spacing h2, wherein the first spacing h1 and the second spacing h2 may be the same or different, and the main purpose of setting the first spacing h1 and the second spacing h2 is to avoid contact between the first portion of virtual channel structures 61 and the second portion of virtual channel structures 62 and the second isolation structure 4.

[0189] In some embodiments, continue to refer to Figure 2A The semiconductor structure 50 further includes a support column 7 located in the peripheral area BB, the support column 7 penetrates the stacked structure 1 ; the support column 7 is located between the first partial dummy channel structure 61 and the second partial dummy channel structure 62 .

[0190] It can be understood that the first partial virtual channel structure 61 and the second partial virtual channel structure 62 are partially isolated by the second isolation structure 4, and the first partial virtual channel structure 61 and the second partial virtual channel structure 62 on the side away from the first isolation structure 2 can be isolated by the support column 7. At the same time, the support column 7 has a supporting function and can also prevent collapse during the gate replacement process.

[0191] Exemplarily, the material of the support column 7 is, for example, an insulating material.

[0192] According to the introduction of the above content, it can be known that the multiple virtual channel structures 6 and the multiple channel structures 3 are formed together, and the filling materials of the two are consistent, both of which are channel materials G2. The support column 7 has the same supporting function as the multiple virtual channel structures 6, but the two have different preparation processes due to the inconsistent filling. For example, after S1, it also includes the step of forming a support hole, and the support hole penetrates the initial stacking structure. Before forming the second partition groove in S6, it also includes the step of filling the support hole with insulating material to form the support column 7, so that in the gate replacement process, the support column can play a certain supporting role.

[0193] In some embodiments, reference Figure 3 As shown, the semiconductor structure 50 also includes a third isolation structure 5 extending along the second direction X, and the third isolation structure 5 runs through the stacking structure 1; the third isolation structure 5 is located between two adjacent second isolation structures 4; the third isolation structure 5 is at least located in the storage area CN; each storage block P is divided into two sub-storage blocks P1 by the third isolation structure 5, and the third isolation structure is formed by a third partition groove, and the third isolation structure 5 also has the function of the second isolation structure 4. When the gate is replaced, the etching liquid can enter the initial stacking structure through the second partition groove and the third partition groove at the same time, thereby increasing the contact area between the etching liquid and the sacrificial layer, accelerating the reaction rate, and enabling the sacrificial layer to be removed faster and more fully. In addition, the gate material can enter the second cavity through the second partition groove and the third partition groove, thereby accelerating the formation rate of the gate layer, thereby improving the preparation efficiency.

[0194] The orthographic projection of the third isolation structure 5 on the first plane M1 at least partially overlaps with the orthographic projection of the first isolation structure 2 on the first plane M1.

[0195] It can be understood that the orthographic projection of the third isolation structure 5 on the first plane M1 overlaps at least partially with the orthographic projection of the first isolation structure 2 on the first plane M1, that is, the third isolation structure 5 penetrates at least a portion of the first isolation structure 2. Figure 3 When forming the third partition groove, the third partition groove is made to penetrate at least part of the first isolation structure 2. This arrangement can ensure that the sub-memory blocks are fully separated, increase the reaction contact area between the sacrificial layer near the first isolation structure 2 and the etching liquid, ensure that the sacrificial layer can be fully in contact with the etching liquid, and thus ensure that the sacrificial layer is completely replaced by the gate layer, thereby improving the reliability of the semiconductor structure. In addition, with this arrangement, the first isolation structure 2 can still be tightly combined with the end (multi-layer insulation layer) of the sub-memory block P1, and the supporting function of the first isolation structure 2 on the initial stacking structure will not be affected.

[0196] Exemplarily, the third isolation structure 5 enters the first isolation structure 2 near the end of the first isolation structure 2 .

[0197] Exemplarily, the third isolation structure 5 penetrates the first isolation structure 2 near the end of the first isolation structure 2 and is flush with the side surface of the first isolation structure 2 near the peripheral area BB.

[0198] Exemplarily, the third isolation structure 5 passes through the first isolation structure 2 and enters the peripheral region BB.

[0199] The above are three specific forms of the positional relationship between the third isolation structure 5 and the first isolation structure 2 in some embodiments, which are not limited here, and all have the above-mentioned beneficial effects, which will not be described one by one here.

[0200] In some embodiments, reference Figure 2A , a dimension H3 of the first isolation structure 2 in the second direction X is greater than a dimension H4 of the second isolation structure 4 in the first direction Y.

[0201] It should be noted that, according to the introduction of the aforementioned preparation method, the first isolation structure 2 is formed before the second isolation structure 4, and the first isolation structure 2 has a certain supporting effect during the gate replacement process. Therefore, the dimension H3 of the first isolation structure 2 in the second direction X is set to be larger than the dimension H4 of the second isolation structure 4 in the first direction Y to ensure that the supporting effect is fully realized.

[0202] The following describes the specific steps of the method for preparing the semiconductor structure. Figure 5 to Figure 21 As shown, the method for preparing the semiconductor structure includes S21, S22, S221, S23, S24, S241, S242, S242-1, S242-2, S242-3, S243, S3, S41, S4-1, S4-2, S51, S6, S71, S72, S73 and S8 arranged in sequence.

[0203] In some embodiments, according to the above-mentioned step S1 and step S2 of the method for preparing the semiconductor structure 50, as shown in FIG. Figure 4E As shown, the process specifically includes the following steps S21 to S24:

[0204] S21, such as Figure 5 As shown, an initial first stacking structure 1a1 is formed.

[0205] For example, Figure 5 As shown, the initial first stacked structure 1 a 1 includes a plurality of insulating layers 11 and a plurality of sacrificial layers 13 , and the plurality of insulating layers 11 and the plurality of sacrificial layers 13 are alternately stacked.

[0206] For example, refer to Figure 5 , the initial first stacked structure 1 a 1 is, for example, formed on one side of the substrate 101 .

[0207] The number of layers of the initial first stacking structure 1 a 1 is, for example, half the number of layers of the initial stacking structure 1 a .

[0208] S22, such as Figure 6 As shown, a plurality of first sub-channel holes K1 and first sub-grooves 21a are formed. The plurality of first sub-channel holes K1 penetrate the initial first stacking structure 1a1. The first sub-grooves 21a penetrate the initial first stacking structure 1a1. The first sub-grooves 21a extend along the first direction Y.

[0209] Illustratively, an etching process is used to form a plurality of first sub-channel holes K1 and first sub-grooves 21 a in the initial first stacking structure 1 a 1 , and bottoms of the plurality of first sub-channel holes K1 and first sub-grooves 21 a may be embedded in the substrate 101 .

[0210] like Figure 6 As shown, in the process of forming the first sub-channel hole K1 and the first sub-groove 21a, the etching difficulty increases with the increase of the etching depth, and the size of the end of the first sub-channel hole K1 formed close to the substrate is smaller than the size of the end away from the substrate. For example, along the direction pointing to the substrate, the size of the first sub-channel hole K1 gradually decreases. The size of the end of the first sub-groove 21a formed close to the substrate is smaller than the size of the end away from the substrate. For example, along the direction pointing to the substrate, the size of the first sub-groove 21a gradually decreases.

[0211] S221, such as Figure 7 As shown, a first sacrificial material R1 is deposited in the plurality of first sub-channel holes K1 and the first sub-trench 21 a.

[0212] Exemplarily, a deposition process is used to fill the first sacrificial material R1 in the plurality of first sub-channel holes K1 and the first sub-grooves 21a. The deposition process includes but is not limited to a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.

[0213] Exemplarily, the first sacrificial material R1 is, for example, carbon.

[0214] S23, such as Figure 7 As shown, an initial second stacking structure 1a2 is formed on the initial first stacking structure 1a1; the initial second stacking structure and the initial first stacking structure 1a1 constitute an initial stacking structure 1a.

[0215] For example, Figure 7 As shown, the initial second stacked structure 1 a 2 includes a plurality of insulating layers 11 and a plurality of sacrificial layers 13 , and the plurality of insulating layers 11 and the plurality of sacrificial layers 13 are alternately stacked.

[0216] For example, Figure 7 As shown, the initial second stacking structure 1 a 2 is, for example, formed on the initial first stacking structure 1 a 1 , and the initial second stacking structure 1 a 2 is farther away from the substrate 101 than the initial first stacking structure 1 a 1 .

[0217] S24, such as Figure 8 As shown, a plurality of second sub-channel holes K2 and second sub-grooves 21b are formed. The plurality of second sub-channel holes K2 penetrate the initial second stacking structure 1a2. The second sub-grooves 21b penetrate the initial second stacking structure 1a2. The second sub-grooves 21b extend along the first direction Y.

[0218] Exemplarily, an etching process is used to form a plurality of second sub-channel holes K2 and second sub-grooves 21b in the initial second stacking structure 1a2, the plurality of second sub-channel holes K2 and the plurality of first sub-channel holes K1 correspond in position, and the second sub-grooves 21b and the first sub-grooves 21a correspond in position. The corresponding position here means that the centers of the plurality of second sub-channel holes K2 and the centers of the plurality of first sub-channel holes K1 are located on the same straight line, and the centers of the second sub-grooves 21b and the centers of the first sub-grooves 21a are located on the same straight line.

[0219] The corresponding first sub-channel hole K1 and the second sub-channel hole K2 form a channel structure K, and the corresponding first sub-grooves 21 a and second sub-grooves 21 b form a first groove 21 .

[0220] like Figure 8As shown, in the process of forming the second sub-channel hole K2 and the second sub-slot 21b, the etching difficulty increases with the increase of the etching depth, and the size of the end of the second sub-channel hole K2 formed close to the substrate is smaller than the size of the end away from the substrate. For example, along the direction pointing to the substrate, the size of the second sub-channel hole K2 gradually decreases. The size of the end of the second sub-slot 21b formed close to the substrate is smaller than the size of the end away from the substrate. For example, along the direction pointing to the substrate, the size of the second sub-slot 21b gradually decreases.

[0221] like Figure 4E and Figure 4F As shown, step 24 specifically also includes the following steps S241 to S243:

[0222] S241, such as Fig. 9 As shown, the first sacrificial material R1 in the plurality of first sub-channel holes K1 and the first sub-grooves 21 a is removed.

[0223] Exemplarily, the first sacrificial material R1 is carbon, for example. When the first sacrificial material R1 is removed, impurities in the plurality of first sub-channel holes K1 and the first sub-grooves 21 a can be removed together, which has a certain cleaning effect and facilitates subsequent material filling.

[0224] The process of removing the first sacrificial material is, for example, a wet cleaning process.

[0225] S242, such as Fig.10 As shown, the second sacrificial material R2 is deposited in the plurality of first sub-channel holes K1 , the first sub-grooves 21 a , and the plurality of second sub-channel holes K2 and the second sub-grooves 21 b .

[0226] For example, the deposition process is described above and will not be described in detail here.

[0227] Exemplarily, the second sacrificial material R2 is, for example, carbon.

[0228] During the deposition of the second sacrificial material R2, Fig.10 As shown, the surface of the initial stacked structure 1 a is also covered with a second sacrificial material.

[0229] S242-1, reference Fig.11A , remove the second sacrificial material R2 on the surface of the initial second stacking structure 1a2.

[0230] Exemplarily, the second sacrificial material R2 on the surface of the initial second stacking structure 1a2 is removed by a grinding process to expose the surface of the initial second stacking structure 1a2.

[0231] S242-2, reference Fig.11A, a first insulating material G5 is deposited on the initial second stacked structure 1 a 2 to form a first insulating layer 15 .

[0232] S242-3, reference Fig. 11B , a portion of the first insulating layer 15 located on the second sub-groove 21 b is removed to expose the second sacrificial material R2 in the second sub-groove 21 b.

[0233] Exemplarily, a photolithography process is used to remove the portion of the first insulating layer 15 located on the second sub-groove 21 b . Fig. 11B The film layer located above the first insulating layer 15 is a mask, and the opening of the mask exposes the portion of the first insulating layer 15 located on the second sub-groove 21b, so as to perform an exposure and development process on the first insulating layer 15, and finally remove the portion exposed by the opening.

[0234] S243, such as Fig.12 As shown, the second sacrificial material R2 in the second sub-grooves 21 b and the first sub-grooves 21 a is removed.

[0235] Exemplarily, the second sacrificial material R2 has the function of the first sacrificial material R1 , and specific reference is made to the above description of the first sacrificial material R1 .

[0236] Exemplarily, the process of removing the second sacrificial material R2 is, for example, a wet cleaning process.

[0237] After the second sacrificial material R2 is removed, the side surfaces of the insulating layer 11 and the sacrificial layer 13 are exposed in the second sub-groove 21 b and the first sub-groove 21 a. The second sub-groove 21 b and the first sub-groove 21 a form the first groove 21 .

[0238] S3. Reference Fig.13 , a portion of the sacrificial layer 13 around the first partition 21 is removed to form a first cavity Q1 between two adjacent insulating layers 11 .

[0239] For a detailed description of S3, please refer to the previous description.

[0240] S41. Reference Fig.14 The first isolation material G1 is filled in the first sub-groove 21 a , the second sub-groove 21 b and the first cavity Q1 to form a first isolation structure 2 .

[0241] It should be noted that the first sub-groove 21a and the second sub-groove 21b constitute the first groove 21, and filling the first sub-groove 21a, the second sub-groove 21b and the first cavity Q1 with the first isolation material G1 is equivalent to filling the first groove 21 and the first cavity Q1 with the first isolation material G1.

[0242] Illustratively, the specific configuration of the first isolation material G1 refers to the introduction in the aforementioned part, which will not be described in detail here.

[0243] Exemplarily, the process of filling the first isolation material G1 may be chemical vapor deposition, atomic layer deposition, plasma deposition, etc. During the process of filling the first isolation material G1, the first isolation material G1 is also formed on the surface of the initial stacking structure to cover the first insulating layer 15.

[0244] S4-1, such as Fig.14 and Fig.15 As shown, the first isolation material G1 and the first insulation layer 15 located on the surface of the first insulation layer are removed to expose the second sacrificial material R2 in the second sub-channel hole K2.

[0245] Exemplarily, a grinding process is used to remove the first isolation material G1 and the first insulating layer 15 to expose the second sacrificial material R2 .

[0246] S4-2, such as Fig.16 As shown, the second sacrificial material R2 in the first sub-channel hole K1 and the second sub-channel hole K2 is removed.

[0247] Exemplarily, the process of removing the second sacrificial material R2 is a wet cleaning process.

[0248] S51. Reference Fig.17 , a channel material G2 is filled in the plurality of first sub-channel holes K1 and the plurality of second sub-channel holes K2 to form a plurality of channel structures 3 .

[0249] It should be noted that the plurality of first sub-channel holes K1 and the plurality of second sub-channel holes K2 constitute a plurality of channel holes K. Filling the plurality of first sub-channel holes K1 and the plurality of second sub-channel holes K2 with the channel material G2 is equivalent to filling the plurality of channel holes K with the channel material G2.

[0250] For example, the specific configuration of the channel material G2 is described in the foregoing sections and will not be described in detail here.

[0251] In the process of forming the first isolation structure 2 and the plurality of channel structures 3, an initial stacking structure is formed in sequence of first forming an initial first stacking structure 1a1 and then forming an initial second stacking structure 1a2. In the etching process of the first partition groove 21 and the channel hole K, a plurality of first sub-channel holes K1 and first sub-partition grooves 21a are first formed, and then a plurality of second sub-channel holes K2 and second sub-partition grooves 21b are formed. Compared with the prior art method of preparing partition grooves and channel holes by etching once, it is equivalent to reducing the etching depth to a certain extent, thereby reducing the etching difficulty, avoiding the phenomenon of the first partition groove being offset and bent during the etching process, causing the first partition groove 21 to contact the channel hole K, and affecting the reliability of the semiconductor structure 50.

[0252] S6. Reference Figure 18A to Figure 19 , forming a second partition groove 41, the second partition groove 41 extends along the second direction X and penetrates the initial stacking structure 1a; the second partition groove 41 extends along the second direction X.

[0253] For the introduction of S6, please refer to the previous description, which will not be repeated here.

[0254] S71, reference Fig.18B , at least the sacrificial layer 13 located in the storage area CN is removed through the second partition groove 41 to form a second cavity Q2.

[0255] S72, such as Fig.19 As shown, a dielectric material is filled in the second cavity Q2 to form a dielectric layer 14 attached to the cavity wall of the second cavity Q2 and the bottom and sidewall of the second partition groove 41 .

[0256] S73, such as Fig. 20 As shown, a conductive material G4 is filled in the second cavity Q2 to form a multi-layer gate layer 12 .

[0257] For the introduction of S71 to S73, please refer to the previous description and will not be repeated here.

[0258] S8. Reference Fig.21 , a second isolation material G3 is deposited in the second isolation groove 41 to form a second isolation structure 4.

[0259] For the introduction of S8, please refer to the previous description, which will not be repeated here.

[0260] Based on the specific steps of the method for preparing the semiconductor structure described above, the corresponding semiconductor structure is introduced below.

[0261] In some embodiments, reference Figure 4AAs shown, the stacking structure 1 includes a first stacking structure 10 and a second stacking structure 20, and the second stacking structure 20 is arranged on the first stacking structure 10; wherein the first isolation structure 2 includes a first sub-isolation structure 210 and a second sub-isolation structure 220; the first sub-isolation structure 210 passes through the first stacking structure 10, and the second sub-isolation structure 220 passes through the second stacking structure 20; the dimension d1' of one end of the first sub-isolation structure 210 close to the second sub-isolation structure 220 is greater than the dimension d2 of one end of the second sub-isolation structure 220 close to the first sub-isolation structure 210.

[0262] It should be noted that, referring to the above-mentioned preparation method, it can be known that the two-step method is used to respectively etch the first sub-groove 21a and the second sub-groove 21b in the first stacking structure 10 and the second stacking structure 20, which can reduce the etching difficulty in the process of preparing the first groove 21, thereby avoiding the first isolation structure 2 and the channel structure 3 from contacting each other and causing leakage, thereby improving the reliability of the semiconductor structure 50.

[0263] Since the above-mentioned first sub-isolation structure 210 and the second sub-isolation structure 220 are both prepared by the same etching process, and the positions of the two correspond, and during the formation process, the size of the end of the first sub-isolation groove 21a close to the substrate is smaller than the size of the end away from the substrate, and the size of the end of the second sub-isolation groove 21b close to the substrate is smaller than the size of the end away from the substrate, after the first sub-isolation groove 21a and the second sub-isolation groove 21b are filled to form the first sub-isolation structure 210 and the second sub-isolation structure 220, the size d1' of the end of the first sub-isolation structure 210 close to the second sub-isolation structure 220 is larger than the size d2 of the end of the second sub-isolation structure 220 close to the first sub-isolation structure 210.

[0264] In some embodiments, reference Figure 4A As shown, the dimension d1' of the end of the first sub-isolation structure 210 close to the second sub-isolation structure 220 in the second direction X is greater than the dimension d1 of the end of the first sub-isolation structure 210 away from the second sub-isolation structure 220 in the second direction X; the dimension d2' of the end of the second sub-isolation structure 220 away from the first sub-isolation structure 210 in the second direction X is greater than the dimension d2 of the end of the second sub-isolation structure 220 close to the first sub-isolation structure 210 in the second direction X.

[0265] For example, refer to Figure 4A As described in the above steps S22 and S24, during the process of etching to form the first sub-groove 21a and the second sub-groove 21b, both present an inverted trapezoidal structure, and therefore have the above-mentioned dimensional relationship.

[0266] In some embodiments, reference Figure 4A and Figure 4BThe first sub-isolation structure 210 includes a first main structure 210a and a plurality of first sub-structures 210b respectively located on both sides of the first main structure 210a along the second direction X, the first sub-structure 210b is connected to the side wall of the first main structure 210a, and each first sub-structure 210b is inserted between two adjacent insulating layers 11; the second sub-isolation structure 220 includes a second main structure 220a and a plurality of second sub-structures 220b respectively located on both sides of the second main structure 220a along the second direction X, the second sub-structure 220b is connected to the side wall of the second main structure 220a, and each second sub-structure 220b is inserted between two adjacent insulating layers 11.

[0267] Exemplarily, the first sub-isolation structure 210 including the first main structure 210a and the multiple first sub-structures 210b, and the second sub-isolation structure 220 including the second main structure 220a and the multiple second sub-structures 220b, can enhance the bonding force between the first isolation structure 2 and the stacking structure 1, thereby enhancing the supporting force and preventing the stacking structure 1 from collapsing in subsequent processes.

[0268] In some embodiments, continue to refer to Figure 4A , along the direction in which the first stacking structure 10 is away from the second stacking structure 20, the dimension d1' of one end of the first main structure 210a close to the second main structure 220a in the second direction X is greater than the dimension d1 of one end of the first main structure 210a away from the second main structure 220a in the second direction X; the dimension d2' of one end of the second main structure 220a away from the first main structure 210a in the second direction X is greater than the dimension d2 of one end of the second main structure 220a close to the first main structure 210a in the second direction X.

[0269] For example, refer to Figure 4A The dimensions of both ends of the first main structure 210a correspond to the dimensions of both ends of the first sub-isolation structure 210, and the dimensions of both ends of the second main structure 220a correspond to the dimensions of both ends of the second sub-isolation structure 220, therefore, they have the above-mentioned dimensional relationship.

[0270] In some embodiments, the size of the first main structure 210 a in the second direction X ranges from 150 nm to 200 nm; the size of the second main structure 220 a in the second direction X ranges from 150 nm to 200 nm.

[0271] It should be noted that, according to the introduction of the above preparation steps, the first main structure 210a and the second main structure 220a are prepared by the same process, but the preparation order is different, so they have the same shape and the formed sizes are consistent. The size range of the first main structure 210a and the second main structure 220a in the second direction X is 150nm to 200nm, for example, it can be 150nm, 180nm or 200nm.

[0272] It can be understood that the size range of the first main structure 210a and the second main structure 220a corresponds to the size range of the first sub-groove 21a and the second sub-groove 21b.

[0273] In some embodiments, reference Figure 4A The semiconductor structure 50 also includes a plurality of channel structures 3 located in the core area AA, and the plurality of channel structures 3 penetrate the stacking structure 1; the channel structure 3 includes a first sub-channel structure 31 and a second sub-channel structure 32, the first sub-channel structure 31 penetrates the first stacking structure 10, and the second sub-channel structure 32 penetrates the second stacking structure 20; a dimension d5 of the first sub-channel structure 31 at one end close to the second sub-channel structure 32 is greater than a dimension d6 of the second sub-channel structure 32 at one end close to the first sub-channel structure 31.

[0274] It should be noted that, as can be seen from the introduction of the aforementioned preparation steps, the two-step method of etching the first stacking structure 10 and the second stacking structure 20 to form the first channel hole K1 and the second channel hole K2 can reduce the difficulty of etching in the process of preparing the channel hole K, thereby avoiding contact between the first isolation structure 2 and the channel structure 3 to cause leakage, thereby improving the reliability of the semiconductor structure 50.

[0275] Since the first sub-channel structure 31 and the second sub-channel structure 32 are prepared by the same etching process and their positions correspond, during the formation process, the size of the end of the first sub-channel hole K1 close to the substrate is smaller than the size of the end away from the substrate, and the size of the end of the second sub-channel hole K2 close to the substrate is smaller than the size of the end away from the substrate. Therefore, after the first sub-channel hole K1 and the second sub-channel hole K2 are filled, the size d5 of the end of the first sub-channel structure 31 close to the second sub-channel structure 32 is larger than the size d6 of the end of the second sub-channel structure 32 close to the first sub-channel structure 31.

[0276] In some embodiments, reference Figure 2A to Figure 2C, a first spacing H1 is provided between the channel structure 3 closest to the first isolation structure 2 among the multiple channel structures 3 and the first isolation structure 2, and the first spacing H1 is 50nm~120nm; a first spacing H1 is provided between the virtual channel structure 6 closest to the first isolation structure 2 among the multiple virtual channel structures 6 and the first isolation structure 2, and the first spacing H1 is 50nm~120nm.

[0277] It should be noted that the range of the first spacing H1 is set, on the one hand, mainly to avoid the channel structure 3 or the virtual channel structure 6 and the first isolation structure 2 from bending and contacting each other on the side close to the substrate 101 due to the first spacing H1 being too small during the process of forming the channel structure 3 and the virtual channel structure 6 at the same time as the first isolation structure 2; on the other hand, if the first spacing H1 is too large, the first isolation structure 2 cannot play a good supporting role for the stacking structure 1, which may easily lead to collapse due to insufficient supporting force during the gate replacement process.

[0278] Exemplarily, the first interval H1 is, for example, 50 nm, 80 nm, 100 nm or 120 nm.

[0279] In some embodiments, reference Figure 2A to Figure 2C A second spacing H2 is provided between the plurality of dummy channel structures 6 and the plurality of channel structures 3 along the second direction X, and a size range of the second spacing H2 is 600 nm to 650 nm.

[0280] It should be noted that the range of the second spacing H2 is set, on the one hand, mainly to avoid the channel structure 3 and the first isolation structure 2 from bending and contacting on the side close to the substrate 101 due to the second spacing H2 being too small during the process of forming the channel structure 3 and the virtual channel structure 6 while forming the first isolation structure 2; on the other hand, if the second spacing H2 is too large, the first isolation structure 2 cannot play a good supporting role for the stacking structure 1, which may easily lead to collapse due to insufficient supporting force during the gate replacement process.

[0281] Exemplarily, the second interval H2 is, for example, 600 nm, 630 nm or 650 nm.

[0282] In some embodiments, the semiconductor structure 50 provided in the above embodiments of the present disclosure is a memory, or a part of a memory (see the three-dimensional memory described below for details).

[0283] Some embodiments of the present disclosure also provide a three-dimensional memory 100. Fig. 22 As shown, the three-dimensional memory 100 includes: a semiconductor structure 50 and a peripheral device 30. The peripheral device 30 is electrically connected to the semiconductor structure 50.

[0284] In some embodiments, the peripheral device includes a substrate and a peripheral circuit. The substrate includes a substrate and a peripheral circuit disposed on the substrate, and the peripheral circuit is electrically coupled to the semiconductor structure. The coupling method may be, for example, binding or bonding.

[0285] The material of the substrate may be, for example, single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0286] The above-mentioned peripheral circuits may include transistors. The above-mentioned peripheral circuits are configured to control and sense the above-mentioned semiconductor structure. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the semiconductor structure, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., Programmable Logic Device, referred to as PLD, processors and programmable logic devices), or storage circuits (e.g., Static random-Access Mmemory, referred to as SRAM, static random access memory).

[0287] Some embodiments of the present disclosure also provide a storage system 1000. Fig.23A , Fig. 23B As shown, the storage system 1000 includes: a controller 200 and a three-dimensional memory 100 provided by any of the above embodiments. The controller 200 is coupled to the three-dimensional memory 100 to control the three-dimensional memory 100 to store data.

[0288] In some embodiments, Fig.23A As shown, the storage system 1000 includes: a three-dimensional memory 100, and the storage system 1000 can be integrated into a memory card.

[0289] Memory cards include, for example, PC cards (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) cards, Smart Media (SM) cards, memory sticks, Multimedia Cards (MMC), Secure Digital (SD) cards, and UFS.

[0290] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0291] In other embodiments, Fig. 23B As shown, the storage system 1000 includes: a controller 200 and a plurality of three-dimensional memories 100, and the storage system 1000 is integrated into a solid state drive (SSD).

[0292] In the storage system 1000, in some embodiments, the controller 200 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0293] In other embodiments, the controller 200 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0294] In some embodiments, the controller 200 may be configured to manage data stored in the three-dimensional memory 100 and communicate with an external device (eg, a host).

[0295] In some embodiments, the controller 200 may also be configured to control operations of the three-dimensional memory 100 , such as read, erase, and program operations.

[0296] In some embodiments, the controller 200 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 100 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0297] In some embodiments, the controller 200 is further configured to process an error correction code regarding data read from or written to the three-dimensional memory 100 .

[0298] Of course, the controller 200 may also perform any other suitable functions, such as formatting the three-dimensional memory 100; for example, the controller 200 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0299] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0300] The embodiment of the present disclosure also provides an electronic device 10000, such as Fig.24 As shown, the electronic device 10000 includes a storage system 1000.

[0301] The electronic device 10000 includes but is not limited to any one of a mobile phone, a tablet computer, a laptop computer, a television, a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a netbook, a wearable device (such as a smart watch, a smart bracelet, smart glasses), etc. The embodiments of the present application do not limit the type of electronic device.

[0302] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0303] In some embodiments, Fig.24 As shown, the electronic device 10000 further includes a printed circuit board 2000 , and the printed circuit board 2000 is coupled to the storage system 1000 .

[0304] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A stacked structure, the stacked structure comprising a plurality of insulating layers and a plurality of gate layers, the plurality of insulating layers and the plurality of gate layers being alternately stacked; A first isolation structure, wherein the first isolation structure penetrates the stacked structure and extends along a first direction; the first isolation structure comprises a main structure and a plurality of sub-structures respectively located on both sides of the main structure along a second direction, the sub-structures are connected to the side walls of the main structure, and each of the sub-structures is inserted between two adjacent insulating layers; the second direction intersects with the first direction.

2. The semiconductor structure according to claim 1, characterized in that: The main structure and the plurality of substructures of the first isolation structure both include a first isolation material.

3. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure further includes a dielectric layer, wherein the dielectric layer is at least located between the adjacent insulating layer and the gate layer; The dielectric layer is also arranged between the substructure and the gate layer in the same layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a second isolation structure extending along a second direction; the second isolation structure penetrates the stacked structure, the stacked structure includes a core region and a peripheral region located outside the core region, the first isolation structure separates the core region and the peripheral region; the core region includes a connection region and a storage region, the second isolation structure penetrates the connection region and the storage region; The orthographic projection of the second isolation structure on the first plane at least partially overlaps with the orthographic projection of the first isolation structure on the first plane; The first plane is parallel to a surface of the stacked structure.

5. The semiconductor structure according to claim 4, characterized in that: The second isolation structure passes through the first isolation structure and enters the peripheral area; The semiconductor structure further includes a plurality of virtual channel structures located in the peripheral region, wherein the plurality of virtual channel structures include a first partial virtual channel structure and a second partial virtual channel structure, and the first partial virtual channel structure and the second partial virtual channel structure are respectively located on both sides of the second isolation structure.

6. The semiconductor structure according to claim 5, characterized in that: The semiconductor structure further includes a support column located in the peripheral region, wherein the support column penetrates the stacked structure; and the support column is located between the first partial virtual channel structure and the second partial virtual channel structure.

7. The semiconductor structure according to claim 4, characterized in that: The semiconductor structure further includes a third isolation structure extending along the second direction, wherein the third isolation structure penetrates the stack structure; the third isolation structure is located between two adjacent second isolation structures; The core area includes a storage area and a connection area, and the third isolation structure is at least located in the storage area; The orthographic projection of the third isolation structure on the first plane at least partially overlaps with the orthographic projection of the first isolation structure on the first plane.

8. The semiconductor structure according to claim 4, characterized in that: The second isolation structure includes a dielectric structure and a filling structure; The dielectric structure is located at the bottom of the filling structure and between the filling structure and the plurality of insulating layers.

9. The semiconductor structure according to claim 4, characterized in that: A size of the first isolation structure in the second direction is greater than a size of the second isolation structure in the first direction.

10. The semiconductor structure according to claim 1, characterized in that The stacking structure includes a first stacking structure and a second stacking structure, wherein the second stacking structure is arranged on the first stacking structure; Among them, the first isolation structure includes a first sub-isolation structure and a second sub-isolation structure; the first sub-isolation structure runs through the first stacking structure, and the second sub-isolation structure runs through the second stacking structure; the size of one end of the first sub-isolation structure close to the second sub-isolation structure is larger than the size of one end of the second sub-isolation structure close to the first sub-isolation structure.

11. The semiconductor structure according to claim 10, characterized in that: The dimension of one end of the first sub-isolation structure close to the second sub-isolation structure in the second direction is greater than the dimension of one end of the first sub-isolation structure away from the second sub-isolation structure in the second direction; the dimension of one end of the second sub-isolation structure away from the first sub-isolation structure in the second direction is greater than the dimension of one end of the second sub-isolation structure close to the first sub-isolation structure in the second direction.

12. The semiconductor structure according to claim 10, characterized in that The first sub-isolation structure includes a first main structure and a plurality of first sub-structures respectively located on both sides of the first main structure along the second direction, the first sub-structures are connected to the sidewalls of the first main structure, and each of the first sub-structures is inserted between two adjacent insulating layers; The second sub-isolation structure includes a second main structure and a plurality of second sub-structures respectively located on both sides of the second main structure along the second direction, the second sub-structures are connected to the side walls of the second main structure, and each second sub-structure is inserted between two adjacent insulating layers.

13. The semiconductor structure according to claim 12, characterized in that: Along the direction in which the first stacking structure is away from the second stacking structure, the dimension of one end of the first main structure close to the second main structure in the second direction is greater than the dimension of one end of the first main structure away from the second main structure in the second direction; A dimension of an end of the second main structure away from the first main structure in the second direction is greater than a dimension of an end of the second main structure close to the first main structure in the second direction.

14. The semiconductor structure according to claim 10, characterized in that The semiconductor structure further includes a plurality of channel structures located in the core region, wherein the plurality of channel structures penetrate the stack structure; The channel structure includes a first sub-channel structure and a second sub-channel structure, the first sub-channel structure runs through the first stacked structure, and the second sub-channel structure runs through the second stacked structure; A size of an end of the first sub-channel structure close to the second sub-channel structure is larger than a size of an end of the second sub-channel structure close to the first sub-channel structure.

15. A storage system, characterized in that: include: A three-dimensional memory, wherein the three-dimensional memory comprises a semiconductor structure as claimed in any one of claims 1 to 14; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

16. A method for preparing a semiconductor structure, characterized in that: include: forming an initial stacking structure, wherein the initial stacking structure comprises a plurality of insulating layers and a plurality of sacrificial layers, wherein the plurality of insulating layers and the plurality of sacrificial layers are alternately stacked; forming a first partition groove and a plurality of channel holes; the first partition groove penetrates the initial stacking structure, and the plurality of channel holes penetrates the initial stacking structure; Removing a portion of the sacrificial layer around the first partition groove to form a first cavity between two adjacent insulating layers; A first isolation material is filled in the first isolation groove and the first cavity to form a first isolation structure; the first isolation structure extends along a first direction, and includes a main structure and a plurality of sub-structures respectively located on both sides of the main structure along a second direction, the sub-structures are connected to the side walls of the main structure, each of the sub-structures is inserted between two adjacent insulating layers, and the second direction intersects with the first direction; A channel material is filled in the plurality of channel holes to form a plurality of channel structures.

17. The preparation method according to claim 16, characterized in that: After forming a plurality of channel structures, the method further includes: forming a second partition groove, wherein the second partition groove extends along a second direction and penetrates the initial stacking structure; the second partition groove extends along the second direction; Replacing at least part of the sacrificial layer with a gate layer via the second partition groove to form a stacked structure; A second isolation material is deposited in the second isolation trench to form a second isolation structure.

18. The preparation method according to claim 16, characterized in that: The forming of the initial stacking structure, and the forming of the first partition groove and the plurality of channel holes, comprises: forming an initial first stacking structure; forming a plurality of first sub-channel holes and first sub-grooves, wherein the plurality of first sub-channel holes penetrate the initial first stacking structure, and the first sub-grooves penetrate the initial first stacking structure; and the first sub-grooves extend along a first direction; forming an initial second stacking structure on the initial first stacking structure; the initial second stacking structure and the initial first stacking structure constitute the initial stacking structure; forming a plurality of second sub-channel holes and second sub-grooves, wherein the plurality of second sub-channel holes penetrate the initial second stacking structure, and the second sub-grooves penetrate the initial second stacking structure; and the second sub-grooves extend along the first direction; The first isolation groove and the first cavity are filled with a first isolation material to form a first isolation structure, including: Filling the first sub-grooves, the second sub-grooves and the first cavity with a first isolation material to form a first isolation structure; The step of filling the plurality of channel holes with channel materials to form a plurality of channel structures comprises: A channel material is filled in the plurality of first sub-channel holes and the plurality of second sub-channel holes to form a plurality of channel structures.

19. The preparation method according to claim 18, characterized in that: The preparation method further comprises: After forming the plurality of first sub-channel holes and the first sub-grooves and before forming the initial second stacking structure on the first stacking structure, the method further includes: depositing a first sacrificial material in the plurality of first sub-channel holes and the first sub-trench; After forming a plurality of second sub-channel holes and second sub-grooves and before filling the first sub-grooves and the second sub-grooves with a first isolation material, the method further includes: removing the first sacrificial material in the plurality of first sub-channel holes and the first sub-grooves; Depositing a second sacrificial material in the plurality of first sub-channel holes, the first sub-grooves and the plurality of second sub-channel holes and the second sub-grooves; The second sacrificial material in the second sub-grooves and the first sub-grooves is removed.

20. The preparation method according to claim 17, characterized in that: The step of replacing at least a portion of the sacrificial layer with a gate layer via the second partition groove to form a stacked structure includes: At least removing the sacrificial layer located in the storage area via the second partition groove to form a second cavity; forming a dielectric material in the second cavity to form a dielectric layer attached to the cavity wall of the second cavity and the bottom and sidewall of the second partition groove; The second cavity is filled with a conductive material to form a multi-layer gate layer.

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