Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method of manufacturing the same are provided. The semiconductor memory device includes a pass gate disposed over the gate stack in a first direction, a plurality of active pillars respectively disposed in a plurality of active holes included in the pass gate, and a gate stack.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device and a method for manufacturing the same. Background Art

[0002] Semiconductor memory devices are used in electronic devices in various fields such as automobiles, medical treatments, and data centers, as well as small electronic devices. Therefore, the demand for semiconductor memory devices is increasing.

[0003] A semiconductor memory device may include memory cells for data storage. In order to increase the capacity of a semiconductor memory device, technology development for a three-dimensional semiconductor memory device including memory cells arranged three-dimensionally is being actively conducted. Summary of the invention

[0004] According to an embodiment of the present disclosure, a semiconductor memory device may include a through gate, a plurality of active pillars respectively arranged in a plurality of active holes included in the through gate, and a gate stack, the through gate being arranged above the gate stack in a first direction, and the gate stack may include a plurality of conductive patterns spaced apart from each other in the first direction and stacked in the first direction.

[0005] According to an embodiment of the present disclosure, a semiconductor memory device may include: a peripheral circuit structure including a first region and a second region; a through gate, which is spaced apart from the peripheral circuit structure in a first direction and overlaps with the first region of the peripheral circuit structure; an active pillar, which is arranged in an active hole through the gate; a doped semiconductor layer, which is spaced apart from the peripheral circuit structure in the first direction and overlaps with the second region of the peripheral circuit structure; a gate stack, which includes a contact region between the first region of the peripheral circuit structure and the through gate and a cell array region extending from the contact region to overlap with the second region of the peripheral circuit structure; a channel pillar, which is connected to the doped semiconductor layer and passes through the cell array region of the gate stack; a memory layer, which is between the channel pillar and the gate stack; and a gate contact plug, which is connected to the active pillar and passes through the contact region of the gate stack.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device may include: forming a plurality of active pillars by etching a first region in a semiconductor substrate including a first region and a second region; forming an insulating layer surrounding a side of each of the plurality of active pillars; forming a through gate surrounding the plurality of active pillars and the insulating layer interposed between the plurality of active pillars and the through gate; forming a memory cell array including a gate stack overlapping the plurality of active pillars and the second region of the semiconductor substrate, a channel hole extending into the second region of the semiconductor substrate by passing through the gate stack, and a memory layer and a channel pillar disposed within the channel hole; forming a first conductive bonding pattern above the memory cell array; forming a structure including a peripheral circuit structure and a second conductive bonding pattern; performing a bonding process to connect the first conductive bonding pattern and the second conductive bonding pattern; and separating the plurality of active pillars from each other by removing a portion of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 is a circuit diagram showing a memory cell array and a pass circuit according to an embodiment of the present disclosure.

[0009] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A and Figure 7B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Fig. 8A , Figure 8B , Figure 8C , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig. 13C , Fig.13D , Fig.13E , Fig.13F , Figure 13G , Fig.13H , Fig.13I and Fig.13J is a diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Fig.14 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The specific structure and function description disclosed herein are only illustrative, and are for describing the implementation of the concept according to the present disclosure. The implementation of the concept according to the present disclosure can be modified in various forms and replaced by other equivalent implementations. Therefore, the present disclosure should not be interpreted as being limited to the implementations set forth herein.

[0013] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, and the order or number of components is not limited by these terms. In addition, unless there is a special limitation on the components expressed in the singular or plural, it should not be interpreted as limiting the number of components.

[0014] Embodiments of the present disclosure may provide a semiconductor memory device capable of improving integration and a method of manufacturing the same.

[0015] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Reference Figure 1 , the semiconductor memory device 50 may include a memory cell array 10, a pass circuit 40, and a peripheral circuit structure PS.

[0017] The memory cell array 10 may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory cell may be a nonvolatile memory cell. As an embodiment, each memory cell may be a NAND flash memory cell. Hereinafter, an embodiment of the present disclosure is described based on a semiconductor memory device 50 including a NAND flash memory cell, but the present disclosure is not limited thereto. As another embodiment, each memory cell may be configured by a ferroelectric memory cell, a variable resistance memory cell, etc.

[0018] The pass circuit 40 may be connected to the memory cell array 10 through a plurality of local lines. As an embodiment, the plurality of local lines may include a plurality of word lines WL, at least one source select line SSL, and at least one drain select line DSL.

[0019] The peripheral circuit structure PS may be configured to perform a program operation for storing data in the memory cell array 10, a read operation for outputting data stored in the memory cell array 10, and an erase operation for erasing data stored in the memory cell array 10. As an embodiment, the peripheral circuit structure PS may include an input / output circuit 21, a control circuit 23, a voltage generating circuit 31, a block decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0020] The input / output circuit 21 may transfer a command CMD and an address ADD received from an external device (eg, a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 may exchange data DATA with the external device and the column decoder 35.

[0021] The control circuit 23 may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to a command CMD and an address ADD.

[0022] The voltage generating circuit 31 may generate and output various operating voltages for program operation, read operation, and erase operation in response to the operating signal OP_S. The operating voltages output from the voltage generating circuit 31 may be transmitted to the pass circuit 40 through the plurality of global lines GLL.

[0023] The block decoder 33 may output a block selection signal in response to the row address RADD. The block selection signal output from the block decoder 33 may be transmitted to the pass circuit 40 through the block selection line BSEL.

[0024] The pass circuit 40 may transfer the operating voltage transmitted to the plurality of global lines GLL to the drain select line DSL, the word line WL, and the source select line SSL in response to the block select signal transmitted to the block select line BSEL.

[0025] In response to the column address CADD, the column decoder 35 may transmit the data DATA input from the input / output circuit 21 to the page buffer 37 or transmit the data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 may exchange the data DATA with the input / output circuit 21 through the column line CL. The column decoder 35 may exchange the data DATA with the page buffer 37 through the data line DL.

[0026] The page buffer 37 may store read data received through the bit line BL in response to the page buffer control signal PB_S. The page buffer 37 may sense a voltage or current of the bit line BL during a read operation. The page buffer 37 may be connected to the memory cell array 10 through the bit line BL.

[0027] The source line driver 39 may control a voltage applied to the common source line CSL in response to a source line control signal SL_S. The source line driver 39 may be connected to the memory cell array 10 through the common source line CSL.

[0028] Figure 2 is a circuit diagram showing a memory cell array and a pass circuit according to an embodiment of the present disclosure.

[0029] Reference Figure 2 , the memory cell array 10 may include a plurality of memory cell strings CS. The plurality of memory cell strings CS may be connected to a plurality of bit lines BL and a common source line CSL.

[0030] Each memory cell string CS may include at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST.

[0031] The source select transistor SST may control electrical connection between the plurality of memory cells MC and the common source line CSL. The drain select transistor DST may control electrical connection between the plurality of memory cells MC and the bit line BL.

[0032] One source selection transistor SST may be provided, or two or more source selection transistors connected in series may be provided between a common source line CSL and a plurality of memory cells MC. One drain selection transistor DST may be provided, or two or more drain selection transistors connected in series may be provided between each bit line BL and a plurality of memory cells MC of a memory cell string CS corresponding thereto.

[0033] A plurality of gates of a plurality of memory cells MC may be respectively connected to a plurality of word lines WL. A gate of a source selection transistor SST may be connected to a source selection line SSL. A gate of a drain selection transistor DST may be connected to a drain selection line DSL.

[0034] The source selection line SSL, the drain selection line DSL, and the plurality of word lines WL may be connected to the pass circuit 40. The pass circuit 40 may include a plurality of pass transistors PT. The plurality of pass transistors PT may be respectively connected to the plurality of gate contact plugs GCT. The plurality of gate contact plugs GCT may be respectively connected to the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL. Each pass transistor PT may be connected to a corresponding gate line among the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL via the gate contact plug GCT corresponding thereto.

[0035] The plurality of pass transistors PT may transmit a voltage applied to the plurality of global lines GLL to the source select line SSL, the drain select line DSL, and the plurality of word lines WL in response to a block select signal applied to the block select line BSEL. The plurality of global lines GLL may include a global source select line GSSL, a global drain select line GDSL, and a plurality of global word lines GWL corresponding to the source select line SSL, the drain select line DSL, and the plurality of word lines WL, respectively.

[0036] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A and Figure 7B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0037] Figure 3 is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure. Figure 4 It is shown Figure 3 A perspective view of a memory cell array, doped semiconductor layer, gate contact plugs, and via circuitry is shown. Figure 5 It is shown Figure 3 A plan view of a memory cell array, doped semiconductor layer, gate contact plugs, and via circuits is shown. Figure 6 It is shown Figure 3 An exploded perspective view of a gate and multiple active pillars is shown.

[0038] Reference Figure 3 , the semiconductor memory device may include a first structure ST1, a second structure ST2, a doped semiconductor layer DPS, a plurality of contacts CT1 to CT3, and a plurality of upper lines UL1 to UL3. The first structure ST1 may include a through circuit 40, a plurality of gate contact plugs GCT connected to the through circuit 40, a memory cell array 10 connected to the plurality of gate contact plugs GCT, a bit line BL connected to the memory cell array 10, and a plurality of first conductive bonding patterns 77. The second structure ST2 may include a peripheral circuit structure PS, a plurality of interconnections 93 connected to the peripheral circuit structure PS, and a plurality of second conductive bonding patterns 97 connected to the plurality of interconnections 93. The peripheral circuit structure PS may include a first region AR1 and a second region AR2.

[0039] The pass circuit 40 may include Figure 2 The plurality of pass transistors PT shown include a pass gate 67 , a plurality of active pillars 61P, and a plurality of first pass gate insulating layers 65A.

[0040] The pass gate 67 may be spaced apart from the second structure ST2 including the peripheral circuit structure PS in the first direction DR1. The pass gate 67 may overlap the first region AR1 of the peripheral circuit structure PS. The pass gate 67 may be used as Figure 2 The gate of each of the plurality of pass transistors PT is shown.

[0041] Reference Figures 3 to 6 , the gate 67 may include a plurality of active holes 67H corresponding to the plurality of active pillars 61P, respectively. The gate 67 may include at least one of a doped semiconductor layer and a metal layer. As an embodiment, the doped semiconductor layer of the gate 67 may include a doped silicon layer. As an embodiment, the metal layer of the gate 67 may include tungsten, copper, molybdenum, etc. The gate 67 may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The metal nitride layer may be formed along the surface of the metal layer.

[0042] A plurality of active pillars 61P may be respectively disposed in a plurality of active holes 67H of the through gate 67. The plurality of active pillars 61P may include a semiconductor material such as silicon or germanium. Each of the plurality of first through gate insulating layers 65A may surround the side of the active pillar 61P corresponding thereto. Therefore, each first through gate insulating layer 65A may be interposed between the through gate 67 and the active pillar 61P corresponding thereto.

[0043] Reference Figure 3 , each active pillar 61P may include a channel region 61C, a first junction 61J1, and a second junction 61J2. The channel region 61C of the active pillar 61P may be used as a channel of a corresponding pass transistor, and each of the first junction 61J1 and the second junction 61J2 of the active pillar 61P may be used as a source or a drain of a corresponding pass transistor. Each of the channel region 61C, the first junction 61J1, and the second junction 61J2 may include at least one of an n-type impurity and a p-type impurity. As an embodiment, the channel region 61C may include a p-type impurity as a majority carrier, and the first junction 61J1 and the second junction 61J2 may include an n-type impurity as a majority carrier. The first junction 61J1 may face the gate stack GST of the memory cell array 10, and the second junction 61J2 may face a direction opposite to the direction of the first junction 61J1. The channel region 61C may be disposed between the first junction 61J1 and the second junction 61J2.

[0044] Reference Figures 3 to 5 , the memory cell array 10 of the first structure ST1 may include a channel pillar CHP extending in the first direction DR1, a memory layer ML surrounding a side of the channel pillar CHP, and the above-mentioned gate stack GST.

[0045] The gate stack GST may be disposed between the gate 67 and the peripheral circuit structure PS. The gate stack GST may include a plurality of conductive patterns CP spaced apart from each other and stacked in the first direction DR1. The gate stack GST may also include a plurality of interlayer insulating layers ILD alternately stacked with the plurality of conductive patterns CP in the first direction DR1. Each conductive pattern CP and each interlayer insulating layer ILD may be formed in a plate shape. As an embodiment, each conductive pattern CP and each interlayer insulating layer ILD may include a surface extending in the second direction DR2 and the third direction DR3. The second direction DR2 and the third direction DR3 may be defined as directions facing axes intersecting each other. In addition, each of the second direction DR2 and the third direction DR3 may be defined as a direction facing the side of each active pillar 61P.

[0046] The gate stack GST may include a contact region CTR overlapping the through gate 67 and a cell array region CAR extending from the contact region CTR in the second direction DR2. The cell array region CAR of the gate stack GST may overlap the second region AR2 of the peripheral circuit structure PS.

[0047] The plurality of conductive patterns CP and the plurality of interlayer insulating layers ILD of the gate stack GST may be formed into a staircase structure in the contact region CTR. The plurality of ends of the plurality of conductive patterns CP may be configured with a plurality of pad portions PAD1 to PAD9. The plurality of pad portions PAD1 to PAD9 may correspond to the plurality of steps forming the staircase structure of the gate stack GST. The plurality of pad portions PAD1 to PAD9 may overlap with the plurality of active pillars 61P, respectively.

[0048] The plurality of conductive patterns CP and the plurality of interlayer insulating layers ILD of the gate stack GST may extend from the contact region CTR to the cell array region CAR to overlap with the second region AR2 of the peripheral circuit structure PS. The plurality of conductive patterns CP may be used as Figure 2 The drain selection line DSL, the plurality of word lines WL, and the source selection line SSL are shown. Among the plurality of conductive patterns CP, at least one of the conductive pattern adjacent to the peripheral circuit structure PS and the conductive pattern adjacent to the through gate 67 may be penetrated by the selection line separation structure 70 to be separated into the selection line, and the remaining conductive pattern may overlap with the selection line separation structure 70 to extend continuously without being separated by the selection line separation structure 70. For example, among the plurality of conductive patterns CP, the conductive pattern adjacent to the peripheral circuit structure PS may be separated by the selection line separation structure 70 into the first drain selection line and the second drain selection line, and the remaining conductive pattern may extend continuously to overlap with the first drain selection line and the second drain selection line.

[0049] The plurality of conductive patterns CP may include at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer of each conductive pattern CP may include a doped silicon layer. The metal layer of each conductive pattern CP may include tungsten, copper, molybdenum, etc. The plurality of conductive patterns CP may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The plurality of interlayer insulating layers ILD may include a silicon oxide layer, etc.

[0050] A plurality of conductive patterns CP and a plurality of interlayer insulating layers ILD of the gate stack GST may be penetrated by a plurality of channel holes CHH in the cell array region CAR. A channel column CHP may be disposed in each channel hole CHH. The channel column CHP may be formed of a semiconductor material. As an embodiment, the channel column CHP may include silicon, germanium, or a mixture thereof. A core insulating layer CO may be disposed in the channel column CHP. The core insulating layer CO may include an insulating material such as silicon oxide. The channel column CHP may include a channel layer CHL and a capping pattern CAP. The channel layer CHL may be used as a channel region of a memory cell string corresponding thereto, and may surround the side of the core insulating layer CO. The channel layer CHL may extend to cover a first surface of the core insulating layer CO facing the first direction DR1. The capping pattern CAP may cover a second surface of the core insulating layer CO facing the fourth direction DR4 opposite to the first direction DR1. The capping pattern CAP may be used as a drain junction of the memory cell string. The capping pattern CAP may include at least one of an n-type impurity and a p-type impurity. As an embodiment, the capping pattern CAP may include n-type impurities as majority carriers.

[0051] The memory layer ML may be disposed between the channel pillar CHP and the gate stack GST. The memory layer ML may include a blocking insulating layer between the channel pillar CHP and the gate stack GST, a data storage layer between the blocking insulating layer and the channel pillar CHP, and a tunnel insulating layer between the data storage layer and the channel pillar CHP. The blocking insulating layer may include an insulating material capable of blocking charges. The tunnel insulating layer may include an insulating material capable of charge tunneling. The blocking insulating layer may include an insulating layer having a dielectric constant higher than that of the tunnel insulating layer. The data storage layer may be formed of a material layer capable of storing changed data using Fowler-Nordheim tunneling. As an embodiment, the data storage layer may be formed of a charge trapping insulating layer or an insulating layer including conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. The present disclosure is not limited thereto, and the data storage layer may be formed of a material layer capable of storing information based on an operating principle other than Fowler-Nordheim tunneling. As an embodiment, the data storage layer may include a phase change material layer, a ferroelectric layer, etc. In this case, the channel pillar CHP may be replaced with a columnar electrode structure.

[0052] A plurality of gate contact plugs GCT may be connected to a plurality of active pillars 61P, respectively. As an embodiment, each gate contact plug GCT may contact the first junction 61J1 of the active pillar 61P corresponding thereto and extend in the fourth direction DR4. A plurality of gate contact plugs GCT may pass through the gate stack GST in the contact region CTR of the gate stack GST. Each gate contact plug GCT may include at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer of the gate contact plug GCT may include a doped silicon layer. The metal layer of the gate contact plug GCT may include tungsten, copper, molybdenum, etc. Each gate contact plug GCT may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The metal nitride layer may be formed along the surface of the metal layer.

[0053] Fig. 7A and Figure 7B It is shown Figure 3 A perspective view of a portion of a gate stack and a portion of a gate contact plug is shown. Fig. 7A A part of the configuration of the semiconductor memory device is shown by perspective to facilitate recognition.

[0054] Reference Figure 3 , Fig. 7A and Figure 7B , the plurality of gate contact plugs GCT may respectively pass through the plurality of pad portions PAD1 to PAD9. Each gate contact plug GCT may form a contact surface CTS with a pad portion of a corresponding conductive pattern among the plurality of pad portions PAD1 to PAD9 of the plurality of conductive patterns CP. For example, the plurality of gate contact plugs GCT may include a first gate contact plug GCT1. The plurality of conductive patterns CP may include a first conductive pattern CP1 and a second conductive pattern CP2 adjacent to each other in the first direction DR1. The first conductive pattern CP1 may form a contact surface CTS with the first gate contact plug GCT1, and the second conductive pattern CP2 may be insulated from the first gate contact plug GCT1.

[0055] A first insulating spacer SP1 and at least one second insulating spacer SP2 may be buried in each of the plurality of conductive patterns CP. The first insulating spacer SP1 may be adjacent to a contact surface CTS between each conductive pattern CP and a gate contact plug GCT corresponding thereto, and may surround a portion of a side surface of the gate contact plug GCT. The second insulating spacer SP2 may be interposed between the conductive pattern CP and the gate contact plug GCT that need to be insulated from each other, and may be formed in a ring shape to surround the side surface of the gate contact plug GCT. For example, the first insulating spacer SP1 may be adjacent to a contact surface CTS between the first gate contact plug GCT1 and the first conductive pattern CP1, and may surround a portion of a side surface of the first gate contact plug GCT1. The second insulating spacer SP2 may be interposed between the first gate contact plug GCT1 and the second conductive pattern CP2, and may surround the side surface of the first gate contact plug GCT1 in a ring shape.

[0056] Each conductive pattern (e.g., CP1) may include a first inner sidewall IW1 and a second inner sidewall IW2. The first inner sidewall IW1 of each conductive pattern (e.g., CP1) may form a contact surface CTS with its corresponding gate contact plug (e.g., GCT1). The second inner sidewall IW2 may extend from the first inner sidewall IW1 along a side of the first insulating spacer SP1.

[0057] Each of the first insulating spacer SP1 and the second insulating spacer SP2 may be interposed between the interlayer insulating layers ILD adjacent to each other in the first direction DR1. For example, the plurality of interlayer insulating layers ILD may include the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 adjacent to each other in the first direction DR1 and the first conductive pattern CP1 is interposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and the first insulating spacer SP1 may be interposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0058] Each of the plurality of conductive patterns CP may include a metal nitride layer L1 and a metal layer L2, and each of the plurality of gate contact plugs GCT may include a metal nitride layer L1' and a metal layer L2'. In this case, a contact surface CTS may be defined by contact between the metal nitride layer L1 of the conductive pattern CP and the metal nitride layer L1' of the gate contact plug GCT.

[0059] Reference Figures 3 to 5, the first structure ST1 may further include a semiconductor pattern 61S and a second through gate insulating layer 65B. The semiconductor pattern 61S may be disposed at a height at which the plurality of active pillars 61P are disposed. The semiconductor pattern 61S may include the same semiconductor material as the plurality of active pillars 61P. The semiconductor pattern 61S may include impurities of the same conductivity as the channel region 61C of each active pillar 61P. The semiconductor pattern 61S may be spaced apart from the through gate 67 and may surround the sidewall of the through gate 67. The second through gate insulating layer 65B may be interposed between the semiconductor pattern 61S and the through gate 67.

[0060] The first structure ST1 may also include an intercalation insulating layer 63 intercalated between each of the plurality of active pillars 61P and the semiconductor pattern 61S and the gate stack GST. The intercalation insulating layer 63 may include a plurality of first intercalation portions 63A and a second intercalation portion 63B. A plurality of first intercalation portions 63A may be disposed between the gate stack GST and the plurality of active pillars 61P. A second intercalation portion 63B may be disposed between the gate stack GST and the semiconductor pattern 61S. The second intercalation portion 63B of the intercalation insulating layer 63 may extend to overlap with the cell array region CAR of the gate stack GST and the second region AR2 of the peripheral circuit structure PS. A gate 67 may extend between the plurality of first intercalation portions 63A and the second intercalation portion 63B to separate the plurality of first intercalation portions 63A and the second intercalation portion 63B from each other.

[0061] The plurality of gate contact plugs GCT may respectively pass through the plurality of first insertion portions 63A of the insertion insulating layer 63 and contact the plurality of active pillars 61P. The plurality of conductive patterns CP may be electrically connected to the plurality of active pillars 61P of the via circuit 40 through the plurality of gate contact plugs GCT.

[0062] The channel pillar CHP and the memory layer ML may extend to pass through the second insertion portion 63B of the insertion insulating layer 63. The channel pillar CHP may protrude in the first direction DR1 compared to the second insertion portion 63B of the insertion insulating layer 63 and the memory layer ML. The protrusion of the channel pillar CHP may contact the doped semiconductor layer DPS.

[0063] The doped semiconductor layer DPS may be spaced apart from the peripheral circuit structure PS in the first direction DR1 and may overlap with the second region AR2 of the peripheral circuit structure PS. The doped semiconductor layer DPS may overlap with the plurality of conductive patterns CP and the plurality of interlayer insulating layers ILD of the gate stack GST and have the second intercalation portion 63B of the intercalation insulating layer 63 interposed therebetween. The doped semiconductor layer DPS may be spaced apart from the plurality of active pillars 61P and the through gate 67 in the second direction DR2. The doped semiconductor layer DPS may surround the protrusion of the channel pillar CHP protruding in the first direction DR1 compared to the memory layer ML. The doped semiconductor layer DPS may extend in the second direction DR2 and the third direction DR3 to overlap with the cell array region CAR of the gate stack GST. A plurality of channel pillars CHP may be disposed between the doped semiconductor layer DPS and the peripheral circuit structure PS, and the plurality of channel pillars CHP may be connected in parallel to the doped semiconductor layer DPS.

[0064] The doped semiconductor layer DPS may include at least one of an n-type impurity and a p-type impurity. The doped semiconductor layer DPS may be used as at least one of a source region and a well region. As an embodiment, the doped semiconductor layer DPS may be provided as a source region including n-type impurities as majority carriers. The embodiments of the present disclosure are not limited thereto. As another embodiment, the doped semiconductor layer DPS may include at least one of a first conductive type doped region including n-type impurities as majority carriers and a second conductive type doped region including p-type impurities as majority carriers. The first conductive type doped region may be used as a source region, and the second conductive type doped region may be used as a well region.

[0065] Reference Figure 3 The gate electrode 67 and the doped semiconductor layer DPS may be covered by the first upper insulating layer 79 and the second upper insulating layer 81, respectively. The first upper insulating layer 79 may extend to cover the plurality of active pillars 61P and the semiconductor pattern 61S. Figure 3 and Figure 5 As shown, the second upper insulating layer 81 may extend between the semiconductor pattern 61S and the doped semiconductor layer DPS.

[0066] Reference Figure 3 , a plurality of upper lines UL1 to UL3 may be disposed above any one of the first upper insulating layer 79 and the second upper insulating layer 81. The plurality of upper lines UL1 to UL3 are conductive lines for transmitting electrical signals, and may include first to third upper lines UL1 to UL3. The first upper line UL1 may be connected to an active pillar 61P corresponding thereto, and may be used as a global line GLL. The second upper line UL2 may be connected to a through gate 67, and may be used as a block selection line BSEL. The third upper line UL3 may be connected to a doped semiconductor layer DPS, and may be used as a common source line CSL.

[0067] The plurality of contacts CT1 to CT3 may be formed of a conductive material and may include first to third contacts CT1 to CT3 connected to the first to third upper lines UL1 to UL3, respectively. The first contact CT1 may contact the second junction 61J2 of the active pillar 61P corresponding thereto and pass through the first upper insulating layer 79 to connect the second junction 61J2 to the first upper line UL1. The second contact CT2 may contact the through gate 67 and pass through the first upper insulating layer 79 to connect the through gate 67 to the second upper line UL2. The third contact CT3 may contact the doped semiconductor layer DPS and pass through the second upper insulating layer 81 to connect the doped semiconductor layer DPS to the third upper line UL3.

[0068] The channel pillar CHP of the first structure ST1 may be disposed between the doped semiconductor layer DPS and the bit line BL. The bit line BL may be formed of a conductive material and may be connected to the corresponding channel pillar CHP. As an embodiment, the bit line BL may be connected to the capping pattern CAP of the corresponding channel pillar CHP via a conductive bit line contact BCT.

[0069] The conductive bit line contact BCT may pass through a buffer insulating layer 66 interposed between the gate stack GST and the bit line BL. The bit line BL may pass through an insulating layer 71 between the buffer insulating layer 66 and the second structure ST2. The insulating layer 71 may extend between the gate stack GST and the first area AR1 of the peripheral circuit structure PS. A filling insulating layer 69 may be provided between the stepped structure of the gate stack GST and the insulating layer 71. A plurality of gate contact plugs GCT may extend to pass through the filling insulating layer 69.

[0070] The plurality of first conductive bonding patterns 77 of the first structure ST1 may be disposed in the first insulating structure 73. The first insulating structure 73 may be interposed between the second structure ST2 and the insulating layer 71. The first insulating structure 73 may include a plurality of layers of insulating layers. The plurality of first conductive bonding patterns 77 may include a metal such as copper. A portion of the plurality of first conductive bonding patterns 77 may be connected to the bit line BL. As an embodiment, the bit line BL may be connected to a portion of the plurality of first conductive bonding patterns 77 via a first conductive bonding contact 75. The first conductive bonding contact 75 may be disposed in the first insulating structure 73 between the bit line BL and the first conductive bonding pattern 77 corresponding thereto.

[0071] The peripheral circuit structure PS of the second structure ST2 may include a plurality of transistors TR formed on a peripheral circuit substrate 83. The peripheral circuit substrate 83 may be a semiconductor substrate of silicon, germanium, etc. A portion of the plurality of transistors TR may be configured Figure 1 The page buffer 37 is shown.

[0072] Each transistor TR may include a gate insulating layer 87, a gate electrode 89, a source junction 83J1, and a drain junction 83J2. The gate insulating layer 87 and the gate electrode 89 may be stacked above the active region 83A of the peripheral circuit substrate 83. The active region 83A of the peripheral circuit substrate 83 may be separated by an isolation layer 85. The source junction 83J1 and the drain junction 83J2 may be formed in the active region 83A on both sides of the gate electrode 89.

[0073] The peripheral circuit structure PS may be covered by the second insulating structure 91. The second insulating structure 91 may include a plurality of layers of insulating layers.

[0074] The plurality of interconnects 93 of the second structure ST2 may be disposed in the second insulating structure 91. The plurality of interconnects 93 may include a plurality of conductive patterns connected to the gate electrode 89, the source junction 83J1, and the drain junction 83J2. The plurality of interconnects 93 may be connected to the plurality of second conductive bonding patterns 97 via the plurality of second conductive bonding contacts 95.

[0075] The plurality of second conductive bonding patterns 97 may include a metal such as copper. Each of the plurality of second conductive bonding contacts 95 may be disposed between the second conductive bonding pattern 97 corresponding thereto and the interconnection 93 , and may be disposed in the second insulating structure 91 .

[0076] The plurality of second conductive bonding patterns 97 may be bonded to the plurality of first conductive bonding patterns 77 to be structurally and electrically connected to the plurality of first conductive bonding patterns 77. A portion of the plurality of second conductive bonding patterns 97 may be connected to a transistor of a page buffer among the plurality of transistors TR. The transistor of the page buffer may be connected to the corresponding second conductive bonding pattern 97 via a second conductive bonding contact 95 and an interconnection 93.

[0077] Reference Figures 3 to 6 , the pass gate 67 may be used as a plurality of gates of a plurality of pass transistors of the pass circuit 40. Therefore, the plurality of pass transistors of the pass circuit 40 may be commonly controlled according to an electrical signal applied to the second upper line UL2.

[0078] Reference Figures 3 to 6 In an embodiment, since the plurality of active pillars 61P are respectively disposed in the plurality of active holes 67H of the through gate 67, each of the plurality of pass transistors may be formed into a gate-all-around transistor (SGT) structure. Therefore, in an embodiment, an area occupied by the plurality of pass transistors may be reduced, and on / off characteristics of each pass transistor may be improved.

[0079] Reference Figure 3In an embodiment, since the pass circuit 40 is disposed to overlap with the peripheral circuit structure PS with the gate stack GST interposed therebetween, the area allocated to the pass circuit 40 in the peripheral circuit substrate 83 can be reduced. Therefore, in an embodiment, the integration degree of the semiconductor memory device can be improved.

[0080] Reference Figure 3 and Figure 4 , the plurality of active pillars 61P of the through circuit 40 may overlap with the contact region CTR of the gate stack GST opened by the doped semiconductor layer DPS. Therefore, in an embodiment, because the area allocated to the through circuit 40 can be reduced, the integration of the semiconductor memory device can be improved. In addition, the plurality of active pillars 61P of the through circuit 40 may overlap with the plurality of gate contact plugs GCT disposed in the contact region CTR of the gate stack GST. Therefore, in an embodiment, because the plurality of gate contact plugs GCT and the plurality of active pillars 61P can be directly connected, the connection structure between the plurality of conductive patterns CP and the through circuit 40 can be simplified.

[0081] FIG. 8A to FIG. 8C , Fig.9A , Fig. 9B , FIG. 10A to FIG. 10C , FIG. 11A to FIG. 11D , Fig. 12A , Fig. 12B and FIG. 13A to FIG. 13J is a diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0082] FIG. 8A to FIG. 8C is a perspective view illustrating a process of forming a plurality of active pillars and through gates.

[0083] Reference Fig. 8A , an interposition insulating layer 163 may be formed to cover a second surface 161SU2 of a semiconductor substrate 161 including a first surface 161SU1 and a second surface 161SU2 facing opposite directions. The semiconductor substrate 161 may include a first impurity region 161A adjacent to the first surface 161SU1 and a second impurity region 161B adjacent to the second surface 161SU2. The first impurity region 161A and the second impurity region 161B may include at least one of an n-type impurity and a p-type impurity. As an embodiment, the first impurity region 161A and the second impurity region 161B may include a p-type impurity as a majority carrier. The first impurity region 161A may include a conductive impurity having a concentration higher than that of the second impurity region 161B so that the first impurity region 161A may be selectively removed later. As an embodiment, the first impurity region 161A may include a p-type impurity having a concentration higher than that of the second impurity region 161B.

[0084] The direction facing the first surface 161SU1 of the semiconductor substrate 161 may be defined as a first direction DR1, each of the first impurity region 161A and the second impurity region 161B of the semiconductor substrate 161 may extend in the second direction DR2 and the third direction DR3, and the direction facing the second surface 161SU2 of the semiconductor substrate 161 may be defined as a fourth direction DR4. The first direction DR1 and the fourth direction DR4 may correspond to the -Z axis direction and the +Z axis direction, respectively, and the second direction DR2 and the third direction DR3 may correspond to the X axis direction and the Y axis direction, respectively.

[0085] The semiconductor substrate 161 may include a first region AR1′ and a second region AR2′. The second region AR2′ of the semiconductor substrate 161 may extend from the first region AR1′ in the second direction DR2. The first impurity region 161A and the second impurity region 161B may be formed in the first region AR1′ and the second region AR2′ of the semiconductor substrate 161, respectively.

[0086] A first mask pattern 101 may be formed over the interposition insulating layer 163. The first mask pattern 101 may include a first mask portion 101A and a plurality of second mask portions 101B. The first mask portion 101A may have a first opening 101OP, and a plurality of second mask portions 101B may be disposed in the first opening 101OP. The first opening 101OP and the plurality of second mask portions 101B may overlap with the first region AR1' of the semiconductor substrate 161.

[0087] Reference Figure 8B , you can use Fig. 8A The illustrated first mask pattern 101 serves as an etching barrier to etch the interposing insulating layer 163 and the first region AR1 ′ of the semiconductor substrate 161 through an etching process.

[0088] Through the etching process of the interposition insulating layer 163, the interposition insulating layer 163 may be separated into a plurality of first interposition parts 163A and a second interposition part 163B. The first trench 163T surrounded by the second interposition part 163B may be defined by partially etching the interposition insulating layer 163. The plurality of first interposition parts 163A may be separated from each other in the first trench 163T. The plurality of first interposition parts 163A may be defined in the first trench 163T. Fig. 8A In the region corresponding to the plurality of second mask portions 101B of the first mask pattern 101 shown in FIG. 1 , the second insertion portion 163B may be defined in the region corresponding to the plurality of second mask portions 101B of the first mask pattern 101 shown in FIG. Fig. 8A The first mask pattern 101 shown corresponds to the region of the first mask portion 101A.

[0089] Through the etching process for the first region AR1' of the semiconductor substrate 161, the second impurity region 161B of the semiconductor substrate 161 may be etched. Therefore, a second trench 161T may be defined in the semiconductor substrate 161, and a plurality of active pillars 161P may be defined. The second trench 161T may be formed at the same Fig. 8A In the region corresponding to the first opening 101OP of the first mask pattern 101 shown in FIG. 1 , a plurality of active pillars 161P may be formed in the region corresponding to the first opening 101OP of the first mask pattern 101. Fig. 8A The semiconductor pattern 161S may be defined in an area corresponding to the plurality of second mask portions 101B of the first mask pattern 101 shown in FIG. Fig. 8A The first mask pattern 101 shown corresponds to the region of the first mask portion 101A. Fig. 8A The illustrated first mask pattern 101 may be removed after forming the plurality of active pillars 161P and the second trenches 161T.

[0090] A plurality of active pillars 161P may be formed between the first impurity region 161A and the plurality of first interposing portions 163A of the semiconductor substrate 161. The plurality of active pillars 161P may be spaced apart from each other in the second trench 161T. A semiconductor pattern 161S may be formed between the first impurity region 161A and the second interposing portions 163B of the semiconductor substrate 161.

[0091] Reference Figure 8C , can be followed Figure 8B The insulating layer 165 is formed on the surface of each of the first trench 163T and the second trench 161T. The insulating layer 165 may be formed along the Figure 8B The insulating layer 165 may be formed by depositing an insulating layer such as an oxide layer or by using an oxidation process. The insulating layer 165 may include a first vertical portion 165A, a second vertical portion 165B, and a horizontal portion 165C. The first vertical portion 165A of the insulating layer 165 may surround the first vertical portion 165A of the insulating layer 165. Figure 8B The second vertical portion 165B of the insulating layer 165 may be formed along the side of each of the plurality of first interposition portions 163A of the interposition insulating layer 163 and the side of each of the plurality of active pillars 161P. Figure 8B The inner wall of the first groove 163T shown in FIG. Figure 8B The horizontal portion 165C may extend along the inner wall of the second groove 161T. Figure 8B The bottom surface of the second trench 161T is shown extending.

[0092] Subsequently, a through gate 167 may be formed. The through gate 167 may be formed at Figure 8BThe first trench 163T and the second trench 161T shown in FIG. The first trench 163T and the second trench 161T may include an area opened by the insulating layer 165, the plurality of active pillars 161P, and the plurality of first interposed portions 163A of the interposed insulating layer 163. The pass gate 167 may fill the open area of ​​the first trench 163T and the second trench 161T. The pass gate 167 may extend in the fourth direction DR4 to surround not only the insulating layer 165 interposed therebetween, but also the first active pillar 161P and the plurality of first interposed portions 163A of the interposed insulating layer 163. Figure 8B The through gate 167 is formed to be thicker than the active pillars 161P in the fourth direction DR4, so that the sheet resistance of the through gate 167 can be reduced. The through gate 167 may include at least one of a doped semiconductor layer and a metal layer. In addition to the metal layer, the through gate 167 may further include a metal nitride layer.

[0093] Fig.9A and Fig. 9B are perspective views and cross-sectional views illustrating a process of forming a preliminary stack, a memory layer, and a channel pillar. Fig. 9B It is along Fig.9A A cross-sectional view taken along line II' is shown.

[0094] Reference Fig.9A and Fig. 9B The preliminary stack 170 may be formed to overlap the semiconductor substrate 161 including the semiconductor pattern 161S and the plurality of active pillars 161P through the gate 167. The preliminary stack 170 may be formed by alternately stacking a plurality of first material layers 171 and a plurality of second material layers 173 over the interposition insulating layer 163 in the fourth direction DR4.

[0095] The plurality of second material layers 173 may be formed of a material having an etching selectivity with respect to the plurality of first material layers 171. As an embodiment, the plurality of first material layers 171 may include an insulating material such as a silicon oxide layer and a silicon oxynitride layer, and the plurality of second material layers 173 may include a sacrificial insulating material such as a silicon nitride layer.

[0096] Subsequently, the second area AR2' of the semiconductor substrate 161 may be exposed by etching a portion where each of the plurality of first material layers 171, the plurality of second material layers 173, and the second interposing portion 163B of the interposing insulating layer 163 overlaps with the second area AR2' of the semiconductor substrate 161. Thereafter, the second area AR2' of the semiconductor substrate 161 may be etched. At this time, a portion of the semiconductor pattern 161S may be etched in the second area AR2' of the semiconductor substrate 161. Thus, a plurality of channel holes 175 may be formed. Each of the channel holes 175 may pass through the preliminary stack 170 and extend into the semiconductor pattern 161S disposed in the second area AR2' of the semiconductor substrate 161.

[0097] Thereafter, a memory layer 177 may be formed along the surface of each channel hole 175. Figures 3 to 5 As described, the memory layer 177 may include a blocking insulating layer, a data storage layer, and a tunnel insulating layer. Subsequently, a channel pillar 179 may be formed in the channel hole 175 opened through the memory layer 177.

[0098] As an embodiment, forming the channel pillar 179 may include: forming a channel layer 179A by depositing a semiconductor material such as silicon or germanium on a surface of the memory layer 177; forming a core insulating layer 181 in the channel hole 175 opened by the channel layer 179A; opening a portion of the channel hole 175 by removing a portion of the core insulating layer 181; and filling a portion of the opened channel hole 175 with a capping pattern 179B. The capping pattern 179B may include a doped semiconductor material.

[0099] FIG. 10A to FIG. 10C are a plan view, a perspective view, and a cross-sectional view illustrating a process of forming a stepped structure and a buffer insulating layer. Fig. 10B is a perspective view of a preliminary stack showing a portion of each of a buffer insulating layer, a plurality of first material layers, and a plurality of second material layers by perspectively showing the stack so as to facilitate recognition of a stepped structure, Fig. 10C It is along Fig. 10A A cross-sectional view taken along line II' is shown.

[0100] Reference FIG. 10A to FIG. 10C , a selection line separation structure 183 may be formed passing through at least one layer of the second material layer 173 of the preliminary stack 170. The selection line separation structure 183 may be formed of an insulating material.

[0101] Subsequently, a buffer insulating layer 185 may be formed over the preliminary stack 170. The buffer insulating layer 185 may include an oxide such as a silicon oxide layer. Thereafter, an etching process for forming the stepped structure 170ST may be performed. Forming the stepped structure 170ST may include forming a mask layer (not shown) over the buffer insulating layer 185 and using the mask layer as an etching barrier to etch a portion of each of the buffer insulating layer 185, the plurality of first material layers 171, and the plurality of second material layers 173 by an etching process. Etching a portion of the plurality of first material layers 171 and a portion of the plurality of second material layers 173 may include a trimming process that reduces the size of the mask layer and an etching process for an exposed region of the plurality of first material layers 171 and an exposed region of the plurality of second material layers 173. The trimming process and the etching process may be repeated until a plurality of pad portions 170P1 to 170P9 are formed. The mask layer may be removed after the stepped structure 170ST is formed.

[0102] A plurality of pad portions 170P1 to 170P9 may be arranged at different heights and overlap with a plurality of active pillars 161P, respectively. Each of the plurality of pad portions 170P1 to 170P9 may be configured by a pair of first material layers 171 and second material layers 173 corresponding thereto. The plurality of pad portions 170P1 to 170P9 may correspond to a plurality of steps of the stepped structure 170ST forming the preliminary stack 170.

[0103] FIG. 11A to FIG. 11D is a cross-sectional view illustrating a process of replacing a plurality of second material layers with a plurality of third material layers and a process of forming a plurality of contact holes.

[0104] Reference Fig.11A , a plurality of first recessed regions 173R1 may be formed by etching a portion of the plurality of second material layers 173 from the edge of the step structure 170ST in the preliminary stack 170. Fig. 10B The plurality of pad portions 170P1 to 170P9 shown may form a plurality of first recessed regions 173R1 corresponding to a portion of the plurality of second material layers 173. The plurality of first recessed regions 173R1 may be defined between the plurality of first material layers 171 adjacent to each other in the fourth direction DR4.

[0105] Reference Fig. 11B , multiple third material layers 187 may be used to fill Fig.11A The plurality of first recessed regions 173R1 are shown. The plurality of third material layers 187 may include a material having an etching selectivity relative to the plurality of first material layers 171 and the plurality of second material layers 173. As an embodiment, the process of forming the plurality of third material layers 187 may include forming a silicon layer to fill Fig.11AThe plurality of first recessed regions 173R1 are shown and a portion of the silicon layer is removed using an etching process such as etch-back so that the silicon layer is separated into a plurality of third material layers 187 .

[0106] Reference Fig. 11C , a filling insulating layer 189 may be formed to cover the reference Fig. 10B A plurality of third material layers 187 and a plurality of pad portions 170P1 to 170P9 are described. The filling insulating layer 189 may include an oxide such as a silicon oxide layer.

[0107] Subsequently, a portion of each of the plurality of first interposition portions 163A of the filling insulation layer 189, the plurality of first material layers 171, the plurality of second material layers 173, the plurality of third material layers 187, and the plurality of interposition insulation layers 163 may be etched. Thus, a plurality of contact holes 191 exposing each of the plurality of active pillars 161P may be formed.

[0108] Reference Fig.11D , a portion of each of the plurality of second material layers 173 may be etched through the plurality of contact holes 191. Thus, a plurality of second recessed regions 173R2 may be defined. Each of the plurality of second recessed regions 173R2 may be defined between the first material layers 171 adjacent in the fourth direction DR4.

[0109] Fig. 12A and Fig. 12B are perspective views and cross-sectional views illustrating a process of forming a spacer layer, a plurality of fourth material layers, and slits. Fig. 12A It is a perspective view showing the filling insulating layer by perspective to facilitate identification of the spacer layer and the plurality of fourth material layers. Fig. 12B It is along Fig. 12A A cross-sectional view taken along line II' is shown.

[0110] Reference Fig. 12A and Fig. 12B , a spacer layer 193 may be formed in each of the plurality of contact holes 191 to fill the plurality of second recessed regions 173R2. The spacer layer 193 may include an insulating material having an etching selectivity with respect to the plurality of second material layers 173 and the plurality of third material layers 187. As an embodiment, the spacer layer 193 may include an oxide such as a silicon oxide layer.

[0111] The spacer layer 193 may extend along a surface of each of the plurality of contact holes 191. A central region of each of the plurality of contact holes 191 may be open without being filled with the spacer layer 193.

[0112] Thereafter, a central region of each of the plurality of contact holes 191 opened through the spacer layer 193 may be filled with a fourth material layer 195. The fourth material layer 195 may include a material having an etching selectivity with respect to the spacer layer 193. As an embodiment, the fourth material layer 195 may include silicon. The spacer layer 193 may be interposed between each third material layer 187 and the fourth material layer 195 corresponding thereto.

[0113] Subsequently, a slit 197 may be formed by etching the buffer insulating layer 185, the filling insulating layer 189, the plurality of first material layers 171, the plurality of second material layers 173, and the plurality of third material layers 187. The slit 197 may extend in the second direction DR2. A side surface of each of the plurality of second material layers 173 and the plurality of third material layers 187 may be exposed through the slit 197.

[0114] FIG. 13A to FIG. 13J It is shown that the formation Fig. 12A A cross-sectional view of an embodiment of subsequent processing after the slit 197 is shown.

[0115] Reference Fig.13A , can be obtained through Fig. 12A The slits 197 shown are replaced with a plurality of conductive patterns 199. Fig. 12A and Fig. 12B The plurality of second material layers 173 and the plurality of third material layers 187 are shown. More specifically, Fig. 12A The slit 197 shown is selectively removed Fig. 12A and Fig. 12B The plurality of second material layers 173 and the plurality of third material layers 187 are shown. At this time, even if the fourth material layer 195 is made of Fig. 12B The fourth material layer 195 may also be protected by the spacer layer 193 and may be used as a support. Subsequently, a conductive material may be formed in the region where the plurality of second material layers 173 and the plurality of third material layers 187 are removed. Thereafter, the conductive material may be removed. Fig. 12A A portion of the conductive material within the slit 197 is shown so that the conductive material is separated into a plurality of conductive patterns 199. Although not shown in the figure, before forming the conductive material, a metal oxide layer such as an aluminum oxide layer may be formed along the surface of the region where the plurality of second material layers 173 and the plurality of third material layers 187 are removed.

[0116] As described above, the gate stack 170G may be defined by replacing the plurality of second material layers 173 and the plurality of third material layers 187 with the plurality of conductive patterns 199. In addition, the memory cell array 100 including the gate stack 170G, the memory layer 177, and the channel pillar 179 may be formed.

[0117] The gate stack 170G may include a plurality of first material layers 171 and a plurality of conductive patterns 199. Each of the plurality of first material layers 171 may be used as an interlayer insulating layer. Each of the plurality of first material layers 171 and the plurality of conductive patterns 199 of the gate stack 170G may overlap with the second region AR2' of the semiconductor substrate 161, and may be penetrated by the memory layer 177 and the channel pillar 179. The plurality of conductive patterns 199 of the gate stack 170G may be spaced apart from each other by the plurality of first material layers 171. The plurality of conductive patterns 199 may include a plurality of end portions 199EG respectively overlapping with the plurality of active pillars 161P. The plurality of end portions 199EG of the plurality of conductive patterns 199 may form a stepped structure. Each of the plurality of end portions 199EG of the plurality of conductive patterns 199 may be spaced apart from the fourth material layer 195 by the spacer layer 193 corresponding thereto.

[0118] Although not shown in the figure, after forming the memory cell array 100, Fig. 12A Vertical structures are shown formed within the slots 197. The vertical structures may include insulating material, or may include insulating material and conductive material.

[0119] Reference Fig. 13B , can be etched Fig.13A The fourth material layer 195 and the spacer layer 193 are shown to open the plurality of contact holes 191. Although not shown in the figure, when a metal oxide layer is additionally formed before forming the plurality of conductive patterns 199, a portion of the metal oxide layer may be formed through Fig.13A The illustrated etching process of the spacer layer 193 exposes, and may additionally etch, exposed portions of the metal oxide layer.

[0120] According to the above process, the plurality of end portions 199EG of the plurality of conductive patterns 199 may be exposed through the plurality of contact holes 191. The exposed region of each of the plurality of end portions 199EG of the plurality of conductive patterns 199 may be as shown in FIG. Figure 7B The formation of the first inner sidewall IW1 is described.

[0121] Controllable Fig.13A The etching process of the spacer layer 193 shown in FIG. 1 is performed so that a portion of the spacer layer remains as an insulating spacer 193S. The insulating spacer 193S may be disposed at Fig.13A In each second recessed area 173R2 shown. Fig.13A The spacer layer 193 is shown to be etched so that the plurality of active pillars 161P are exposed through the plurality of contact holes 191 , respectively.

[0122] Subsequently, the first junction 161J1 may be formed by injecting at least one of n-type impurities and p-type impurities into a portion of the plurality of active pillars 161P through the plurality of contact holes 191 .

[0123] Reference Fig. 13C , can be filled with conductive materials Fig. 13B The plurality of contact holes 191 shown are used to form a plurality of gate contact plugs 201. Each gate contact plug 201 may contact an exposed region of an end portion 199EG of a corresponding conductive pattern 199. Each gate contact plug 201 may contact a first junction 161J1 of a corresponding active pillar 161P. Therefore, the plurality of gate contact plugs 201 may connect the plurality of conductive patterns 199 of the memory cell array 100 to the plurality of active pillars 161P.

[0124] Thereafter, a bit line contact 203 , a bit line 207 , a first conductive bonding contact 213 , and a first conductive bonding pattern 215 may be formed over the memory cell array 100 .

[0125] As an embodiment, the bit line contact 203 may be formed in the buffer insulating layer 185. The bit line contact 203 may pass through the buffer insulating layer 185 to contact the channel pillar 179 of the memory cell array 100. Thereafter, the insulating layer 205 may be formed to cover the bit line contact 203, the plurality of gate contact plugs 201, the buffer insulating layer 185, and the filling insulating layer 189. Subsequently, a bit line 207 may be formed in the insulating layer 205. The bit line 207 may pass through the insulating layer 205 to contact the bit line contact 203. Subsequently, a first insulating structure 211 in which a first conductive bonding contact 213 and a first conductive bonding pattern 215 are buried may be formed.

[0126] Reference Fig.13D , which can be provided with reference Figure 3 The second structure ST2 described corresponds to the structure 220. Figure 3 As described above, the structure 220 may include a peripheral circuit substrate 221 , a peripheral circuit structure 223 , a plurality of interconnections 225 , a plurality of second conductive bonding contacts 227 , and a plurality of second conductive bonding patterns 229 .

[0127] Subsequently, a bonding process may be performed such that the plurality of second conductive bonding patterns 229 of the structure 220 are connected to the plurality of first conductive bonding patterns 215 .

[0128] Reference Fig.13E , can be removed Fig.13D The first impurity region 161A of the semiconductor substrate 161 is shown. At this time, Fig.13D The horizontal portion 165C of the insulating layer 165 shown may be removed, and Fig.13D The first vertical portion 165A and the second vertical portion 165B of the insulating layer 165 shown may be separated to configure a first through gate insulating layer and a second through gate insulating layer, respectively. The selective etching process may be used to remove the Fig.13DThe first impurity region 161A of the semiconductor substrate 161 is shown.

[0129] along with Fig.13D The first impurity region 161A of the semiconductor substrate 161 is shown removed, and the plurality of active pillars 161P and the semiconductor pattern 161S may be separated from each other. The thickness of each of the plurality of active pillars 161P and the pass gate 167 in the first direction DR1 may be controlled by a planarization process such as chemical mechanical polishing (CMP).

[0130] Subsequently, a first upper insulating layer 301 may be formed to cover the through gate 167 and the plurality of active pillars 161P. The first upper insulating layer 301 may be formed to open a portion of the semiconductor pattern 161S remaining in the second region AR2' of the semiconductor substrate 161. Subsequently, the second region AR2' of the semiconductor substrate 161 opened by the first upper insulating layer 301 may be removed. Thus, the second insertion portion 163B of the insertion insulating layer 163 may be formed as shown in FIG. Fig.13F As shown, a portion of the memory layer 177 may be exposed as shown. Fig.13F The dotted lines indicate exposure.

[0131] Reference Fig.13F , a portion of the memory layer 177 indicated by the dotted line may be removed. Therefore, a portion of the channel pillar 179 may be exposed.

[0132] Reference Figure 13G , a doped semiconductor layer 303 connected to the channel pillar 179 may be formed. The doped semiconductor layer 303 may include at least one of n-type impurities and p-type impurities. As an embodiment, the doped semiconductor layer 303 may include n-type impurities as majority carriers.

[0133] The doped semiconductor layer 303 may be spaced apart from the semiconductor pattern 161S remaining in the first region AR1′ of the semiconductor substrate 161 in the second direction DR2. The doped semiconductor layer 303 may be formed on the second interposing portion 163B of the interposing insulating layer 163 to cover the exposed region of the channel pillar 179. The doped semiconductor layer 303 may contact the exposed region of the channel pillar 179.

[0134] Reference Fig.13H , a second upper insulating layer 305 may be formed to cover the doped semiconductor layer 303. The second upper insulating layer 305 may fill a region between the semiconductor pattern 161S and the doped semiconductor layer 303.

[0135] Reference Fig.13I, a second mask pattern 351 may be formed over the first upper insulating layer 301 and the second upper insulating layer 305. The second mask pattern 351 may include a plurality of openings 351OP1 to 351OP3. The plurality of openings 351OP1 to 351OP3 may include a plurality of first openings 351OP1, a second opening 351OP2, and a third opening 351OP3. The plurality of first openings 351OP1 may overlap with the corresponding plurality of active pillars 161P. The second opening 351OP2 may overlap with the pass gate 167. The third opening 351OP3 may overlap with the doped semiconductor layer 303.

[0136] Subsequently, the first upper insulating layer 301 and the second upper insulating layer 305 may be etched by an etching process using the second mask pattern 351 as an etching barrier. At this time, a portion of each of the first upper insulating layer 301 and the second upper insulating layer 305 exposed by the plurality of openings 351OP1 to 351OP3 may be etched, and thus a plurality of upper holes 301H1, 301H2, and 305H may be formed. The plurality of upper holes 301H1, 301H2, and 305H may include a plurality of first upper holes 301H1, a second upper hole 301H2, and a third upper hole 305H. The plurality of first upper holes 301H1 may pass through the first upper insulating layer 301 to expose each of the plurality of active pillars 161P. The second upper hole 301H2 may pass through the first upper insulating layer 301 to expose the through gate 167. The third upper hole 305H may pass through the second upper insulating layer 305 to expose the doped semiconductor layer 303.

[0137] Subsequently, the second junction 161J2 may be formed by injecting at least one of n-type impurities and p-type impurities into a portion of the plurality of active pillars 161P through the plurality of first upper holes 301H1. In each active pillar 161P, a region between the first junction 161J1 and the second junction 161J2 may serve as a channel region.

[0138] Thereafter, the second mask pattern 351 may be removed.

[0139] Reference Fig.13J , a plurality of contacts 311A ​​to 311C may be formed by filling the plurality of upper holes 301H1 to 301H3 with a conductive material. The plurality of contacts 311A ​​to 311C may include a plurality of first contacts 311A, second contacts 311B, and third contacts 311C.

[0140] The plurality of first contacts 311A ​​may be respectively arranged at Fig.13I Each first contact 311A ​​may contact the second junction 161J2 of the corresponding active pillar 161P. The second contact 311B may be disposed in the plurality of first upper holes 301H1. Fig.13I The second upper hole 301H2 shown in FIG. 1 and can contact the gate 167. The third contact 311C can be set Fig.13IThe third upper hole 305H is shown and can contact the doped semiconductor layer 303 .

[0141] After that, the execution can be performed Figure 3 The subsequent processes of the plurality of upper lines UL1 to UL3 are shown.

[0142] Fig.14 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure.

[0143] Reference Fig.14 The electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200 .

[0144] The host 1100 may store data in the storage device 1200 or read data stored in the storage device 1200 based on the interface. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a high-speed PCI (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a Firewire interface, a universal flash memory (UFS) interface, and a high-speed non-volatile memory (NVMe) interface.

[0145] The storage device 1200 may include a storage controller 1210 and a semiconductor memory device 1220. As an embodiment, the storage device 1200 may be a storage medium such as a solid state drive (SSD) or a USB memory.

[0146] The memory controller 1210 may store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100 .

[0147] The semiconductor memory device 1220 may include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data under the control of the memory controller 1210.

[0148] The semiconductor memory device 1220 may be a non-volatile memory device. Figure 3 As described, the semiconductor memory device 1220 may include a gate stack disposed between a peripheral circuit structure and a through gate, and the through gate may include a plurality of active holes for a plurality of active pillars.

[0149] According to various embodiments of the present disclosure, a gate stack may be disposed between a through gate and a peripheral circuit structure. Therefore, in embodiments, the integration degree of a semiconductor memory device may be improved.

[0150] CROSS-REFERENCE TO RELATED APPLICATIONS

[0151] This application claims the priority of Korean Patent Application No. 10-2023-0094708 filed on July 20, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: Through the gate; a plurality of active pillars, the plurality of active pillars being respectively disposed in the plurality of active holes included in the through gate; as well as a gate stack, the pass gate being disposed above the gate stack in a first direction, The gate stack includes a plurality of conductive patterns that are spaced apart from each other in the first direction and stacked in the first direction.

2. The semiconductor memory device according to claim 1, further comprising: A first passing gate insulating layer is disposed between each of the plurality of active pillars and the passing gate.

3. The semiconductor memory device according to claim 1, wherein: Each of the plurality of active pillars comprises: a first junction, the first junction facing the gate stack; a second knot facing in a direction opposite to the direction of the first knot; and A channel region is between the first junction and the second junction.

4. The semiconductor memory device according to claim 1, further comprising: a plurality of gate contact plugs, the plurality of gate contact plugs passing through the gate stack and corresponding to the plurality of active pillars respectively, Each of the plurality of gate contact plugs connects a corresponding active pillar among the plurality of active pillars to a corresponding conductive pattern among the plurality of conductive patterns.

5. The semiconductor memory device according to claim 1, further comprising: a semiconductor pattern surrounding a sidewall of the through gate at a height at which the plurality of active pillars are disposed; as well as A second pass gate insulating layer is interposed between the semiconductor pattern and the pass gate.

6. The semiconductor memory device according to claim 1, wherein: The gate stack includes a contact region overlapping the plurality of active pillars and a cell array region extending from the contact region, and The plurality of conductive patterns are formed in a stepped structure in the contact region of the gate stack.

7. The semiconductor memory device according to claim 1, wherein: The gate stack includes a plurality of pad portions forming a stepped structure, and The plurality of pad portions are configured by end portions of the plurality of conductive patterns and overlap the plurality of active pillars, respectively.

8. The semiconductor memory device according to claim 1, further comprising: A channel pillar, the channel pillar being disposed in a channel hole of the gate stack; as well as a memory layer between the channel pillar and the gate stack, The gate stack includes a contact region overlapping the plurality of active pillars and a cell array region extending from the contact region in a second direction faced by the side surfaces of the plurality of active pillars, and The channel hole passes through the plurality of conductive patterns in the cell array region of the gate stack.

9. The semiconductor memory device according to claim 1, further comprising: a peripheral circuit structure, wherein the pass gate is disposed above the peripheral circuit structure in the first direction, wherein the pass gate is spaced apart from the peripheral circuit structure in the first direction, and wherein the gate stack is disposed between the pass gate and the peripheral circuit structure; a doped semiconductor layer, the doped semiconductor layer being spaced apart from the pass gate in a second direction faced by the sides of the plurality of active pillars; a channel column, the channel column being disposed between the peripheral circuit structure and the doped semiconductor layer, the channel column extending in the first direction and connected to the doped semiconductor layer; and a memory layer surrounding a side of the channel pillar, The plurality of conductive patterns extend between the doped semiconductor layer and the peripheral circuit structure to surround the memory layer.

10. A semiconductor memory device, comprising: A peripheral circuit structure, the peripheral circuit structure comprising a first region and a second region; a pass gate spaced apart from the peripheral circuit structure in a first direction and overlapping the first region of the peripheral circuit structure; an active pillar, the active pillar being disposed in the active hole through the gate; a doped semiconductor layer, the doped semiconductor layer being spaced apart from the peripheral circuit structure in the first direction and overlapping the second region of the peripheral circuit structure; a gate stack including a contact region between the first region of the peripheral circuit structure and the pass gate and a cell array region extending from the contact region to overlap with the second region of the peripheral circuit structure; a channel pillar connected to the doped semiconductor layer and passing through the cell array region of the gate stack; a memory layer, the memory layer being between the channel pillar and the gate stack; as well as A gate contact plug is connected to the active pillar and passes through the contact region of the gate stack.

11. The semiconductor memory device according to claim 10, wherein: The gate stack includes a plurality of conductive patterns spaced apart from each other in the first direction and stacked in the first direction, and The plurality of conductive patterns include a first conductive pattern contacting the gate contact plug and a second conductive pattern insulated from the gate contact plug.

12. The semiconductor memory device according to claim 11, further comprising: a first insulating spacer interposed between the gate contact plug and the first conductive pattern; as well as A second insulating spacer is interposed between the gate contact plug and the second conductive pattern.

13. The semiconductor memory device according to claim 12, wherein: The first conductive pattern comprises: a first inner sidewall contacting the gate contact plug; and A second inner sidewall extends from the first inner sidewall along a side surface of the first insulating spacer.

14. The semiconductor memory device according to claim 12, wherein: The second insulating spacer is formed in a ring shape to surround a side surface of the gate contact plug.

15. The semiconductor memory device according to claim 10, further comprising: A through gate insulating layer is disposed between the active pillar and the through gate.

16. The semiconductor memory device according to claim 10, wherein: The active column comprises: a first junction contacting the gate contact plug; a second knot facing in a direction opposite to the direction of the first knot; and A channel region is between the first junction and the second junction.

17. The semiconductor memory device according to claim 16, further comprising: a global line connected to the second junction; as well as A block selection line is connected to the pass gate.

18. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a plurality of active pillars by etching the first region in a semiconductor substrate including the first region and the second region; forming an insulating layer surrounding a side surface of each of the plurality of active pillars; forming a pass gate surrounding the plurality of active pillars, with the insulating layer interposed between the plurality of active pillars and the pass gate; forming a memory cell array including a gate stack overlapping the plurality of active pillars and the second region of the semiconductor substrate, a channel hole extending into the second region of the semiconductor substrate by passing through the gate stack, and a memory layer and a channel pillar disposed in the channel hole; forming a first conductive bonding pattern on the memory cell array; forming a structure including a peripheral circuit structure and a second conductive bonding pattern; performing a bonding process to connect the first conductive bonding pattern and the second conductive bonding pattern; as well as The plurality of active pillars are separated from each other by removing a portion of the semiconductor substrate.

19. The method according to claim 18, wherein: The step of forming the plurality of active pillars comprises: forming an interposing insulating layer above the semiconductor substrate; forming a mask pattern over the interposition insulating layer, the mask pattern including a first mask portion having a first opening and a plurality of second mask portions disposed in the first opening; etching the intervening insulating layer and the semiconductor substrate using the mask pattern as an etching barrier so that a trench corresponding to the first opening is defined in the semiconductor substrate and the plurality of active pillars respectively corresponding to the plurality of second mask portions are defined in the trench; and The mask pattern is removed.

20. The method according to claim 19, wherein: The insulating layer extends along the trench and a surface of each of the plurality of active pillars, and The through gate is formed to fill the inside of the trench opened by the insulating layer and the plurality of active pillars.

21. The method according to claim 18, wherein: The steps of forming the memory cell array include: Alternatingly stacking a plurality of first material layers and a plurality of second material layers over the semiconductor substrate and the through gate including the plurality of active pillars; forming the channel hole by etching the plurality of first material layers, the plurality of second material layers, and the second region of the semiconductor substrate; forming the memory layer along a surface of the channel hole; forming the channel pillar in the channel hole opened through the memory layer; forming a stepped structure having a plurality of pad portions by etching the plurality of first material layers and the plurality of second material layers overlapping the first region of the semiconductor substrate, the plurality of pad portions being arranged at different heights and respectively overlapping the plurality of active pillars; Using a plurality of third material layers to replace a plurality of edge regions of the plurality of second material layers respectively corresponding to the plurality of pad portions; forming a filling insulating layer covering the plurality of third material layers and the pad portion; forming slits by etching the plurality of first material layers, the plurality of second material layers, and the plurality of third material layers so that a side surface of each of the plurality of second material layers and the plurality of third material layers is exposed; and The plurality of second material layers and the plurality of third material layers are replaced with a plurality of conductive patterns through the slits.

22. The method according to claim 21, further comprising the steps of: forming a plurality of contact holes exposing the corresponding plurality of active pillars by etching a portion of each of the filling insulating layer, the plurality of first material layers, the plurality of second material layers, and the plurality of third material layers; forming a plurality of recessed areas by etching a portion of the plurality of second material layers through the plurality of contact holes; forming a spacer layer filling an interior of each of the plurality of recessed regions and extending along a surface of each of the plurality of contact holes; filling the interior of each of the plurality of contact holes opened through the spacer layer with a fourth material layer; opening the plurality of contact holes by etching the fourth material layer and the spacer layer so that the plurality of active pillars and the plurality of conductive patterns are opened; as well as A plurality of gate contact plugs are formed in the opened plurality of contact holes.

23. The method according to claim 22, wherein: An etching process of the spacer layer is controlled so that a portion of the spacer layer remains as an insulating spacer within each of the plurality of recessed regions.

24. The method according to claim 18, wherein: The gate stack includes a plurality of conductive patterns spaced apart from each other and stacked over the semiconductor substrate, The plurality of ends of the plurality of conductive patterns form a stepped structure overlapping the plurality of active pillars, and The plurality of end portions of the plurality of conductive patterns are exposed through a plurality of contact holes.

25. The method according to claim 24, further comprising the steps of: forming a plurality of gate contact plugs in the plurality of contact holes respectively, The plurality of gate contact plugs connect the plurality of conductive patterns to the plurality of active pillars.

26. The method according to claim 18, further comprising the steps of: forming an upper insulating layer covering the through gate and the plurality of active pillars; exposing a portion of the memory layer by removing the second region of the semiconductor substrate opened by the upper insulating layer; exposing a portion of the channel pillar by removing an exposed portion of the memory layer; as well as A doped semiconductor layer is formed covering the exposed portion of the channel pillar and spaced apart from the first region of the semiconductor substrate.

27. The method according to claim 26, further comprising the steps of: A plurality of first contacts and a second contact are formed, the plurality of first contacts passing through the upper insulating layer to be connected to the plurality of active pillars, and the second contacts passing through the upper insulating layer to be connected to the passing gate.

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