Semiconductor memory device and method of manufacturing the same

Abstract

The invention relates to a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes: a gate stack; overlapping, by the gate, with a contact region of the gate stack and opening a cell array region of the gate stack; a doped semiconductor layer spaced apart by the gate and overlapping a cell array region of the gate stack; and an active pillar passing through the through gate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device and a method of manufacturing the three-dimensional semiconductor memory device. Background Art

[0002] Semiconductor memory devices are used in electronic devices in various fields, such as automobiles, medical care, and data centers, as well as small electronic devices. Therefore, the demand for semiconductor memory devices is increasing.

[0003] A semiconductor memory device may include memory cells for data storage. In order to increase the capacity of a semiconductor memory device, technology development for a three-dimensional semiconductor memory device including memory cells arranged in three dimensions is being actively studied. Summary of the invention

[0004] According to an embodiment of the present disclosure, a semiconductor memory device may include: a gate stack, the gate stack including a plurality of conductive patterns spaced apart from each other in a first direction and stacked in the first direction, the gate stack including a contact area and a cell array area extending from the contact area in a second direction intersecting the first direction; a through gate, the through gate overlapping the contact area of ​​the gate stack and opening the cell array area of ​​the gate stack; a doped semiconductor layer, the doped semiconductor layer spaced apart from the through gate in the second direction and overlapping with the cell array area of ​​the gate stack; and a plurality of active pillars, the plurality of active pillars passing through the through gate.

[0005] According to an embodiment of the present disclosure, a semiconductor memory device may include: a peripheral circuit structure, the peripheral circuit structure including a first region and a second region; a through gate, the through gate being spaced apart from the peripheral circuit structure in a first direction and overlapping with the first region of the peripheral circuit structure; a doped semiconductor layer, the doped semiconductor layer being spaced apart from the peripheral circuit structure in the first direction and being spaced apart from the through gate in a second direction intersecting the first direction; a gate stack, the gate stack including a contact region between the peripheral circuit structure and the through gate and a cell array region extending from the contact region to a region between the peripheral circuit structure and the doped semiconductor layer; an active pillar, the active pillar passing through the through gate; a through gate insulating layer, the through gate insulating layer being located between the through gate and the active pillar; a channel pillar, the channel pillar being in contact with the doped semiconductor layer and passing through the cell array region of the gate stack; a memory layer, the memory layer being located between the channel pillar and the gate stack; and a gate contact plug, the gate contact plug being connected to the active pillar and passing through the contact region of the gate stack.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device may include the following steps: forming an active pillar surrounded by a through gate insulating layer in an initial through gate layer, wherein the initial through gate layer includes a first region and a second region, and wherein the active pillar is formed in the first region of the initial through gate layer; forming a memory cell array above the initial through gate layer including the active pillar; forming a first conductive bonding pattern above the memory cell array; forming a structure including a peripheral circuit structure and a second conductive bonding pattern; performing a bonding process so that the first conductive bonding pattern and the second conductive bonding pattern are connected; etching the second region of the initial through gate layer so that the first region of the initial through gate layer is retained as a through gate surrounding the active pillar; and forming a doped semiconductor layer in the region where the second region of the initial through gate layer is etched. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 is a circuit diagram showing a memory cell array and a pass circuit according to an embodiment of the present disclosure.

[0009] Figure 3 , Figure 4 , Figure 5 , Fig. 6A and Figure 6B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0010] 7A to 7C , Figure 8 , 9A to 9D , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B and FIG. 12A to FIG. 12K is a diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Fig.13 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0012] The specific structure and function description disclosed herein are only exemplified for the purpose of describing the embodiments according to the conception of the present disclosure. The embodiments according to the conception of the present disclosure can be modified in various forms and replaced with other equivalent embodiments. Therefore, the present disclosure should not be interpreted as being limited to the embodiments set forth herein.

[0013] It should be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and the order or number of components is not limited by these terms. In addition, unless there is a special limitation on the components represented in the singular or plural, it is not interpreted as a limitation on the number of components.

[0014] Embodiments of the present disclosure may provide a semiconductor memory device capable of improving integration and a method of manufacturing the same.

[0015] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Reference Figure 1 , the semiconductor memory device 50 may include a memory cell array 10, a pass circuit 40, and a peripheral circuit structure PS.

[0017] The memory cell array 10 may include a plurality of memory blocks. Each of the memory blocks may include a plurality of memory cells. Each of the memory cells may be a nonvolatile memory cell. As an embodiment, each memory cell may be a NAND flash memory cell. Hereinafter, embodiments of the present disclosure are described based on a semiconductor memory device 50 including a NAND flash memory cell, but the present disclosure is not limited thereto. As another embodiment, each memory cell may be composed of a ferroelectric memory cell, a variable resistance memory cell, etc.

[0018] The pass circuit 40 may be connected to the memory cell array 10 through a plurality of local lines. As an embodiment, the plurality of local lines may include a plurality of word lines WL, at least one source select line SSL, and at least one drain select line DSL.

[0019] The peripheral circuit structure PS may be configured to perform a program operation for storing data in the memory cell array 10, a read operation for outputting data stored in the memory cell array 10, and an erase operation for erasing data stored in the memory cell array 10. As an embodiment, the peripheral circuit structure PS may include an input / output circuit 21, a control circuit 23, a voltage generating circuit 31, a block decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0020] The input / output circuit 21 may transfer a command CMD and an address ADD received from an external device (eg, a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 may exchange data DATA with the external device and the column decoder 35.

[0021] The control circuit 23 may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to a command CMD and an address ADD.

[0022] The voltage generation circuit 31 may generate and output various operation voltages for program operation, read operation, and erase operation in response to the operation signal OP_S. The operation voltages output from the voltage generation circuit 31 may be transmitted to the pass circuit 40 through the plurality of global lines GLL.

[0023] The block decoder 33 may output a block selection signal in response to the row address RADD. The block selection signal output from the block decoder 33 may be transmitted to the pass circuit 40 through the block selection line BSEL.

[0024] The pass circuit 40 may transmit the operating voltage transmitted to the plurality of global lines GLL to the drain select line DSL, the word line WL, and the source select line SSL in response to the block select signal transmitted to the block select line BSEL.

[0025] The column decoder 35 may transfer data DATA input from the input / output circuit 21 to the page buffer 37 in response to the column address CADD or transfer data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 may exchange data DATA with the input / output circuit 21 through the column lines CL. The column decoder 35 may exchange data DATA with the page buffer 37 through the data lines DL.

[0026] The page buffer 37 may store read data received through the bit line BL in response to the page buffer control signal PB_S. The page buffer 37 may sense a voltage or current of the bit line BL during a read operation. The page buffer 37 may be connected to the memory cell array 10 through the bit line BL.

[0027] The source line driver 39 may control a voltage applied to the common source line CSL in response to a source line control signal SL_S. The source line driver 39 may be connected to the memory cell array 10 through the common source line CSL.

[0028] Figure 2 is a circuit diagram showing a memory cell array and a pass circuit according to an embodiment of the present disclosure.

[0029] Reference Figure 2 , the memory cell array 10 may include a plurality of memory cell strings CS. The plurality of memory cell strings CS may be connected to a plurality of bit lines BL and a common source line CSL.

[0030] Each memory cell string CS may include at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST.

[0031] The source select transistor SST may control electrical connection between the plurality of memory cells MC and a common source line CSL. The drain select transistor DST may control electrical connection between the plurality of memory cells MC and a bit line BL.

[0032] One source selection transistor SST may be provided between the common source line CSL and the plurality of memory cells MC, or two or more source selection transistors connected in series may be provided between the common source line CSL and the plurality of memory cells MC. One drain selection transistor DST may be provided between each bit line BL and the plurality of memory cells MC corresponding to each bit line of the memory cell string CS, or two or more drain selection transistors connected in series may be provided between each bit line BL and the plurality of memory cells MC corresponding to each bit line of the memory cell string CS.

[0033] A plurality of gates of a plurality of memory cells MC may be respectively connected to a plurality of word lines WL. A gate of a source selection transistor SST may be connected to a source selection line SSL. A gate of a drain selection transistor DST may be connected to a drain selection line DSL.

[0034] The source selection line SSL, the drain selection line DSL, and the plurality of word lines WL may be connected to the pass circuit 40. The pass circuit 40 may include a plurality of pass transistors PT. The plurality of pass transistors PT may be respectively connected to the plurality of gate contact plugs GCT. The plurality of gate contact plugs GCT may be respectively connected to the source selection line SSL, the drain selection line DSL, and the plurality of word lines WL. Each pass transistor PT may be connected to the source selection line SSL, the drain selection line DSL, and the gate line corresponding thereto among the plurality of word lines WL via the gate contact plug GCT corresponding thereto.

[0035] The plurality of pass transistors PT may transmit a voltage applied to the plurality of global lines GLL to the source select line SSL, the drain select line DSL, and the plurality of word lines WL in response to a block select signal applied to the block select line BSEL. The plurality of global lines GLL may include a global source select line GSSL, a global drain select line GDSL, and a plurality of global word lines GWL corresponding to the source select line SSL, the drain select line DSL, and the plurality of word lines WL, respectively.

[0036] Figure 3 , Figure 4 , Figure 5 , Fig. 6A and Figure 6B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0037] Figure 3 is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0038] Reference Figure 3 , the semiconductor memory device may include a first structure ST1, a second structure ST2, a doped semiconductor layer DPS, a plurality of contacts CT1 and CT2, and a plurality of upper lines UL1 and UL2. The first structure ST1, the doped semiconductor layer DPS, and the plurality of contacts CT1 and CT2 may be disposed between the second structure ST2 and the plurality of upper lines UL1 and UL2.

[0039] The first structure ST1 may include a via circuit 40, a plurality of gate contact plugs GCT connected to the via circuit 40, a memory cell array 10 connected to the plurality of gate contact plugs GCT, a bit line BL connected to the memory cell array 10, and a plurality of first conductive bonding patterns 77. The via circuit 40 may include Figure 2 The memory cell array 10 may include a plurality of pass transistors PT composed of a pass gate 61PG, a plurality of active pillars 67P, and a plurality of pass gate insulating layers 65A. The memory cell array 10 may include a gate stack GST, a channel pillar CHP passing through the gate stack GST, and a memory layer ML interposed between the channel pillar CHP and the gate stack GST.

[0040] The through gate 61PG and the doped semiconductor layer DPS may overlap the gate stack GST. The gate stack GST may extend from between the through gate 61PG and the second structure ST2 to between the doped semiconductor layer DPS and the second structure ST2.

[0041] The first structure ST1 and the doped semiconductor layer DPS may be covered with at least one upper insulating layer 79 or 81. As an embodiment, the via circuit 40 of the first structure ST1 may be covered with a first upper insulating layer 79, and the first upper insulating layer 79 and the doped semiconductor layer DPS may be covered with a second upper insulating layer 81.

[0042] The plurality of contacts CT1 and CT2 may pass through at least one of the first upper insulating layer 79 and the second upper insulating layer 81. The plurality of contacts CT1 and CT2 may be formed of a conductive material. The plurality of contacts CT1 and CT2 may include a plurality of first contacts CT1 and a plurality of second contacts CT2. The plurality of first contacts CT1 may pass through the first upper insulating layer 79 and the second upper insulating layer 81 and may be respectively connected to the plurality of active pillars 67P of the through circuit 40. The second contact CT2 may pass through the second upper insulating layer 81 and may be connected to the doped semiconductor layer DPS.

[0043] A plurality of upper lines UL1 and UL2 may be disposed above the second upper insulating layer 81. The plurality of upper lines UL1 and UL2 may be conductive lines for transmitting electrical signals, and may include a plurality of first upper lines UL1 and a second upper line UL2. The plurality of first upper lines UL1 may be connected to a plurality of first contacts CT1, respectively, and may be used as a plurality of global lines GLL. The second upper line UL2 may be connected to a second contact CT2, and may be used as a common source line CSL.

[0044] Although not shown in the figure, the semiconductor memory device may further include Figure 1 The block select line BSEL shown in FIG. Figure 1 The block selection line BSEL is shown connected to the third contact of the pass gate 61PG. The block selection line may be disposed over the second upper insulating layer 81, and the third contact may pass through the first and second upper insulating layers 79 and 81 to be connected to the pass gate 61PG.

[0045] The second structure ST2 may include a peripheral circuit structure PS, a plurality of interconnections 93 connected to the peripheral circuit structure PS, and a plurality of second conductive bonding patterns 97 connected to the plurality of interconnections 93. The peripheral circuit structure PS may include a first area AR1 and a second area AR2.

[0046] Figure 4 It is shown Figure 3The memory cell array 10 , the doped semiconductor layer DPS, the gate contact plugs GCT and the via circuit 40 are shown in a perspective view. Figure 5 It is shown Figure 3 A plan view of the memory cell array 10 , the doped semiconductor layer DPS, the gate contact plugs GCT and the via circuit 40 is shown.

[0047] Reference Figures 3 to 5 , the through gate 61PG and the doped semiconductor layer DPS may be spaced apart from the peripheral circuit structure PS in the first direction DR1. The through gate 61PG may overlap with the first region AR1 of the peripheral circuit structure PS, wherein the gate stack GST and the plurality of gate contact plugs GCT are interposed between the through gate 61PG and the first region AR1. The doped semiconductor layer DPS may overlap with the second region AR2 of the peripheral circuit structure PS, wherein the gate stack GST is interposed between the doped semiconductor layer DPS and the second region AR2. The doped semiconductor layer DPS may be spaced apart from the through gate 61PG in the second direction DR2.

[0048] Through the gate 61PG can be used as Figure 2 The gate of each of the multiple pass transistors PT shown. The pass gate 61PG may include a plurality of active holes 60H corresponding to the multiple active pillars 67P, respectively. The pass gate 61PG may include a semiconductor material of a single crystal structure or a polycrystalline structure. As an embodiment, the semiconductor material of the pass gate 61PG may be formed by an epitaxial wafer. The semiconductor material of the pass gate 61PG may include at least one of an n-type impurity and a p-type impurity. As an embodiment, the semiconductor material of the pass gate 61PG may be doped silicon including a p-type impurity as a majority carrier.

[0049] A plurality of active pillars 67P may be respectively disposed in a plurality of active holes 60H through the gate 61PG. A plurality of active pillars 67P may include semiconductor materials such as silicon or germanium. Each of a plurality of through gate insulating layers 65A may surround the side of the active pillar 67P corresponding thereto. Therefore, each through gate insulating layer 65A may be interposed between the through gate 61PG and the active pillar 67P corresponding thereto.

[0050] Reference Figure 3, each active pillar 67P may include a channel region 67CH, a first junction 67J1, and a second junction 67J2. The channel region 67CH of the active pillar 67P may be used as a channel of a corresponding pass transistor, and each of the first junction 67J1 and the second junction 67J2 of the active pillar 67P may be used as a source or a drain of a corresponding pass transistor. The channel region 67CH may be an undoped region or a doped region including at least one of a p-type impurity and an n-type impurity. Each of the first junction 67J1 and the second junction 67J2 may include at least one of an n-type impurity and a p-type impurity. As an embodiment, the first junction 67J1 and the second junction 67J2 may include an n-type impurity as a majority carrier, and the channel region 67CH may be an undoped region. The first junction 67J1 of the memory cell array 10 may face the gate stack GST, and the second junction 67J2 may face the first direction DR1, which is the opposite direction to the first junction 67J1. The channel region 67CH may be disposed between the first junction 67J1 and the second junction 67J2. The channel region 67CH may surround the first core insulating layer 68A. The first core insulating layer 68A may include a first surface facing the gate stack GST and a second surface facing a direction opposite to the direction of the first surface. The first junction 67J1 may extend to cover the first surface of the first core insulating layer 68A, and the second junction 67J2 may extend to cover the second surface of the first core insulating layer 68A. The gate insulating layer 65A may extend to cover the second junction 67J2 and may be penetrated by the first contact CT1 corresponding thereto.

[0051] Reference Figures 3 to 5 , the gate stack GST may include a plurality of conductive patterns CP spaced apart from each other in the first direction DR1 and stacked in the first direction DR1. The gate stack GST may also include a plurality of interlayer insulating layers ILD alternately stacked with the plurality of conductive patterns CP in the first direction DR1. Each conductive pattern CP and each interlayer insulating layer ILD may be formed in a plate shape. As an embodiment, each conductive pattern CP and each interlayer insulating layer ILD may include a surface extending in the second direction DR2 and the third direction DR3. The first direction DR1, the second direction DR2, and the third direction DR3 may be defined as directions pointed by three axes, each of the three axes intersecting a plane defined by the other two axes. The fourth direction DR4 may be opposite to the first direction DR1. The plurality of conductive patterns CP may be used as Figure 2The drain selection line DSL, the multiple word lines WL and the source selection line SSL shown. The multiple conductive patterns CP may include at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer of each conductive pattern CP may include a doped silicon layer. The metal layer of each conductive pattern CP may include tungsten, copper, molybdenum, etc. The multiple conductive patterns CP may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The multiple interlayer insulating layers ILD may include a silicon oxide layer, etc.

[0052] The gate stack GST may include a contact region CTR and a cell array region CAR extending from the contact region CTR in the second direction DR2. The contact region CTR of the gate stack GST may overlap with the through gate 61PG, and the cell array region CAR of the gate stack GST may be opened by the through gate 61PG. The doped semiconductor layer DPS may overlap with the cell array region CAR of the gate stack GST opened by the through gate 61PG. The side of the through gate 61PG may include a region overlapping with the side of the doped semiconductor layer DPS.

[0053] A plurality of conductive patterns CP and a plurality of interlayer insulating layers ILD may configure a contact region CTR of a gate stack GST between the first region AR1 of the peripheral circuit structure PS and the gate 61PG. A plurality of conductive patterns CP and a plurality of interlayer insulating layers ILD may be formed as a stepped structure in the contact region CTR. A plurality of pad portions PAD may be configured at a plurality of ends of a plurality of conductive patterns CP. A plurality of pad portions PAD may form a stepped structure of a gate stack GST, and may correspond to a plurality of steps arranged at different heights. A plurality of pad portions PAD may overlap with a plurality of active pillars 67P, respectively. A plurality of pad portions PAD and a plurality of active pillars 67P may be arranged in a row in the second direction DR2. The embodiments of the present disclosure are not limited thereto. As another embodiment, a plurality of pad portions PAD and a plurality of active pillars 67P may be arranged in multiple rows and columns.

[0054] A plurality of conductive patterns CP and a plurality of interlayer insulating layers ILD may extend between the doped semiconductor layer DPS and the second region AR2 of the peripheral circuit structure PS to configure the cell array region CAR. The plurality of conductive patterns CP and the plurality of interlayer insulating layers ILD may be penetrated by the plurality of channel holes CHH in the cell array region CAR. A channel pillar CHP may be disposed in each channel hole CHH. The channel pillar CHP may be formed of a semiconductor material. As an embodiment, the channel pillar CHP may include silicon, germanium, or a mixture thereof. The second core insulating layer CO may be disposed inside the channel pillar CHP. The second core insulating layer CO may include an insulating material such as silicon oxide. The channel pillar CHP may include a channel layer CHL and a covering pattern CAP. The channel layer CHL may be used as a channel region of a memory cell string corresponding thereto, and may surround the side of the second core insulating layer CO. The channel layer CHL may extend to cover a first surface of the second core insulating layer CO facing the first direction DR1. The covering pattern CAP may cover a second surface of the second core insulating layer CO facing the fourth direction DR4. The covering pattern CAP may be used as a drain junction of a memory cell string. The capping pattern CAP may include at least one of an n-type impurity and a p-type impurity. As an embodiment, the capping pattern CAP may include an n-type impurity as a majority carrier.

[0055] The memory layer ML may include a blocking insulating layer between the channel pillar CHP and the gate stack GST, a data storage layer between the blocking insulating layer and the channel pillar CHP, and a tunnel insulating layer between the data storage layer and the channel pillar CHP. The blocking insulating layer may include an insulating material capable of blocking charges. The tunnel insulating layer may include an insulating material capable of performing charge tunneling. The blocking insulating layer may include an insulating layer having a dielectric constant higher than that of the tunnel insulating layer. The data storage layer may be formed of a material layer capable of storing changed data using Fowler Nordheim tunneling. As an embodiment, the data storage layer may be formed of a charge trapping insulating layer or an insulating layer including conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. The present disclosure is not limited thereto, and the data storage layer may be formed of a material layer capable of storing information based on an operating principle other than Fowler Nordheim tunneling. As an embodiment, the data storage layer may include a phase change material layer, a ferroelectric layer, etc. In this case, the channel pillar CHP may be replaced with a columnar electrode structure.

[0056] A plurality of gate contact plugs GCT may be connected to a plurality of active pillars 67P, respectively. As an embodiment, each gate contact plug GCT may contact the first junction 67J1 of the active pillar 67P corresponding thereto and extend in the fourth direction DR4. A plurality of gate contact plugs GCT may pass through the gate stack GST in the contact region CTR of the gate stack GST. Each gate contact plug GCT may include at least one of a doped semiconductor layer and a metal layer. The doped semiconductor layer of the gate contact plug GCT may include a doped silicon layer. The metal layer of the gate contact plug GCT may include tungsten, copper, molybdenum, etc. Each gate contact plug GCT may also include a metal nitride layer. The metal nitride layer may include titanium nitride, tantalum nitride, etc. The metal nitride layer may be formed along the surface of the metal layer.

[0057] Fig. 6A and Figure 6B It is shown Figure 3 A perspective view of a portion of the gate stack GST and a portion of the gate contact plug GCT is shown. For easy identification, Fig. 6A A part of the configuration of a semiconductor memory device is shown in a perspective view.

[0058] Reference Figure 3 , Figure 5 , Fig. 6A and Figure 6B , a plurality of gate contact plugs GCT may respectively pass through a plurality of pad portions PAD. Each gate contact plug GCT may form a contact surface CTS with an end portion of a conductive pattern of a corresponding pad portion among a plurality of pad portions PAD configuring a plurality of conductive patterns CP. For example, the plurality of gate contact plugs GCT may include a first gate contact plug GCT1. The plurality of conductive patterns CP may include a first conductive pattern CP1 and a second conductive pattern CP2 adjacent to each other in a first direction DR1. An end portion of the first conductive pattern CP1 may form a contact surface CTS with the first gate contact plug GCT1, and the second conductive pattern CP2 may be insulated from the first gate contact plug GCT1.

[0059] A plurality of insulating spacers SP1 and SP2 may be interposed between a plurality of gate contact plugs GCT and a plurality of conductive patterns CP. The plurality of insulating spacers SP1 and SP2 may include a first insulating spacer SP1 and a plurality of second insulating spacers SP2 buried in each conductive pattern CP. The first insulating spacer SP1 may be adjacent to a contact surface CTS between a conductive pattern CP and a gate contact plug GCT corresponding thereto, and may surround a portion of a side surface of the gate contact plug GCT to open the contact surface CTS. Each second insulating spacer SP2 may be spaced apart from the contact surface CTS, and may be interposed between a gate contact plug GCT and a conductive pattern CP that need to be insulated from each other. Each second insulating spacer SP2 may be formed in a ring shape to surround a side surface of the gate contact plug GCT. For example, the first insulating spacer SP1 may be adjacent to a contact surface CTS between a first gate contact plug GCT1 and a first conductive pattern CP1, and may surround a portion of a side surface of the first gate contact plug GCT1. The second insulating spacer SP2 may be interposed between the first gate contact plug GCT1 and the second conductive pattern CP2 , and may surround a side of the first gate contact plug GCT1 in a ring shape.

[0060] Each conductive pattern (e.g., CP1) may include a first inner sidewall IW1 and a second inner sidewall IW2. The first inner sidewall IW1 of each conductive pattern (e.g., CP1) may form a contact surface CTS with a gate contact plug (e.g., GCT1) corresponding thereto. The second inner sidewall IW2 may extend from the first inner sidewall IW1 along a side of the first insulating spacer SP1.

[0061] Each of the first insulating spacer SP1 and the plurality of second insulating spacers SP2 may be interposed between interlayer insulating layers ILD adjacent to each other in the first direction DR1. For example, the plurality of interlayer insulating layers ILD may include a first interlayer insulating layer ILD1 and a second interlayer insulating layer ILD2 adjacent to each other in the first direction DR1, wherein the first conductive pattern CP1 is interposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2, and the first insulating spacer SP1 may be interposed between the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2.

[0062] Each conductive pattern CP may include a metal nitride layer L1 and a metal layer L2, and each gate contact plug GCT may include a metal nitride layer L1' and a metal layer L2'. In this case, a contact surface CTS may be defined by contact between the metal nitride layer L1 of the conductive pattern CP and the metal nitride layer L1' of the gate contact plug GCT.

[0063] Reference Figures 3 to 5, the gate stacks GST may be separated in the memory block unit by the slits SI. As an embodiment, the gate stack of the first memory block may be adjacent to the gate stack of the second memory block in the third direction DR3 with the slits SI interposed therebetween.

[0064] The pass gate 61PG may be separated by the trench 60T. As an embodiment, the first pass gate may overlap with the gate stack of the first memory block, and the second pass gate may overlap with the gate stack of the second memory block. In this case, the first pass gate may be adjacent to the second pass gate in the third direction DR3, with the trench 60T interposed therebetween.

[0065] The trench 60T may be filled with a partition wall structure 67PT and a partition wall insulating layer 65B. The partition wall insulating layer 65B may cover the side of the partition wall structure 67PT. The partition wall structure 67PT may include the same material as the plurality of active pillars 67P. As an embodiment, the partition wall structure 67PT may include a partition wall channel layer 67A and a partition wall covering pattern 67B. The partition wall channel layer 67A may include the same material as the channel region 67CH of the active pillar 67P. The partition wall core insulating layer 68B may be disposed inside the partition wall channel layer 67A. The partition wall channel layer 67A may extend to cover the first surface of the partition wall core insulating layer 68B facing the first direction DR1. The partition wall covering pattern 67B may include the same material as the first junction 67J1 of the active pillar 67P. The partition wall covering pattern 67B may cover the second surface of the partition wall core insulating layer 68B facing the fourth direction DR4. The partition wall insulating layer 65B may include the same material as the gate insulating layer 65A. The partition wall insulating layer 65B may extend to cover a surface of the partition wall structure 67PT facing the first direction DR1 .

[0066] The semiconductor memory device may further include a semiconductor pattern 61S between the pass gate PG and the doped semiconductor layer DPS. The semiconductor pattern 61S may overlap the gate stack GST. The semiconductor pattern 61S may include the same material as the pass gate PG. Each of the trench 60T, the partition wall structure 67PT, and the partition wall insulating layer 65B may extend between the semiconductor pattern 61S and the pass gate 61PG.

[0067] The first upper insulating layer 79 may extend to cover the pass gate PG, the partition wall structure 67PT, the partition wall insulating layer 65B, and the semiconductor pattern 61S. The second upper insulating layer 81 may extend between the semiconductor pattern 61S and the doped semiconductor layer DPS.

[0068] The first structure ST1 may further include an insertion insulating layer 63. The insertion insulating layer 63 may include a first insertion portion 63A and a second insertion portion 63B. The first insertion portion 63A may be disposed between the gate stack GST and the through gate 61PG. The second insertion portion 63B may be disposed between the gate stack GST and the doped semiconductor layer DPS, and may extend between the gate stack GST and the semiconductor pattern 61S.

[0069] The plurality of active pillars 67P, the plurality of pass gate insulating layers 65A, the partition wall structure 67PT, and the partition wall insulating layer 65B may extend to pass through the insertion insulating layer 63. The first insertion portion 63A and the second insertion portion 63B of the insertion insulating layer 63 may be spaced apart from the partition wall structure 67PT and the partition wall insulating layer 65B interposed therebetween.

[0070] The plurality of active pillars 67P may pass through the first insertion portion 63A of the insertion insulating layer 63 to contact the plurality of gate contact plugs GCT. The plurality of conductive patterns CP may be electrically connected to the plurality of active pillars 67P of the via circuit 40 through the plurality of gate contact plugs GCT.

[0071] The channel pillar CHP and the memory layer ML may extend to pass through the second insertion portion 63B of the insertion insulating layer 63. The channel pillar CHP may protrude in the first direction DR1 compared to the second insertion portion 63B of the insertion insulating layer 63 and the memory layer ML. More specifically, the channel pillar CHP may include a first portion P1 and a second portion P2. The first portion P1 of the channel pillar CHP may pass through the gate stack GST and the second insertion portion 63B of the insertion insulating layer 63, and the second portion P2 may be embedded in the doped semiconductor layer DPS by extending from the first portion P1. The second portion P2 of the channel pillar CHP may contact the doped semiconductor layer DPS. A portion of the side of the through gate 61PG may overlap with the second portion P2 of the channel pillar CHP.

[0072] The doped semiconductor layer DPS may surround the second portion P2 of the channel pillar CHP. The doped semiconductor layer DPS may extend in the second direction DR2 and the third direction DR3 to overlap the cell array region CAR of the gate stack GST. A plurality of channel pillars CHP may be disposed between the doped semiconductor layer DPS and the peripheral circuit structure PS, and the plurality of channel pillars CHP may be connected in parallel to the doped semiconductor layer DPS.

[0073] The doped semiconductor layer DPS may include at least one of an n-type impurity and a p-type impurity. The doped semiconductor layer DPS may be used as at least one of a source region and a well region. As an embodiment, the doped semiconductor layer DPS may be provided as a source region including n-type impurities as majority carriers. The embodiments of the present disclosure are not limited thereto. As another embodiment, the doped semiconductor layer DPS may include at least one of a first conductive type doped region including n-type impurities as majority carriers and a second conductive type doped region including p-type impurities as majority carriers. The first conductive type doped region may be used as a source region, and the second conductive type doped region may be used as a well region.

[0074] Reference Figure 3 , the channel pillar CHP of the first structure ST1 may be disposed between the doped semiconductor layer DPS and the bit line BL. The bit line BL may be formed of a conductive material and may be connected to the channel pillar CHP corresponding thereto. As an embodiment, the bit line BL may be connected to the capping pattern CAP of the channel pillar CHP corresponding thereto via a conductive bit line contact BCT.

[0075] The conductive bit line contact BCT may pass through the buffer insulating layer 66 interposed between the gate stack GST and the bit line BL. The bit line BL may pass through the buffer insulating layer 66 and the insulating layer 71 between the second structure ST2. The insulating layer 71 may extend between the gate stack GST and the first area AR1 of the peripheral circuit structure PS. A filling insulating layer 69 may be provided between the stepped structure of the gate stack GST and the insulating layer 71. The gate contact plug GCT may extend to pass through the filling insulating layer 69.

[0076] A plurality of first conductive bonding patterns 77 of the first structure ST1 may be disposed in the first insulating structure 73. The first insulating structure 73 may be interposed between the second structure ST2 and the insulating layer 71. The first insulating structure 73 may include a plurality of insulating layers. The plurality of first conductive bonding patterns 77 may include a metal such as copper. A portion of the plurality of first conductive bonding patterns 77 may be connected to the bit line BL. As an embodiment, the bit line BL may be connected to a portion of the plurality of first conductive bonding patterns 77 via a first conductive bonding contact 75. The first conductive bonding contact 75 may be disposed in the first insulating structure 73 between the bit line BL and the first conductive bonding pattern 77 corresponding thereto.

[0077] The peripheral circuit structure PS of the second structure ST2 may include a plurality of transistors TR formed on a semiconductor layer 83. The semiconductor layer 83 may include silicon, germanium, etc. A portion of the plurality of transistors TR may constitute Figure 1 The page buffer 37 is shown.

[0078] Each transistor TR may include a gate insulating layer 87, a gate electrode 89, a source junction 83J1, and a drain junction 83J2. The gate insulating layer 87 and the gate electrode 89 may be stacked on the active region 83A of the semiconductor layer 83. The active region 83A of the semiconductor layer 83 may be separated by an isolation layer 85. The source junction 83J1 and the drain junction 83J2 may be formed in the active region 83A on both sides of the gate electrode 89.

[0079] The peripheral circuit structure PS may be covered with a second insulating structure 91. The second insulating structure 91 may include a plurality of insulating layers.

[0080] The plurality of interconnects 93 of the second structure ST2 may be disposed in the second insulating structure 91. The plurality of interconnects 93 may include a plurality of conductive patterns connected to the gate electrode 89, the source junction 83J1, and the drain junction 83J2. The plurality of interconnects 93 may be connected to the plurality of second conductive bonding patterns 97 via the plurality of second conductive bonding contacts 95.

[0081] The plurality of second conductive bonding patterns 97 may include a metal such as copper, etc. Each of the plurality of second conductive bonding contacts 95 may be disposed between the second conductive bonding pattern 97 corresponding thereto and the interconnection 93 , and may be disposed in the second insulating structure 91 .

[0082] The plurality of second conductive bonding patterns 97 may be bonded to the plurality of first conductive bonding patterns 77 to be structurally and electrically connected to the plurality of first conductive bonding patterns 77. A portion of the plurality of second conductive bonding patterns 97 may be connected to a portion of the plurality of transistors TR via the second conductive bonding contacts 95 and the interconnections 93. In an embodiment, at least one of the second conductive bonding patterns 97 may be connected to a transistor of the page buffer via the second conductive bonding contacts 95 and the interconnections 93.

[0083] Reference Figures 3 to 5 , the pass gate 61PG can be used as a plurality of gates of a plurality of pass transistors of the pass circuit 40. Therefore, the plurality of pass transistors of the pass circuit 40 can be collectively controlled according to an electrical signal applied to the pass gate 61PG.

[0084] Reference Figures 3 to 5 Since the plurality of active pillars 61P are respectively disposed in the plurality of active holes 60H of the through gate 61PG, each of the plurality of pass transistors can be formed in the surrounding gate transistor (SGT) structure. Therefore, the area occupied by the plurality of pass transistors can be reduced, and the on / off characteristics of each pass transistor can be improved.

[0085] Reference Figure 3Since the via circuit 40 is arranged to overlap with the peripheral circuit structure PS with the gate stack GST interposed between the via circuit 40 and the peripheral circuit structure PS, the area allocated to the via circuit 40 in the semiconductor layer 83 can be reduced. Therefore, the integration degree of the semiconductor memory device can be improved.

[0086] Reference Figures 3 to 5 , the plurality of active pillars 67P of the through circuit 40 may overlap with the contact region CTR of the gate stack GST opened by the doped semiconductor layer DPS. Therefore, since the area allocated to the through circuit 40 can be reduced, the integration of the semiconductor memory device can be improved. In addition, the plurality of active pillars 67P of the through circuit 40 may overlap with the plurality of gate contact plugs GCT disposed in the contact region CTR of the gate stack GST. Therefore, since the plurality of gate contact plugs GCT and the plurality of active pillars 67P can be directly connected, the connection structure between the plurality of conductive patterns CP and the through circuit 40 can be simplified.

[0087] 7A to 7C , Figure 8 , 9A to 9D , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B and FIG. 12A to FIG. 12K is a diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0088] 7A to 7C is a perspective view showing a process of forming a plurality of active pillars and through gates.

[0089] Reference Fig. 7A , an insertion insulating layer 163 may be formed over the initial through gate layer 161 including the first region AR1' and the second region AR2'. The initial through gate layer 161 may include a semiconductor material of a single crystal structure or a polycrystalline structure. As an embodiment, the initial through gate layer 161 may be an epitaxial wafer. As an embodiment, the epitaxial wafer may be a silicon wafer. The initial through gate layer 161 formed by the epitaxial wafer may include a seed region 161A and an epitaxial region 161B. The seed region 161A and the epitaxial region 161B may include at least one of an n-type impurity and a p-type impurity. The concentration of majority carriers in the seed region 161A may be higher than the concentration of majority carriers in the epitaxial region 161B. Therefore, the etching selectivity of the seed region 161A relative to the epitaxial region 161B may be increased. As an embodiment, the seed region 161A and the epitaxial region 161B may include a p-type impurity as a majority carrier, and the seed region 161A may include a p-type impurity having a concentration higher than that of the epitaxial region 161B.

[0090] Hereinafter, the direction facing the rear surface of the gate layer 161 initially passed through may be defined as a first direction DR1, the direction extending from the rear surface of the gate layer 161 initially passed through may be defined as a second direction DR2 and a third direction DR3, and the direction opposite to the first direction DR1 may be defined as a fourth direction DR4. The first direction DR1 and the fourth direction DR4 may correspond to the -Z axis direction and the +Z axis direction, respectively, and the second direction DR2 and the third direction DR3 may correspond to the X axis direction and the Y axis direction, respectively. The second region AR2' initially passed through the gate layer 161 may extend from the first region AR1' in the second direction DR2. Each of the seed region 161A and the epitaxial region 161B initially passed through the gate layer 161 may be formed in the first region AR1' and the second region AR2' initially passed through the gate layer 161. The rear surface of the gate layer 161 initially passed through may be defined as the rear surface of the seed region 161A. The insertion insulating layer 163 may be disposed in contact with the epitaxial region 161B.

[0091] Subsequently, a first mask pattern 101 may be formed on the insertion insulating layer 163. The first mask pattern 101 may include a plurality of first mask portions 101A and a plurality of second mask portions 101B. The plurality of first mask portions 101A may overlap with the first region AR1' initially passing through the gate layer 161, and may be spaced apart from each other in the third direction DR3, wherein the groove-type openings 101T are interposed between the plurality of first mask portions 101A. Each first mask portion 101A may have a plurality of hole-type openings 101H. The second mask portion 101B may overlap with the second region AR2' initially passing through the gate layer 161. The groove-type opening 101T may extend between each of the plurality of first mask portions 101A and the second mask portion 101B.

[0092] Reference Figure 7B , you can Fig. 7A The illustrated mask pattern 101 is used as an etching process of an etching barrier to etch the insertion insulating layer 163 and the initial passing gate layer 161. A trench 160T and a plurality of active holes 160H may be defined in a region in which the insertion insulating layer 163 and the initial passing gate layer 161 are etched.

[0093] The insertion insulating layer 163 may be separated into a plurality of first insertion portions 163A and a second insertion portion 163B by an etching process of the insertion insulating layer 163. The plurality of first insertion portions 163A and the second insertion portions 163B may be separated from each other by the trench 160T. Each of the first insertion portions 163A may be penetrated by a plurality of active holes 160H.

[0094] Through the etching process of initially passing through the gate layer 161, a portion of the boundary between the first region AR1' and the second region AR2' initially passing through the gate layer 161 may be etched, and a portion of the first region AR1' initially passing through the gate layer 161 may be etched. Fig. 7A The epitaxial region 161B of the initial through gate layer 161 shown may be separated into a plurality of through gates 161PG and a semiconductor pattern 161S. The plurality of through gates 161PG and the semiconductor pattern 161S may be spaced apart from each other by the trench 160T. Each through gate 161PG may be penetrated by a plurality of active holes 160H. The plurality of through gates 161PG and the semiconductor pattern 161S may be connected to the seed region 161A of the initial through gate layer 161. The seed region 161A of the initial through gate layer 161 may be exposed by the trench 160T and the plurality of active holes 160H.

[0095] The plurality of first insertion portions 163A of the insertion insulating layer 163 and the plurality of pass gates 161PG of the initial pass gate layer 161 may be defined at the same Fig. 7A The second insertion portion 163B of the insulating layer 163 and the semiconductor pattern 161S initially passing through the gate layer 161 may be defined in a region corresponding to the plurality of first mask portions 101A of the first mask pattern 101 shown. Fig. 7A The first mask pattern 101 is shown in a region corresponding to the second mask portion 101B.

[0096] The trench 160T and the plurality of active holes 160H may be formed by passing through Fig. 7A The trench 160T may be defined by an intervening insulating layer 163 and an epitaxial region 161B initially formed by the gate layer 161. Fig. 7A In the region corresponding to the trench-type opening 101T of the first mask pattern 101 shown, a plurality of active holes 160H may be defined in the region corresponding to the trench-type opening 101T of the first mask pattern 101. Fig. 7A In the region corresponding to the plurality of hole-shaped openings 101H of the first mask pattern 101 shown in FIG. 1 , the plurality of active holes 160H may be removed after the trenches 160T and the plurality of active holes 160H are formed. Fig. 7A The mask pattern 101 is shown.

[0097] Reference Figure 7C , along the Figure 7B After forming an insulating layer on the surface of each of the trench 160T and the plurality of active holes 160H, a channel layer may be formed on the insulating layer. Subsequently, a filling layer may be formed on the channel layer. Figure 7BThe gap of the central region of each of the trench 160T and the plurality of active holes 160H shown is filled with an insulating layer and a doped semiconductor layer. Thereafter, a planarization process such as chemical mechanical polishing may be performed so that the inserted insulating layer 163 is exposed. The insulating layer may be formed by depositing an insulating material such as a silicon oxide layer or by using an oxidation process. The channel layer may include a semiconductor material such as silicon or germanium. The doped semiconductor layer may include at least one of a p-type impurity and an n-type impurity. As an embodiment, the doped semiconductor layer may be formed by an n-type doped silicon layer including an n-type impurity as a majority carrier.

[0098] Through the above series of processes, Figure 7B Each of the plurality of active holes 160H shown has an active pillar 167P formed therein and surrounded by a gate insulating layer 165A, and can be formed in Figure 7B A partition wall structure 167PT surrounded by a partition wall insulating layer 165B is formed inside the trench 160T shown.

[0099] Figure 8 Shown along Figure 7C The cross section of the active pillar 167P and the partition wall structure 167PT is taken along line II′.

[0100] Reference Figure 7C and Figure 8 , you can refer to Figure 7C The described series of processes separates the insulating layer into the gate insulating layer 165A and the partition wall insulating layer 165B, and can be referred to by Figure 7C The described series of processes separates the channel layer into the first channel layer 167A of the active pillar 167P and the partition wall channel layer 167A' of the partition wall structure 167PT. In addition, the gap filling insulating layer can be separated into a first core insulating layer 168A surrounded by the first channel layer 167A and a partition wall core insulating layer 168B surrounded by the partition wall channel layer 167A' of the partition wall structure 167PT, and the doped semiconductor layer can be separated into a first covering pattern 167B of the active pillar 167P and a partition wall covering pattern 167B' of the partition wall structure 167PT.

[0101] The gate insulating layer 165A may extend along the surface of the active hole 160H. The active pillar 167P may be formed inside the active hole 160H opened by the gate insulating layer 165A. The active pillar 167P may include a first channel layer 167A and a first capping pattern 167B. The first capping pattern 167B may serve as a first junction 167J1 of the active pillar 167P. The first core insulating layer 168A and the first capping pattern 167B may be formed inside the active hole 160H opened by the first channel layer 167A.

[0102] The partition wall insulating layer 165B may extend along the surface of the trench 160T. The partition wall structure 167PT may be formed inside the trench 160T opened by the partition wall insulating layer 165B. The partition wall structure 167PT may include a partition wall channel layer 167A' and a partition wall capping pattern 167B'. The partition wall core insulating layer 168B and the partition wall capping pattern 167B' may be formed inside the trench 160T opened by the partition wall channel layer 167A'.

[0103] According to an embodiment of the present disclosure, the channel length of the pass transistor may be variously formed by controlling the depth of the active hole 160H. In addition, the channel width of the pass transistor may be variously formed by controlling the inner diameter of the active hole 160H.

[0104] 9A to 9D is shown in reference Figure 7C and Figure 8 Cross-sectional views of embodiments of subsequent processes following the described process.

[0105] Reference Fig. 9A The initial stack 170 may be formed over the initial pass gate layer 161 including the active pillars 167P and the partition wall structures 167PT. The initial stack 170 may be formed by alternately stacking a plurality of first material layers 171 and a plurality of second material layers 173 over the insertion insulating layer 163 in the fourth direction DR4.

[0106] The plurality of second material layers 173 may be formed of a material having an etching selectivity with respect to the plurality of first material layers 171. As an embodiment, the plurality of first material layers 171 may include an insulating material such as a silicon oxide layer and a silicon oxynitride layer, and the plurality of second material layers 173 may include a sacrificial insulating material such as a silicon nitride layer.

[0107] Subsequently, the second region AR2' of the initial through gate layer 161 may be exposed by etching a portion of each of the plurality of first material layers 171, the plurality of second material layers 173, and the first insertion portion 163A of the insertion insulating layer 163 overlapping the second region AR2' of the initial through gate layer 161. Thereafter, the second region AR2' of the initial through gate layer 161 may be etched. At this time, a portion of the semiconductor pattern 161S may be etched in the second region AR2' of the initial through gate layer 161. Thus, a plurality of channel holes 175 may be formed. Each channel hole 175 may pass through the initial stack 170 and extend into the semiconductor pattern 161S disposed in the second region AR2' of the initial through gate layer 161.

[0108] Thereafter, a memory layer 177 may be formed along the surface of each channel hole 175. Figures 3 to 5As described above, the memory layer 177 may include a blocking insulating layer, a data storage layer, and a tunnel insulating layer. Subsequently, a channel pillar 179 may be formed in the channel hole 175 opened by the memory layer 177 .

[0109] As an embodiment, forming the channel pillar 179 may include forming a second channel layer 179A by depositing a semiconductor material such as silicon or germanium on a surface of the memory layer 177, forming a second core insulating layer 181 in the channel hole 175 opened by the second channel layer 179A, opening a portion of the channel hole 175 by removing a portion of the second core insulating layer 181, and filling a portion of the opened channel hole 175 with a second capping pattern 179B. The second capping pattern 179B may include a doped semiconductor material.

[0110] Reference Fig. 9B , a buffer insulating layer 185 may be formed on the initial stack 170. The buffer insulating layer 185 may include an oxide such as a silicon oxide layer. Thereafter, an etching process for forming the stepped structure 170ST may be performed. Forming the stepped structure 170ST may include forming a mask layer (not shown) on the buffer insulating layer 185 and etching portions of the buffer insulating layer 185, the plurality of first material layers 171, and the plurality of second material layers 173 by an etching process using the mask layer as an etching barrier. At this time, portions of the buffer insulating layer 185, the plurality of first material layers 171, and the plurality of second material layers 173 may be portions overlapping with the first region AR1' initially passed through the gate layer 161. Etching portions of the plurality of first material layers 171 and the plurality of second material layers 173 may include a trimming process for reducing the size of the mask layer and an etching process for the exposed regions of the plurality of first material layers 171 and the plurality of second material layers 173. The trimming process and the etching process may be repeated until a plurality of pad portions 170P are formed. The mask layer may be removed after forming the stepped structure 170ST.

[0111] A plurality of pad portions 170P may be arranged at different heights and overlap with a plurality of active pillars 161P, respectively. Each of the plurality of pad portions 170P may be configured by a pair of corresponding first material layers 171 and corresponding second material layers 173. The plurality of pad portions 170P may correspond to a plurality of steps of the stepped structure 170ST forming the initial stack 170. Each of the plurality of pad portions 170P may be configured by a plurality of end portions of the plurality of second material layers 173 forming the stepped structure 170ST.

[0112] Reference Fig. 9C, a plurality of first recess regions 173R1 may be formed by etching a plurality of ends of a plurality of second material layers 173 from the edge of the stepped structure 170ST in the preliminary stack 170. The plurality of first recess regions 173R1 may be defined between a plurality of first material layers 171 adjacent in the fourth direction DR4.

[0113] Reference Fig.9D , can be filled with multiple third material layers 187 Fig. 9C The plurality of first recessed regions 173R1 are shown. The plurality of third material layers 187 may include a material having an etching selectivity relative to the plurality of first material layers 171 and the plurality of second material layers 173. As an embodiment, the process of forming the plurality of third material layers 187 may include forming a silicon layer to fill Fig. 9C A plurality of first recessed regions 173R1 are shown, and a portion of the silicon layer is removed using an etching process such as etch-back, so that the silicon layer is separated into a plurality of third material layers 187 .

[0114] Fig. 10A and Fig. 10B is shown in reference Fig.9D Cross-sectional views of embodiments of subsequent processes following the described process.

[0115] Reference Fig. 10A A filling insulating layer 189 may be formed to cover the plurality of third material layers 187 and the reference Fig. 9B A plurality of pad parts 170P are depicted. The filling insulating layer 189 may include an oxide such as a silicon oxide layer.

[0116] Subsequently, a portion of each of the filling insulation layer 189, the plurality of first material layers 171, the plurality of second material layers 173, and the plurality of third material layers 187 overlapping the plurality of active pillars 167P may be etched. Thus, a plurality of contact holes 191 may be formed to expose the plurality of active pillars 167P, respectively.

[0117] Reference Fig. 10B , a portion of each of the plurality of second material layers 173 may be etched through the plurality of contact holes 191. Thus, a plurality of second recess regions 173R2 may be defined. Each of the plurality of second recess regions 173R2 may be defined between the first material layers 171 adjacent in the fourth direction DR4.

[0118] Fig.11A and Fig. 11B is shown in reference Fig. 10B Perspective and cross-sectional views of embodiments of subsequent processes following the described process. Fig.11A is a perspective view showing the filling insulating layer 189 to facilitate identification of the stepped structure, and Fig. 11B It is along Fig.11A A cross-sectional view taken along line II' is shown.

[0119] Reference Fig.11A and Fig. 11B , a spacer layer 193 may be formed inside each of the plurality of contact holes 191 to fill the plurality of second recess regions 173R2. The spacer layer 193 may include an insulating material having an etching selectivity with respect to the plurality of second material layers 173 and the plurality of third material layers 187. As an embodiment, the spacer layer 193 may include an oxide such as a silicon oxide layer.

[0120] The spacer layer 193 may extend along a surface of each of the plurality of contact holes 191. A central region of each of the plurality of contact holes 191 may be opened without being filled with the spacer layer 193.

[0121] Thereafter, a central region of each of the plurality of contact holes 191 opened by the spacer layer 193 may be filled with a fourth material layer 195. The fourth material layer 195 may include a material having an etching selectivity with respect to the spacer layer 193. As an embodiment, the fourth material layer 195 may include silicon. The spacer layer 193 may be interposed between each third material layer 187 and the fourth material layer 195 corresponding thereto.

[0122] Subsequently, the buffer insulating layer 185, the filling insulating layer 189, the plurality of first material layers 171, the plurality of second material layers 173, and the plurality of third material layers 187 may be etched to form slits 197. The slits 197 may extend in the second direction DR2. The side surfaces of each of the plurality of second material layers 173 and the plurality of third material layers 187 may be exposed through the slits 197.

[0123] FIG. 12A to FIG. 12K It is shown in the formation Fig.11A A cross-sectional view of an embodiment of subsequent processing after the slit 197 is shown.

[0124] Reference Fig. 12A , Fig.11A and Fig. 11B The plurality of second material layers 173 and the plurality of third material layers 187 shown may be Fig.11A The slits 197 shown are replaced with a plurality of conductive patterns 199. More specifically, the Fig.11A The slits 197 are shown to selectively remove Fig.11A and Fig. 11B The plurality of second material layers 173 and the plurality of third material layers 187 are shown. At this time, even if the fourth material layer 195 is Fig. 11BThe third material layer 187 shown is formed of the same material, and the fourth material layer 195 may also be protected by the spacer layer 193 and may serve as a support. Subsequently, a conductive material may be formed in the region where the plurality of second material layers 173 and the plurality of third material layers 187 are removed. Thereafter, the Fig.11A 197, so that the conductive material is separated into a plurality of conductive patterns 199. Although not shown in the figure, before forming the conductive material, a metal oxide layer such as an aluminum oxide layer may be formed along the surface of the region where the plurality of second material layers 173 and the plurality of third material layers 187 are removed.

[0125] As described above, the gate stack 170G may be defined by replacing the plurality of second material layers 173 and the plurality of third material layers 187 with the plurality of conductive patterns 199. In addition, the memory cell array 100 including the gate stack 170G, the memory layer 177, and the channel pillar 179 may be formed.

[0126] The gate stack 170G may include a plurality of first material layers 171 and a plurality of conductive patterns 199. Each of the plurality of first material layers 171 may be used as an interlayer insulating layer. Each of the plurality of first material layers 171 and the plurality of conductive patterns 199 of the gate stack 170G may overlap with the second region AR2' initially passing through the gate layer 161, and may be penetrated by the memory layer 177 and the channel pillar 179. The plurality of conductive patterns 199 of the gate stack 170G may be spaced apart from each other by the plurality of first material layers 171. The plurality of conductive patterns 199 may include a plurality of end portions 199EG respectively overlapping with the plurality of active pillars 167P. The plurality of end portions 199EG of the plurality of conductive patterns 199 may form a stepped structure. Each of the plurality of end portions 199EG of the plurality of conductive patterns 199 may be spaced apart from the fourth material layer 195 by the spacer layer 193 corresponding thereto.

[0127] Although not shown in the figure, after forming the memory cell array 100, Fig.11A The vertical structures are shown formed inside the slots 197. The vertical structures may include insulating materials or may include insulating materials and conductive materials.

[0128] Reference Fig. 12B , can be achieved by Fig. 12A The fourth material layer 195 and the spacer layer 193 are etched to open a plurality of contact holes 191. Although not shown in the figure, when a metal oxide layer is additionally formed before forming a plurality of conductive patterns 199, the metal oxide layer can be formed by Fig. 12A The etching process of the spacer layer 193 is shown to expose a portion of the metal oxide layer, and the exposed portion of the metal oxide layer may be additionally etched.

[0129] According to the above process, the plurality of end portions 199EG of the plurality of conductive patterns 199 may be exposed through the plurality of contact holes 191. The exposed region of each of the plurality of end portions 199EG of the plurality of conductive patterns 199 may form a reference Figure 6B Described is the first inner side wall IW1.

[0130] Can be controlled Fig. 12A The etching process of the spacer layer 193 shown in FIG. 1 is performed so that a portion of the spacer layer remains as an insulating spacer 193S. The insulating spacer 193S may be disposed at Fig. 12A Each of the second recessed regions 173R2 shown can be controlled Fig. 12A The etching process of the spacer layer 193 is shown so that the plurality of active pillars 167P are respectively exposed through the plurality of contact holes 191 . At this time, the first junction 167J1 of the active pillar 167P corresponding to each contact hole 191 may be exposed through each contact hole 191 .

[0131] Reference Fig. 12C , can be achieved by filling the Fig. 12B The plurality of contact holes 191 shown are used to form a plurality of gate contact plugs 201. Each gate contact plug 201 can contact an exposed region of an end portion 199EG of a corresponding conductive pattern 199. Each gate contact plug 201 can contact a first junction 167J1 of an active pillar 167P corresponding thereto. Therefore, the plurality of gate contact plugs 201 can connect the plurality of conductive patterns 199 of the memory cell array 100 to the plurality of active pillars 167P.

[0132] Thereafter, a bit line contact 203 , a bit line 207 , a first conductive bonding contact 213 , and a first conductive bonding pattern 215 may be formed on the memory cell array 100 .

[0133] As an embodiment, the bit line contact 203 may be formed in the buffer insulating layer 185. The bit line contact 203 may pass through the buffer insulating layer 185 to contact the channel pillar 179 of the memory cell array 100. Afterwards, the insulating layer 205 may be formed to cover the bit line contact 203, the plurality of gate contact plugs 201, the buffer insulating layer 185, and the filling insulating layer 189. Subsequently, a bit line 207 may be formed in the insulating layer 205. The bit line 207 may pass through the insulating layer 205 to contact the bit line contact 203. Subsequently, a first insulating structure 211 in which a first conductive bonding contact 213 and a first conductive bonding pattern 215 are buried may be formed.

[0134] Reference Fig.12D , you can set and reference Figure 3 The structure 220 corresponding to the second structure ST2 described above. Figure 3 The structure 220 described above may include a semiconductor layer 221 , a peripheral circuit structure 223 , a plurality of interconnections 225 , a plurality of second conductive bonding contacts 227 , and a plurality of second conductive bonding patterns 229 .

[0135] Subsequently, a bonding process may be performed such that the plurality of second conductive bonding patterns 229 of the structure 220 are connected to the plurality of first conductive bonding patterns 215 .

[0136] Reference Fig.12E , can be obtained from Fig.12D The initial removal of the back surface 161BS of the gate layer 161 is shown Fig.12D The seed region 161A of the gate layer 161 is initially shown. At this point, the selective etching can be performed by a wet etching process. Fig.12D The initial pass through seed region 161A of the gate layer 161 is shown.

[0137] When to remove Fig.12D When the seed region 161A of the initial through gate layer 161 is shown, the initial through gate layer 161' with a reduced thickness may be retained. In addition, the through gate insulating layer 165A and the partition wall insulating layer 165B may be exposed. The initial through gate layer 161' with a reduced thickness may be separated into a semiconductor pattern 161S and a through gate 161PG, wherein a partition wall structure 167PT is interposed between the semiconductor pattern 161S and the through gate 161PG. The through gate 161PG may be configured as a portion of the initial through gate layer 161' retained in the first region AR1', and may surround a plurality of active pillars 167P. The semiconductor pattern 161S may be configured as a portion of the initial through gate layer 161' retained in the second region AR2'.

[0138] Reference Fig.12F , a first upper insulating layer 301 may be formed over the initial through gate layer 161'. Subsequently, a second mask pattern 302 may be formed over the first upper insulating layer 301. The second mask pattern 302 may overlap with the plurality of active pillars 167P and the through gate 161PG, and may not overlap with the second region AR2' of the initial through gate layer 161'. Thereafter, the second region AR2' of the initial through gate layer 161' may be exposed by etching a portion of the first upper insulating layer 301 through an etching process using the second mask pattern 302 as an etching barrier.

[0139] Afterwards, you can Fig.12F The first gate layer 161' is initially etched through a portion of the second region AR2' exposed by the first upper insulating layer 301. Figure 12GAs shown, the second insertion portion 163B of the insertion insulating layer 163 may be exposed, and as shown in FIG. Figure 12G As shown by the dotted line, a portion of the memory layer 177 may be exposed. Thereafter, the second mask pattern 302 may be removed. The first region AR1' of the initial through gate layer 161' may remain as the through gate 161PG, and a portion of the second region AR2' of the initial through gate layer 161' adjacent to the partition wall structure 167PT may remain as the semiconductor pattern 161S.

[0140] Reference Figure 12G , a portion of the memory layer 177 indicated by a dotted line may be removed. Thus, a portion of the channel pillar 179 may be exposed.

[0141] Reference Fig.12H , a doped semiconductor layer 303 connected to the channel pillar 179 may be formed. The doped semiconductor layer 303 may include at least one of n-type impurities and p-type impurities. As an embodiment, the doped semiconductor layer 303 may include n-type impurities as majority carriers.

[0142] The doped semiconductor layer 303 may be formed on a Fig.12F and Figure 12G The doped semiconductor layer 303 may overlap the sidewall of the through gate 161PG. In addition, the doped semiconductor layer 303 may be spaced apart from the semiconductor pattern 161S in the second direction DR2.

[0143] The doped semiconductor layer 303 may be formed over the second insertion portion 163B of the insertion insulating layer 163 to cover the exposed region of the channel pillar 179 . The doped semiconductor layer 303 may be in contact with the exposed region of the channel pillar 179 .

[0144] Reference Fig.12I , a second upper insulating layer 305 may be formed to cover the doped semiconductor layer 303 and the first upper insulating layer 301 . The second upper insulating layer 305 may fill a region between the semiconductor pattern 161S and the doped semiconductor layer 303 .

[0145] Reference Fig.12J , a third mask pattern 351 may be formed over the first upper insulating layer 301 and the second upper insulating layer 305. The third mask pattern 351 may include a plurality of openings 351OP1 and 351OP2. The plurality of openings 351OP1 and 351OP2 may include a plurality of first openings 351OP1 and second openings 351OP2. The plurality of first openings 351OP1 may overlap with the plurality of active pillars 167P, respectively. The second openings 351OP2 may overlap with the doped semiconductor layer 303.

[0146] Subsequently, a portion of each of the first upper insulating layer 301, the second upper insulating layer 305, and the through gate insulating layer 165A may be etched by an etching process using the third mask pattern 351 as an etching barrier. Thus, a plurality of upper holes 300H1 and 300H2 may be formed. The plurality of upper holes 300H1 and 300H2 may include a plurality of first upper holes 300H1 and a second upper hole 300H2. The plurality of first upper holes 300H1 may expose each of the plurality of active pillars 167P by passing through the first upper insulating layer 301, the second upper insulating layer 305, and the through gate insulating layer 165A. The second upper hole 300H2 may expose the doped semiconductor layer 303 by passing through the second upper insulating layer 305.

[0147] Subsequently, a second junction 167J2 may be formed by implanting at least one of n-type impurities and p-type impurities into a portion of the plurality of active pillars 167P through the plurality of first upper holes 300H1. A region between the first junction 167J1 and the second junction 167J2 may be used as a channel region in each active pillar 167P.

[0148] Thereafter, the mask pattern 351 may be removed.

[0149] Reference Figure 12K , a plurality of contacts 311A ​​and 311B may be formed by filling the plurality of upper holes 300H1 and 300H2 with a conductive material. The plurality of contacts 311A ​​and 311B may include a plurality of first contacts 311A ​​and second contacts 311B.

[0150] The plurality of first contact members 311A ​​may be respectively arranged at Fig.12J Each first contact 311A ​​may contact the second junction 167J2 of the active pillar 167P corresponding thereto. The second contact 311B may be disposed at Fig.12J The second upper hole 300H2 is shown inside and may contact the doped semiconductor layer 303 .

[0151] Afterwards, the formation can be performed Figure 3 1 and 2 , and a subsequent process of the plurality of upper lines UL1 and UL2 shown in FIG.

[0152] Fig.13 is a block diagram showing an electronic system 1000 including a semiconductor memory device 1220 according to an embodiment of the present disclosure.

[0153] Reference Fig.13 The electronic system 1000 may be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 may include a host 1100 and a storage device 1200 .

[0154] The host 1100 may store data in the storage device 1200 or read data stored in the storage device 1200 based on an interface. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a PCI-express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial-ATA interface, a parallel-ATA interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE) interface, a FireWire interface, a universal flash memory (UFS) interface, and a non-volatile memory express (NVMe) interface.

[0155] The storage device 1200 may include a memory controller 1210 and a semiconductor memory device 1220. As an embodiment, the storage device 1200 may be a storage medium such as a solid state drive (SSD) or a USB memory.

[0156] The memory controller 1210 may store data in the semiconductor memory device 1220 or read data stored in the semiconductor memory device 1220 under the control of the host 1100 .

[0157] The semiconductor memory device 1220 may include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data under the control of the memory controller 1210.

[0158] The semiconductor memory device 1220 may be a non-volatile memory device. Figure 3 As described above, the semiconductor memory device 1220 may include a through gate and a doped semiconductor layer overlapping a gate stack.

[0159] According to an embodiment of the present disclosure, the gate electrode may overlap a portion of the gate stack, and the doped semiconductor layer may overlap another portion of the gate stack, thereby improving the integration of the semiconductor memory device.

[0160] CROSS-REFERENCE TO RELATED APPLICATIONS

[0161] This application claims the priority of Korean Patent Application No. 10-2023-0094774 filed in the Korean Intellectual Property Office on July 20, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a gate stack including a plurality of conductive patterns spaced apart from each other in a first direction and stacked in the first direction, the gate stack including a contact region and a cell array region extending from the contact region in a second direction intersecting the first direction; a through gate that overlaps the contact region of the gate stack and opens the cell array region of the gate stack; a doped semiconductor layer, the doped semiconductor layer being spaced apart from the pass gate in the second direction and overlapping the cell array region of the gate stack; as well as A plurality of active pillars are provided, and the plurality of active pillars pass through the passing gate.

2. The semiconductor memory device according to claim 1, wherein The side surface of the through gate includes a region overlapping with a side surface of the doped semiconductor layer.

3. The semiconductor memory device according to claim 1, further comprising: a channel pillar including a first portion extending in the first direction and passing through the cell array region of the gate stack, and a second portion extending from the first portion and embedded in the doped semiconductor layer; as well as A memory layer is located between the first portion of the channel pillar and the gate stack.

4. The semiconductor memory device according to claim 3, wherein: The side surface of the through gate includes a region overlapping with the second portion of the channel pillar.

5. The semiconductor memory device according to claim 1, further comprising: A peripheral circuit structure overlaps the pass gate, wherein the gate stack is interposed between the peripheral circuit structure and the pass gate.

6. The semiconductor memory device according to claim 1, further comprising: a plurality of gate contact plugs, the plurality of gate contact plugs passing through the contact region of the gate stack and respectively contacting the plurality of active pillars, Each of the plurality of gate contact plugs includes a contact surface that contacts a corresponding conductive pattern among the plurality of conductive patterns.

7. The semiconductor memory device according to claim 6, further comprising: a plurality of insulating spacers interposed between adjacent gate contact plugs and conductive patterns among the plurality of gate contact plugs and the plurality of conductive patterns, Wherein, the plurality of insulating spacers include: a first insulating spacer adjacent to the contact surface of each of the plurality of gate contact plugs; and A second insulating spacer is spaced apart from the contact surface of each of the plurality of gate contact plugs and is formed in a ring shape to surround a side surface of each of the plurality of gate contact plugs.

8. The semiconductor memory device according to claim 1, further comprising: A through gate insulating layer is disposed between each of the plurality of active pillars and the through gate.

9. The semiconductor memory device according to claim 1, wherein: Each of the plurality of active pillars comprises: a first junction, the first junction facing the gate stack; a second knot facing in a direction opposite to the direction of the first knot; and A channel region is located between the first junction and the second junction.

10. The semiconductor memory device according to claim 1, further comprising: a semiconductor pattern, the semiconductor pattern being disposed between the doped semiconductor layer and the pass gate, the semiconductor pattern overlapping the gate stack; a partition wall structure, the partition wall structure being disposed between the semiconductor pattern and the pass gate; as well as A partition wall insulating layer surrounds a side surface of the partition wall structure.

11. The semiconductor memory device according to claim 10, wherein: The semiconductor pattern includes the same material as the pass gate, and Wherein, the partition wall structure comprises the same material as that of the plurality of active pillars.

12. The semiconductor memory device according to claim 1, wherein: End portions of the plurality of conductive patterns overlap the plurality of active pillars, respectively, and form a stepped structure in the contact region of the gate stack.

13. A semiconductor memory device, comprising: A peripheral circuit structure, the peripheral circuit structure comprising a first region and a second region; a pass gate spaced apart from the peripheral circuit structure in a first direction and overlapping the first region of the peripheral circuit structure; a doped semiconductor layer, the doped semiconductor layer being spaced apart from the peripheral circuit structure in the first direction and being spaced apart from the pass gate in a second direction intersecting the first direction; a gate stack including a contact region between the peripheral circuit structure and the pass gate and a cell array region extending from the contact region to a region between the peripheral circuit structure and the doped semiconductor layer; an active pillar, the active pillar passing through the through gate; a through gate insulating layer, wherein the through gate insulating layer is located between the through gate and the active pillar; a channel pillar, the channel pillar being in contact with the doped semiconductor layer and passing through the cell array region of the gate stack; a memory layer, the memory layer being located between the channel pillar and the gate stack; as well as A gate contact plug is connected to the active pillar and passes through the contact region of the gate stack.

14. The semiconductor memory device according to claim 13, wherein: The gate stack includes a plurality of conductive patterns spaced apart from each other in the first direction and stacked in the first direction, and The plurality of conductive patterns include a first conductive pattern in contact with the gate contact plug and a second conductive pattern insulated from the gate contact plug.

15. The semiconductor memory device according to claim 14, further comprising: a first insulating spacer interposed between the gate contact plug and the first conductive pattern and opening a contact surface between the gate contact plug and the first conductive pattern; as well as A second insulating spacer is interposed between the gate contact plug and the second conductive pattern and is formed in a ring shape to surround a side surface of the gate contact plug.

16. The semiconductor memory device according to claim 13, wherein: The active column comprises: a first junction, the first junction being in contact with the gate contact plug; a second knot facing in a direction opposite to the direction of the first knot; and A channel region is located between the first junction and the second junction.

17. The semiconductor memory device according to claim 13, further comprising: at least one upper insulating layer, the at least one upper insulating layer covering the through gate and the doped semiconductor layer; a global line and a common source line, the global line and the common source line being located above the at least one upper insulating layer; a first contact passing through the at least one upper insulating layer to connect the active pillar to the global line; as well as A second contact passes through the at least one upper insulating layer to connect the doped semiconductor layer to the common source line.

18. The semiconductor memory device according to claim 13, further comprising: an insertion insulating layer, the insertion insulating layer comprising a first insertion portion between the gate stack and the pass gate and a second insertion portion between the gate stack and the doped semiconductor layer, Wherein, the active pillar and the channel pillar extend to pass through the insertion insulating layer.

19. The semiconductor memory device according to claim 13, further comprising: a semiconductor pattern, the semiconductor pattern being disposed between the doped semiconductor layer and the pass gate, the semiconductor pattern overlapping the gate stack; a partition wall structure, the partition wall structure being disposed between the semiconductor pattern and the pass gate; as well as A partition wall insulating layer surrounds a side surface of the partition wall structure.

20. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming an active pillar surrounded by a through gate insulating layer in an initial through gate layer, wherein the initial through gate layer includes a first region and a second region, and wherein the active pillar is formed in the first region of the initial through gate layer; forming a memory cell array over the initial through gate layer including the active pillars; forming a first conductive bonding pattern over the memory cell array; forming a structure including a peripheral circuit structure and a second conductive bonding pattern; performing a bonding process so that the first conductive bonding pattern and the second conductive bonding pattern are connected; etching the second region of the initial through gate layer so that the first region of the initial through gate layer remains as a through gate surrounding the active pillar; and A doped semiconductor layer is formed in the region initially etched through the second region of the gate layer.

21. The method according to claim 20, wherein: The step of forming the active pillar surrounded by the gate insulating layer comprises the following steps: forming an insertion insulating layer above the initial pass gate layer; forming an active hole by etching the insertion insulating layer and the first region of the initial through gate layer; forming the through gate insulating layer on the surface of the active hole; and The active pillar is formed inside the active hole opened by the gate insulating layer.

22. The method according to claim 21, further comprising the steps of: forming a trench by etching a portion of the initial passing gate layer at a boundary of the first region and the second region of the initial passing gate layer by using a process for forming the active hole; forming a partition wall insulating layer on the surface of the trench by using the process of forming the through gate insulating layer; as well as A partition wall structure is formed in the trench opened by the partition wall insulating layer by utilizing a process of forming the active pillar.

23. The method according to claim 22, wherein: A portion of the second region of the initial passing gate layer is retained as a semiconductor pattern between the passing gate and the doped semiconductor layer, wherein the partition wall structure is interposed between the semiconductor pattern and the passing gate.

24. The method according to claim 20, wherein: The step of forming the memory cell array comprises the following steps: Alternatingly stacking a plurality of first material layers and a plurality of second material layers over the initial pass gate layer including the active pillar; forming a channel hole by etching the plurality of first material layers, the plurality of second material layers, and the second region of the initial through gate layer; forming a memory layer along a surface of the channel hole; forming a channel pillar in the channel hole opened by the memory layer; Forming a stepped structure having a plurality of pad portions disposed at different heights by etching the plurality of first material layers and the plurality of second material layers overlapping the first region of the initial through gate layer; replacing a plurality of end portions of the plurality of second material layers corresponding to the plurality of pad portions with a plurality of third material layers; forming a filling insulating layer to cover the plurality of third material layers and the plurality of pad portions; Forming slits by etching the plurality of first material layers, the plurality of second material layers, and the plurality of third material layers so that a side surface of each of the plurality of second material layers and a side surface of each of the plurality of third material layers are exposed; and The plurality of second material layers and the plurality of third material layers are replaced with a plurality of conductive patterns through the slits.

25. The method according to claim 24, further comprising the steps of: forming a contact hole exposing the active pillar by etching at least one of the filling insulating layer, the plurality of first material layers, the plurality of second material layers, and the plurality of third material layers; forming a recess region by etching at least one second material layer exposed through the contact hole among the plurality of second material layers; forming a spacer layer filling the recessed region and extending along a surface of the contact hole; filling the contact hole opened by the spacer layer with a fourth material layer; opening the contact hole by etching the fourth material layer and the spacer layer so that one conductive pattern among the plurality of conductive patterns is exposed through the contact hole; as well as A gate contact plug is formed inside the opened contact hole.

26. The method according to claim 25, wherein: An etching process of the spacer layer is controlled such that a portion of the spacer layer remains as an insulating spacer in the recess region.

27. The method according to claim 24, further comprising the steps of: etching a portion of the initial passing gate layer from a rear surface of the initial passing gate layer facing a direction opposite to a direction facing the memory cell array so that a thickness of the initial passing gate layer is reduced; as well as forming a first upper insulating layer over the initial through gate layer having a reduced thickness, wherein the second region of the initial through gate layer is opened by the first upper insulating layer, When etching is performed on the second region initially passing through the gate layer, a portion of the memory layer opened by the first upper insulating layer is exposed.

28. The method according to claim 27, further comprising the steps of: Before forming the doped semiconductor layer, a portion of the channel pillar is exposed by removing an exposed portion of the memory layer.

29. The method according to claim 28, further comprising the steps of: forming a second upper insulating layer to cover the first upper insulating layer and the doped semiconductor layer; as well as A first contact and a second contact are formed by penetrating at least one of the first upper insulating layer and the second upper insulating layer, the first contact being connected to the active pillar and the second contact being connected to the doped semiconductor layer.

30. The method of claim 20, wherein: The memory cell array includes a plurality of conductive patterns spaced apart from each other and stacked over the initial pass gate layer, wherein the plurality of conductive patterns include a first conductive pattern having an end portion overlapping the active pillar, and The end of the first conductive pattern is penetrated by a contact hole that exposes the active pillar.

31. The method according to claim 30, further comprising the steps of: forming a gate contact plug inside the contact hole, The gate contact plug connects the first conductive pattern to the active pillar.

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