Semiconductor device and data storage system including same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device may include a first semiconductor structure including a substrate, an active region in the substrate, a device isolation region defining the active region, and a capacitor structure on and vertically overlapping the device isolation region. The capacitor structure may include a first electrode structure extending in a first direction and including first capacitor electrodes stacked in the first direction, a second electrode structure including second capacitor electrodes stacked in the first direction, and a first insulating structure extending in the first direction. The first insulating structure is located between the first electrode structure and the second electrode structure. The first and second capacitor electrodes are alternately arranged and spaced apart from each other in a second direction parallel to the upper surface of the substrate, extend in a third direction perpendicular to the first and second directions, and each have a plate shape.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0095010 filed on July 21, 2023, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Aspects of the present disclosure relate to a semiconductor device, and to a data storage system including the semiconductor device. Background Art

[0003] Semiconductor devices capable of storing large amounts of data in data storage systems requiring data storage are increasingly desired. Therefore, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, a method for increasing the data storage capacity of a semiconductor device has been proposed, in which the semiconductor device includes three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the invention

[0004] Some embodiments of the present disclosure provide semiconductor devices that can be easily manufactured and have improved electrical properties and reliability.

[0005] Some embodiments of the present disclosure provide data storage systems including semiconductor devices with improved electrical properties and reliability that can be easily manufactured.

[0006] According to some embodiments of the present disclosure, a semiconductor device may include: a first semiconductor structure including a substrate, an active region, a circuit device, a device isolation region, an impurity region, a circuit interconnection structure, and a capacitor structure, wherein the active region is located in the substrate, the circuit device is located on the substrate, the device isolation region defines the active region, the impurity region is located in the active region on a first side and a second side of the circuit device, the circuit interconnection structure is electrically connected to the circuit device, and the capacitor structure is located on the device isolation region and vertically overlapped with the device isolation region; and a second semiconductor structure including a plate layer, a gate electrode, a channel structure, and an upper interconnection structure, wherein the plate layer is located on the first semiconductor structure, the gate electrodes are stacked on the plate layer along a first direction perpendicular to an upper surface of the plate layer and are spaced apart from each other and And are stacked in sequence, the channel structure extends through the gate electrode in a first direction, and the upper interconnect structure is electrically connected to the channel structure, wherein the capacitor structure includes a first electrode structure, a second electrode structure and a first insulating structure, the first electrode structure extends in the first direction and includes a first capacitor electrode stacked in the first direction, the second electrode structure includes a second capacitor electrode stacked in the first direction, and the first insulating structure is located between the first electrode structure and the second electrode structure, wherein the first capacitor electrode and the second capacitor electrode are alternately arranged and spaced apart from each other in a second direction parallel to the upper surface of the substrate, and extend in a third direction perpendicular to the first direction and the second direction, wherein the first capacitor electrode and the second capacitor electrode both have a plate shape.

[0007] According to some embodiments of the present disclosure, a semiconductor device may include: a substrate including an active region; a circuit device located on the active region; a device isolation region defining the active region; an impurity region located in the active region on a first side and a second side of the circuit device; a first electrode structure located on the device isolation region, vertically overlapping the device isolation region, and extending in a first direction perpendicular to an upper surface of the substrate; a second electrode structure located on the device isolation region, vertically overlapping the device isolation region, and spaced apart from the first electrode structure in a second direction perpendicular to the first direction; and an insulating structure located between the first electrode structure and the second electrode structure, wherein each of the first electrode structure and the second electrode structure extends in a third direction perpendicular to the first direction and the second direction, and has a plate shape.

[0008] According to some embodiments of the present disclosure, a data storage system includes: a semiconductor memory device including a substrate, an active area, a circuit device, a device isolation area, a circuit interconnection structure, a capacitor structure, a memory cell and an input / output pad, wherein the active area is located in the substrate, the circuit device is located on the substrate, the device isolation area defines the active area, the circuit interconnection structure is electrically connected to the circuit device, and the capacitor structure is located on the device isolation area and vertically overlapped with the device isolation area; and a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device, wherein the capacitor structure includes a first electrode structure, a second electrode structure and a first insulating structure, the first electrode structure extends in a first direction perpendicular to an upper surface of the substrate and includes a first capacitor electrode stacked in the first direction, the second electrode structure includes a second capacitor electrode stacked in the first direction, and the first insulating structure is located between the first electrode structure and the second electrode structure, wherein the first capacitor electrode and the second capacitor electrode are spaced apart from each other and alternately arranged in a second direction parallel to the upper surface of the substrate, and extend in a third direction perpendicular to the first direction and the second direction, wherein each of the first capacitor electrode and the second capacitor electrode has a plate shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a semiconductor device according to some embodiments of the present disclosure;

[0011] Figure 2 is a circuit diagram showing a charge pump circuit included in a voltage generator of a semiconductor device according to some embodiments of the present disclosure;

[0012] Figure 3 is a perspective view showing a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 4 is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 5A is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments of the present disclosure;

[0015] Figure 5B is a plan view showing a capacitor structure of a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 5C is a perspective view showing a capacitor structure of a semiconductor device according to some embodiments of the present disclosure;

[0017] Figures 6 to 8 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments of the present disclosure;

[0018] Fig.9A is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments of the present disclosure;

[0019] Fig. 9B is a plan view showing a capacitor structure of a semiconductor device according to some embodiments of the present disclosure;

[0020] Fig.10 and Fig.11 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments of the present disclosure;

[0021] Figures 12 to 15 is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure;

[0022] Fig.16 is a diagram illustrating a data storage system including a semiconductor device according to some embodiments of the present disclosure;

[0023] Fig.17 is a perspective view showing a data storage system including a semiconductor device according to some embodiments of the present disclosure; and

[0024] Fig.18 is a cross-sectional view illustrating a semiconductor package according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0025] Hereinafter, some examples of embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0026] Figure 1 is a block diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0027] Reference Figure 1 , the semiconductor device 100 may include a memory cell array 20 and a peripheral circuit 30. The semiconductor device 100 may be implemented as a memory device, for example, implemented as or including a nonvolatile memory (such as a flash memory), and / or implemented as or including a volatile memory (such as a dynamic random access memory (DRAM) and / or a static random access memory (SRAM)).

[0028] The memory cell array 20 may include a plurality of memory cells, and the plurality of memory cells may be arranged in rows and columns. The plurality of memory cells may be connected to a row decoder 33 through a plurality of word lines WL, and may be connected to a read / write circuit 35 through a plurality of bit lines BL. In some embodiments, a plurality of memory cells arranged in or along the same row may be connected to the same word line WL, and a plurality of memory cells arranged in or along the same column may be connected to the same bit line BL. In some example embodiments, a plurality of memory blocks may be included, each of which may include a plurality of memory cells.

[0029] The peripheral circuit 30 may be provided from an external entity (not shown) located outside the semiconductor device 100. Figure 1 ) receives an address ADDR, a command CMD, and a control signal CTRL, and may transmit data DATA to an external entity and / or a device (not shown in FIG. 1 ) existing outside the semiconductor device 100. Figure 1 ), and from an external entity and / or a device existing outside the semiconductor device 100 (not shown in Figure 1 The peripheral circuit 30 may include a row decoder 33, a read / write circuit 35, and a control logic 37. The peripheral circuit 30 may include a voltage generator 38. The voltage generator 38 may generate various voltages used in the operation of the semiconductor device 100. In some embodiments, the peripheral circuit 30 may also include Figure 1 Various sub-circuits not shown in the figure, such as an input / output circuit and / or an error correction circuit for correcting errors in the data DATA read from the memory cell array 20.

[0030] The control logic 37 may be connected to the row decoder 33, the voltage generator 38, and the input / output circuit (or referred to as the read / write circuit) 35. The control logic 37 may control and may be configured to control the overall operation of the semiconductor device 100. The control logic 37 may generate various internal control signals used in the semiconductor device 100 in response to the control signal CTRL received from the external entity discussed above. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 37 may adjust the voltage levels provided to the word lines WL and the bit lines BL.

[0031] In response to the address ADDR, the row decoder 33 may select a portion of the plurality of memory cells and may select at least one word line WL. The row decoder 33 may transfer a voltage used when performing a memory operation to the selected word line WL.

[0032] The read / write circuit 35 may be connected to the memory cell array 20 through the bit line BL. The read / write circuit 35 may include a write driver and / or a sense amplifier. Specifically, during a programming operation, the read / write circuit 35 may operate as a write driver and may apply a voltage to the bit line BL according to the data DATA to be stored in the memory cell array 20. During a read operation, the read / write circuit 35 may operate as a sense amplifier and may detect the data DATA stored in the memory cell array 20.

[0033] The voltage generator 38 may include a controller 52 , an oscillator 54 , and a charge pump circuit 56 .

[0034] The charge pump circuit 56 may include a plurality of charge pumps, each of which may include at least one switching device and at least one pumping capacitor. The output voltage of the charge pump circuit 56 may be used for the operation of the semiconductor device 100. For example, using the output voltage of the charge pump circuit 56, the row decoder 33 may input a bias voltage to perform a program operation, an erase operation, and / or a read operation on the word line WL.

[0035] The controller 52 may control the operation of the oscillator 54. For example, based on at least one of the process, voltage, and temperature PVT information of the semiconductor device 100 and based on the target level of the voltage that the charge pump circuit 56 may need to output, the controller 52 may determine the frequency of the clock signal CLK that may be output by the oscillator 54 to the charge pump circuit 56. For example, when the charge pump circuit 56 includes a plurality of charge pumps, the selection of the plurality of charge pumps that are actually operated may be determined by the controller 52.

[0036] The oscillator 54 may output a clock signal CLK that turns on and off at least one switching device included in the charge pump circuit 56. The clock signal CLK output by the oscillator 54 may be determined in response to a control signal VGC from the controller 52. For example, the oscillator 54 may differently determine the frequency and swing range of the clock signal CLK according to the control signal VGC sent by the controller 52.

[0037] Figure 2 is a circuit diagram illustrating a charge pump circuit included in a voltage generator of a semiconductor device according to some example embodiments.

[0038] Reference Figure 2, the charge pump circuit 56a may include a plurality of diodes DI, a plurality of pumping capacitors CP, and an output capacitor COUT. The plurality of diodes DI may be connected in series to each other, and each of the plurality of pumping capacitors CP may be connected to a corresponding node between the plurality of diodes DI. The first diode may receive a power supply voltage VCC having a predetermined level, and the last diode may send an output current IOUT to an output node.

[0039] Each of the plurality of pumping capacitors CP may be charged or discharged by the clock signal CLK or the complementary clock signal CLKB, and the complementary clock signal CLKB may be phase-converted by the inverter INV to have a phase opposite to that of the clock signal CLK. For example, odd-numbered pumping capacitors CP may be charged or discharged by the clock signal CLK, and even-numbered pumping capacitors CP may be charged or discharged by the complementary clock signal CLKB.

[0040] Figure 3 is a perspective view illustrating a semiconductor device according to some example embodiments.

[0041] Reference Figure 3 The semiconductor device 10a may include a peripheral circuit structure PERI and a memory cell structure CELL. The memory cell structure CELL may be disposed on the peripheral circuit structure PERI. The memory cell structure CELL may be disposed on the peripheral circuit structure PERI. Figure 1 In the region of the memory cell array 20, the peripheral circuit structure PERI may be arranged Figure 1 In some example embodiments, the memory cell structure CELL may be optionally below the peripheral circuit structure PERI.

[0042] The memory cell structure CELL may include a first region R1 and a second region R2. The memory cell array 20 may be in the first region R1. The second region R2 may be configured to electrically connect the memory cells of the memory cell array 20 to the peripheral circuit. The second region R2 may be arranged in at least one direction of the first region R1. For example, the second region R2 may be arranged on at least one end of the first region R1 in the X direction.

[0043] form Figure 1 and Figure 2 The plurality of pumping capacitors CP of the charge pump circuits 56 and 56a in the peripheral circuit structure PERI may be in the peripheral circuit structure PERI. For example, the plurality of pumping capacitors CP may be located below the second region R2 of the memory cell structure CELL in the peripheral circuit structure PERI, but the present disclosure is not limited thereto. In some example embodiments, the plurality of pumping capacitors CP may be located below the first region R1 of the memory cell structure CELL in the peripheral circuit structure PERI.

[0044] Figure 4 is a cross-sectional view illustrating a semiconductor device according to some embodiments. Figure 5A is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments, which shows Figure 4 Area "A" in the. Figure 5B is a plan view showing a capacitor structure of a semiconductor device according to some embodiments, which is along Figure 5A The line I-I' is intercepted. Figure 5C is a perspective view illustrating a capacitor structure of a semiconductor device according to some embodiments.

[0045] Reference Figures 4 to 5C The semiconductor device 100 may include a peripheral circuit structure PERI and a memory cell structure CELL. The peripheral circuit structure PERI may be a first semiconductor structure S1 including a substrate 201 , and the memory cell structure CELL may be a second semiconductor structure S2 including a board layer 101 .

[0046] The first semiconductor structure S1 may include a substrate 201 , an impurity region 205 and a device isolation region 209 in the substrate 201 , a circuit device 221 on the substrate 201 , a peripheral region insulating layer 290 , a circuit contact plug 270 , and a circuit interconnection line 275 .

[0047] The substrate 201 may have an upper surface extending in the X direction and the Y direction. The active region may be defined in the substrate 201 by the device isolation region 209. The impurity region 205 including impurities may be in a portion of the active region. The substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0048] The circuit devices 221 may include planar transistors. Each of the circuit devices 221 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. The impurity region 205 may be located in the substrate 201 on the first and second sides (the first and second sides in the X direction) of the circuit gate electrode 225 as a source / drain region.

[0049] The peripheral region insulating layer 290 may be located on the circuit device 221 on the substrate 201. The peripheral region insulating layer 290 may include a plurality of insulating layers formed in or through different processes. The peripheral region insulating layer 290 may be formed of an insulating material.

[0050] The circuit contact plug 270 and the circuit interconnection line 275 may form circuit interconnection structures 270 and 275, which may be electrically connected to the circuit device 221 and the impurity region 205. The circuit interconnection structures 270 and 275 may be referred to as lower interconnection structures. The circuit contact plug 270 may have a relatively cylindrical shape, and the circuit interconnection line 275 may have a line shape or a relatively linear shape. An electrical signal may be applied to the circuit device 221 through the circuit contact plug 270 and the circuit interconnection line 275. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. The circuit interconnection line 275 may be connected to the circuit contact plug 270 and may be arranged in a plurality of layers. The circuit contact plug 270 and the circuit interconnection line 275 may include a conductive material (e.g., tungsten (W), copper (Cu), or aluminum (Al)), and each component may also include a diffusion barrier. In some embodiments, the number of layers of the circuit contact plug 270 and the circuit interconnection line 275 may vary.

[0051] The circuit interconnect structures 270 and 275 may include a capacitor structure 200. The capacitor structure 200 may include a contact at the same level as the level of other circuit contact plugs 270 and a line at the same level as the level of other circuit interconnect lines 275. The capacitor structure 200 may be horizontally spaced apart from other regions of the circuit interconnect structures 270 and 275. The capacitor structure 200 may be electrically connected to a portion of the circuit device 221. The capacitor structure 200 may be below the second region R2 of the memory cell structure CELL, but the present disclosure is not limited thereto. In some exemplary embodiments, the capacitor structure 200 may be below the first region R1 of the memory cell structure CELL, or may be below both the first region R1 and the second region R2.

[0052] The memory cell structure CELL may have a first region R1 and a second region R2, and may include a source structure SS, a gate electrode 130 stacked on the source structure SS, an interlayer insulating layer 140 and the gate electrode 130 alternately stacked, a channel structure CH penetrating or extending through the stacked structure of the gate electrode 130, and a contact plug 170 connected to the gate electrode 130 and extending vertically or in a vertical direction. The memory cell structure CELL may include a horizontal insulating layer 113 below the gate electrode 130, a base insulating layer 121 penetrating or extending through the plate layer 101, a stud 185 on the contact plug 170, and a cell region insulating layer 190 covering the gate electrode 130.

[0053] In the memory cell structure CELL, in the first region R1, the gate electrodes 130 may be vertically stacked and may form a memory cell or may be connected to the contact plug 170. The second region R2 may be configured as an outer region of the plate layer 101.

[0054] The source structure SS may include a plate layer 101, a first horizontal conductive layer 102, and a second horizontal conductive layer 104 stacked in sequence. The plate layer 101 may have a plate shape and may be used as at least a portion of a common source line of the semiconductor device 100. The plate layer 101 may include a conductive material, such as a semiconductor material. The plate layer 101 may also include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer (such as a polysilicon layer) or an epitaxial layer.

[0055] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be stacked in sequence and may be located on the upper surface of the plate layer 101 in a region where the channel structure CH is arranged. The first horizontal conductive layer 102 may be used as a part of a common source line of the semiconductor device 100, for example, may be used as a common source line together with the plate layer 101. The first horizontal conductive layer 102 may be directly connected to the channel layer in the channel structure CH. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material, for example, polysilicon.

[0056] The horizontal insulating layer 113 may be located on the plate layer 101 at the same level as the first horizontal conductive layer 102. The horizontal insulating layer 113 may include the first horizontal insulating layer 111 and the second horizontal insulating layer 112 alternately stacked on the plate layer 101. The horizontal insulating layer 113 may be a layer remaining after a portion thereof is replaced by the first horizontal conductive layer 102 in a process of manufacturing the semiconductor device 100. The horizontal insulating layer 113 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 may include different insulating materials.

[0057] The base insulating layer 121 may penetrate or extend through the board layer 101, the horizontal insulating layer 113, and the second horizontal conductive layer 104. The base insulating layer 121 may include an insulating material such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0058] The gate electrodes 130 may be stacked on the plate layer 101 and vertically spaced apart from each other, and may form a stacked structure together with the interlayer insulating layer 140. The stacked structure may include a lower stacked structure and an upper stacked structure stacked vertically. The gate electrode 130 may include first upper gate electrodes 130U1 and 130U2 forming a string selection transistor, a memory gate electrode 130M forming a plurality of memory cells, and second lower gate electrodes 130L1 and 130L2 forming a ground selection transistor. The number of memory gate electrodes 130M forming a memory cell may be determined according to the capacity of the semiconductor device 100.

[0059] The gate electrodes 130 may be stacked vertically on the first region R1 and spaced apart from each other, and may extend to different lengths in the X direction, and may form a step structure in the form of a staircase. Due to the step structure, the lower gate electrode 130 among the gate electrodes 130 may extend longer than the upper gate electrode 130 above the lower gate electrode 130, and the gate electrodes 130 may respectively have contact regions 130P exposed upward from the interlayer insulating layer 140. The gate electrodes 130 may be respectively connected to the contact plugs 170 in the contact regions 130P which may serve as end regions.

[0060] The gate electrode 130 may include a metal material, such as tungsten (W). In some embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. All gate electrodes 130 may include the same material. In some embodiments, the gate electrode 130 may also include a diffusion barrier. For example, the diffusion barrier may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination of two or more thereof.

[0061] Interlayer insulating layers 140 may be between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 140 may be spaced apart from each other in a direction perpendicular to the upper surface of plate layer 101 and may extend in the X direction. Interlayer insulating layers 140 may include an insulating material such as silicon oxide or silicon nitride.

[0062] The channel structure CH may penetrate or extend through the gate electrode 130, may extend in the Z direction, and may be connected to the plate layer 101. Each of the channel structures CH may form a memory cell string, and may be spaced apart from each other on the plate layer 101 while forming rows and columns. The channel structure CH may form a grid pattern in the XY plane, or may be in a zigzag pattern in one direction. The channel structure CH may have a column shape, and may have an inclined side surface, and the width of the channel structure in the horizontal direction decreases toward the plate layer 101 in the vertical direction.

[0063] The channel structure CH may include a lower channel structure CH1 and an upper channel structure CH2, and the lower channel structure CH1 and the upper channel structure CH2 may be stacked vertically. In the channel structure CH, the lower channel structure CH1 and the upper channel structure CH2 may be connected to each other, and due to the width difference in the connection area, the channel structure CH may have a curved portion. However, in some embodiments, the number of channel structures stacked in the Z direction may vary. Each channel structure CH may include a channel layer in a channel hole, a gate dielectric layer, a channel filling insulating layer, and a channel pad on its upper end.

[0064] The contact plug 170 may be connected to the contact region 130P of the gate electrode 130. The contact plug 170 may penetrate or extend through at least a portion of the cell region insulating layer 190, and may be connected to each contact region 130P of the gate electrode 130 that is exposed upward. The contact plug 170 may penetrate or extend through the gate electrode 130, the second horizontal conductive layer 104, the horizontal insulating layer 113, and the board layer 101 below the contact region 130P, and may be connected to the circuit interconnection line 275 in the peripheral circuit structure PERI. The contact plug 170 may be spaced apart from the gate electrode 130 below the contact region 130P by the contact insulating layer 160. The contact plug 170 may be spaced apart from the board layer 101, the horizontal insulating layer 113, and the second horizontal conductive layer 104 by the base insulating layer 121.

[0065] Each of the contact plugs 170 may extend horizontally in the contact region 130P. The contact plug 170 may include a vertical extension portion 170V extending in the Z direction and a horizontal extension portion 170H extending horizontally from the vertical extension portion 170V and contacting the gate electrode 130. The horizontal extension portion 170H may be arranged along the periphery of the vertical extension portion 170V, and the entire side surface of the horizontal extension portion 170H may be surrounded by the gate electrode 130. The contact plug 170 may be spaced apart from the gate electrode 130 below the contact region 130P (i.e., the gate electrode 130 that may not be electrically connected) by the contact insulating layer 160.

[0066] Contact plug 170 may include at least one of a conductive material such as tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some embodiments, contact plug 170 may include a barrier layer extending along side and bottom surfaces thereof, or may have an air gap therein.

[0067] The contact insulating layer 160 may surround the side surface of each of the contact plugs 170 below the contact region 130P. The contact insulating layers 160 may be spaced apart from each other along the Z direction on the periphery of each of the contact plugs 170. The contact insulating layers 160 may be at substantially the same level as that of the gate electrode 130, respectively. The contact insulating layer 160 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0068] The stud 185 may form a cell interconnect structure that may be electrically connected to a memory cell in the memory cell structure CELL. The stud 185 may be connected to the channel structure CH and the contact plug 170, and may be electrically connected to the channel structure CH and the gate electrode 130. The stud 185 may include a metal such as tungsten (W), copper (Cu), and aluminum (Al).

[0069] The cell region insulating layer 190 may cover the stack structure of the gate electrode 130 and the contact plug 170. The cell region insulating layer 190 may be formed of an insulating material, and may be formed of a plurality of insulating layers.

[0070] The through plug 164 and the plurality of capacitor contacts 165 may be in the second region R2 of the memory cell structure CELL, and the second region R2 of the memory cell structure CELL may be the outer region of the plate layer 101. The through plug 164 and the capacitor contact 165 may penetrate or extend through the cell region insulating layer 190, and may extend to the peripheral circuit structure PERI. The through plug 164 and the capacitor contact 165 may connect the pin 185 of the memory cell structure CELL to the circuit interconnection line 275 of the peripheral circuit structure PERI. The through plug 164 and the capacitor contact 165 may include a conductive material, for example, a metal material (such as tungsten (W), copper (Cu), or aluminum (Al)). The through plug 164 and the capacitor contact 165 may be formed in the same process of forming the contact plug 170, may include the same material, and may have the same internal structure.

[0071] In some embodiments, the capacitor structure 200 may also be in the second region R2 of the memory cell structure CELL, and may be arranged throughout the peripheral circuit structure PERI and the memory cell structure CELL. The capacitor structure 200 may perform a function of storing charge. The capacitor structure 200 may include a first electrode structure 210, a second electrode structure 220, and an insulating structure IL. The capacitor structure 200 may form the above reference Figures 1 to 3 The pumping capacitor CP of the charge pump circuits 56 and 56 a is depicted. The capacitor structure 200 may be on the device isolation region 209 and may vertically overlap the device isolation region 209 .

[0072] The first electrode structure 210 may include first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f stacked in a direction perpendicular to the upper surface of the substrate 201 (e.g., in the Z direction). The second electrode structure 220 may include second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f stacked in the Z direction. The first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may be alternately arranged in the X direction parallel to the upper surface of the substrate 201 and spaced apart from each other. Since the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may be formed together in a process of forming the circuit contact plug 270 and the circuit interconnection line 275, the capacitor electrodes may be at substantially the same level as the circuit interconnection structures 270 and 275. Since the first electrode structure 210 and the second electrode structure 220 are on the device isolation region 209, the electrode structures may not be electrically connected to the circuit device 221, e.g., may be electrically isolated from the circuit device 221.

[0073] The capacitor structure 200 may be on the substrate 201. The first electrode structure 210 and the second electrode structure 220 may be on the device isolation region 209 and may penetrate at least a portion of the device isolation region 209. The lowest portion of each of the first electrode structure 210 and the second electrode structure 220 may be at a level lower than the level of the lowest portion of the circuit interconnection structures 270 and 275, but the present disclosure is not limited thereto. The first electrode structure 210 and the second electrode structure 220 may have different potentials. In some embodiments, the first electrode structure 210 and the second electrode structure 220 may receive an electrical signal through wiring connected to at least a portion of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f. In some embodiments, the capacitor contact 165 may apply a bias voltage to the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f. Therefore, a potential difference may be formed between the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f. The amount of charge that the capacitor structure 200 can store may be proportional to the product of the potential difference and the capacitance of the capacitor structure 200. The capacitance can be proportional to the product of the dielectric constant of the insulating structure IL and the areas of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f on the left and right sides of the insulating structure IL relative to each other, and can be inversely proportional to the distance between the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f on the left and right sides of the insulating structure IL.

[0074] like Figure 5C As shown in the figure, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f may have a plate shape extending in the Y direction and the Z direction, but the present disclosure is not limited thereto. In some embodiments, at least a portion of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f may have a line shape or a column shape.

[0075] The first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f can be set to a plate shape, so that compared with being set to a column shape, the area of ​​the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f can be increased, and the capacitance of the capacitor structure 200 can be increased. In addition, each of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may penetrate or extend through at least a portion of the device isolation region 209 and may extend in the Z direction, and thus, the capacitance of the capacitor structure 200 may be increased. As the depth of the device isolation region 209, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f increases, the capacitance of the capacitor structure 200 may be increased.

[0076] In some embodiments, the number of layers forming the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the number of layers forming the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may vary.

[0077] The first electrode structure 210 and the second electrode structure 220 may include a metal material, such as tungsten (W), copper (Cu) and aluminum (Al). The first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f may include the same material, but the present disclosure is not limited thereto. In some embodiments, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f may include a material different from the material of the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f. For example, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f may include a metal material, and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f may include a semiconductor material. The insulating structure IL may be an insulating layer including an insulating material (e.g., silicon oxide, silicon nitride, silicon carbide or silicon oxynitride). In some embodiments, the insulating structure IL may include a plurality of insulating layers. When the insulating structure IL includes a plurality of insulating layers, the dielectric constant of the insulating structure IL may increase toward the substrate 201 or the device isolation region 209.

[0078] like Figure 5A As shown in , the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f at the same level as the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the insulating structure IL therebetween may form a metal-insulator-metal (MIM) capacitor, and their capacitances may be C1a, C1b, C1c, C1d, C1e and C1f, respectively, and the values ​​may be different, but the present disclosure is not limited thereto. In addition, as Figure 5B As shown in FIG. 1 , the lowermost first capacitor electrode 210 a and the lowermost second capacitor electrode 220 a and the device isolation region 209 therebetween may form a MIM capacitor, and the capacitance thereof may be C2 .

[0079] Figure 6 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments, which shows Figure 5A The corresponding area.

[0080] Reference Figure 6In the capacitor structure 200a, the lowest end of each of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may be at a level higher than the level of the highest surface of the substrate 201. In some embodiments, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may be spaced apart from the upper surface of the device isolation region 209 on the device isolation region 209. In part of the process of manufacturing the semiconductor device 100a, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e and 220f can be formed together in the process of forming the circuit interconnection structures 270 and 275 without the need for another process that penetrates the device isolation region 209, so that the process cost and difficulty can be reduced.

[0081] Figure 7 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments, which shows Figure 5A The corresponding area.

[0082] Reference Figure 7 , the first semiconductor structure S1 may further include a stop layer SL, which is located on a portion of the surface of the substrate 201 along the surface of the substrate 201 in the device isolation region 209. In some embodiments, at least a portion of the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f of the capacitor structure 200b may contact the stop layer SL, but the present disclosure is not limited thereto. In some embodiments, the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f may be spaced apart from the stop layer SL. The stop layer SL may prevent the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f from contacting the substrate 201. The stop layer SL may include at least one of insulating materials such as SiN, SiON, SiCN, SiOC, SiOCN, and SiO. The stop layer SL and the insulating structure IL may include other materials or different materials, but the present disclosure is not limited thereto.

[0083] Figure 8 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments, which shows Figure 5A The corresponding area.

[0084] Reference Figure 8 , the capacitor structure 200c of the semiconductor device may further include a third electrode structure 230 and a fourth electrode structure 240 on the impurity region 205 and the circuit device 221. The third electrode structure 230 may extend in the Y direction and may be stacked on the impurity region 205 in the Z direction, and the fourth electrode structure 240 may extend in the Y direction and may be stacked on the circuit device 221 in the Z direction. The second insulating structure IL2 may be between the third electrode structure 230 and the fourth electrode structure 240. The second insulating structure IL2 may represent the insulating structure IL on the impurity region 205 and the circuit device 221, but may be formed in substantially the same process as forming the first insulating structure IL1, so that the second insulating structure IL2 may include the same material as the first insulating structure IL1. Figure 8 As shown in, the third electrode structure 230 may include third capacitor electrodes 230a, 230b, 230c, 230d, 230e and 230f, and the fourth electrode structure 240 may include fourth capacitor electrodes 240b, 240c, 240d, 240e and 240f, but the present disclosure is not limited thereto. The third electrode structure 230, the fourth electrode structure 240 and the second insulating structure IL2 between the third electrode structure 230 and the fourth electrode structure 240 may form a MIM capacitor, and their capacitances may be C1b, C1c, C1d, C1e and C1f, respectively, and the values ​​may be different, but the present disclosure is not limited thereto. In addition, the second electrode structure 220, the third electrode structure 230 and the insulating structure IL between the second electrode structure 220 and the third electrode structure 230 may form a MIM capacitor, and their capacitances may be C3, C1b, C1c, C1d and C1e, C1f, respectively, and the values ​​may be different, but the present disclosure is not limited thereto.

[0085] Fig.9A is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments, which shows Figure 5A The corresponding area. Fig. 9B is a plan view showing a capacitor structure of a semiconductor device according to some embodiments, which is along Fig.9A The line II-II' is intercepted.

[0086] Reference Fig.9A and Fig. 9B, the first semiconductor structure S1 may further include dummy patterns DP spaced apart from each other in the X-direction and the Y-direction and in a region vertically overlapping with the capacitor structure 200d. The dummy pattern DP may be defined by the device isolation region 209. In some embodiments, the device isolation region 209 may be between the dummy patterns DP. The circuit device 221 may not be on the dummy pattern DP, but the present disclosure is not limited thereto. When the circuit device 221 is on the dummy pattern DP, the circuit device 221 may not be connected to the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f, and may be referred to as a dummy circuit device. The dummy pattern DP may prevent a butterfly-shaped sinking (dishing) in which the device isolation region 209 becomes convex when a subsequent planarization process is performed. The dummy patterns DP may be spaced apart in an island type, but the present disclosure is not limited thereto. At least a portion of the first electrode structure 210 and the second electrode structure 220 may vertically overlap the dummy pattern DP. In some embodiments, the first electrode structure 210 and the second electrode structure 220 vertically overlapping the dummy pattern DP may be spaced apart from the dummy pattern DP, and the first electrode structure 210 and the second electrode structure 220 not vertically overlapping the dummy pattern DP may be on the device isolation region 209 between the dummy patterns DP. Since the first electrode structure 210 and the second electrode structure 220 may penetrate or extend through at least a portion of the device isolation region 209, the area in which the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f included in the capacitor structure 200d face each other may be increased, so that the capacitance may be increased. The lowermost first capacitor electrode 210a, the lowermost second capacitor electrode 220a, and the device isolation region 209 between the lowermost first capacitor electrode 210a and the lowermost second capacitor electrode 220a may form a MIM capacitor, whose capacitance may be C2. In some embodiments, the MIM capacitor formed by the lowermost first capacitor electrode 210a, the lowermost second capacitor electrode 220a, and the insulating structure IL may have capacitances of C1a1, C1a2, and C1a3, respectively. The capacitance may vary according to the area, length, and material of the lowermost first capacitor electrode 210a and the lowermost second capacitor electrode 220a.

[0087] Fig.10 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments. Figure 5A The corresponding area.

[0088] Reference Fig.10 ,and Fig.9A Compared to the capacitor structure 200d in FIG. 1 , the first capacitor electrodes 210a, 210b, 210c, 210d, 210e, and 210f and the second capacitor electrodes 220a, 220b, 220c, 220d, 220e, and 220f of the capacitor structure 200e may be at a level higher than the upper surface of the device isolation region 209 and may be spaced apart from the dummy pattern DP. Fig.9A and Fig. 9B The description of the description can be further applied to the description of the dummy pattern DP.

[0089] Fig.11 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments, which shows Figure 5A The corresponding area.

[0090] Reference Fig.11 The semiconductor device may further include dummy patterns DP spaced apart from each other in the X direction and the Y direction and between the circuit devices 221. In addition, a stop layer SL may be further included, and the stop layer SL is located on a portion of the surface of the substrate 201 and the surface of the dummy pattern DP along the surface of the substrate 201 and the dummy pattern DP in the device isolation region 209. For the description of the dummy pattern DP, reference may be applied. Fig.9A and Fig. 9B After forming the stop layer SL to cover the dummy pattern DP, the device isolation region 209 may be formed to cover the region between the dummy patterns DP and to cover the stop layer SL, and the upper surface of the dummy pattern DP may be exposed by a planarization process. Therefore, the stop layer SL may not cover the upper surface of the dummy pattern DP. Figure 7 The description of the stop layer SL is described. In addition, for the description of the capacitor structure 200f, reference can be further applied. Fig.9A and Fig. 9B A description is made of the capacitor structure 200d described.

[0091] Fig.12 is a cross-sectional view illustrating a semiconductor device according to some embodiments.

[0092] Reference Fig.12 , the semiconductor device 100 a may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded to each other using a wafer bonding method.

[0093] Figure 4The description of the peripheral circuit structure PERI in the first semiconductor structure S1 can be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may also include a first bonding via 282, a first bonding pad 284, and a first bonding insulating layer 286, which may be together as a first bonding structure (or referred to as a lower bonding structure) 280. The first bonding via 282 may be connected to the circuit interconnect structures 270 and 275. The first bonding pad 284 may be connected to the first bonding via 282. The first bonding via 282 and the first bonding pad 284 may include a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc., and each component may also include a diffusion barrier. The first bonding insulating layer 286 may also be used as a diffusion barrier for the first bonding pad 284, and may include at least one of SiCN, SiO, SiN, SiOC, SiON, and SiOCN. The first bonding insulating layer 286 may have a thickness less than that of the first bonding pad 284, but the present disclosure is not limited thereto.

[0094] Figure 4 The description of the memory cell structure CELL in the embodiment of the present invention can be applied to the second semiconductor structure S2. The second semiconductor structure S2 may further include a second bonding structure (or upper bonding structure) 180, which may include a second bonding via 182, a second bonding pad 184, and a second bonding insulating layer 186. The second semiconductor structure S2 may further include a cell interconnection line 181 and a passivation layer 106 covering the upper surface of the plate layer 101.

[0095] The first bonding pad 284 may be connected to the second bonding pad 184 of the second semiconductor structure S2. The first bonding structure 280 may be bonded or connected to the second bonding structure 180 by hybrid bonding via direct contact with the second bonding structure 180. For example, each first bonding pad 284 may be contacted and bonded to the corresponding second bonding pad 184 by copper (Cu)-copper (Cu) bonding (copper to copper bonding), and the first bonding insulating layer 286 may be contacted and bonded to the second bonding insulating layer 186 by dielectric to dielectric bonding. The first bonding structure 280 and the second bonding structure 180 together may provide an electrical connection path according to the bonding between the first semiconductor structure S1 and the second semiconductor structure S2. A portion of the first bonding pad 284 may not be connected to the circuit interconnect line 275 located below, but may be set only for bonding. The first bonding insulating layer 286 may be arranged around the first bonding pad 284.

[0096] The second bonding via 182 and the second bonding pad 184 may be below the pin 185. In some embodiments, the cell interconnect line 181 may be further between the second bonding via 182 and the pin 185. The second bonding via 182 may connect the pin 185 to the second bonding pad 184, and the second bonding pad 184 may be bonded to the first bonding pad 284 of the first semiconductor structure S1. The second bonding insulating layer 186 may be connected to the first bonding insulating layer 286 of the first semiconductor structure S1 by bonding. The second bonding via 182 and the second bonding pad 184 may include a conductive material, such as copper (Cu). The second bonding insulating layer 186 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0097] The cell interconnection line 181 may form an upper interconnection structure electrically connected to the memory cell in the memory cell structure CELL. The cell interconnection line 181 may be connected to the contact plug 170 and the through plug 164, and may be electrically connected to the gate electrode 130 and the channel structure CH. In some embodiments, the number of interconnection lines included in the upper interconnection structure may vary. The cell interconnection line 181 may include a metal, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0098] The passivation layer 106 may be on the upper surface of the plate layer 101 and may protect the semiconductor device 100a. The passivation layer 106 may include at least one of an insulating material (e.g., silicon oxide, silicon nitride, and silicon carbide), and may include a plurality of insulating layers in some embodiments. In some embodiments, the upper end of the contact plug 170 may be in the base insulating layer 121.

[0099] Fig.13 is an enlarged cross-sectional view showing a portion of a semiconductor device and a cross-sectional view showing a capacitor structure according to some embodiments.

[0100] Reference Fig.13 , the semiconductor device 100b can be Fig.12 The semiconductor device 100a in the embodiment further includes a second capacitor structure 300. The second capacitor structure 300 may include a capacitor contact 165 and a base insulating layer 121. The second capacitor structure 300 may be in a second region R2 on the outer side of the plate layer 101. The capacitor contact 165 may penetrate or extend through a portion of the base insulating layer 121. In the base insulating layer 121, the capacitor contacts 165 adjacent to each other may have different potentials. In some embodiments, based on the capacitor contacts 165 having different potentials and with the base insulating layer 121 interposed therebetween, a semiconductor device 100b with improved capacitance may be provided.

[0101] Fig.14is a cross-sectional view illustrating a semiconductor device according to some embodiments.

[0102] Reference Fig.14 , the semiconductor device 100c may include a first semiconductor structure S1 and a second semiconductor structure S2 bonded to each other by wafer bonding. The second semiconductor structure S2 may include a memory semiconductor chip, and the first semiconductor structure S1 may include a logic semiconductor chip, but the present disclosure is not limited thereto.

[0103] The second semiconductor structure S2 may be in the lower portion, and the first semiconductor structure S1 may be located on the second semiconductor structure S2 in a mirror shape. Figure 4 The description of the peripheral circuit structure PERI described above may be applied to the first semiconductor structure S1. However, the first semiconductor structure S1 may further include a first bonding via 282, a first bonding pad 284, and a first bonding insulating layer 286 that may serve as a first bonding structure 280. Figure 4 The description of the memory cell structure CELL described in the description may be applied to the second semiconductor structure S2. The second semiconductor structure S2 may further include a second bonding via 182, a second bonding pad 184, and a second bonding insulating layer 186 that may serve as a second bonding structure 180. The first bonding pad 284 may be connected to an upper surface of the second bonding pad 184 of the second semiconductor structure S2. The first bonding structure 280 may be bonded or connected to the second bonding structure 180 by direct contact with the second bonding structure 180 through hybrid bonding. For the sake of brevity, the above description will not be provided herein. Fig.12 Descriptions that overlap with the content described in .

[0104] Fig.15 is a cross-sectional view illustrating a semiconductor device according to some embodiments.

[0105] Reference Fig.15 ,exist Fig.14 Based on the semiconductor device 100c, the third semiconductor structure S3 may be on the first semiconductor structure S1. Figure 4The description of the peripheral circuit structure PERI described may be applied to the third semiconductor structure S3. The third semiconductor structure S3 may be symmetrical with the first semiconductor structure S1, and the description of the first semiconductor structure S1 may be applied to the third semiconductor structure S3. The description of the substrate 201, the device isolation region 209, and the peripheral region insulating layer 290 of the first semiconductor structure S1 may be applied to the substrate 301, the device isolation region 309, and the peripheral region insulating layer 390 of the third semiconductor structure S3. The third semiconductor structure S3 may further include a third capacitor structure 400 vertically overlapped on the device isolation region 309 and with the device isolation region 309. On the lower surface of the third semiconductor structure S3, a portion of the substrate 301 and the device isolation region 309 may be removed by a planarization process, so that a portion of the third capacitor structure 400 may be exposed. On the upper surface of the first semiconductor structure S1, the substrate 201 and the device isolation region 209 may be partially removed by a planarization process, so that a portion of the first capacitor structure 200 may be exposed. The first capacitor structure 200 of the first semiconductor structure S1 may be connected and bonded to the third capacitor structure 400 of the third semiconductor structure S3. The substrate 201 of the first semiconductor structure S1 and the substrate 301 of the third semiconductor structure S3 may be bonded to each other by directly contacting each other. The device isolation region 209 of the first semiconductor structure S1 and the device isolation region 309 of the third semiconductor structure S3 may be connected to each other by directly contacting each other. The first semiconductor structure S1 may include a first capacitor structure 200 on the device isolation region 209, the second semiconductor structure S2 may include a second capacitor structure 300 on the substrate insulating layer 121, and the third semiconductor structure S3 may include a third capacitor structure 400 on the device isolation region 309, so that the capacitance in the semiconductor device 100d can be maximized, and the integration density and electrical properties of the semiconductor device 100d can be improved.

[0106] Fig.16 is a diagram illustrating a data storage system including a semiconductor device according to some embodiments.

[0107] Reference Fig.16 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0108] The semiconductor device 1100 may be implemented as a nonvolatile memory device, such as a Figures 1 to 15 The NAND flash memory device in the above-described embodiment is described as an example. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some embodiments, the first structure 1100F may be on the side of the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1, a second gate upper line UL2, a first gate lower line LL1, a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0109] In the second structure 1100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In different embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary.

[0110] In some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be configured as a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0111] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series to each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation to erase data stored in the memory cell transistor MCT using a GIDL phenomenon.

[0112] The common source line CSL, the first gate lower line LL1, the second gate lower line LL2, the word line WL, the first gate upper line UL1, and the second gate upper line UL2 may be electrically connected to the decoder circuit 1110 through a first connection interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnect 1125 extending from the first structure 1110F to the second structure 1100S.

[0113] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0114] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In some embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0115] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a controller interface 1221 configured to handle communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written into the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be sent. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command from an external host is received through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0116] Fig.17 is a perspective view illustrating a data storage system including a semiconductor device according to some embodiments.

[0117] Reference Fig.17In some embodiments, the data storage system 2000 may include a mainboard 2001, a controller 2002 mounted on the mainboard 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnection pattern 2005 formed on the mainboard 2001.

[0118] The mainboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host (not shown). The number and arrangement of the plurality of pins in the connector 2006 may vary according to the communication interface between the data storage system 2000 and the external host. In some embodiments, the data storage system 2000 may communicate with the external host according to one of the interfaces from the universal serial bus (USB), the peripheral component interconnect fast (PCI-Express), the serial advanced technology attachment (SATA), and the M-Phy for universal flash memory (UFS). In some embodiments, the data storage system 2000 may operate by power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing the power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0119] The controller 2002 may write data to or read data from the semiconductor package 2003 , and may increase the operation speed of the data storage system 2000 .

[0120] The DRAM 2004 may be configured as a buffer memory for alleviating the speed difference between the semiconductor package 2003, which may be a data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 may operate as a cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003. When the data storage system 2000 may include the DRAM 2004, the controller 2002 may include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0121] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b that may be spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 on the lower surface of the semiconductor chip 2200, respectively, a connection structure 2400 that electrically connects the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 that covers the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0122] The package substrate 2100 may be configured as a printed circuit board including a package upper pad 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.16 Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include a reference Figures 1 to 15 The semiconductor devices in the above embodiments are described.

[0123] In some embodiments, the connection structure 2400 may be configured as a bonding wire that electrically connects the input / output pad 2210 to the package upper pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the package upper pad 2130 of the package substrate 2100. In some embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through-hole electrode (TSV) instead of the connection structure 2400 of the bonding wire method.

[0124] In some embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate different from the mainboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through interconnections formed on the interposer substrate.

[0125] Fig.18 is a cross-sectional view showing a semiconductor package according to some embodiments, showing Fig.17 2 is an example of a semiconductor package 2003 taken along line III-III'.

[0126] Reference Fig.18 In the semiconductor package 2003, the package substrate 2100 may be implemented as a printed circuit substrate. The package substrate 2100 may include a package substrate body portion 2120, a package upper pad 2130 (see FIG. 213 ) on an upper surface of the package substrate body portion 2120, and a printed circuit substrate. Fig.17 ), a lower pad 2125 exposed on or through the lower surface of the package substrate body portion 2120, and an internal interconnect 2135 that electrically connects the package upper pad 2130 to the lower pad 2125 in the package substrate body portion 2120. The lower pad 2125 can be connected to the interconnect pattern 2005 (such as the interconnect pattern 2005 of the main board 2001 of the data storage system 2000) through the conductive connection portion 2800. Fig.17 ).

[0127] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating or extending through the gate stack structure 3210, a bit line 3240 electrically connected to the channel structure 3220, and a word line WL (see FIG. 1 ) connected to the gate stack structure 3210. Fig.16 ) is electrically connected to the contact plug 3235. Figures 1 to 15 As described in the above-described embodiments, each of the semiconductor chips 2200 may include a capacitor structure 200 vertically overlapped with the device isolation region 209 on the device isolation region 209 .

[0128] Each of the semiconductor chips 2200 may include a through interconnect 3245 that is electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extends into the second structure 3200. The through interconnect 3245 may be on the outside of the gate stack structure 3210, and may also be arranged to penetrate or extend through the gate stack structure 3210. Each of the semiconductor chips 2200 may also include an input / output pad 2210 (see FIG. 2 ) that is electrically connected to the peripheral interconnect 3110 of the first structure 3100. Fig.17 ).

[0129] According to the above-described examples of embodiments, by providing a capacitor structure on and vertically overlapping a device isolation region, a semiconductor device having improved electrical properties and reliability and a data storage system including the semiconductor device may be provided.

[0130] While some examples of embodiments have been shown and described above, it will be constructed as apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: a first semiconductor structure, comprising a substrate, an active region, a circuit device, a device isolation region, an impurity region, a circuit interconnection structure, and a capacitor structure, wherein the active region is located in the substrate, the circuit device is located on the substrate, the device isolation region defines the active region, the impurity region is located in the active region on a first side and a second side of the circuit device, the circuit interconnection structure is electrically connected to the circuit device, and the capacitor structure is located on the device isolation region and vertically overlaps the device isolation region; as well as a second semiconductor structure including a plate layer, a gate electrode, a channel structure and an upper interconnection structure, wherein the plate layer is located on the first semiconductor structure, the gate electrodes are stacked on the plate layer along a first direction perpendicular to an upper surface of the plate layer and are spaced apart from each other and stacked in sequence, the channel structure extends through the gate electrode in the first direction, and the upper interconnection structure is electrically connected to the channel structure, The capacitor structure includes a first electrode structure, a second electrode structure and a first insulating structure, the first electrode structure extends in a first direction and includes a first capacitor electrode stacked in the first direction, the second electrode structure includes a second capacitor electrode stacked in the first direction, and the first insulating structure is located between the first electrode structure and the second electrode structure. wherein the first capacitor electrodes and the second capacitor electrodes are alternately arranged and spaced apart from each other in a second direction parallel to an upper surface of the substrate, and extend in a third direction perpendicular to the first direction and the second direction, and The first capacitor electrode and the second capacitor electrode both have a plate shape.

2. The semiconductor device according to claim 1, in, Each of the first electrode structure and the second electrode structure is located on the device isolation region, and At least a portion of the first capacitor electrode and the second capacitor electrode extends into at least a portion of the device isolation region.

3. The semiconductor device according to claim 2, in, The first semiconductor structure further includes a stop layer located on a portion of the surface of the substrate along the surface of the substrate in the device isolation region, and At least a portion of the first capacitor electrode and the second capacitor electrode is in contact with the stop layer.

4. The semiconductor device according to claim 3, in, The stop layer includes an insulating material, and The stop layer and the first insulating structure include different materials.

5. The semiconductor device according to claim 2, in, The first capacitor electrode includes a metal material, and The second capacitor electrode includes a metal material or a semiconductor material.

6. The semiconductor device according to claim 2, wherein: A lowest portion of each of the first electrode structure and the second electrode structure is located at a level lower than a level of a lowest portion of the circuit interconnection structure.

7. The semiconductor device according to claim 1, wherein The first semiconductor structure further includes dummy patterns that are spaced apart from each other in the second direction and the third direction and are located in a region vertically overlapping the capacitor structure.

8. The semiconductor device according to claim 7, further comprising: A stop layer is located on a portion of the surface of the substrate and the surface of the dummy pattern along the surface of the substrate and the surface of the dummy pattern in the device isolation region.

9. The semiconductor device according to claim 7, in, The device isolation area is located between the dummy patterns, and Wherein, at least a portion of the first electrode structure and the second electrode structure vertically overlaps the dummy pattern.

10. The semiconductor device according to claim 7, wherein: At least a portion of the first electrode structure and the second electrode structure vertically overlapping the device isolation region extends into at least a portion of the device isolation region.

11. The semiconductor device according to claim 1, in, The first insulating structure includes a plurality of dielectric layers, and Wherein, the dielectric constants of the plurality of dielectric layers increase toward the upper surface of the substrate.

12. The semiconductor device according to claim 1, wherein The first electrode structure and the second electrode structure are located at substantially the same level as the circuit interconnect structure.

13. The semiconductor device according to claim 1, further comprising: a third electrode structure extending in the first direction and stacked on the impurity region in the first direction; a fourth electrode structure extending in the first direction and stacked on the circuit device in the first direction; as well as The second insulating structure is located between the third electrode structure and the fourth electrode structure.

14. The semiconductor device according to claim 1, further comprising: a lower bonding structure connected to the circuit interconnect structure; as well as The upper bonding structure is connected to the lower bonding structure, Wherein, the lower bonding structure includes a lower bonding via connected to the circuit interconnection structure and a lower bonding pad connected to the lower bonding via, Wherein, the upper bonding structure includes an upper bonding via connected to the upper interconnect structure and an upper bonding pad connected to the upper bonding via, and Wherein, the lower bonding pad and the upper bonding pad are bonded to each other.

15. A semiconductor device, comprising: a substrate, including the active region; Circuit devices, located on the active area; Device isolation area, defining the active area; an impurity region located in an active region on a first side and a second side of the circuit device; a first electrode structure, located on the device isolation region, vertically overlapping the device isolation region, and extending in a first direction perpendicular to the upper surface of the substrate; a second electrode structure located on the device isolation region, vertically overlapping the device isolation region, and spaced apart from the first electrode structure in a second direction perpendicular to the first direction; as well as The insulating structure is located between the first electrode structure and the second electrode structure. Each of the first electrode structure and the second electrode structure extends in a third direction perpendicular to the first direction and the second direction and has a plate shape.

16. The semiconductor device according to claim 15, wherein: At least a portion of the first electrode structure and the second electrode structure extends into at least a portion of the device isolation region.

17. The semiconductor device according to claim 15, further comprising: The dummy patterns are spaced apart from each other in the second direction and the third direction and are located between the circuit devices, Wherein, at least a portion of the first electrode structure and the second electrode structure vertically overlaps the dummy pattern.

18. The semiconductor device according to claim 15, further comprising: a stop layer located on a portion of the surface of the substrate along the surface of the substrate in the device isolation region, At least a portion of the first electrode structure and the second electrode structure is in contact with the stop layer.

19. A data storage system, the data storage system comprising: A semiconductor memory device, comprising a substrate, an active region, a circuit device, a device isolation region, a circuit interconnection structure, a capacitor structure, a memory cell, and an input / output pad, wherein the active region is located in the substrate, the circuit device is located on the substrate, the device isolation region defines the active region, the circuit interconnection structure is electrically connected to the circuit device, and the capacitor structure is located on the device isolation region and vertically overlaps the device isolation region; as well as a controller electrically connected to the semiconductor memory device through an input / output pad and configured to control the semiconductor memory device, The capacitor structure includes a first electrode structure, a second electrode structure and a first insulating structure, the first electrode structure extends in a first direction perpendicular to the upper surface of the substrate and includes first capacitor electrodes stacked in the first direction, the second electrode structure includes second capacitor electrodes stacked in the first direction, and the first insulating structure is located between the first electrode structure and the second electrode structure. wherein the first capacitor electrodes and the second capacitor electrodes are spaced apart from each other and alternately arranged in a second direction parallel to the upper surface of the substrate, and extend in a third direction perpendicular to the first direction and the second direction, and Wherein, each of the first capacitor electrode and the second capacitor electrode has a plate shape.

20. The data storage system according to claim 19, wherein: The first electrode structure and the second electrode structure are electrically isolated from the circuit device.

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