Ferroelectric 3D NAND flash memory device and operation method and manufacturing method thereof

Abstract

The invention discloses a ferroelectric type 3D NAND flash memory device and an operation method and a manufacturing method thereof, the 3D NAND flash memory device comprises a substrate and a stacking structure located on the surface of the substrate, and the stacking structure comprises a plurality of gate dielectric oxide layers and gate electrode layers which are arranged in a staggered mode; the channel hole penetrates through the stacked structure; the first isolation layer is located on the side wall of the channel hole; the channel layer covers the first isolation layer and the bottom of the channel hole; the ferroelectric layer is positioned on the surface of the channel layer; the back gate layer is located on the surface of the ferroelectric layer; the residual space of the channel hole is filled with the filling layer; the insulating layer covers the channel hole and the stacking structure, the insulating layer is provided with a first through hole and a second through hole, the first through hole exposes at least part of the surface of the channel layer, and the second through hole exposes at least part of the surface of the back gate layer; the drain electrode is electrically connected with the channel layer through the first through hole; and the back grid electrode is electrically connected with the back grid layer through the second through hole. According to the 3D NAND flash memory device, the ferroelectric layer is used as a charge storage layer, and the operation speed is high.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a ferroelectric 3D NAND flash memory device and an operation method and a manufacturing method thereof. Background Art

[0002] 3D NAND flash memory devices are non-volatile memory devices that improve storage density and performance by vertically stacking memory cells. Specifically, the vertical stacking of memory cells in 3D NAND flash memory devices is mainly achieved by gate metal stacking and thin film deposition in high aspect ratio channel holes. The channel structure of traditional 3D NAND flash memory devices includes metal gate-blocking oxide layer-charge storage layer-tunneling oxide layer-channel layer-oxide filling layer. Among them, the metal gate serves as the control gate of the 3D NAND flash memory device; the blocking oxide layer serves as a blocking layer to block the charge leakage of the charge storage layer; the charge storage layer usually uses silicon nitride (SiN) material, which serves to store charge. In specific operation, the information storage function is realized by changing the threshold voltage of the 3D NAND flash memory device; the tunneling oxide layer serves as a tunneling channel for charge tunneling into the charge storage layer; the channel layer serves as a semiconductor conductive channel. In specific operation, the metal gate controls the conductive channel to realize the function of gate voltage controlling channel current; the oxide filling layer fills the remaining space in the channel hole to play a supporting and insulating role.

[0003] With the development of storage technology, users have higher and higher requirements on the operation speed of 3D NAND flash memory devices. Therefore, how to improve the operation speed of 3D NAND flash memory devices has become a research hotspot for technicians in this field. Summary of the invention

[0004] In view of the above problems, the present application provides a ferroelectric 3D NAND flash memory device and an operation method and a manufacturing method thereof to improve the operation speed of the 3D NAND flash memory device. The specific scheme is as follows:

[0005] A ferroelectric 3D NAND flash memory device, comprising:

[0006] substrate;

[0007] A stacked structure located on the first surface of the substrate, the stacked structure comprising a plurality of gate dielectric oxide layers and gate electrode layers arranged alternately in a direction perpendicular to the plane of the substrate;

[0008] A channel hole penetrating the stacked structure, wherein the channel hole extends into the first surface of the substrate;

[0009] a first isolation layer located on the sidewall of the channel hole;

[0010] a channel layer covering the first isolation layer and the bottom of the channel hole;

[0011] a ferroelectric layer located on a surface of the channel layer;

[0012] A back gate layer located on the surface of the ferroelectric layer;

[0013] A filling layer filling the remaining space of the channel hole;

[0014] an insulating layer covering the channel hole and the stacked structure, the insulating layer having a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer;

[0015] A drain electrode electrically connected to the channel layer through the first through hole and a back gate electrode electrically connected to the back gate layer through the second through hole.

[0016] Optionally, the ferroelectric layer is a single-layer ferroelectric thin film.

[0017] Optionally, the ferroelectric layer further includes a silicon dioxide layer located on a surface of the single-layer ferroelectric film on a side away from the channel layer.

[0018] Optionally, the back gate is made of a metal material that can induce the ferroelectric layer to form a ferroelectric phase.

[0019] Optionally, the back gate is tungsten or titanium nitride.

[0020] Optionally, the channel layer is a polysilicon layer, an IGZO layer, or a thin molybdenum disulfide layer.

[0021] An operating method of a 3D NAND flash memory device is applied to any of the above 3D NAND flash memory devices, wherein the 3D NAND flash memory device includes a plurality of storage units, and the operating method includes at least one of the following:

[0022] When performing a read operation on the 3D NAND flash memory device, a read voltage is applied to the gate of the memory cell to be read in the 3D NAND flash memory device, a pass voltage is applied to the gates of other memory cells in the same channel hole, a detection voltage is uniformly applied to the drains of the memory cells in the same channel hole to detect whether the memory cell to be read is turned on, and at the same time, the sources of the memory cells in the same channel hole are uniformly connected to a zero potential and the back gates are uniformly floated;

[0023] When performing a programming operation on the 3D NAND flash memory device, controlling the gate of the memory cell to be programmed in the 3D NAND flash memory device to apply a programming voltage, connecting the back gate to a zero potential, and leaving other electrodes floating;

[0024] When performing an erase process operation on the 3D NAND flash memory device, the gate of the storage unit to be erased in the 3D NAND flash memory device is controlled to apply a zero potential, the back gate is applied with an erase voltage, and the source and the drain are floating.

[0025] A method for manufacturing a ferroelectric 3D NAND flash memory device, comprising:

[0026] providing a substrate;

[0027] Fabricate a stacked structure on the first surface of the substrate, wherein the stacked structure includes a plurality of gate dielectric oxide layers and gate electrode layers arranged alternately in a direction perpendicular to the plane of the substrate;

[0028] Making a channel hole penetrating the stacked structure, wherein the channel hole extends into the first surface of the substrate;

[0029] Forming a first isolation layer on the sidewall of the channel hole;

[0030] Sequentially forming a channel layer, a ferroelectric layer, a back gate layer covering the first isolation layer and the bottom of the channel hole, and a filling layer filling the remaining space of the channel hole;

[0031] Manufacturing an insulating layer covering the channel hole and the stacked structure, wherein the insulating layer has a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer;

[0032] A drain electrode electrically connected to the channel layer through the first through hole and a back gate electrode electrically connected to the back gate layer through the second through hole are manufactured.

[0033] Optionally, sequentially manufacturing a channel layer covering the surface of the first isolation layer and the bottom of the channel hole, a ferroelectric layer, a back gate layer, and a filling layer filling the remaining space of the channel hole comprises:

[0034] Manufacturing a channel layer covering the surface of the first isolation layer, the bottom of the channel hole, and the surface of the stack structure away from the substrate;

[0035] Making a ferroelectric layer covering the surface of the channel layer;

[0036] Making a back gate layer covering the surface of the ferroelectric layer away from the channel layer;

[0037] Making a filling layer that covers the surface of the back gate layer away from the ferroelectric layer and fills the remaining space of the channel hole;

[0038] The channel layer, the ferroelectric layer, the back gate layer and the filling layer are removed from a portion of the surface of the stacked structure away from the substrate.

[0039] Optionally, after the first isolation layer is manufactured and before the channel layer is manufactured, the method further includes: implanting ions into the substrate through the channel hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0041] Figure 1 A schematic diagram of the structure of a ferroelectric 3D NAND provided in this application;

[0042] Figure 2 A schematic diagram of an equivalent circuit when a ferroelectric 3D NAND performs a read operation provided in this application;

[0043] Figure 3 A schematic diagram of an equivalent circuit when a ferroelectric 3D NAND performs a programming operation provided in this application;

[0044] Figure 4 A schematic diagram of an equivalent circuit when a ferroelectric 3D NAND is performing an erase operation provided in this application;

[0045] Figure 5 A flowchart of a method for manufacturing a ferroelectric 3D NAND provided in this application;

[0046] Figure 6-Figure 18 A schematic diagram of some structures involved in the manufacturing process of a ferroelectric 3D NAND provided in this application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments in the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0048] It is obvious to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and changes of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0049] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0050] As described in the background technology section, how to improve the operating speed of 3D NAND flash memory devices has become a research hotspot for those skilled in the art.

[0051] The inventors have found that ferroelectricity is a property of certain dielectric crystals. In some dielectric crystals, the structure of the unit cell causes the centers of positive and negative charges to not overlap, resulting in an electric dipole moment, which produces an electric polarization intensity that is not equal to zero, making the crystal spontaneously polarized, and the direction of the electric dipole moment can be changed by an external electric field, showing characteristics similar to those of ferromagnets. This property of the crystal is called ferroelectricity. The relationship curve between the degree of polarization of the crystal and the electric field intensity is similar to the shape of the hysteresis loop of a ferromagnet. Based on the hysteresis phenomenon in ferroelectricity, the polarized charge generated by ferroelectric polarization can be used to store information. In the 3D NAND flash memory structure, a charge storage layer can be made of ferroelectric materials to realize a ferroelectric 3D NAND flash memory device, so as to improve the operating speed of the 3D NAND flash memory device.

[0052] Specifically, hafnium-based ferroelectric materials refer to ferroelectric materials with hafnium (Hf) as the basic element. Hafnium-based ferroelectric materials have the advantages of simple composition, thin thickness, excellent ferroelectric properties, and compatibility with metal oxide semiconductor technology (CMOS). They are ideal ferroelectric materials for 3D NAND flash memory applications.

[0053] However, hafnium-based ferroelectric materials require specific process conditions to form a ferroelectric lattice structure. The high-temperature growth and long-term high-temperature annealing in the process steps of 3D NAND flash memory devices will cause the hafnium-based ferroelectric materials to change from the ferroelectric phase to the paraelectric phase, and no longer have storage functions. In particular, in the growth process of the polysilicon channel in 3D NAND flash memory devices, it is necessary to grow at a temperature of about 800°C and anneal for a long time. Therefore, if the SiN material of the charge storage layer is directly replaced with hafnium-based ferroelectric materials, it is necessary to grow hafnium-based ferroelectric materials first and then grow polysilicon channels, which will cause the ferroelectric layer to change from the ferroelectric phase to the paraelectric phase, and the storage function will disappear.

[0054] In view of this, the present application provides a ferroelectric 3D NAND flash memory device and a method for manufacturing the same to improve the operating speed of the 3D NAND flash memory device. In the method for manufacturing the 3D NAND flash memory device, a polysilicon channel is first grown and then a ferroelectric layer is grown to prevent the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing during the growth of the polysilicon channel, thereby affecting the storage function of the 3D NAND flash memory device.

[0055] Specifically, Figure 1As shown, the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application includes:

[0056] A substrate 10, optionally, the substrate 10 is a silicon substrate;

[0057] A stacked structure 20 located on the first surface of the substrate 10, the stacked structure 20 comprising a plurality of gate dielectric oxide layers 21 and gate electrode layers 22 arranged in an interlaced manner in a direction perpendicular to the plane of the substrate, optionally, the gate dielectric oxide layer 21 is an isolation oxide layer, such as a silicon dioxide layer, and the gate electrode layer 22 is a metal layer, such as a tungsten metal layer, but the present application does not limit this, and it depends on the specific situation;

[0058] A channel hole penetrating the stacked structure 20 , wherein the channel hole extends into the first surface of the substrate 10 ;

[0059] A first isolation layer 30 located on the sidewall of the channel hole, the first isolation layer is used to isolate the metal gate (i.e., the gate electrode layer) from the channel layer. Optionally, the first isolation layer may be a silicon dioxide layer, or an aluminum dioxide layer or a high-K oxide such as hafnium dioxide. The present application does not limit this, and the specific conditions may vary;

[0060] A channel layer 40 covering the first isolation layer 30 and the bottom of the channel hole. Optionally, the channel layer 40 may be a polysilicon layer, an IGZO layer, or a thin layer of molybdenum disulfide layer, which is not limited in the present application and depends on the specific circumstances;

[0061] A ferroelectric layer 50 located on the surface of the channel layer 40;

[0062] A back gate layer 60 located on the surface of the ferroelectric layer 50;

[0063] A filling layer 70 for filling the remaining space of the channel hole. Optionally, the filling layer 70 is an oxide layer, such as a silicon dioxide layer, for filling the channel hole and playing a supporting role;

[0064] an insulating layer 80 covering the channel hole and the stacked structure 20, the insulating layer 80 having a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer 40, and the second through hole exposes at least a portion of the surface of the back gate layer 60;

[0065] A drain electrode 91 electrically connected to the channel layer 40 through the first through hole and a back gate electrode 92 electrically connected to the back gate layer 60 through the second through hole.

[0066] The ferroelectric 3D NAND flash memory device provided in the embodiment of the present application utilizes a ferroelectric layer as a charge storage layer, and the ferroelectric material has a faster flipping speed under an electric field, so that the operation speed of the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application is faster, which is specifically manifested in that the programming speed and the erasing speed become faster, so as to improve the performance of the ferroelectric 3D NAND flash memory device, thereby meeting the users' increasingly higher requirements for 3D NAND flash memory devices.

[0067] Moreover, in the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application, the ferroelectric layer is located on the surface of the channel layer, that is, when the ferroelectric 3D NAND flash memory device is manufactured, the channel layer is manufactured first, and then the ferroelectric layer is manufactured, thereby preventing the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing during the manufacturing process of the channel layer, thereby preventing the occurrence of a phenomenon that affects the storage function of the 3D NAND flash memory device.

[0068] Optionally, in an embodiment of the present application, the ferroelectric layer is a single-layer ferroelectric thin film. Specifically, the single-layer ferroelectric thin film may be a hafnium zirconium oxide thin film.

[0069] In another embodiment of the present application, the ferroelectric layer also includes a silicon dioxide layer located on the surface of the single-layer ferroelectric film away from the channel layer, that is, the ferroelectric layer includes a single-layer ferroelectric film and a silicon dioxide layer arranged in a direction away from the channel layer, so that the silicon dioxide layer plays a role of transition and isolation between the channel layer and the single-layer ferroelectric film, thereby preventing excessive leakage current from being generated between the channel layer and the single-layer ferroelectric film, and at the same time, the thermal expansion coefficient of the silicon dioxide layer is used to induce the single-layer ferroelectric film to form a ferroelectric phase.

[0070] On the basis of any of the above embodiments, in one embodiment of the present application, the thickness of the ferroelectric layer ranges from 8 nm to 12 nm, and the present application does not impose any limitation thereto, and the specific thickness depends on the circumstances.

[0071] On the basis of any of the above embodiments, in one embodiment of the present application, the back gate layer is made of a metal material that can induce the ferroelectric layer to form a ferroelectric phase, such as tungsten or titanium nitride, so that the thermal expansion coefficient of the back gate layer can induce the ferroelectric film to form a ferroelectric phase while ensuring that the back gate layer can be conductive. It should be noted that when the 3D NAND memory device is working, the back gate layer acts as an electrode plate for polarizing the ferroelectric layer, which is used to add a programming voltage or an erase voltage to achieve ferroelectric polarization reversal of the ferroelectric layer.

[0072] Accordingly, an embodiment of the present application further provides an operating method of a 3D NAND flash memory device, which is applied to the 3D NAND flash memory device provided by any of the above embodiments. Specifically, the 3D NAND flash memory device includes a plurality of storage units, and the operating method includes at least one of the following:

[0073] like Figure 2 As shown, when a read operation is performed on the 3D NAND flash memory device, a read voltage V is applied to the gate G of the memory cell to be read in the 3D NAND flash memory device. RD , the gate G of other memory cells in the same channel hole is applied with a voltage V PS , the drain D of each storage unit in the same channel hole is uniformly applied with a detection voltage R BL , to detect whether the memory cell to be read is turned on, and at the same time control the source S of each memory cell in the same channel hole to be uniformly connected to the zero potential GND and the back gate to be uniformly floating;

[0074] like Figure 3 As shown, when performing a programming operation on the 3D NAND flash memory device, the gate G of the memory cell to be programmed in the 3D NAND flash memory device is controlled to apply a programming voltage V PRG , the back gate is connected to zero potential GND, and the other electrodes are floating (that is, the gate G of other storage cells is floating, and the drain D and source S of each storage cell are also floating);

[0075] like Figure 4 As shown, when the 3D NAND flash memory device is erased, the gate G of the storage unit to be erased in the 3D NAND flash memory device is controlled to apply a zero potential GND, and the back gate is applied with an erase voltage V ERS , the source S and drain D of each storage unit are floating.

[0076] It should be noted that if Figure 4 As shown, when performing a programming operation on the 3D NAND flash memory device, if multiple storage cells need to be erased at the same time, the gates of all storage cells to be erased are connected to GND, and the back gates are applied with an erase voltage V ERS , the source S and drain D of each storage unit are floating.

[0077] In summary, the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application utilizes a ferroelectric layer as a charge storage layer, and the ferroelectric material has a faster flipping speed under an electric field, so that the operation speed of the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application is faster, which is specifically manifested in that the programming speed and the erasing speed become faster, so as to improve the performance of the ferroelectric 3D NAND flash memory device, thereby meeting the users' increasingly higher requirements for 3D NAND flash memory devices.

[0078] Moreover, in the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application, the ferroelectric layer is located on the surface of the channel layer, that is, when the ferroelectric 3D NAND flash memory device is manufactured, the channel layer is manufactured first, and then the ferroelectric layer is manufactured, thereby preventing the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing during the manufacturing process of the channel layer, thereby preventing the occurrence of a phenomenon that affects the storage function of the 3D NAND flash memory device.

[0079] In addition, the present application also provides a method for manufacturing a ferroelectric 3D NAND flash memory device, such as Figure 5 As shown, the production method includes:

[0080] S1: Figure 6 As shown, a substrate 10 is provided. Optionally, the substrate 10 is a silicon substrate.

[0081] S2: Figure 7 As shown, a stacked structure 20 is manufactured on the first surface of the substrate 10, and the stacked structure 20 includes a plurality of gate dielectric oxide layers 21 and gate electrode layers 22 which are staggeredly arranged along a direction perpendicular to the plane of the substrate. Optionally, the gate dielectric oxide layer 21 is an isolation oxide layer, which may be a silicon dioxide layer, and the gate electrode layer 22 is a metal layer, such as a tungsten metal layer, but the present application does not limit this, and it depends on the specific circumstances.

[0082] S3: Figure 8 As shown, a channel hole 23 penetrating the stacked structure 20 is manufactured, and the channel hole 23 extends into the first surface of the substrate 10. Optionally, the channel hole is formed by an etching process.

[0083] S4: forming a first isolation layer on the sidewall of the channel hole.

[0084] Optionally, in one embodiment of the present application, forming a first isolation layer on the sidewall of the channel hole includes:

[0085] like Fig. 9 As shown, a first isolation layer 30 is formed on the surface of the channel hole 23 and the surface of the stacked structure 20 away from the substrate 10 by atomic layer deposition. The function of the first isolation layer is to isolate the metal gate (i.e., the gate electrode layer) from the subsequently formed channel layer;

[0086] like Fig.10 As shown, the first isolation layer 30 is etched to remove the first isolation layer 30 located at the bottom of the channel hole 23 and the portion located on the surface of the stack structure 20 away from the substrate 10 to ensure that the subsequently manufactured channel layer can be connected to the substrate.

[0087] On the basis of the above-mentioned embodiments, in one embodiment of the present application, after the first isolation layer is produced, the method further includes: performing ion implantation into the substrate through the channel hole so that the substrate portion located at the bottom of the channel hole forms an ohmic contact with a subsequently formed channel layer having a relatively low contact resistance, but the present application does not limit this and it depends on the specific circumstances.

[0088] Specifically, in one embodiment of the present application, the first isolation layer may be a silicon dioxide layer, or may be an aluminum dioxide layer or a high-K oxide such as hafnium dioxide. The present application does not limit this, and it depends on the specific circumstances.

[0089] S5: sequentially manufacturing a channel layer, a ferroelectric layer, a back gate layer covering the first isolation layer and the bottom of the channel hole, and a filling layer filling the remaining space of the channel hole.

[0090] Specifically, in one embodiment of the present application, sequentially manufacturing a channel layer covering the surface of the first isolation layer and the bottom of the channel hole, a ferroelectric layer, a back gate layer, and a filling layer filling the remaining space of the channel hole comprises:

[0091] like Fig.11 As shown, a channel layer 40 is manufactured to cover the surface of the first isolation layer 30, the bottom of the channel hole, and the surface of the stacked structure 20 away from the substrate 10;

[0092] like Fig.12 As shown, a ferroelectric layer 50 is formed to cover the surface of the channel layer 40;

[0093] like Fig.13 As shown, a back gate layer 60 is formed to cover the surface of the ferroelectric layer 50 away from the channel layer 30;

[0094] like Fig.14 As shown, a filling layer 70 is formed to cover the surface of the back gate layer 60 away from the ferroelectric layer 50 and fill the remaining space of the channel hole. Optionally, the filling layer 70 is an oxide layer, such as a silicon dioxide layer, to fill the channel hole and play a supporting role;

[0095] like Fig.15 As shown, portions of the channel layer 40 , the ferroelectric layer 50 , the back gate layer 60 , and the filling layer 70 located on the surface of the stacked structure 20 away from the substrate 10 are removed.

[0096] Optionally, in one embodiment of the present application, forming a channel layer covering the surface of the first isolation layer, the bottom of the channel hole, and the surface of the stack structure on the side away from the substrate includes: using chemical vapor deposition to form a channel layer covering the surface of the first isolation layer, the bottom of the channel hole, and the surface of the stack structure on the side away from the substrate. Specifically, the channel layer is a channel film, and its material can be polysilicon or other channel materials, such as IGZO (indium gallium zinc oxide) and a thin layer of molybdenum disulfide (MoS2). The present application does not limit this and it depends on the specific circumstances.

[0097] It should be noted that when the material of the channel layer is polysilicon material, after the polysilicon material layer is grown, it is necessary to perform an annealing operation on the polysilicon material layer to ensure that the deposited polysilicon material layer can form a polysilicon film with a suitable grain size.

[0098] Based on any of the above embodiments, in one embodiment of the present application, the ferroelectric layer is a single-layer ferroelectric thin film. In this embodiment, making the ferroelectric layer covering the surface of the channel layer includes: growing the ferroelectric layer on the surface of the channel layer by atomic layer deposition, and optionally, the thickness of the ferroelectric layer ranges from 8 nm to 12 nm, which is not limited in the present application and depends on the specific situation.

[0099] In another embodiment of the present application, the ferroelectric layer includes a single-layer ferroelectric film and a silicon dioxide layer arranged in a direction away from the channel layer, so that the silicon dioxide layer plays a transition and isolation role between the channel layer and the single-layer ferroelectric film, and at the same time, the thermal expansion coefficient of the silicon dioxide layer is used to induce the single-layer ferroelectric film to form a ferroelectric phase. In this embodiment, making the ferroelectric layer covering the surface of the channel layer includes:

[0100] First, a silicon dioxide layer is grown on the surface of the channel layer by atomic layer deposition. Optionally, the thickness of the silicon dioxide layer is in the range of 1 nm to 3 nm, which is not limited in the present application and depends on the specific situation.

[0101] A ferroelectric layer is then grown on the surface of the silicon dioxide layer by atomic layer deposition. Optionally, the thickness of the ferroelectric layer ranges from 8 nm to 12 nm, which is not limited in the present application and depends on specific circumstances.

[0102] Based on any of the above embodiments, in one embodiment of the present application, the back gate layer uses a metal material that can easily induce the ferroelectric film to form a ferroelectric phase, such as tungsten or titanium nitride, so that the thermal expansion coefficient of the back gate layer can induce the ferroelectric film to form a ferroelectric phase while ensuring that the back gate layer can be conductive.

[0103] Based on any of the above embodiments, in one embodiment of the present application, removing the channel layer, the ferroelectric layer, the back gate layer and the filling layer located on the surface of the stack structure away from the substrate includes: using chemical mechanical grinding and polishing to remove the channel layer, the ferroelectric layer, the back gate layer and the filling layer located on the surface of the stack structure away from the substrate, but the present application does not limit this and it depends on the specific circumstances.

[0104] S6: Make an insulating layer covering the channel hole and the stacking structure to play an insulating role, the insulating layer has a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer to facilitate the lead-out of the electrode in the subsequent channel hole.

[0105] Optionally, in one embodiment of the present application, manufacturing an insulating layer covering the channel hole and the stacked structure, wherein the insulating layer has a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer comprises:

[0106] like Fig.16 As shown, an insulating layer 80 covering the channel hole and the stacking structure is manufactured. Optionally, the insulating layer 80 is a silicon dioxide layer to play an insulating role;

[0107] like Fig.17 As shown, the insulating layer 80 is etched to form a first through hole 81 and a second through hole 82 in the insulating layer 80 , wherein the first through hole 81 exposes at least a portion of the surface of the channel layer 40 , and the second through hole 82 exposes at least a portion of the surface of the back gate layer 60 .

[0108] S7: Fig.18 As shown, a drain electrode 91 electrically connected to the channel layer 40 through the first through hole and a back gate electrode 92 electrically connected to the back gate layer 60 through the second through hole are manufactured.

[0109] Optionally, in one embodiment of the present application, manufacturing the drain electrode electrically connected to the channel layer through the first through hole and the back gate electrode electrically connected to the back gate layer through the second through hole includes:

[0110] Depositing a metal electrode layer, wherein the metal electrode layer covers the insulating layer and fills the first through hole and the second through hole;

[0111] The metal electrode layer is etched to retain the portion of the metal electrode layer located in the first through hole and the second through hole, so as to form a drain electrode electrically connected to the channel layer through the first through hole and a back gate electrode electrically connected to the back gate layer through the second through hole.

[0112] In summary, the method for manufacturing the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application utilizes the ferroelectric layer as the charge storage layer, and the ferroelectric material has a faster flipping speed under an electric field, so that the operation speed of the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application is faster, which is specifically manifested in that the programming speed and the erasing speed become faster, so as to improve the performance of the ferroelectric 3D NAND flash memory device, thereby meeting the users' increasingly higher requirements for 3D NAND flash memory devices.

[0113] Moreover, in the ferroelectric 3D NAND flash memory device provided in the embodiment of the present application, the ferroelectric layer is located on the surface of the channel layer, that is, when the ferroelectric 3D NAND flash memory device is manufactured, the channel layer is manufactured first, and then the ferroelectric layer is manufactured, thereby preventing the ferroelectric phase of the ferroelectric layer from disappearing due to high-temperature growth and high-temperature annealing during the manufacturing process of the channel layer, thereby preventing the occurrence of a phenomenon that affects the storage function of the 3D NAND flash memory device.

[0114] In this specification, each embodiment is described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0115] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure marks throughout the embodiments of the specification identify the same structure. It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the article or equipment including a series of elements includes not only those elements, but also includes other elements that are not clearly listed, or also includes elements inherent to such articles or equipment. In the absence of more restrictions, the elements limited by the sentence "including one..." do not exclude the existence of other identical elements in the article or equipment including the above elements.

[0116] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A ferroelectric 3D NAND flash memory device, characterized in that: include: substrate; A stacked structure located on the first surface of the substrate, the stacked structure comprising a plurality of gate dielectric oxide layers and gate electrode layers arranged alternately in a direction perpendicular to the plane of the substrate; A channel hole penetrating the stacked structure, wherein the channel hole extends into the first surface of the substrate; a first isolation layer located on the sidewall of the channel hole; a channel layer covering the first isolation layer and the bottom of the channel hole; a ferroelectric layer located on a surface of the channel layer; A back gate layer located on the surface of the ferroelectric layer; A filling layer filling the remaining space of the channel hole; an insulating layer covering the channel hole and the stacked structure, the insulating layer having a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer; A drain electrode electrically connected to the channel layer through the first through hole and a back gate electrode electrically connected to the back gate layer through the second through hole.

2. The 3D NAND flash memory device according to claim 1, characterized in that: The ferroelectric layer is a single-layer ferroelectric thin film.

3. The 3D NAND flash memory device according to claim 2, characterized in that: The ferroelectric layer further comprises a silicon dioxide layer located on the surface of the single-layer ferroelectric film at a side away from the channel layer.

4. The 3D NAND flash memory device according to claim 1, characterized in that: The back gate is made of a metal material that can induce the ferroelectric layer to form a ferroelectric phase.

5. The 3D NAND flash memory device according to claim 4, characterized in that: The back gate is made of tungsten or titanium nitride.

6. The 3D NAND flash memory device according to claim 1, characterized in that: The channel layer is a polysilicon layer, an IGZO layer, or a thin molybdenum disulfide layer.

7. A method for operating a 3D NAND flash memory device, characterized in that: Applied to the 3D NAND flash memory device according to any one of claims 1 to 6, the 3D NAND flash memory device comprises a plurality of storage cells, and the operating method comprises at least one of the following: When performing a read operation on the 3D NAND flash memory device, a read voltage is applied to the gate of the memory cell to be read in the 3D NAND flash memory device, a pass voltage is applied to the gates of other memory cells in the same channel hole, a detection voltage is uniformly applied to the drains of the memory cells in the same channel hole to detect whether the memory cell to be read is turned on, and at the same time, the sources of the memory cells in the same channel hole are uniformly connected to a zero potential and the back gates are uniformly floated; When performing a programming operation on the 3D NAND flash memory device, controlling the gate of the memory cell to be programmed in the 3D NAND flash memory device to apply a programming voltage, connecting the back gate to a zero potential, and leaving other electrodes floating; When performing an erase process operation on the 3D NAND flash memory device, the gate of the storage unit to be erased in the 3D NAND flash memory device is controlled to apply a zero potential, the back gate is applied with an erase voltage, and the source and the drain are floating.

8. A method for manufacturing a ferroelectric 3D NAND flash memory device, characterized in that: include: providing a substrate; Fabricate a stacked structure on the first surface of the substrate, wherein the stacked structure includes a plurality of gate dielectric oxide layers and gate electrode layers arranged alternately in a direction perpendicular to the plane of the substrate; Making a channel hole penetrating the stacked structure, wherein the channel hole extends into the first surface of the substrate; Forming a first isolation layer on the sidewall of the channel hole; Sequentially forming a channel layer, a ferroelectric layer, a back gate layer covering the first isolation layer and the bottom of the channel hole, and a filling layer filling the remaining space of the channel hole; Manufacturing an insulating layer covering the channel hole and the stacked structure, wherein the insulating layer has a first through hole and a second through hole, wherein the first through hole exposes at least a portion of the surface of the channel layer, and the second through hole exposes at least a portion of the surface of the back gate layer; A drain electrode electrically connected to the channel layer through the first through hole and a back gate electrode electrically connected to the back gate layer through the second through hole are manufactured.

9. The manufacturing method according to claim 8, characterized in that: Sequentially manufacturing a channel layer, a ferroelectric layer, a back gate layer covering the surface of the first isolation layer and the bottom of the channel hole, and a filling layer filling the remaining space of the channel hole comprises: Manufacturing a channel layer covering the surface of the first isolation layer, the bottom of the channel hole, and the surface of the stack structure away from the substrate; Making a ferroelectric layer covering the surface of the channel layer; Making a back gate layer covering the surface of the ferroelectric layer away from the channel layer; Making a filling layer that covers the surface of the back gate layer away from the ferroelectric layer and fills the remaining space of the channel hole; The channel layer, the ferroelectric layer, the back gate layer and the filling layer are removed from a portion of the surface of the stacked structure away from the substrate.

10. The manufacturing method according to claim 8, characterized in that: After the first isolation layer is manufactured and before the channel layer is manufactured, the method further includes: implanting ions into the substrate through the channel hole.

Images