Deep trench capacitor unit, deep trench capacitor and preparation method thereof
By etching L-shaped trenches on the substrate of the deep trench capacitor and adopting a rotationally symmetrical array arrangement, the problems of substrate warping and capacitor consistency and reliability in the existing technology are solved, and a more uniform stress distribution is achieved. and higher capacitance density.
Patent Information
- Application Number
- CN202411436712.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-15
- Publication Date
- 2025-01-21
AI Technical Summary
In the process of increasing the capacitance density, existing deep trench capacitors lead to an increase in the warpage of the substrate, affecting subsequent processing and packaging, and reducing the consistency and reliability of the capacitor.
The design of the L -shaped groove is used to etch on the substrate, and a deep groove with a uniform distribution is formed through the L -shaped groove and the symmetrical array discharge of the rotating symmetrical array to reduce the stress concentration and reduce the warranty of the substrate.
It effectively reduces the warpage of the substrate and improves the consistency and reliability of the capacitor. At the same time, the L-shaped trench structure is easy to prepare and optimizes the layout space.
Smart Images
Figure CN119342843A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of capacitors, and in particular relates to a deep trench capacitor unit, a deep trench capacitor and a preparation method thereof. Background Art
[0002] Deep trench capacitors are capacitors used in logic chips, high-density integrated circuits, automotive electronics and other fields. Compared with other capacitors, deep trench capacitors have higher effective area, higher capacitance, lower equivalent series resistance and lower equivalent series inductance than MIM capacitors; compared with multi-layer ceramic capacitors, they have higher voltage and temperature stability and smaller size.
[0003] In order to increase the capacitance density, existing deep trench capacitors usually use deep silicon etching technology, that is, forming a vertical downward, closely adjacent trench structure in the substrate, and growing multiple layers of metal and dielectric layers in the trench structure. This method can effectively improve the capacitance density of deep trench capacitors. Usually, in order to increase the arrangement density of the capacitor array, the grooves will be arranged in parallel. Due to the difference in thermal expansion coefficients of the dielectric layer, the metal layer and the substrate, the warping of the substrate will increase, which will have a more serious impact on the subsequent processing and packaging measurement operations of the deep trench capacitor, and will also reduce the consistency and reliability of the deep trench capacitor. Summary of the invention
[0004] The present invention overcomes the deficiencies of the prior art and provides a deep trench capacitor unit, a deep trench capacitor and a preparation method thereof to solve the problems existing in the prior art.
[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a deep trench capacitor unit, comprising a substrate, on which a plurality of square units are arranged, the square units are evenly distributed on the substrate, the square units include at least one group of units, the sub-units include a plurality of L-shaped grooves of different sizes, the long sides of the L-shaped grooves are arranged along a first direction, the short sides of the L-shaped grooves are arranged along a second direction, and the L-shaped grooves of the same size are distributed in positive and negative symmetry to form a rectangular cavity.
[0006] In a preferred embodiment of the present invention, the length of the L-shaped groove in the first direction is
[0007] H=(2N-1)nw+(2Nn-n-1)d
[0008] The length of the L-shaped groove in the second direction is
[0009] h=2nw+(2n-1)d
[0010] in:
[0011] w is the width of the L-shaped groove;
[0012] d is the distance between adjacent L-shaped grooves;
[0013] N is the number of subunits;
[0014] n is the number of L-shaped grooves.
[0015] In a preferred embodiment of the present invention, the L-shaped groove has a depth of 1-100 um, a width of 0.1-20 um, a spacing between adjacent L-shaped grooves of 0.1-20 um, and the L-shaped groove is formed in the substrate by etching.
[0016] In a preferred embodiment of the present invention, the substrate is one of silicon, high-resistance silicon, polysilicon and glass, and the thickness of the substrate is 50-750 um.
[0017] The present invention also provides a deep trench capacitor, including a deep trench capacitor unit, and also including a dielectric layer and a metal layer, wherein the dielectric layer and the metal layer are sequentially deposited in the deep trench and are alternately arranged in the deep trench.
[0018] In a preferred embodiment of the present invention, the medium of the dielectric layer is one or more combinations of ZrO2, Al2O3, HfO2, SiN, SiO2, and the thickness of the dielectric layer is 1-500nm.
[0019] In a preferred embodiment of the present invention, the metal of the metal layer is one of TiN, Al, Cu, TaN, and Poly Si, and the thickness of the metal layer is 5-500 nm.
[0020] The present invention also discloses a method for preparing a deep trench capacitor, comprising the following steps:
[0021] S1. Deep trench etching: etching a plurality of L-shaped trenches on the substrate so that the L-shaped trenches form deep trenches on the substrate;
[0022] S2, the first step of deposition: depositing the metal layer and the dielectric layer in the deep trench in sequence to form a capacitor structure;
[0023] S3, second step deposition: depositing a protective layer on the surface and sidewall of the metal layer and the dielectric layer to protect the metal layer and the dielectric layer;
[0024] S4, patterned etching: etching the alternately deposited dielectric layers and metal layers in sequence to ensure that the metal layer of each layer is partially exposed for electrical connection;
[0025] S5. Deposit ILD layer: the material is 0.01-10um SiO2 material, and the deposition method is one of the following: atomic layer deposition, plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition;
[0026] S6, ILD layer patterning: etching SiO2 material to stop at SiNx protective layer, using one of the following etching methods: inductively coupled plasma etching, reactive ion etching, ion beam etching, after etching stops SiNx, adjusting etching parameters, and continuing to further etch the metal layer window of the capacitor structure;
[0027] S7. Interconnection metal preparation: The metal is filled by the following methods: atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, and the filled metal material is one of the following: W, Al, Cu.
[0028] The present invention solves the defects existing in the background technology and has the following beneficial effects:
[0029] Generally, the common simple substrate groove shape is a rectangular array arrangement, which will make the stress concentration phenomenon in the long side direction of the rectangle much greater than that in the short side direction, causing excessive warping of the substrate. The present invention etches L-shaped grooves on the substrate, and forms evenly distributed deep grooves through L-shaped grooves and rotationally symmetrical array arrangement design. When there are L-shaped grooves on the substrate, the direction is limited to the width direction of the L-shaped groove as the second direction, and the length direction of the L-shaped groove as the first direction. Usually, the width of the L-shaped groove is smaller than the length of the L-shaped groove. The stress concentration lines of the L-shaped groove are interrupted by each other in the length and width directions. At the same time, the length of the stress concentration lines in the same direction is reduced, so that the stress distribution of the groove array is uniform and the stress concentration in a certain direction is avoided, so as to achieve the purpose of reducing the substrate warping. At the same time, the structure of the L-shaped groove is easy to prepare, so that the layout space is more optimized. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] The present invention is further described below in conjunction with the accompanying drawings and embodiments;
[0031] Figure 1 This is a schematic structural diagram of a deep trench capacitor unit according to a first preferred embodiment of the present invention;
[0032] Figure 2 for Figure 1 Schematic diagram of the local structure;
[0033] Figure 3 This is a schematic structural diagram of a deep trench capacitor according to a second preferred embodiment of the present invention;
[0034] Figure 4 This is a flow chart of Embodiment 3 of the preferred embodiment of the present invention;
[0035] Figure 5 This is a schematic diagram of the capacitor structure formed in Example 3 of the preferred embodiment of the present invention;
[0036] In the figure: 10, substrate; 11, square unit; 111, subunit; 1111, L-shaped groove; 20, dielectric layer; 30, metal layer. DETAILED DESCRIPTION
[0037] The following will disclose multiple embodiments of the present invention with drawings. For the purpose of clear description, many physical details will be described together in the following description. However, it should be understood that these physical details should not be used to limit the present invention. That is, in some embodiments of the present invention, these physical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and components will be depicted in a simple schematic manner in the drawings.
[0038] In addition, in the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes, and do not specifically refer to the order or sequence, nor are they used to limit the present invention. They are only used to distinguish components or operations described with the same technical terms, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.
[0039] Embodiment 1
[0040] The present embodiment provides a deep trench capacitor unit, which can effectively reduce the warping degree of the substrate 10 to facilitate subsequent processing and packaging of the capacitor.
[0041] Combination Figure 1 and Figure 2As shown, the deep trench capacitor unit of this embodiment includes a substrate 10, on which a plurality of square units 11 are arranged, the square units 11 are evenly distributed on the substrate 10, the square units 11 include at least one group of units 111, the sub-units 111 include a plurality of L-shaped grooves 1111 of different sizes, the long sides of the L-shaped grooves 1111 are arranged along a first direction, the short sides of the L-shaped grooves 1111 are arranged along a second direction, and the L-shaped grooves 1111 of the same size are distributed in positive and negative symmetry to form a rectangular cavity. In this embodiment, the L-shaped grooves 1111 are etched on the substrate 10 by dry etching or wet etching. 1111 will form a corresponding deep groove. When there is an L-shaped groove 1111 on the substrate, the direction is limited to the width direction of the L-shaped groove 1111 as the second direction, and the length direction of the L-shaped groove 1111 as the first direction. Usually, the width of the L-shaped groove 1111 is smaller than the length of the L-shaped groove 1111. The stress concentration lines of the L-shaped groove 1111 are interrupted by each other in the length and width directions. At the same time, the length of the stress concentration lines in the same direction is reduced, so that the stress distribution is uniform and excessive stress concentration is avoided, so as to achieve the purpose of reducing the warping of the substrate. At the same time, the structure of the L-shaped groove 1111 is easy to prepare, so that the layout space is more optimized.
[0042] In this embodiment, the length of the L-shaped groove 1111 in the first direction is
[0043] H=(2N-1)nw+(2Nn-n-1)d
[0044] The length of the L-shaped groove 1111 in the second direction is
[0045] h=2nw+(2n-1)d
[0046] in:
[0047] w is the width of the L-shaped groove 1111;
[0048] d is the distance between adjacent L-shaped grooves 1111;
[0049] N is the number of subunits 111;
[0050] n is the number of L-shaped grooves 1111 .
[0051] Specifically, the L-shaped groove 1111 has a depth of 1-100 um, a width of 0.1-20 um, a spacing between adjacent L-shaped grooves 1111 of 0.1-20 um, and the L-shaped groove 1111 is formed in the substrate 10 by etching.
[0052] In this embodiment, the substrate 10 is one of silicon, high-resistance silicon, polysilicon and glass, and the thickness of the substrate 10 is 50-750 um.
[0053] The deep trench capacitor unit of the present embodiment is formed by a substrate 10 and a deep trench, and the deep trench is formed by a plurality of L-shaped grooves 1111. The L-shaped groove 1111 is formed inside the substrate 10 by dry etching or wet etching. When the width of the L-shaped groove 1111 is smaller than the length of the L-shaped groove 1111, compared with the structure without a groove, the stress line in the second direction is interrupted by the periodic L-shaped grooves 1111, so that the stress in the second direction is smaller than that in the structure without a groove. Due to the shape of the L-shaped groove 1111 in the first direction, the stress is concentrated in the first direction, and the stress is greater than that in the structure without a groove. The L-shaped groove 1111 can effectively interrupt the stress concentration in the second direction and the first direction, so as to achieve the purpose of reducing the warping of the substrate 10. At the same time, the structure of the L-shaped groove 1111 is easy to prepare, so that the layout space is more optimized.
[0054] Embodiment 2
[0055] like Figure 3 As shown, the present embodiment provides a deep trench capacitor, including a deep trench capacitor unit, and also including a dielectric layer 20 and a metal layer 30. The dielectric layer 20 and the metal layer 30 are sequentially deposited in the deep trench and are alternately arranged in the deep trench. When a single-layer capacitor needs to be prepared, a dielectric layer 20 and two metal layers 30 are deposited in the deep trench. When a multilayer capacitor needs to be prepared, the dielectric layer 20 and the metal layer 30 are alternately deposited in the deep trench. The capacitor of the present embodiment selects a suitable material and thickness according to different capacitance values and breakdown characteristics.
[0056] Specifically, the medium of the dielectric layer 20 is one or more combinations of ZrO2, Al2O3, HfO2, SiN, SiO2, the thickness of the dielectric layer 20 is 1-500nm, the metal of the metal layer 30 is one of TiN, Al, Cu, TaN, Poly Si, the thickness of the metal layer 30 is 5-500nm.
[0057] Embodiment 3
[0058] Combination Figure 4 and Figure 5 As shown, this embodiment discloses a method for preparing a deep trench capacitor, comprising the following steps:
[0059] S1. Deep trench etching: etching a plurality of L-shaped grooves 1111 on the substrate 10, so that the L-shaped grooves 1111 form deep grooves on the substrate 10. Dry etching or wet etching can form the L-shaped grooves 1111 on the substrate 10. The plurality of L-shaped grooves 1111 form deep grooves. The L-shaped grooves 1111 can effectively disconnect the stress concentration in the first direction and the second direction, so as to reduce the warping of the substrate 10.
[0060] S2, the first step of deposition: depositing the metal layer 30 and the dielectric layer 20 in the deep trench in sequence to form a capacitor structure. The number and material of the metal layer 30 and the dielectric layer 20 are selected according to the different capacitance values and breakdown characteristics of the capacitor, and the thickness of each metal layer 30 or dielectric layer 20 can be varied;
[0061] S3, second step of deposition: depositing a protective layer on the surface and sidewall of the metal layer 30 and the dielectric layer 20 to protect the metal layer 30 and the dielectric layer 20. The protective layer of this embodiment is used as a protective layer for the metal layer 30 and the dielectric layer 20, and also as an etching stop layer for the ILD dielectric layer 20. The protective layer can protect the surface and sidewall of the metal layer 30 and the dielectric layer 20, and the thickness thereof is 5-500 nm, thereby ensuring coverage of the surface and sidewall of the metal layer 30 and the dielectric layer 20.
[0062] S4, patterned etching: etching the alternately deposited dielectric layer 20 and metal layer 30 in sequence to ensure that a portion of the metal layer 30 of each layer is exposed for electrical connection. The etching method is not limited to dry or wet etching. The dry etching gas is usually SF6, HBr, O2, C4F8, Cl2, BCl3 or a mixed gas thereof;
[0063] S5. Deposit ILD layer: the material is 0.01-10um SiO2 material, and the deposition method includes but is not limited to atomic layer deposition, plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition;
[0064] S6, ILD layer patterning: etching SiO2 material to stop at the SiNx protective layer. Due to the different depths, SiNx / SiO2 needs to have a larger etching selectivity ratio. The commonly used etching methods include but are not limited to inductively coupled plasma etching, reactive ion etching, ion beam etching, etc. After etching stops SiNx, the etching parameters are adjusted, and the metal layer 30 of the capacitor structure is further etched to open windows;
[0065] S7. Interconnection metal preparation: Filling methods include but are not limited to atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, etc. The filling metal material can be selected from W, Al, Cu, etc.
[0066] In combination with Embodiments 1 to 3, the present invention provides a deep trench capacitor unit, a deep trench capacitor and a method for preparing the same. An L-shaped groove 1111 exists in the substrate 10 of the deep trench capacitor. The L-shaped groove 1111 can effectively disconnect the stress concentration in the second direction and the first direction, thereby reducing the degree of warping of the substrate 10. The L-shaped groove 1111 is easy to process, which is conducive to optimizing the spatial layout.
[0067] Although the present invention has been described above with reference to various embodiments, it should be understood that many changes and modifications may be made without departing from the scope of the present invention. That is, the methods, systems or devices discussed above are all examples. Various configurations may appropriately omit, replace or add various processes or components. For example, in alternative configurations, the method may be performed in an order different from the order described, and / or various stages may be added, omitted and / or combined. Moreover, the features described with respect to certain configurations may be combined in various other configurations. Different aspects and elements of the configurations may be combined in a similar manner. In addition, with the development of technology, many elements are merely examples and do not limit the scope of the present disclosure or claims.
[0068] Specific details are given in the specification to provide a thorough understanding of the exemplary configurations including implementations. However, the configurations can be practiced without these specific details, for example, well-known circuits, processes, algorithms, structures, and techniques have been shown without unnecessary details to avoid obscuring the configurations. This description provides only example configurations and does not limit the scope, applicability, or configurations of the claims. On the contrary, the foregoing description of the configurations will provide those skilled in the art with an enabling description for implementing the described techniques. Various changes may be made to the functions and arrangements of the elements without departing from the spirit or scope of the present disclosure.
[0069] In addition, although each operation may describe the operation as a sequential process, many operations may be performed in parallel or simultaneously. In addition, the order of the operations may be rearranged. A process may have additional steps. In addition, examples of methods may be implemented by hardware, software, firmware, middleware, code, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or code, program code or code segments for performing the necessary tasks may be stored in a non-transitory computer-readable medium such as a storage medium, and the described tasks are performed by a processor.
[0070] In summary, it is intended that the above detailed description is considered to be exemplary rather than restrictive, and it should be understood that the claims (including all equivalents) are intended to limit the spirit and scope of the present invention. The above embodiments should be understood to be only used to illustrate the present invention and not to limit the scope of protection of the present invention. After reading the content of the record of the present invention, the technician can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall into the scope limited by the claims of the present invention.
Claims
1. A deep trench capacitor unit, characterized in that: The invention comprises a substrate (10), wherein a plurality of square units (11) are arranged on the substrate (10), wherein the square units (11) are evenly distributed on the substrate (10), wherein the square units (11) comprise at least one group of units (111), wherein the group of units (111) comprises a plurality of L-shaped grooves (1111) of different sizes, wherein the long sides of the L-shaped grooves (1111) are arranged along a first direction, and the short sides of the L-shaped grooves (1111) are arranged along a second direction, and wherein the L-shaped grooves (1111) of the same size are distributed in a positive and negative symmetric manner to form a rectangular cavity.
2. A deep trench capacitor unit according to claim 1, characterized in that: The length of the L-shaped groove (1111) in the first direction is H=(2N-1)nw+(2Nn-n-1)d The length of the L-shaped groove (1111) in the second direction is h=2nw+(2n-1)d in: w is the width of the L-shaped groove (1111); d is the distance between adjacent L-shaped grooves (1111); N is the number of the subunits (111); n is the number of L-shaped grooves (1111).
3. A deep trench capacitor unit according to claim 2, characterized in that: The L-shaped groove (1111) has a depth of 1-100 um and a width of 0.1-20 um, and a spacing between adjacent L-shaped grooves (1111) is 0.1-20 um. The L-shaped groove (1111) is formed in the substrate (10) by etching.
4. The deep trench capacitor unit according to claim 1, characterized in that: The substrate (10) is one of silicon, high-resistance silicon, polysilicon and glass, and the thickness of the substrate (10) is 50-750 um.
5. A deep trench capacitor, comprising a deep trench capacitor unit according to any one of claims 1 to 4, characterized in that: It also comprises a dielectric layer (20) and a metal layer (30), wherein the dielectric layer (20) and the metal layer (30) are sequentially deposited in the deep trench and are alternately arranged in the deep trench.
6. The deep trench capacitor according to claim 5, characterized in that: The medium of the dielectric layer (20) is one or more combinations of ZrO2, Al2O3, HfO2, SiN, and SiO2, and the thickness of the dielectric layer (20) is 1-500 nm.
7. The deep trench capacitor according to claim 5, characterized in that: The metal of the metal layer (30) is one of TiN, Al, Cu, TaN and Poly Si, and the thickness of the metal layer (30) is 5-500 nm.
8. A method for preparing a deep trench capacitor, applied to a deep trench capacitor according to any one of claims 5 to 7, characterized in that: The following steps are involved: S1, deep groove etching: etching a plurality of L-shaped grooves (1111) on the substrate (10), so that the L-shaped grooves (1111) form deep grooves on the substrate (10); S2, the first step of deposition: depositing the metal layer (30) and the dielectric layer (20) in sequence in the deep trench to form a capacitor structure; S3, second step of deposition: depositing a protective layer on the surface and sidewall of the metal layer (30) and the dielectric layer (20) to protect the metal layer (30) and the dielectric layer (20); S4, patterned etching: etching the alternately deposited dielectric layers (20) and metal layers (30) in sequence to ensure that a portion of the metal layer (30) of each layer is exposed for electrical connection; S5. Deposit ILD layer: the material is 0.01-10um SiO2 material, and the deposition method is one of the following: atomic layer deposition, plasma enhanced chemical vapor deposition and low pressure chemical vapor deposition; S6, ILD layer patterning: etching the SiO2 material until the SiNx protective layer stops, using one of the following etching methods: inductively coupled plasma etching, reactive ion etching, ion beam etching, adjusting the etching parameters after the SiNx etching stops, and continuing to further etch the metal layer (30) of the capacitor structure; S7. Interconnection metal preparation: The metal is filled by the following methods: atomic layer deposition, chemical vapor deposition, physical vapor deposition, electroplating, and the filled metal material is one of the following: W, Al, Cu.