Transistor device

Abstract

A transistor device is a bipolar transistor having a semiconductor structure including channels of the same semiconductor type as a collector region and an emitter region. The channel is thinner than the base region bordering it. According to the structure, the current gain can be improved, and when the transistor device is turned on, the working mode of unipolar conduction or bipolar conduction can be realized by selectively controlling the voltage penetrating through the emitter terminal and the collector terminal.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of the invention patent application with application date of December 9, 2021, application number 202180083276.9, and invention name “A transistor device”. Technical Field

[0003] The present invention relates to a transistor device, and more particularly to a transistor device having a current gain characteristic superior to that of a conventional lateral bipolar junction transistor (BJT). Background Art

[0004] The semiconductor structure and corresponding structural configuration of the BJT make the current (controlled current) between its emitter and collector the result of the movement of electron and hole charge carriers, which is called bipolar conduction.

[0005] In contrast, in a field effect transistor (FET) or junction field effect transistor (JFET), the current between the source and drain terminals (the controlled current) is primarily due to the movement of either electrons or holes, and not both. This is called unipolar conduction or single-carrier operation.

[0006] US6251716B1, US200316704A1, US2009206375, US4496963, EP0268426, WO2011 / 053932 and US6251716 relate to JFETs, the current between the source and the drain of which is mainly due to unipolar conduction. That is, those skilled in the art are generally unable to obtain transistor devices that meet the requirements of practical applications. Summary of the invention

[0007] The main purpose of the present invention is to overcome the above-mentioned technical problems encountered in the prior art and provide a transistor device which, due to the presence of a channel, is different from a traditional BJT semiconductor structure and can be operated as a normally-on device or a normally-off device, depending on the voltage applied across the emitter terminal and the collector terminal.

[0008] In a first aspect, the present invention provides a transistor device having: a collector region provided by a first area of ​​a first type semiconductor; a collector terminal associated with the collector region; an emitter region provided by a second area of ​​the first type semiconductor; an emitter terminal associated with the emitter region; a base region provided by a third area of ​​a semiconductor located between and bordering the collector region and the emitter region; a base terminal associated with the base region; wherein the base region includes: a sub-region of the second type semiconductor, and a channel of the first type semiconductor, wherein the base terminal contacts the sub-region; the sub-region borders the channel to provide a first diode junction, and borders both the emitter region and the collector region to further form a plurality of diode junctions, the channel borders both the collector region and the emitter region and is interconnected with both, so that when the device is implemented in a circuit under a first condition, a voltage higher than a first threshold voltage is configured to pass through the emitter terminal and the collector terminal, and the base terminal is When floating or shorted to the emitter terminal, the current between the collector terminal and the emitter terminal is at least mainly due to unipolar conduction; the net doping concentration of the channel is less than the net doping concentration of the emitter region and the collector region; and the channel has a sufficiently small depth extending away from the first diode junction surface so that when the device is implemented in a circuit under a second condition, that is, the voltage across the emitter terminal and the collector terminal is lower than a first threshold voltage, and the base terminal, when floating or shorted to the emitter terminal, forms a depletion region near the first diode junction surface to constrain the channel so that there is substantially no current between the collector terminal and the emitter terminal of the device; and when the device is implemented in a circuit under a third condition, that is, a voltage is applied across the emitter terminal and the collector terminal, and the voltage across the emitter terminal and the base terminal causes a current to pass through the base terminal, the current between the collector terminal and the emitter terminal is at least mainly due to bipolar conduction.

[0009] Due to the presence of the channel, unlike the conventional BJT semiconductor structure, the device can be operated as a normally-on device or a normally-off device, depending on the voltage applied across the emitter terminal and the collector terminal.

[0010] The threshold voltage value is related to the length of the channel extending between the emitter region and the collector region, and thus is generally related to the separation distance between the emitter region and the collector region. Thus, for a desired emitter-collector voltage range, the transistor device can be made to operate in a normally-on or normally-off state by selecting the length of the channel.

[0011] The same shielding effect can be used to define the spacing of all transistor devices in the circuit. This has the advantage that it is possible to manufacture integrated circuits containing normally-on and normally-off transistors without requiring additional processing steps. Such circuits can be used to perform functions that would normally require the use of complementary transistors, such as NMOS and PMOS, which would require more semiconductor layers and / or production steps to implement. Further applications that may be based on this beneficial effect include logic gate circuits, analog comparators, and operational amplifier circuits.

[0012] When operating under the first condition, the voltage applied across the emitter and collector terminals (Vce) is greater than the first threshold and the transistor device acts as a normally-on device; the channel allows unipolar conduction between the collector and emitter terminals despite no current passing through the base terminal.

[0013] When operating under the second condition, the voltage across the emitter and collector terminals is below the first threshold, and the very small depth of the channel (depth being a function of the small depth of the semiconductor layer provided for the channel) means that the depletion region present near the first diode junction is sufficient to make the channel have a sufficiently high resistance to prevent current from passing through the channel.

[0014] In other words, when Vce is greater than the threshold, it is sufficient to overcome the depletion region, allowing current to flow between the emitter and collector. As the channel length increases, the Vce value required to overcome the depletion region also increases.

[0015] The very small absolute depth of the channel, and its relatively small depth compared to the depth of the base sub-division, means that when operating under the third condition, that is, when the voltage across the emitter terminal and the base terminal (Vbe) is greater than the forward bias voltage (bias voltage) of the base-emitter diode junction (Vft), a large part of the current through the base terminal will be due to bipolar conduction of the emitter and the base sub-division, rather than bipolar conduction of the channel.

[0016] Nevertheless, when operating under the third condition, the presence of the channel provides the transistor with improved gain characteristics compared to a BJT transistor with a conventional structure. This is because the channel provides a conduction path between the emitter and collector that does not need to pass through the diode junction and can provide a relatively low resistance.

[0017] One consequence of the operation of the present transistor device is that as the value of Vbe changes above Vft, the proportion of Ice attributable to bipolar conduction and unipolar conduction changes, and so the current gain of the transistor changes; as the proportion of bipolar conduction increases, the current gain decreases.

[0018] Another advantageous feature of the transistor design provided by the present invention is that by selecting the length of the channel within a known voltage range of Vce, the normally-off transistor can be switched on when the Vbe value is lower than the forward bias voltage of the base-emitter diode junction.

[0019] In other words, when the circuit operates under the fourth condition, that is, when the voltage across the emitter terminal and the collector terminal is between the first threshold (Vt) and the second threshold (Vt') (where |Vt'| < |Vt|), a transistor device operating as a normally-off transistor switches on when Vbe is less than the forward bias voltage (Vft) of the base-emitter diode junction.

[0020] When operating under the fourth condition, the current between the emitter and the collector is the result of unipolar conduction through the channel. Therefore, compared with the state under the fourth condition, the device has a higher gain, although the maximum current between the emitter and the collector is smaller.

[0021] When the transistor device is in the off state during operation and switches under the fourth condition, the channel is too long (when Vbe = 0), and for a Vce value less than the Vt value, it can overcome the depletion region near the first diode junction. However, if the channel is short enough, applying a small forward voltage across the base terminal and the emitter terminal (Vbe > 0) is not sufficient to overcome the depletion region near the base-emitter diode junction (Vbe < Vft), so that Ibe = 0, which is sufficient to weaken the depletion region near the first diode junction to an extent that allows current to flow between the emitter and the collector through the channel. The minimum value of Vbe required for the transistor device operating under the fourth condition will depend on the Vce and Vt values of the transistor device.

[0022] An embodiment of the present invention also discloses a driver circuit, which helps several first-stage transistors reduce bipolar conduction (i.e., more unipolar conduction - where there may be only unipolar conduction) to provide higher gain, while several second-stage transistors increase bipolar conduction to allow a higher rated current, and at the same time minimize the surface area (planar area) of the device.

[0023] For an embodiment of the present invention, the presence of the channel allows the transistor device to switch between on (operating under the first or fourth condition) and off in response to a change in Vbe less than the absolute value of the forward voltage of the base-emitter diode (Vft). This allows, for example, two transistor devices with the same configuration, such as both NPN or both PNP, to be used to switch the two sides (high and low) of the drive circuit, rather than according to the requirements of the prior art for a complementary circuit.

[0024] The appropriate depth of the channel will depend on the Vce value used for the operation of the transistor design and / or the doping concentration of the channel.

[0025] For example, for transistors designed to operate at voltages between 0 V and |5 V|, a channel depth of less than 0.25 μm (0.1 μm or less is better) may be suitable.

[0026] However, at a given operating voltage, the maximum depth allowed for the channel will be significantly less than would exist in a JFET designed to operate at a comparable operating voltage.

[0027] Conversely, the depth of the sub-region extending in the opposite direction from the first diode junction may be equal to or greater than five times the depth of the channel; in some embodiments, the depth of the sub-region may be at least twenty times the depth of the channel.

[0028] The sub-region may include a first portion and a second portion, and wherein: the first portion has a higher net doping concentration than the second portion; the base terminal is electrically connected to the second portion through the first portion; and wherein the second portion interfaces with the channel to provide the first diode junction, and interfaces with both the emitter region and the collector region to form the further diode junction. This ensures that a relatively highly doped region is used at the base contact to provide an ohmic contact, while a lower doped region interfaces with the channel, emitter region and collector region.

[0029] In order to ensure that bipolar conduction is dominant when operating under the third condition, the net doping concentration of the sub-divisions of the emitter region, the collector region and the base region, as well as the spacing between the emitter region and the collector region (also known as the base width) need to be carefully selected; the exact values ​​will depend on various variables, such as the expected operating voltage range of Vce and Vbe and the materials used in its semiconductor manufacturing process; the method for selecting the values ​​of the above variables is the same and common as the method for designing traditional BJT structures, so it will be easily understood by those familiar with the technology in this field.

[0030] The net doping concentration of the channel may be equal to or less than (e.g., between 0.1 and 1 times) the net doping concentration of the sub-region; this ensures that the depletion region at the first diode junction is preferentially present in the channel compared to the sub-region. For example, in the case where the channel is composed of a P-type semiconductor material and the sub-region is composed of an N-type semiconductor material, the net doping concentration of the P-type dopant in the channel may be 0.1 to 1 times the net doping concentration of the N-type dopant in the channel.

[0031] To provide good conductive properties in the first portion of the sub-region, the first portion of the sub-region has a net doping concentration per square centimeter of 1e16 to 5e17, inclusive.

[0032] Good bipolar conduction characteristics also depend on a relatively small lateral spacing between the collector and emitter regions, so the lateral spacing between the collector and emitter regions can be less than or equal to 1.5 microns.

[0033] The emitter region and / or the collector region may be located at least partially within a sub-region of the base.

[0034] On the other hand, the present invention provides a transistor device having: a collector region provided by a first region of a first type semiconductor; a collector terminal associated with the collector region; an emitter region provided by a second region of the first type semiconductor; an emitter terminal associated with the emitter region; a base region provided by a third region of a semiconductor located between and bordering the collector region and the emitter region; a base terminal associated with the base region, wherein the base region includes: a sub-region of the second type semiconductor, and a channel of the first type semiconductor, wherein the sub-region borders the channel to provide A diode junction, and the channel borders both the collector region and the emitter region and is interconnected with each other; the net doping concentration of the channel is less than the net doping concentration of the emitter region and the collector region; and the channel has a depth extending far from the first diode junction that is sufficiently small compared to the sub-region, when the device is operated in a circuit, wherein a voltage passes through a plurality of emitter terminals and collector terminals and the base terminal is floating or short-circuited with the emitter terminal, a depletion region is formed near the PN junction surface to constrain the channel, so that there is substantially no current between the collector terminal and the emitter terminal of the device.

[0035] The sub-regions of the base can be formed in the first type semiconductor substrate layer, and the substrate can thus provide the function of isolating a plurality of individual semiconductor body components.

[0036] In order to minimize the effect of parasitic transistors caused by the combination of the substrate, sub-division and collector and / or emitter regions, the device may further include a highly doped region of a semiconductor second type, arranged so as to be separated, between the sub-division and the substrate, the highly doped region having a higher net doping concentration than the sub-division.

[0037] The emitter and collector regions may, at least in part, be provided by a polysilicon layer; a pattern of doped polysilicon may be located on the surface of the silicon chip forming the base region.

[0038] The emitter region may have a higher net doping concentration than the collector region; or, the net doping concentrations of the emitter region and the collector region may be substantially the same. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 is a schematic cross-sectional view of a semiconductor structure of a transistor in one embodiment of the present invention;

[0040] Figure 2 The present invention Figure 1 A schematic diagram showing how the operating characteristics of a transistor device vary with changes in Vbe and Vce;

[0041] Figure 3A The present invention Figure 1 Schematic diagram of a cross section of a transistor configured in an on condition and having conduction between its emitter and collector mainly due to bipolar conduction;

[0042] Figure 3B The present invention Figure 1 A schematic diagram of a cross section of a transistor configured in an off condition;

[0043] Figure 3C The present invention Figure 1 Schematic diagram of a cross section of a transistor configured in an on condition and with conduction between its emitter and collector being primarily due to unipolar conduction;

[0044] Figure 4A The present invention is similar to Figure 1 Schematic diagram of a cross section of a transistor having a shorter spacing X and arranged in an on condition where the current between the emitter and the collector is mainly due to unipolar conduction;

[0045] Figure 4B The present invention Figure 4A A schematic diagram of a cross section of a transistor configured in an off condition;

[0046] Figure 5A is a schematic cross-sectional view of another semiconductor structure of a transistor device in a specific embodiment of the present invention;

[0047] Figure 5B The present invention Figure 5A A schematic diagram of a transistor implemented by a semiconductor structure;

[0048] FIG. 6A to FIG. 6I The present invention Figure 5A and Figure 5B A schematic diagram of a transistor device and its manufacturing process; DETAILED DESCRIPTION

[0049] The present invention will now be described with reference to the following drawings and specific embodiments.

[0050] See also Figure 1 As shown, Figure 1 It is a cross-sectional schematic diagram of a semiconductor structure of a transistor. As shown in the figure: The present invention provides a transistor device 1, which is regarded as an improvement on a bipolar junction transistor (BJT) device and operates in a similar manner in some aspects; for this reason, the present invention uses BJT to mark each terminal of the device.

[0051] The device 1 is of PNP type in this embodiment and is not shown to scale, and is made of doped semiconductor material, providing a collector region 2, an emitter region 3 and a base region 4. The base region 4 is located between the collector region 2 and the emitter region 3.

[0052] The collector region 2 and the emitter region 3 are both P-type semiconductors. Conventionally, the emitter region 3 may have more doping properties than the collector region 2. For example, the net doping concentration of the collector region 2 may be greater than or equal to 1×10 18 cm -3 , the net doping concentration of the emitter region 3 may be greater than or equal to 2×10 18 cm -3 or, for the convenience of manufacturing, they may be changed to have substantially the same net doping concentration. The collector terminal C is connected to the collector region 2, the emitter terminal E is connected to the emitter region 3, and the base terminal B is connected to the base region 4.

[0053] Compared to a conventional BJT, the base region 4 of the transistor device 1 is composed of two different types of semiconductor regions: a first region of N-type material, hereinafter referred to as N-type base region 4A, and a second region of P-type material, hereinafter referred to as the channel 4B.

[0054] The base terminal B is connected to the base region 4 through the N-type region 4A. The N-type base region 4A directly borders the channel 4B to form a PN junction 5. The N-type base region 4A directly borders the collector region 2 and the emitter region 3, respectively.

[0055] The channel 4B extends between the collector region 2 and the emitter region 3 and directly borders both of them. Compared with the collector region 2 and the emitter region 3, the net doping concentration of the channel 4B is very small; for example, the net doping concentration of the channel may be less than or equal to 5×10 16 cm -3 .

[0056] Furthermore, the channel 4B has a depth, ie, a dimension extending orthogonally to the NP junction 5, which is much shallower than that of a conventional junction field effect transistor (JFET).

[0057] The sub-region is composed of a first part and a second part. The net concentration of N dopant in the first part can be 1e17 / cm 3 The net doping concentration of the second portion is preferably, for example, about 1e18 / cm 3 or 1e19 / cm 3 .

[0058] A semiconductor structure implementing the above features is described below.

[0059] The structure has a P-type substrate 100, preferably a silicon wafer or a silicon layer deposited epitaxially on top of the wafer. An N-type region 101 is provided in the substrate 100; the N-type region 101 and the substrate 100 are separated by an N+ region 102; an additional N+ region 101A extending to the surface of the substrate material is provided in the N-type region 101; the N-type region 101 and the additional N+ region 101A constitute the N-type base region 4A of the transistor device 1, with the base contact B connected through the additional N+ region 101A; the net concentration of N dopants in the N-type region 101 can be about 1e17 / cm 3 The net doping concentration of the N+ region 102 and the additional N+ region 101A is preferably about 1e18 / cm 3 or 1e19 / cm 3 .

[0060] A lightly doped P-region 103 extends through the top of the N-type region 101, has a channel 4B and interfaces with the N-type region 101 to provide the diode junction 5; the structure also includes two separate P-type regions 104 and 105. The first portion 104A and 105A of each P-type region 104 and 105 is provided by a respective independent portion of the P-type doped polysilicon layer; the second portion 104B and 105B of each P-type region 104 and 105 is formed in the silicon wafer and interfaces with the N-type region 101 to provide corresponding diode junctions 5A and 5B.

[0061] An exemplary manufacturing process of one of the semiconductor structures is described as follows. A first implantation and diffusion process uses a first mask to form the N+ region 102 in the P-type substrate 100; a second mask is used to form the N-type region 101, and the N+ region 101 is counter-doped with a P dopant to extend the N-type region 101 to the wafer surface.

[0062] Preferably, shielding may not be used, and the wafer surface is further doped with a P dopant to form the P-layer 103 extending through the wafer surface; the net doping concentration of the P-region 103 is preferably, for example, 5e16 / cm 3 or less; ensuring that little or no diffusion occurs, the depth of the P-region 103 is kept very small. For ease of understanding, the relative thickness of the P layer 103 compared to the other layers is Figure 1 It has been exaggerated.

[0063] Using a third mask, N dopants are implanted through the wafer surface to counter-dope a portion of the P− region 103 to form the additional N+ region 101A, which is a continuation of the N region 101 .

[0064] Using a fourth mask, a layer of polysilicon material is deposited and etched to provide portions 104A, 105A of the collector and emitter regions 2, 3. Using a fifth mask, the polysilicon material is doped with P dopants and diffused downward to form second portions 104B, 105B that interface with the N-type region 101.

[0065] The P dopant implantation is followed by a short anneal, for example 10 seconds, to repair the crystal structure of the polysilicon and silicon wafer.

[0066] Specific working mode:

[0067] See also Figure 2 As shown, Figure 2 show Figure 1 A schematic diagram showing how the operating characteristics or modes of a transistor device change according to the changes in the voltage (Vce) across the collector terminal and the emitter terminal and the voltage (Vbe) across the base terminal and the emitter terminal. As shown in the figure:

[0068] By using a PNP device, such as Figure 1 The device shown, regardless of the operating mode, is usually operated with a negative Vce, i.e., the voltage applied to the collector is more negative than the voltage applied to the emitter, and the negative base-emitter junction with Vbe in a positive relationship with the threshold voltage Vft can be either positive or negative. Any current through the base terminal will be negative (i.e., current is drawn out through the base terminal). In contrast, an NPN device is usually operated with a positive Vce and has a positive Vft, and any current through the base will be positive (i.e., current is pushed into the device through the base).

[0069] The five operating modes are indicated as K, J, L, M and N. When the device is off and no current flows through any terminal, the device operates in region K; when the device is on, it can operate in one of modes J, L, M and N.

[0070] When the device is turned on (i.e., there is current between the collector and the emitter) and there is no or almost no (deminimus) current through the base terminal (i.e., Ib=0A), excluding any temporary switching current caused by capacitive effects, the device operates in region L or M; when the device is turned on (i.e., there is a non-zero current between the collector and the emitter) and there is current at the base terminal (i.e., Ib<0A), the device operates in region J or N.

[0071] Operation under |Vce|<|Vt|

[0072] When the transistor device 1 operates when |Vce| is less than |Vt|, the transistor device 1 acts as a normally-off device. That is, when Vbe is zero, there is no current between the emitter 2 and the collector 3 (the device is off (operating in the (K) region)).

[0073] If |Vbe| increases so that the base-emitter diode junction 5B becomes forward biased (i.e., Vbe becomes more negative than –Vft for a PNP transistor; Vbe becomes more positive than Vft for an NPN transistor), the device switches on and operates in the on-majority bipolar region J, with current drawn through the base terminal and the current between the collector and emitter being primarily due to bipolar conduction;

[0074] Alternatively, if |Vbe| increases in the opposite direction, causing the base-emitter diode junction 5B to be more reverse biased (i.e., Vbe becomes more positive for a PNP transistor and more negative for an NPN transistor), the device then remains off (operating in region K).

[0075] When |Vce| is greater than |Vt'| and less than |Vt|, the operation of the device is similar to when |Vce| is less than |Vt'|, except that when |Vbe| is close to but less than |Vft|, the device enters the turned-on main bipolar region L, in which the device is turned on and the current through the base terminal is zero, while the current between the collector and emitter is mainly due to unipolar conduction.

[0076] When |Vbe| becomes greater than |Vft|, it enters the transition region N, in which the unipolar conduction current is maximum, and the bipolar conduction current increases until the bipolar conduction current is greater than the unipolar conduction current, so that the device operates in the main bipolar conduction region J of the turn-on.

[0077] Advantageously, the normally-off device can be switched on and operated in region L at a lower Vbe than existing BJTs, and advantageously lower than the base-emitter diode junction forward voltage (Vft). When operated in the L region, the device has a significantly higher current gain for the same Vce than when operated in the J region, but the maximum collector current is smaller. Due to the significantly lower Vbe, when the device is operated in the L region, it has a significantly higher current gain than existing BJTs—approaching infinite gain, since the current through the base terminal is essentially zero.

[0078] Operation under |Vce|>|Vt|

[0079] The transistor device 1 acts as a normally-on device when |Vce| is greater than the threshold voltage |Vt|, that is, when Vbe is zero, for example because the base is floating or connected to the emitter, the current between the emitter and the collector exceeds the minimum current.

[0080] When |Vce| is greater than |Vt| and Vbe is zero or close to zero, the transistor operates in the turned-on, predominantly unipolar operating region M, where the current through the base terminal is zero and the current between the collector and emitter is primarily due to unipolar conduction.

[0081] When |Vbe| increases above Vft, causing the base-emitter diode junction 5B to become forward biased (i.e., Vbe becomes more negative than -Vft for a PNP transistor and more positive than Vft for an NPN transistor), the device operates in the transition region N, where the unipolar conduction reaches a maximum and the bipolar conduction increases. As |Vbe| increases further, the proportion of Ice attributable to bipolar conduction becomes greater than the proportion attributable to unipolar conduction current, and the operation thereon is on and predominantly bipolar (region J).

[0082] The Vbe amplitude required to operate in this J region increases with the increase in Vce.

[0083] Alternatively, if |Vbe| increases in the opposite direction, causing the base-emitter diode junction 5B to be more reverse biased (i.e., Vbe becomes more positive for a PNP transistor and more negative for an NPN transistor), the device will turn off (operating region K).

[0084] Between the closed region K and the open main unipolar region L and M is a transition region O, where the operation of the device is unpredictable or difficult to control. For example, if the collector current in the closed region K is less than 1 nA, and the collector current in the open region L and M is on the order of 1 uA or greater, then the collector current in the transition region O will be on the order of 10 nA to 100 nA.

[0085] The device 1 has a lateral spacing of distance X between the collector region 2 and the emitter region 3, controlling the length of the channel 4B. The values ​​of Vt and Vt' are related to the spacing X between the emitter and collector regions. As the value of X increases, the magnitude of |Vt| and |Vt'| also increases. In order for the device to have good bipolar conduction characteristics when operating in the J region, the maximum value of X is typically 1.5 microns.

[0086] The rated operating voltage range of the circuit determines the range of Vce values ​​to be applied to the transistors therein. When Vce is known, the spacing X of each transistor device 1 in the circuit can be selected when designing the circuit to determine its operating mode as a normally open device or a normally closed device.

[0087] See also Figure 3A to Figure 3C As shown, they are shown Figure 1 Schematic diagram of a cross section of a transistor configured in an on condition and having conduction between emitter and collector mainly due to bipolar conduction, Figure 1 A schematic diagram of a transistor cross section in a closed condition, and Figure 1 A schematic diagram of a cross section of a transistor configured in an on condition and with the conduction between its emitter and collector mainly attributed to unipolar conduction. As shown in the figure: Figure 3A to Figure 3C show Figure 1 The device has a lateral spacing X between the emitter region and the collector region that is relatively large, so that |Vce| is less than |Vt|, and the device thus operates as a normally-off transistor. In the present example, the spacing X places Vce between Vt and Vt', thereby allowing the device to operate with the characteristics of any of regions J, K, or L, depending on Vbe.

[0088] Figure 3A yes Figure 1 Schematic diagram of a cross section of a transistor in the configuration in the on condition and with conduction between its emitter and collector mainly due to bipolar conduction.

[0089] Figure 3A is shown under mainly open bipolar conditions ( Figure 2 The transistor 3 is a normally-off device that operates in region J of the emitter region. Since the emitter terminal E has a relatively positive voltage compared to the base terminal B, causing Vbe to be more negative than Vft, the diode junction 5B provided by the N-type region 101 between the emitter region 3 and the sub-region 4A is forward biased, allowing current to flow through the diode junction 5B between the emitter terminal E and the base terminal B (indicated by arrow 6). Therefore, there is a corresponding but much larger current between the emitter 3 and the collector 2, which is due to the two unipolar currents (indicated by arrow 7A) flowing together through the channel 4B, and the larger current (indicated by arrow 7B) due to the bipolar conduction flowing through the N-type base region 4A. The presence of unipolar conduction through the channel 4B provides the transistor with a gain characteristic that is superior to that of a transistor having a conventional BJT structure.

[0090] At large collector-emitter currents, the bipolar current 7B can be significantly larger than the unipolar current 7A (e.g., on the order of 10 times larger). In contrast, all (or nearly all) of the current in a JFET is attributable to unipolar conduction through the channel.

[0091] Figure 3B show Figure 2 The device in the closed state is shown in area K in the middle. VCE and Figure 3A The same as shown in , but the base terminal B is floating or connected to the emitter terminal E, so no current flows through the base terminal B.

[0092] Under this condition, a depletion region 8 is generated, as shown by the dotted line near the PN junction surface 5. Since the channel 4B is very shallow and weakly doped compared to the base sub-region, the channel 4B is constrained to increase the resistance of the channel 4B so that there is basically no current between the emitter 3 and the collector 2.

[0093] Figure 3C The device is shown to operate under primarily open unipolar conditions ( Figure 2 Region L) by applying a non-zero voltage Vbe less than Vft across the emitter and base. Since Vbe is less than Vft, the diode junction 5B between the emitter 3 and the N-type base region 4A does not have sufficient forward bias to allow current to pass, and therefore no current passes through the base terminal B or the base region 4A; however, since the net doping level of the channel 4B is very low, Vbe is sufficient to reduce the depletion region 8 around the diode junction 5 to a level that allows current to flow through the channel 4B via unipolar conduction between the emitter region 3 and the collector region 2 (indicated by arrow 7A). When operating in region L, the transistor has a high gain characteristic with Ib=0A. However, since the channel is shallow, the maximum current that can be obtained before the channel is saturated is relatively low compared to operating in region J.

[0094] See also Figure 4A and Figure 4B As shown, they are similar to Figure 1 Schematic diagram of a cross-section of a transistor having a shorter spacing X and arranged in an on condition where the current between the emitter and the collector is mainly due to unipolar conduction, and the Figure 4A A schematic diagram of a transistor cross section in a closed condition. As shown in the figure: Figure 4A and Figure 4B Display with Figure 1 Different devices with the same semiconductor structure differ in that the distance X between the collector region 2 and the emitter region 3 is smaller and thus has a shorter channel 4B. The distance is selected so that Figure 3A to Figure 3C When the device is operated in a circuit providing the same Vce range, Vce is greater than Vt and causes the device to operate as a normally-on transistor.

[0095] It should be noted that although selecting the lateral spacing between the collector and emitter regions is the most convenient way to control the channel length, by forming a circuitous path for the channel between the emitter and collector regions, a longer channel length can be provided for a given lateral emitter-collector spacing.

[0096] Figure 4A is the device shown in a predominantly open unipolar condition. VCE is Figure 3A to Figure 3C The same as the related description in , the difference is that the distance X between the collector 2 and the emitter 3 is closer, and therefore the channel 4B is shorter, so even if the base terminal B is suspended or connected to the emitter terminal E, it is enough to overcome the intrinsic depletion region around the diode junction 5. Therefore, although there is no current passing through the base terminal B, there is still current passing through the channel 4A between the emitter and the collector.

[0097] Figure 4B The device is shown in the off state, which is achieved by making the base terminal B more positive than the emitter terminal E.

[0098] Note that the surface area of ​​the transistor (i.e. Figure 1 , Figures 3A to 3C Figure and Figure 4A , Figure 4B The dimensions shown on the page can be selected according to the maximum rated current that the transistor device 1 needs to meet to increase the width of the base region including the channel 4B.

[0099] The substrate layer 100 may be connected to a low voltage to ensure that the PN junction between the substrate and the N+ layer 102 has a reverse bias, which can suppress the adverse effects of parasitic lateral NPN BJT transistors between adjacent transistor base regions.

[0100] Part of the reason why the lateral N+ layer 102 is required is to prevent the P injection region 103 from causing a short circuit between the emitter and the substrate, and to ensure that the parasitic vertical PNP BJT formed between the emitter and the substrate has very poor current conduction characteristics, which is beneficial to reduce the parasitic current by more than 100 times the collector current of the device.

[0101] Alternative Embodiments with Different Semiconductor Structures and Fabrication Methods

[0102] See also Figure 5A and Figure 5B , and a schematic cross-sectional view of another semiconductor structure of an actual operating transistor device, and the Figure 5A A schematic diagram of the transistor plane in which the semiconductor structure is actually operated. As shown in the figure: Figure 5A It is another semiconductor structure of a practical transistor device. Figure 1 Compared with the structure of Figure 5A The section axis.

[0103] For example, a P-type substrate 200 is provided, which may be a silicon wafer or a silicon crystal layer deposited on the top of a wafer by epitaxy. An N-type well region 210 consisting of an upper N-type region 211, a lower N-type region 212 and an N+ region 213 located therebetween is provided in the substrate 200.

[0104] Another N+ region 214 is formed in a ring system surrounding the upper N-type region 211 and the N+ region 213. The N+ ring 214 overlaps the N-type well 210 and extends outwardly to provide the N-type region 4A of the transistor.

[0105] The P-channel layer 220 providing the channel 4B of the transistor is located above and in direct contact with the upper N-type region 211. The P-channel layer is in direct contact with the N-type region 211 below it to provide a diode junction 5.

[0106] It is worth noting that the N+ ring region 214 extends upward and surrounds the P-channel layer 220 to isolate the channel 4B from the substrate.

[0107] The doping concentration of the N-type region 211 is 1e17 / cm 3 To 5e17 / cm 3 This is in contrast to the high doping levels (>1e19 / cm 3 ) to form a contrast.

[0108] The P-channel layer 220 has a 1e16 / cm 3 to 1e17 / cm 3 The net doping concentration is of the order of magnitude.

[0109] An oxide layer 221 is located above the P-channel layer 220. The structure also includes two separate P-type regions 222, 223, each of which extends through the oxide layer 221 and the P-channel layer 220 to provide corresponding collector and emitter regions 2, 3.

[0110] The first portion 222A, 223A of each P-type region 222, 223 is provided by portions of the P-doped polysilicon layer located on the oxide layer 221 to connect the emitter terminal and the collector terminal to the circuit. The second portion 222B, 223B of each P-type region 222, 223 is provided by portions of the polysilicon layer extending through the oxide layer 221 to contact the wafer surface. The third portion 222C, 223C of each P-type region 222, 223 is formed in the silicon wafer and intersects with the N-type region 211 to provide a corresponding diode junction 5A, 5B.

[0111] A patterned oxide layer 500 and a metal layer 224 are located on the oxide and polysilicon layers 221, 223. A first portion 224A of the metal layer is patterned to provide a plurality of conductive regions. A second portion 224B of the metal layer 224 extends through the holes in the oxide layers 500, 221 to contact the N+ region 214 to provide the base terminal.

[0112] See also FIG. 6A to FIG. 6I As shown, the Figure 5A and Figure 5B The schematic diagram of the manufacturing process of the transistor device is shown in the figure. FIG. 6A to FIG. 6I is an example program showing a portion of the integrated circuit fabrication area for two Figure 5A and Figure 5B structure of transistors.

[0113] The first of the transistors is formed with a relatively small spacing X between the collector region and the emitter region, while the other has a relatively large spacing, the spacing being selected so that, in operation, the first operates as a normally-on transistor and the other operates as a normally-off transistor. The channel length of the second transistor may be selected so that, when turned on, it is connected to the transistor with a relatively large spacing X between the collector region and the emitter region. Figure 2 The L, N or J regions are operated according to the related characteristics.

[0114] Please refer to Fig. 6A , a P-type substrate 200 is provided. Figure 6B , which uses a masking, implantation and diffusion process to form a plurality of separate annular (circular or other similar shape) N+ type regions 214 in the P type wafer 200, one for each transistor.

[0115] Please refer to Figure 6C , a masking and implantation process is used to form a plurality of N-type wells 210 within corresponding rings 214. The diffusion process is omitted to leave the more highly doped N+ layer 213 below the surface (between the N-type layers 211, 212).

[0116] Please refer to Fig.6D , is to use an unshielded P-type implant process to form the P-channel layer 220. This can be implemented without diffusion or annealing. Because the doping required to form the P channel region is very weak, the implant will not have a decisive effect on the N+ region.

[0117] Please refer to Fig. 6E , an oxide layer 221 is added to the wafer by a deposition process. The deposition process is used to ensure that the p-channel layer 220 is not damaged.

[0118] A photoresist 300 is applied to the oxide layer. The photoresist is patterned to define a spacing X between the collector region and the emitter region, and thus define the length of the channel 4B. In this example, the spacing X between the left transistors is selected to be relatively small to provide a normally-on transistor, while the spacing X between the right transistors is selected to be relatively large to provide a normally-off transistor.

[0119] Taking the size of a 1um manufacturing process as an example, the right transistor can have a channel length between 1.2 microns and 1.5 microns; and the left transistor can have a channel length equal to or less than 0.8 microns.

[0120] Please refer to Fig. 6F , is to etch the oxide layer and remove the mask.

[0121] Please refer to Figure 6G , a polysilicon layer 400 is deposited on the wafer (the whole wafer may be selected). The polysilicon layer 223 directly contacts the exposed surface of the P-layer 220, and the oxide layer 221 thereon has been removed to form the collector and emitter contacts 222B, 223B.

[0122] A P-type implantation process 401 (indicated by arrows) is performed to convert the polysilicon to P-type, which also increases the net doping concentration of the P-layer regions directly in contact with the polysilicon to form regions 222C, 223C for collector and emitter terminals 2, 3. A short annealing step activates the implant without initiating diffusion of the P channel 220. Alternatively, to reduce processing time, P-type polysilicon can be deposited.

[0123] Please refer to Figure 6H , is to mask and etch the polysilicon layer 400 to pattern the collector and emitter terminals 2, 3 with tracks 222A, 223A.

[0124] Please refer to Fig.6I , a masking and etching process is further used to subsequently expose a region of the N+ ring 214 and deposit metal 224 to provide the base contact 224B, and then etch a pattern to provide a winding layer 224A.

[0125] The devices described in the above formulas can be replaced by NPN devices, which have N-type channels, multiple emitter and collector regions, and P-type base sub-regions; in this way, the device can be operated with the opposite polarity to that described above.

[0126] The emitter region and / or the collector region may be formed completely within the wafer rather than using a crystalline silicon layer.

[0127] The above structure can be modified in combination with a zener diode by providing an additional P-type region to electrically connect between the base and collector terminals, as described in WO2019 / 229432;

[0128] The metal base contact may be replaced by a polysilicon doped contact; this will introduce a zener diode into the base terminal with the benefit of not requiring any metal layers to be routed adjacent to the device.

Claims

1. A transistor device, characterized in that: have: a collector region provided by a first region of a first type semiconductor; a collector terminal associated with said collector region; an emitter region provided by the second region of the first type semiconductor; an emitter terminal associated with the emitter region; a base region provided by a third region of the semiconductor located between and bordering the collector region and the emitter region; a base terminal associated with the base region; Wherein, the base region comprises: a sub-division of the second type semiconductor, and, a channel of the first type semiconductor, wherein the base terminal contacts the sub-region, The sub-division of the base region includes a first portion and a second portion. The first portion has a higher net doping concentration than the second portion; The base terminal is electrically connected to the second portion through the first portion; and The second portion interfaces with the channel to provide a first diode junction, and interfaces with both the emitter region and the collector region to further form a plurality of diode junctions, The channel interfaces with and interconnects both the collector region and the emitter region.

2. The transistor device according to claim 1, characterized in that The interval between the collector region and the emitter region is less than or equal to 1.5 micrometers.

3. The transistor device according to claim 1 or 2, characterized in that The net doping concentration of the channel is less than the net doping concentration of the emitter region and the collector region.

4. The transistor device according to any one of claims 1 to 3, characterized in that The channel depth extending from the first diode junction is less than or equal to 0.25 microns, and preferably less than or equal to 0.1 microns.

5. The transistor device according to any one of claims 1 to 4, characterized in that The net doping concentration of the second part of the sub-region is 1e16 / cm 3 To 5e17 / cm 3 between.

6. A method for operating a transistor device, the transistor device being a transistor device as claimed in any one of the preceding claims, characterized in that: in, When the device is turned on, |Vce|<|Vft|, and |Vbe|<=|Vce|; Where Vce is the voltage across the collector terminal and the emitter terminal, Vft is the forward bias voltage of the base-emitter diode junction; and Vbe is the voltage across the collector and emitter terminals.

7. The working method according to claim 6, characterized in that: |Vce|≤1 / 2|Vft|.

8. The working method according to claim 6 or 7, characterized in that: When in the closed state: |Vbe|<|Vft|.

9. A transistor device, characterized in that: have: a collector region provided by a first region of a first type semiconductor; a collector terminal associated with said collector region; an emitter region provided by the second region of the first type semiconductor; an emitter terminal associated with the emitter region; a base region provided by a third region of the semiconductor between and bordering the collector region and the emitter region; a base terminal associated with the base region; Wherein, the base region comprises: a sub-division of the second type semiconductor, and, a channel of the first type semiconductor, wherein the base terminal contacts the sub-region; The sub-region is bounded by the channel to provide a diode junction, and the channel is bounded by and interconnected with both the collector region and the emitter region; The net doping concentration of the channel is less than the net doping concentration of the emitter region and the collector region; The channel has a sufficiently small depth extending far from the first diode junction surface. When the device is implemented in a circuit, wherein a voltage passes through a plurality of emitter terminals and collector terminals and the base terminal is floating or short-circuited with the emitter terminal, a depletion region is formed near the corresponding PN junction surface to constrain the channel, so that there is substantially no current between the collector terminal and the emitter terminal of the device.

10. The transistor device according to claim 9, characterized in that The channel is the only interface that provides a boundary with one of the collector region and the emitter region or with both of them.

11. The transistor device according to claim 9, characterized in that The sub-regions are respectively bounded by the emitter region and the collector region to further form a plurality of diode junctions.

12. The transistor device according to claim 9 or 11, characterized in that The sub-regions surround the emitter region and the collector region.

13. A transistor arrangement according to claim 9, 11 or 12, characterized in that The sub-division is formed in a first-type semiconductor substrate layer. The device further includes a highly doped region of a second-type semiconductor located between and separating the sub-division and the substrate. The highly doped region has a high net doping concentration compared to the sub-division.

14. The transistor device according to any one of claims 9 to 13, characterized in that The emitter region and the collector region are provided by a doped polysilicon layer, which is disposed on a silicon chip defining the base region.

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