Asymmetric pulse thyristor structure with buried FS layer and manufacturing method thereof

Abstract

The invention provides an asymmetric pulse thyristor structure with a buried FS layer and a manufacturing method of the asymmetric pulse thyristor structure, and relates to the technical field of pulse power semiconductor devices. The pulse thyristor provided by the invention not only solves the problems that the blocking capability is required in the forward direction and the reverse direction, the blocking voltage is asymmetric and small square sheets are difficult to form, but also improves the pulse discharge characteristic, and ensures the dv / dt tolerance and the ESD reliability of a device. By adopting the pulse thyristor with the buried FS layer, the blocking capability of a device can be improved, and the pulse thyristor is particularly suitable for an application occasion requiring a certain blocking capability in a reverse direction.

Description

Technical Field

[0001] The present invention relates to the technical field of pulse power semiconductor devices, and in particular to an asymmetric pulse thyristor structure with a buried FS layer and a manufacturing method thereof. Background Art

[0002] Thyristor is a traditional power semiconductor device. Due to its high voltage, high current and low loss, it has a wide range of applications in the field of pulse power. Traditional pulse thyristors use wafer chips, which are not only large in size, but also have obvious plasma lateral expansion when triggered, which makes the opening speed slow and the current triggering uneven, resulting in poor pulse discharge characteristics.

[0003] In some applications in the field of pulse power, pulse thyristors need to meet the requirements of high voltage, high current rise rate and high current peak, as well as be small in size and have a certain reverse blocking capability.

[0004] At present, high-voltage thyristors usually adopt a symmetrical structure. Although they can achieve reverse blocking capability, the base region is relatively thick, which not only leads to slow turn-on speed and poor pulse discharge characteristics, but also makes it difficult to make square chips. If the traditional asymmetrical structure is adopted, the thickness of the N base region can be thinned. Although it can improve the pulse discharge characteristics, the reverse blocking voltage is often only tens of volts, which basically does not have reverse blocking capability and cannot meet actual needs. Summary of the invention

[0005] According to the technical problems mentioned in the above background technology, the present invention provides an asymmetric pulse thyristor structure with a buried FS layer and a manufacturing method thereof.

[0006] The technical means adopted by the present invention are as follows:

[0007] An asymmetric pulse thyristor structure with a buried FS layer comprises: a plurality of parallel strip cells arranged on a surface, wherein the plurality of parallel strip cells are evenly distributed on an upper surface of a chip;

[0008] The cross-sectional structure of each strip cell is N 1 - The base region is the substrate, the N 1 - The base area is sequentially provided with NFS layer and N 2 - Base region and P + Anode region, P + The surface of the anode region is provided with an anode A; 1 - The base region is sequentially provided with a P base region upward; an N + cathode region, the N+ A cathode K is provided on the upper surface of the cathode region; + Gate electrodes G are provided on the upper surfaces of the P base regions on both sides of the cathode region.

[0009] Furthermore, the strip-shaped cell has a width of 60 μm to 100 μm.

[0010] Furthermore, the N + The width of the cathode region is 20 μm to 60 μm.

[0011] Furthermore, the thickness of the N FS layer is 20 μm to 30 μm, and the doping concentration of the N FS layer is 1×10 16 cm -3 ~3×10 16 cm -3 .

[0012] Furthermore, the N 2 - The concentration and thickness of the base region are adjusted according to the reverse blocking voltage and N 1 - The base concentration and thickness are not equal.

[0013] The present invention also includes a method for manufacturing an asymmetric pulse thyristor structure with a buried FS layer, comprising the following steps:

[0014] First, the forward and reverse blocking voltages of the asymmetric pulse thyristor are determined; if the reverse blocking voltage is ≥500V, step A is performed, i.e., the pre-epitaxial process is adopted; if the reverse blocking voltage is <500V, step B is performed, i.e., the post-H is adopted. + Ion implantation process.

[0015] Furthermore, the step A comprises the following steps:

[0016] Step A1, select the crystal direction <111> The original high-resistance region molten silicon single crystal is used as the N1-base region, and the surface of the original high-resistance region molten silicon single crystal is corroded and cleaned;

[0017] Step A2: forming a preliminary doping of the N FS layer on the back side of the crystal in step A1 by epitaxial process or phosphorus ion implantation; and forming an N2-base region on the surface of the N FS layer by epitaxial process;

[0018] Step A3, forming a masking film on the crystal subjected to step A2 by using dry oxygen oxidation and deposition process, and marking the crystal to distinguish the front and back sides;

[0019] Step A4, on the front side of the wafer, a P base region of the active region and a P field limiting ring injection window of the terminal region are formed by photolithography, a sacrificial oxide layer is retained, boron ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned;

[0020] Step A5: On the front side of the wafer, a masking film is deposited and advanced to form a P base region and a P field limiting ring, and the N FS layer is further advanced;

[0021] Step A6: On the front side of the wafer, photolithography is performed to form injection windows of the N+ cathode region and the N+ cut-off region, a sacrificial oxide layer is retained, phosphorus ion implantation is performed under the mask of photoresist and SiO2 film, and debonding and cleaning are performed;

[0022] Step A7, forming a deposited oxide layer on both the front and back sides of the wafer, and performing high-temperature densification, performing uniform glue protection on the front side, and rinsing and de-glue cleaning on the back side oxide layer;

[0023] Step A8, photolithography is performed on the back side of the wafer to form an N+ cut-off region injection window, and then phosphorus ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned;

[0024] Step A9, depositing an oxide layer on the front and back sides of the wafer, and advancing to form an N+ cathode region and N+ cut-off regions on the front and back sides, while further advancing the N FS layer;

[0025] Step 10, photolithography is performed on the back of the wafer to form a P+ anode region injection window, and then boron ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned;

[0026] Step A11, depositing oxide layers on the front and back sides of the wafer, and advancing to form a P+ anode region, while further advancing the P base region, N+ cathode region, N+ cutoff region, N FS layer and P field limiting ring of the terminal region;

[0027] Step A12, removing the oxide layer on the front and back sides of the wafer, re-performing dry oxygen oxidation, depositing oxide layers on the front and back sides, performing high-temperature densification, and performing uniform coating protection on the back side;

[0028] Step A13, performing photolithography on the front and back sides of the wafer respectively to form electrode contact holes on the front and back sides; sputtering an aluminum-silicon-copper metal layer on the front side, and sputtering a thicker aluminum layer on the back side;

[0029] Step A14, photolithography of the metal layer is performed on the front and back sides of the wafer respectively, and gate and cathode metal electrode patterns are formed on the front side; titanium, nickel and silver are sputtered on the back side, and anode multilayer metallization electrodes are formed by photolithography, and then alloyed to reduce ohmic contact resistance;

[0030] Step A15, depositing silicon nitride film on the front and back sides of the wafer and performing photolithography, and passivating the front and back terminals of the chip;

[0031] Step A16, a polyimide film is cast on the front side of the wafer, and patterns of the front gate and cathode region bonding area are formed by photolithography, and imidization treatment is performed to passivate and protect the front terminal;

[0032] Step A17, dicing and packaging the wafer.

[0033] Furthermore, in the packaging process of step A18, the back packaging base and the anode bonding area are of the same size, and a certain gap is reserved between the back packaging base and the back terminal area of ​​the chip.

[0034] Furthermore, the step B comprises the following steps:

[0035] Step B1, select the crystal direction <111> The original high-resistance region molten silicon single crystal is used as the N-base region, and the surface of the original high-resistance region molten silicon single crystal is corroded and cleaned;

[0036] Step B2, according to step A3 to step A4, sequentially manufacturing the P field limiting rings of the P base region and the terminal region;

[0037] Step B3, depositing a masking film on the front side of the wafer and advancing it to form a P base region and a P field limiting ring;

[0038] Step B4, according to Step A6 to Step A8, sequentially fabricate the N+ cathode region and the N+ cut-off region on the front side, and the N+ cut-off region on the back side;

[0039] Step B5, depositing an oxide layer on the front and back sides of the wafer, and advancing to form an N+ cathode region and N+ cut-off regions on the front and back sides;

[0040] Step B6, according to step A10, making a P+ anode region on the back side;

[0041] Step B7, depositing an oxide layer on the front and back sides of the wafer, and advancing to form a P+ anode region, while further advancing the P base region, N+ cathode region, N+ cutoff region and P field limiting ring of the terminal region;

[0042] Step B8, on the back side of the wafer, by high energy H ion implantation and low temperature annealing, an N FS buried layer is formed on the side of the N-base region close to the P anode region, and annealing is performed;

[0043] Step B9, according to step A12 to step A17, the front and back electrodes and the passivation layer are manufactured in sequence; the wafer is sliced ​​and packaged.

[0044] Compared with the prior art, the present invention has the following advantages:

[0045] The present invention has a buried FS layer pulse thyristor, which can have a forward blocking voltage and a certain reverse blocking ability at the same time, and can cope with the reverse voltage ranging from hundreds of nanoseconds to microseconds applied during pulse discharge; and under the same structural parameters, the forward and reverse blocking capabilities and dv / dt tolerance are improved to avoid dv / dt false triggering. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0047] Figure 1 It is a schematic cross-sectional diagram of the basic structure of a pulse thyristor with a conventional FS layer;

[0048] Figure 2 It is a schematic cross-sectional view of the basic structure of the pulse thyristor with buried FS layer of the present invention;

[0049] Figure 3 It is a partial schematic diagram of the gate-cathode structure of the pulse thyristor with buried FS layer of the present invention;

[0050] Figure 4 It is a comparison diagram of doping distribution of N FS layer of pulse thyristor with buried FS layer of the present invention and pulse thyristor with conventional FS layer;

[0051] Figure 5 A comparison diagram of the electric field intensity distribution of the pulse thyristor with buried FS layer of the present invention and the conventional FS layer pulse thyristor during forward blocking;

[0052] Figure 6a This is a comparison diagram of the electric field intensity distribution of the conventional FS layer pulse thyristor during reverse blocking;

[0053] Figure 6b This is a diagram showing the electric field intensity distribution of the pulse thyristor with buried FS layer during reverse blocking of the present invention;

[0054] Figure 7 A comparison diagram of forward blocking characteristic curves of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer;

[0055] Figure 8 A comparison diagram of reverse blocking characteristic curves of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer;

[0056] Fig. 9A comparison diagram of forward conduction characteristic curves of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer;

[0057] Fig.10 The pulse discharge characteristic curves of the pulse thyristor with buried FS layer and the conventional FS layer pulse thyristor of the present invention;

[0058] Fig.11 A comparison diagram of dv / dt tolerance curves of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer;

[0059] Fig.12 The gate-cathode forward and reverse ESD discharge waveforms of the pulse thyristor with buried FS layer of the present invention and the conventional FS layer pulse thyristor are shown.

[0060] Fig.13 It is a cross-sectional schematic diagram of the active region and terminal region of the pulse thyristor with a buried FS layer according to the present invention. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] like Figure 1The figure shows a schematic cross-sectional view of the basic structure of a conventional FS layer pulse thyristor. The structure is based on the N1-base region as the substrate. The N FS layer and the P+ anode region are arranged in sequence downward from the N1-base region, and an anode A is arranged on the surface of the P+ anode region; the P base region is arranged in sequence upward from the N1-base region; the N+ cathode region of the pulse thyristor is partially arranged on the upper surface of the P base region, and a cathode K is arranged on the upper surface of the N+ cathode region; gates G are arranged on the upper surfaces of the p+ base regions adjacent to the N+ cathode region on both sides.

[0064] like Figure 2 , Figure 3 The figure shows the basic structure cross-sectional diagram of the pulse thyristor with buried FS layer of the present invention, with multiple parallel strip cells arranged on the surface, and the multiple parallel strip cells are evenly distributed on the upper surface of the chip; the cross-sectional structure of each strip cell is based on the N1-base region as the substrate, and the N FS layer, N2-base region and P+ anode region are arranged in sequence downward from the N1-base region, and the surface of the P+ anode region is the anode A; the P base region is arranged in sequence upward from the N1-base region; the N+ cathode region of the pulse thyristor is partially arranged on the upper surface of the P base region, and the cathode K is arranged on the upper surface of the N+ cathode region; the upper surfaces of the adjacent P base regions on both sides of the N+ cathode region are both arranged with gates G. The difference from the conventional FS layer pulse thyristor is that the N FS layer is buried in the N-base region close to the P+ anode region, resulting in the N-base region being divided into upper and lower parts.

[0065] In the present application, as a preferred embodiment, the width of the strip cell is 60 μm to 100 μm. The width of the N+ cathode region is 20 μm to 60 μm. The thickness of the N FS layer is 20 μm to 30 μm, and the doping concentration of the N FS layer is 1×1016 to 3×1016 cm-3. The doping concentration and thickness of the N2-base region are adjusted according to the reverse blocking voltage, and are not equal to the concentration and thickness of the N1-base region.

[0066] like Figure 4 As shown, in the pulse thyristor with buried FS layer of the present invention, the N FS layer is distributed in an ancient bell shape, and the two sides are respectively N1-base region and N2-base region with uniform and unequal doping concentrations, that is, the N FS layer is buried between the N1-base region and the N2-base region; in the conventional FS layer pulse thyristor, the N FS layer is Gaussian doped, one side is connected to the N-base region, and the other side is connected to the P+ anode region.

[0067] Specifically, the working principle of the pulse thyristor with buried FS layer is:

[0068] When a forward voltage (UAK>0) is applied to the anode and cathode of the device, the J2 junction is reverse biased, the space charge region widens to both sides, and after the N1-base region is punched through, it will be compressed in the N FS layer, forming an approximately trapezoidal electric field intensity distribution. Figure 4, is a comparison diagram of the electric field intensity distribution of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer during forward blocking. It can be seen that the electric field distribution of both is trapezoidal, and the forward blocking voltage is the area surrounded by the electric field distribution. Since the buried FS layer is a Guzhong-shaped doping distribution, at the same peak concentration and thickness, the blocking effect on leakage current is stronger than that of the conventional FS layer. Therefore, the pulse thyristor with buried FS layer can withstand a higher forward blocking voltage.

[0069] When a reverse voltage is applied between the anode and cathode (UAK<0), the J1 junction is reverse biased, and the space charge region of the J1 junction widens to both sides. After the N2-base region is punched through, it will be compressed in the N FS layer, forming an approximately trapezoidal electric field intensity distribution. The electric field intensity distribution diagram of the conventional FS layer pulse thyristor during reverse blocking shows that its electric field intensity distribution during reverse blocking is triangular; the electric field intensity distribution diagram of the pulse thyristor with a buried FS layer of the present invention during reverse blocking shows that its electric field intensity distribution during reverse blocking is trapezoidal.

[0070] When the pulse thyristor is turned on, it is triggered by the gate current, which can be equivalent to a dual-transistor model similar to that of an ordinary thyristor. When the gate current triggers the NPN transistor on the cathode side to turn on, its collector current is equivalent to the base current of the PNP transistor on the anode side, triggering the PNP transistor to turn on. When the sum of the current gain αNPN of the NPN transistor and the current gain αPNP of the PNP transistor on the anode side is greater than or equal to 1 (i.e. αNPN+αPNP≥1), the thyristor can remain on even if the gate current is removed.

[0071] Different from ordinary thyristors, since the gate of pulse thyristors surrounds the comb-shaped cathode, the turn-on process can be approximated as uniform turn-on, and there is no lateral expansion of plasma. Ordinary thyristors are partially turned on, and then the plasma gradually expands, and finally a large area is turned on.

[0072] Taking the capacitor energy storage discharge circuit as an example, during the pulse discharge process, after the gate pulse trigger signal is applied, the device responds quickly and turns on, and the large current of the capacitor discharge flows through the device. At the peak of the discharge, the voltage at the capacitor end drops to 0, and then the device is turned off because the current passes through zero. At the end of the discharge, the external circuit will apply a reverse voltage ranging from hundreds of nanoseconds to microseconds to the device. If the device has a certain reverse blocking ability, it will not affect the discharge reliability and is conducive to repeated use.

[0073] In the pulse thyristor structure of the present invention, a buried FS layer is introduced, so that the N-base region is divided into two parts, the N1-base region and the N2-base region. The forward blocking voltage is mainly borne by the N1-base region, and the reverse blocking voltage is mainly borne by the N2-base region. By adjusting the position, concentration and thickness of the buried FS layer, as well as the concentration and thickness of the N2-base region, various characteristics of the device can be improved under the premise of meeting the forward and reverse blocking voltages. Due to the role of the buried FS layer and the N2-base region, αPNP is reduced, which is conducive to reducing the leakage current during forward and reverse blocking, and at the same time improving the dv / dt tolerance.

[0074] The present invention also includes a method for manufacturing an asymmetric pulse thyristor structure with a buried FS layer, comprising the following steps: first, judging the level of the forward and reverse blocking voltages of the asymmetric pulse thyristor; if the reverse blocking voltage is relatively high (≥500V), executing step A, i.e., adopting a pre-epitaxial process; if the reverse blocking voltage is relatively low (<500V), executing step B, i.e., adopting a post-H+ ion implantation process.

[0075] In this application, the step A comprises the following steps:

[0076] The step A comprises the following steps:

[0077] Step A1, select the crystal direction <111> The original high-resistance region molten silicon single crystal is used as the N1-base region, and the surface of the original high-resistance region molten silicon single crystal is corroded and cleaned;

[0078] Step A2: forming a preliminary doping of the N FS layer on the back side of the crystal in step A1 by epitaxial process or phosphorus ion implantation; and forming an N2-base region on the surface of the N FS layer by epitaxial process;

[0079] Step A3, forming a masking film on the crystal subjected to step A2 by using dry oxygen oxidation and deposition process, and marking the crystal to distinguish the front and back sides;

[0080] Step A4, on the front side of the wafer, a P base region of the active region and a P field limiting ring injection window of the terminal region are formed by photolithography, a sacrificial oxide layer is retained, boron ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned;

[0081] Step A5: On the front side of the wafer, a masking film is deposited and advanced to form a P base region and a P field limiting ring, and the N FS layer is further advanced;

[0082] Step A6: On the front side of the wafer, photolithography is performed to form injection windows of the N+ cathode region and the N+ cut-off region, a sacrificial oxide layer is retained, phosphorus ion implantation is performed under the mask of photoresist and SiO2 film, and debonding and cleaning are performed;

[0083] Step A7, forming a deposited oxide layer on both the front and back sides of the wafer, and performing high-temperature densification, performing uniform glue protection on the front side, and rinsing and de-glue cleaning on the back side oxide layer;

[0084] Step A8, photolithography is performed on the back side of the wafer to form an N+ cut-off region injection window, and then phosphorus ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned;

[0085] Step A9, depositing an oxide layer on the front and back sides of the wafer, and advancing to form an N+ cathode region and N+ cut-off regions on the front and back sides, while further advancing the N FS layer;

[0086] Step 10, photolithography is performed on the back of the wafer to form a P+ anode region injection window, and then boron ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned;

[0087] Step A11, depositing oxide layers on the front and back sides of the wafer, and advancing to form a P+ anode region, while further advancing the P base region, N+ cathode region, N+ cutoff region, N FS layer and P field limiting ring of the terminal region;

[0088] Step A12, removing the oxide layer on the front and back sides of the wafer, re-performing dry oxygen oxidation, depositing oxide layers on the front and back sides, performing high-temperature densification, and performing uniform coating protection on the back side;

[0089] Step A13, performing photolithography on the front and back sides of the wafer respectively to form electrode contact holes on the front and back sides; sputtering an aluminum-silicon-copper metal layer on the front side, and sputtering a thicker aluminum layer on the back side;

[0090] Step A14, photolithography of the metal layer is performed on the front and back sides of the wafer respectively, and gate and cathode metal electrode patterns are formed on the front side; titanium, nickel and silver are sputtered on the back side, and anode multilayer metallization electrodes are formed by photolithography, and then alloyed to reduce ohmic contact resistance;

[0091] Step A15, depositing silicon nitride film on the front and back sides of the wafer and performing photolithography, and passivating the front and back terminals of the chip;

[0092] Step A16, a polyimide film is cast on the front side of the wafer, and patterns of the front gate and cathode region bonding area are formed by photolithography, and imidization treatment is performed to passivate and protect the front terminal;

[0093] Step A17, dicing and packaging the wafer. In the packaging process of step A17, the back packaging base and the anode bonding area have the same size, and a certain gap is left between the back packaging base and the back terminal area of ​​the chip.

[0094] Preferably, step B comprises the following steps:

[0095] Step B1, select the crystal direction <111> The original high-resistance region molten silicon single crystal is used as the N-base region, and the surface of the original high-resistance region molten silicon single crystal is corroded and cleaned;

[0096] Step B2, according to step A3 to step A4, sequentially manufacturing the P field limiting rings of the P base region and the terminal region;

[0097] Step B3, depositing a masking film on the front side of the wafer and advancing it to form a P base region and a P field limiting ring;

[0098] Step B4, according to Step A6 to Step A8, sequentially fabricate the N+ cathode region and the N+ cut-off region on the front side, and the N+ cut-off region on the back side;

[0099] Step B5, depositing an oxide layer on the front and back sides of the wafer, and advancing to form an N+ cathode region and N+ cut-off regions on the front and back sides;

[0100] Step B6, according to step A10, making a P+ anode region on the back side;

[0101] Step B7, depositing an oxide layer on the front and back sides of the wafer, and advancing to form a P+ anode region, while further advancing the P base region, N+ cathode region, N+ cutoff region and P field limiting ring of the terminal region;

[0102] Step B8, on the back side of the wafer, by high energy H ion implantation and low temperature annealing, an N FS buried layer is formed on the side of the N-base region close to the P anode region, and annealing is performed;

[0103] Step B9, according to step A12 to step A17, the front and back electrodes and the passivation layer are manufactured in sequence; the wafer is sliced ​​and packaged.

[0104] Example:

[0105] In order to evaluate the characteristics of the buried FS pulse thyristor of the present invention, according to Figure 1 and Figure 2 A structural model was established, and the characteristics of the pulse thyristor with buried FS layer and the pulse thyristor with conventional FS layer structure were compared and analyzed by using existing software. The performance was analyzed from the following perspectives:

[0106] 1) Forward blocking characteristics

[0107] Reference Figure 7, is a comparison of the forward blocking characteristics of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer. As can be seen from the figure, except for the changes in the distribution of the N2-base region and the FS layer, under the condition of the same parameters, the blocking voltage of the conventional FS layer pulse thyristor is 3800V, while the blocking voltage of the buried FS layer pulse thyristor reaches 4250V. At a voltage of 3500V, the leakage current of the buried FS layer pulse thyristor is about 3 times smaller than that of the conventional FS layer pulse thyristor.

[0108] 2) Reverse blocking characteristics

[0109] Reference Figure 8 , is a comparison of the reverse blocking characteristics of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer. Figure 5 It can be seen that the reverse blocking voltage of the conventional FS layer pulse thyristor is 50V, while the blocking voltage of the buried FS layer pulse thyristor reaches 740V.

[0110] 3) Forward conduction characteristics

[0111] Reference Fig. 9 , is a comparison of the conduction characteristics of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer. It can be seen that the on-state voltage drop of the pulse thyristor with buried FS layer of the present invention is slightly higher than that of the conventional FS layer structure.

[0112] 4) Pulse discharge characteristics

[0113] Depend on Fig.10 FIG. 4 is a comparison of the pulse discharge characteristic curves of the pulse thyristor with buried FS layer of the present invention and the conventional FS layer pulse thyristor. Fig.10 It can be seen that the discharge waveforms of the buried FS layer and the conventional FS layer pulse thyristors are basically the same, and the pulse discharge current peak Ipmax under the corresponding test circuit is basically the same. The turn-on delay of the conventional FS layer pulse thyristor is smaller, but the continuous pulse width when the current passes through zero is larger. In comparison, the di / dt of the conventional FS layer pulse thyristor is 2400A / μs, and the di / dt of the buried FS layer pulse thyristor is about 2250A / μs, and the current rise rate is slightly reduced.

[0114] Reliability evaluation

[0115] 1) Prevent dv / dt false triggering

[0116] like Fig.11 FIG. 1 is a comparison chart of the dv / dt tolerance of the pulse thyristor with buried FS layer of the present invention and the pulse thyristor with conventional FS layer. Fig.11It can be seen that when dv / dt is 1100V / μs, the conventional FS layer pulse thyristor has been mis-triggered, while the buried FS layer pulse thyristor has not been mis-triggered when dv / dt is 1500V / μs, indicating that the buried FS layer pulse thyristor of the present invention has a higher dv / dt tolerance.

[0117] 2) Forward and reverse ESD withstand voltage

[0118] The present invention has a buried FS layer pulse thyristor. In order to achieve rapid conduction of each unit, a strip cell is used, resulting in a small gate-cathode spacing, which is prone to electrostatic discharge failure. The ESD waveform of the pulse thyristor is tested using a conventional human body discharge model (HBM) test circuit. Fig.12 , is the forward and reverse ESD discharge waveform of the buried FS layer pulse thyristor gate-cathode of the present invention. Fig.12 It can be seen that when -2000V static voltage is applied to the gate-cathode, the ESD peak current Ip=1.32A, the rise time tri is 4ns, and the corresponding decay time tdi is 148ns; when +2000V static voltage is applied to the gate-cathode, Ip=1.3A, tri is 7ns, and the corresponding tdi is 146ns, which are in line with the relationship between the simulator charging voltage US and the peak current Ip specified by GJB. It can be seen that the gate-cathode of the pulse thyristor with buried FS layer of the present invention can withstand positive and reverse ESD withstand voltages of more than 2000V.

[0119] like Fig.13 FIG. 1 is a schematic cross-sectional view of the active region and terminal region of the pulse thyristor with a buried FS layer of the present invention. It can be seen that resistance regions of different lengths are added at the junctions of the positive and negative active regions and the terminal regions to suppress current concentration there and improve the reliability of the terminal; at the same time, because the reverse blocking voltage is low and the terminal size is small, the area of ​​the active region on the anode side is increased, so that the positive and reverse resistance regions are asymmetrically distributed.

[0120] The above analysis shows that compared with the conventional FS layer pulse thyristor, the present invention has a buried FS layer pulse thyristor, which can have a forward blocking voltage while also having a certain reverse blocking ability, and can cope with the reverse voltage ranging from hundreds of nanoseconds to microseconds applied during pulse discharge; and under the same structural parameters, it improves the forward and reverse blocking capabilities and dv / dt tolerance to avoid dv / dt false triggering.

[0121] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments. In the above embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An asymmetric pulse thyristor structure with a buried FS layer, characterized in that: include: A plurality of parallel strip-shaped cells are arranged on the surface, and the plurality of parallel strip-shaped cells are evenly distributed on the upper surface of the chip; The cross-sectional structure of each strip cell is N1 - The base region is the substrate, the N1 - The base region is sequentially provided with N FS layer and N2 - Base region and P + Anode region, P + The surface of the anode region is provided with an anode A; the N1 - The base region is sequentially provided with a P base region upward; an N + cathode region, the N + A cathode K is provided on the upper surface of the cathode region; + Gate electrodes G are provided on the upper surfaces of the P base regions on both sides of the cathode region.

2. The asymmetric pulse thyristor structure with a buried FS layer according to claim 1, characterized in that: The strip cell width is 60 μm to 100 μm.

3. The asymmetric pulse thyristor structure with a buried FS layer according to claim 1, characterized in that: The N + The width of the cathode region is 20 μm to 60 μm.

4. The asymmetric pulse thyristor structure with a buried FS layer according to claim 1, characterized in that: The thickness of the N FS layer is 20 μm to 30 μm, and the doping concentration of the N FS layer is 1×10 16 cm -3 ~3×10 16 cm -3 .

5. The asymmetric pulse thyristor structure with a buried FS layer according to claim 1, characterized in that: The N2 - The concentration and thickness of the base region are adjusted according to the reverse blocking voltage, and N1 - The base concentration and thickness are not equal.

6. A method for manufacturing an asymmetric pulse thyristor structure with a buried FS layer, using the structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: First, the reverse blocking voltage of the asymmetric pulse thyristor is judged; if the reverse blocking voltage is ≥500V, step A is executed, that is, the pre-epitaxial process is adopted; if the reverse blocking voltage is <500V, step B is executed, that is, the post-H is adopted. + Ion implantation process.

7. The method for manufacturing an asymmetric pulse thyristor structure with a buried FS layer according to claim 6, characterized in that: The step A comprises the following steps: Step A1, select the crystal direction <111> The original high resistance zone melting silicon single crystal is used as N1 - The base region is then corroded and cleaned on the surface of the original high-resistance region molten silicon single crystal; Step A2: On the crystal of step A1, a preliminary doping of the N FS layer on the back is formed by epitaxial process or phosphorus ion implantation; and at the same time, N2 - base area; Step A3, forming a masking film on the crystal subjected to step A2 by using dry oxygen oxidation and deposition process, and marking the crystal to distinguish the front and back sides; Step A4, on the front side of the wafer, a P base region of the active region and a P field limiting ring injection window of the terminal region are formed by photolithography, a sacrificial oxide layer is retained, boron ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned; Step A5: On the front side of the wafer, a masking film is deposited and advanced to form a P base region and a P field limiting ring, and the N FS layer is further advanced; Step A6: On the front side of the wafer, photolithography is performed to form N + Cathode region and N + The injection window of the cut-off region retains the sacrificial oxide layer, and phosphorus ion implantation is performed under the mask of photoresist and SiO2 film, and then the photoresist is removed and cleaned; Step A7, forming a deposited oxide layer on both the front and back sides of the wafer, and performing high-temperature densification, performing uniform glue protection on the front side, and rinsing and de-glue cleaning on the back side oxide layer; Step A8: Photolithography to form N + The cut-off region is implanted with a window, and then phosphorus ions are implanted under the mask of photoresist and SiO2 film, followed by de-resist and cleaning; Step A9: Deposit an oxide layer on the front and back sides of the wafer and form N + The cathode region and the N + cut-off area, while the N FS layer further advances; Step 10: Photolithography to form P on the back of the wafer + The anode region is injected with a window, and then boron ions are implanted under the mask of photoresist and SiO2 film, followed by de-resist and cleaning; Step A11, depositing an oxide layer on the front and back sides of the wafer, and advancing to form P + Anode region, P base region, N + Cathode region, N + The P field confinement ring in the cut-off area, N FS layer and terminal area is further advanced; Step A12, removing the oxide layer on the front and back sides of the wafer, re-performing dry oxygen oxidation, depositing oxide layers on the front and back sides, performing high-temperature densification, and performing uniform coating protection on the back side; Step A13, performing photolithography on the front and back sides of the wafer respectively to form electrode contact holes on the front and back sides; sputtering an aluminum-silicon-copper metal layer on the front side, and sputtering a thicker aluminum layer on the back side; Step A14, photolithography of the metal layer is performed on the front and back sides of the wafer respectively, and gate and cathode metal electrode patterns are formed on the front side; titanium, nickel and silver are sputtered on the back side, and anode multilayer metallization electrodes are formed by photolithography, and then alloyed to reduce ohmic contact resistance; Step A15, depositing silicon nitride film on the front and back sides of the wafer and performing photolithography, and passivating the front and back terminals of the chip; Step A16, a polyimide film is cast on the front side of the wafer, and patterns of the front gate and cathode region bonding area are formed by photolithography, and imidization treatment is performed to passivate and protect the front terminal; Step A17, dicing and packaging the wafer.

8. The method for manufacturing an asymmetric pulse thyristor structure with a buried FS layer according to claim 7, characterized in that: During the packaging process of step A17, the back packaging base and the anode bonding area have the same size, and a certain gap is left between the back packaging base and the back terminal area of ​​the chip.

9. The method for manufacturing an asymmetric pulse thyristor structure with a buried FS layer according to claim 6, characterized in that: The step B comprises the following steps: Step B1, select the crystal direction <111> The original high-resistance region molten silicon single crystal is used as the N-base region, and the surface of the original high-resistance region molten silicon single crystal is corroded and cleaned; Step B2, according to Step A3 to Step A4, sequentially manufacturing the P field limiting rings of the P base region and the terminal region; Step B3, depositing a masking film on the front side of the wafer and advancing it to form a P base region and a P field limiting ring; Step B4: According to Step A6 to Step A8, make the front N + Cathode region and N + cut-off region, and the back N + Cut-off area; Step B5: Deposit an oxide layer on the front and back sides of the wafer and form N + The cathode region and the N + Cut-off area; Step B6: According to step A10, make the P on the back + Anode area; Step B7: deposit an oxide layer on the front and back sides of the wafer and form a P + Anode region, P base region, N + Cathode region, N + The P field limiting ring in the cut-off and terminal areas is further advanced; Step B8, on the back side of the wafer, by high energy H ion implantation and low temperature annealing, an N FS buried layer is formed on the side of the N-base region close to the P anode region, and annealing is performed; Step B9, according to step A12 to step A17, the front and back electrodes and the passivation layer are manufactured in sequence; the wafer is sliced ​​and packaged.

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