Semiconductor device, manufacturing method thereof and electronic equipment
Through the production of the ring -grid crystal pipe, before the inner wall is etched into the formation of a source leakage and the overlapping area of the channel overlapping area, the GAaFet cannot suppress the problem of the tunnel leakage in the corridor, and realize it to achieve the realization. The effect of reducing leakage and improving the switch ratio.
Patent Information
- Application Number
- CN202411273631.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2025-01-21
AI Technical Summary
The existing GAAFETs cannot completely suppress the interband tunneling leakage in the overlapping area of the source and drain and channel under the off-state, resulting in the device's off-state leakage increase sharply as the gate length shortens, and the static power consumption gradually increases.
In the production of ring grid crystal pipes, before the inside wall is carved into the edge of the channel edge of the channel to inject the same type as the type of the channel and the opposite type of the source, Duplicate.
By forming a reflective weight doping, the concentration gradient of the leakage-channel knot is slowed down, and the leakage tunnel penetrates the gap, thereby reducing the leakage of the device and increasing the switch ratio of the ring of the ring.
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Figure CN119342857A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art
[0002] The structure of field effect transistor (FET) has gone through the development of planar structure transistor (PlanarFET), fin structure transistor (FinFET), and ring gate structure transistor (GAAFET).
[0003] As the feature size of integrated circuits continues to shrink, traditional three-gate or dual-gate FinFETs are limited at nodes below 3nm. GAAFET, which is compatible with the mainstream high-k metal gate FinFET process, will be the next-generation key structure to achieve size shrinkage. Its channel is mainly a stacked nanosheet structure.
[0004] However, the existing GAAFET cannot completely suppress the band-to-band tunneling (BTBT) leakage in the overlapping region of the source, drain and channel in the off state, resulting in a sharp increase in the device off-state leakage as the gate length shortens, and the proportion of static power consumption gradually increases. Therefore, optimizing static leakage is beneficial to reducing power consumption and improving the on-off ratio. Summary of the invention
[0005] The purpose of the present disclosure is to provide a method for manufacturing a semiconductor device, a semiconductor device and an electronic device.
[0006] A first aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising:
[0007] providing a substrate;
[0008] A fin structure for a gate-all-around transistor is formed on the substrate, the fin structure comprising:
[0009] A stacking portion, which is used to form a channel of a gate-all-around transistor, and the stacking portion is disposed on the substrate;
[0010] Performing an inner wall manufacturing process on the stacked portion to complete the inner wall deposition, using the inner wall as a barrier layer before etching the inner wall, and injecting heavy doping of the same type as the channel and opposite to the source and drain at the edge of the channel by ion implantation to form an inverse heavy doping in the overlapping area of the source, drain and channel;
[0011] The manufacturing of the ring-gate transistor is completed through subsequent processes.
[0012] In a possible implementation, the energy range of the ion implantation is 0.1 keV to 10 keV.
[0013] In a possible implementation, the ion implantation dose range is 1e12cm -2 ~1e21cm -2 .
[0014] In a possible implementation, the element types for ion implantation include one or more of B, Al, Ga, In, Ti, N, P, As, Sb, and Bi.
[0015] In a possible implementation, after the ion implantation is performed on the edge of the channel, the method further includes:
[0016] The impurity activation is performed through an annealing process.
[0017] In a possible implementation, the annealing activation temperature in the annealing process ranges from 500 to 1200°C.
[0018] In a possible implementation, the annealing time in the annealing process ranges from 1e -6 ~4s.
[0019] A second aspect of the present disclosure provides a semiconductor device, comprising:
[0020] substrate;
[0021] a gate-all-around transistor formed on the substrate;
[0022] The heavily doped region where the source, drain and channel of the all-around gate transistor overlap is of the same type as the channel and of an opposite type to the source and drain.
[0023] A third aspect of the present disclosure provides an electronic device, comprising the semiconductor device described in the second aspect.
[0024] The advantages of the present invention compared with the prior art are:
[0025] The manufacturing method of the semiconductor device disclosed in the present invention includes: providing a substrate, forming a fin structure for a ring-gate transistor on the substrate, the fin structure including: a stacking part, which is used to form a channel of the ring-gate transistor, the stacking part is arranged on the substrate; performing an inner sidewall manufacturing process on the stacking part to complete the inner sidewall deposition, using the inner sidewall as a barrier layer before etching the inner sidewall, injecting the same type of heavy doping as the channel at the edge of the channel by ion implantation, forming the source, drain and channel overlap region inverse heavy doping; completing the manufacturing of the ring-gate transistor by subsequent processes. It can be seen that in the manufacturing of the ring-gate transistor, the present application forms the source, drain and channel overlap region inverse heavy doping by ion implantation before etching the inner sidewall, so that the concentration gradient of the drain-channel junction is slowed down, which can increase the tunneling band gap at the drain end, thereby reducing the device leakage, and can improve the switching ratio of the ring-gate transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present disclosure. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0027] Figure 1 A schematic diagram of the structure of an existing GAAFET is shown;
[0028] Figure 2 A flow chart of a method for manufacturing a semiconductor device provided by the present disclosure is shown;
[0029] FIG. 3A to FIG. 3F It is a schematic diagram of the structure formed at various stages of the ring gate transistor production. DETAILED DESCRIPTION
[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0031] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0032] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.
[0033] like Figure 1 As shown in the figure, GAAFET is a gate-all-around field effect transistor (hereinafter referred to as a gate-all-around transistor). The essence of its transistor structure is to rotate the Fin of FinFET by 90° and then stack multiple Fins horizontally, and these Fins all pass through the gate. In GAAFET, due to the reduction of the in-situ doped source and drain and the width of the sidewall (Spacer), it becomes increasingly difficult to suppress channel leakage by conventional methods, that is, by reducing the concentration gradient in the SDE (source-drain extension) region.
[0034] In order to solve the above problems existing in the prior art, the embodiments of the present disclosure provide a method for manufacturing a semiconductor device, a semiconductor device and an electronic device, which are described below with reference to the accompanying drawings.
[0035] Figure 2 A flow chart of a method for manufacturing a semiconductor device provided by the present disclosure is shown, which can be used to prepare a ring-gate transistor; FIG. 3A to FIG. 3F It is a schematic diagram of the structure formed at various stages of the ring gate transistor production.
[0036] The method for manufacturing the semiconductor device comprises the following steps:
[0037] Step S101: providing a substrate;
[0038] Step S102: forming a fin structure for a gate-all-around transistor on the substrate, the fin structure comprising: a stacking portion, which is used to form a channel of the gate-all-around transistor, and the stacking portion is disposed on the substrate;
[0039] Step S103: Perform an inner wall manufacturing process on the stacked portion to complete the inner wall deposition. Before the inner wall is etched, the inner wall is used as a barrier layer, and heavy doping of the same type as the channel and opposite to the source and drain is injected into the edge of the channel through ion implantation to form an inverse heavy doping in the overlapping area of the source, drain and channel; and the manufacturing of the ring-gate transistor is completed through subsequent processes.
[0040] In some embodiments, after the step of injecting the same type of heavy doping as the channel into the edge of the channel by ion implantation, the step further includes: activating the impurities by an annealing process.
[0041] In the existing GAAFET manufacturing process, ultra-thin alternating layers of silicon germanium (SiGe) and silicon (Si) are first deposited on a silicon substrate to form a superlattice structure, with multiple layers of each material stacked to form stacked nanosheets. The nanosheets are exposed and etched in the superlattice structure. Then the internal sidewall (spacer) spacers are formed; when the spacer is etched, the surface of the silicon germanium layer in the superlattice structure is partially recessed and then filled with dielectric material. Then the source and drain are formed; the silicon germanium layer in the superlattice structure is removed, leaving a silicon-based sheet, which is the channel. Finally, the gate is formed by depositing high-k (high dielectric constant) dielectric and metal gate materials.
[0042] The present application uses the inner sidewall as a barrier layer before spacer etching, and injects heavy doping of the same type as the channel and opposite to the source and drain at the edge of the channel through ion implantation, so as to form an inverse heavy doping in the overlapping area of the source, drain and channel, thereby inhibiting the diffusion of the source and drain doping into the channel and inhibiting tunnel leakage in the area.
[0043] For details, please refer to FIG. 3A to FIG. 3F , FIG. 3A to FIG. 3F The upper middle figure is a cross-sectional view of the semiconductor device along the XX′ axis, and the lower figure is a cross-sectional view of the semiconductor device along the YY′ axis.
[0044] Figure 3A The figure shows the formation of SiGe / Si stacked epitaxy on a silicon substrate. The specific process is: S1, providing a Si substrate and performing substrate doping, including well lithography, ion implantation and annealing; S2, cleaning and SiGe / Si stacked epitaxy; S3, performing a sidewall transfer process, including Core layer (a-Si) deposition and patterning, HM film (silicon nitride or silicon oxide) deposition, sidewall etching, and Core layer selective removal;
[0045] S4, Fin etching, including anisotropic etching of SiGe / Si Fin to remove HM.
[0046] Figure 3B Shown in Figure 3A The specific process is as follows: S5, shallow trench isolation (STI), specifically, using a silicon nitride mask to form a trench after deposition, patterning, and etching silicon, and filling the trench with deposited oxide for isolation from the silicon substrate; S6, forming a polysilicon dummy gate; S7, forming a sidewall; S8, etching the source and drain regions.
[0047] Figure 3C Shown in Figure 3B The inner wall is made on the basis of the inner wall. The specific process is: S9, SiGe selective etching; S10, inner wall isolation dielectric film (silicon nitride or silicon oxide) deposition; S11, reverse ion implantation, specifically using the inner wall as a barrier layer, and injecting the same type of heavy doping as the channel at the edge of the channel through ion implantation; S12, impurity activation, which can be specifically activated by annealing at a certain temperature.
[0048] Figure 3D Shown in Figure 3C The specific process is as follows: S13, etching the inner sidewall isolation dielectric film to form the inner sidewall; S14, forming the source and drain epitaxy in the source and drain area, specifically, SiGe and Si are selected for the P / NMOS source and drain respectively; S15, performing source and drain doping, specifically, P / NMOS are doped separately, and the source and drain are activated at low temperature after doping; S16, depositing and planarizing the interlayer insulating layer ILD0.
[0049] Figure 3E Shown in Figure 3DBased on this, the channel is released and a high-k metal gate (HKMG) is formed. The specific process is: S17, remove the dummy gate; S18, release the nanosheet channel;
[0050] S19, performing high-k metal gate deposition; S20, performing chemical mechanical polishing (CMP) of the high-k metal gate.
[0051] Figure 3F Shown in Figure 3E The specific process is as follows: S21, depositing and planarizing the interlayer insulating layer ILD1; S22, performing photolithography of source and drain contact holes and depositing metal contacts.
[0052] In some embodiments, the energy range of the ion implantation is 0.1 keV to 10 keV.
[0053] In some embodiments, the ion implantation dose range is 1e12 cm -2 ~1e21cm -2 .
[0054] In some embodiments, the element types of the ion implantation include one or more of B, Al, Ga, In, Ti, N, P, As, Sb, and Bi.
[0055] In some embodiments, the annealing activation temperature in the annealing process ranges from 500 to 1200° C.
[0056] In some embodiments, the annealing time in the annealing process ranges from 1e -6 ~4s.
[0057] In the above method, different inversion doping gradients can be achieved by multiple injections at different angles, different doses and different energies.
[0058] The manufacturing method of the semiconductor device disclosed in the present invention includes: providing a substrate, forming a fin structure for a ring-gate transistor on the substrate, the fin structure including: a stacking part, which is used to form a channel of the ring-gate transistor, the stacking part is arranged on the substrate; performing an inner sidewall manufacturing process on the stacking part to complete the inner sidewall deposition, using the inner sidewall as a barrier layer before etching the inner sidewall, injecting the same type of heavy doping as the channel at the edge of the channel by ion implantation, forming the source, drain and channel overlap region inverse heavy doping; completing the manufacturing of the ring-gate transistor by subsequent processes. It can be seen that in the manufacturing of the ring-gate transistor, the present application forms the source, drain and channel overlap region inverse heavy doping by ion implantation before etching the inner sidewall, so that the concentration gradient of the drain-channel junction is slowed down, which can increase the tunneling band gap at the drain end, thereby reducing the device leakage, and can improve the switching ratio of the ring-gate transistor.
[0059] The present disclosure also provides a semiconductor device manufactured based on the above-mentioned method for manufacturing a semiconductor device, the semiconductor device comprising:
[0060] substrate;
[0061] a gate-all-around transistor formed on the substrate;
[0062] The heavily doped region where the source, drain and channel of the all-around gate transistor overlap is of the same type as the channel and of an opposite type to the source and drain.
[0063] The present disclosure also provides an electronic device, which includes the semiconductor device in the above embodiment. The semiconductor device can be incorporated into at least one of a smart phone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a mobile power supply.
[0064] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0065] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; A fin structure for a gate-all-around transistor is formed on the substrate, the fin structure comprising: A stacking portion, which is used to form a channel of a gate-all-around transistor, and the stacking portion is disposed on the substrate; Performing an inner wall manufacturing process on the stacked portion to complete the inner wall deposition, using the inner wall as a barrier layer before etching the inner wall, and injecting heavy doping of the same type as the channel and opposite to the source and drain at the edge of the channel by ion implantation to form an inverse heavy doping in the overlapping area of the source, drain and channel; The manufacturing of the ring-gate transistor is completed through subsequent processes.
2. The method according to claim 1, characterized in that: The energy range of the ion implantation is 0.1 keV to 10 keV.
3. The production method according to claim 1 or 2, characterized in that: The ion implantation dose range is 1e12cm -2 ~1e21cm -2 .
4. The method according to claim 1 or 2, characterized in that: The element types for ion implantation include one or more of B, Al, Ga, In, Ti, N, P, As, Sb, and Bi.
5. The method according to claim 1, characterized in that: After the method of implanting the same type of heavy doping as the channel at the edge of the channel by ion implantation, the method further comprises: The impurity activation is performed through an annealing process.
6. The method according to claim 5, characterized in that: The annealing activation temperature in the annealing process ranges from 500 to 1200°C.
7. The manufacturing method according to claim 6, characterized in that: The annealing time range in the annealing process is 1e -6 ~4s.
8. A semiconductor device, characterized in that: include: substrate; a gate-all-around transistor formed on the substrate; The heavily doped region where the source, drain and channel of the all-around gate transistor overlap is of the same type as the channel and of an opposite type to the source and drain.
9. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to claim 8.