Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure includes: an active pillar; the active column comprises a source region, a channel and a drain region which are sequentially stacked, the channel is provided with a source end and a drain end which are oppositely arranged, the source end is arranged close to the source region, the drain end is arranged close to the drain region, a doping peak region is arranged in the channel, and the doping concentration of the doping peak region is higher than that of other regions in the channel; the distance between the doped peak region and the source terminal is smaller than the distance between the doped peak region and the drain terminal.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] In the field of semiconductor technology, reducing the critical dimensions of a device is an effective way to improve device performance. A vertical channel transistor (VCT) is a new type of semiconductor device. Compared with traditional planar transistors, a vertical channel transistor has a channel arranged in the height direction, which can reduce the critical dimensions of the transistor and is expected to increase the stacking density of the device. However, the channel performance of the vertical channel transistor needs to be further improved. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problems in the above-mentioned background technology, so as to improve the gate induced drain leakage current problem in the vertical channel transistor, thereby improving the channel performance of the vertical channel transistor.

[0004] According to some embodiments of the present disclosure, a semiconductor structure is provided, which includes an active pillar; the active pillar includes a source region, a channel and a drain region which are stacked in sequence, the channel has a source end and a drain end which are relatively arranged, the source end is arranged close to the source region, the drain end is arranged close to the drain region, the channel has a doping peak region, the doping concentration of the doping peak region is higher than the doping concentration of other regions in the channel, and the distance between the doping peak region and the source end is smaller than the distance between the doping peak region and the drain end.

[0005] In some embodiments of the present disclosure, the doping concentration in the channel gradually decreases from the peak region of the doping concentration toward the drain end.

[0006] In some embodiments of the present disclosure, the doping concentration of the source terminal is higher than the doping concentration of the drain terminal.

[0007] In some embodiments of the present disclosure, the ratio of the distance between the doping peak region and the drain terminal to the length of the channel is (85-95):100.

[0008] In some embodiments of the present disclosure, a bit line, a word line structure and a capacitor are further included, wherein the bit line is electrically connected to the source region, the word line structure is arranged on the side wall of the channel region, and the capacitor is electrically connected to the drain region.

[0009] Furthermore, the present disclosure also provides a method for preparing a semiconductor structure as described in any of the above embodiments, comprising the following steps:

[0010] preparing a functional layer on a substrate;

[0011] The source region and the drain region are prepared in the functional layer, and the functional layer is subjected to ion implantation and annealing to form the channel between the source region and the drain region. The step of ion implantation includes:

[0012] Performing multiple ion implantations on the functional layer, wherein the implantation energy and implantation dose of each ion implantation process are different, and the implantation dose of the ion implantation process in the implantation area closer to the source region is larger, so that the doping peak region in the channel is shifted toward the source region; or,

[0013] Performing a single ion implantation on the functional layer, during which the implantation region is controlled to be closer to the source region, so that the doping peak region in the channel is shifted toward the source region; or,

[0014] The functional layer is subjected to tilted ion implantation. During the tilted ion implantation, the implantation direction is controlled to be tilted relative to the channel direction, and the ion source is controlled to rotate around the channel direction relative to the functional area, so that the doping peak area in the channel is offset toward the source area.

[0015] In some embodiments of the present disclosure, the step of performing multiple ion implantations on the functional region includes more than three ion implantation processes.

[0016] In some embodiments of the present disclosure, in the step of performing inclined ion implantation on the functional region, the angle between the implantation direction and the channel direction is controlled to be 4° to 9°; and / or,

[0017] The implantation energy is controlled to be 18keV to 25keV, and the implantation dose is 10E13 / cm 3 ~10E16 pieces / cm 3 .

[0018] In some embodiments of the present disclosure, the following steps are also included:

[0019] Etching the functional layer along a first direction to form a plurality of first grooves spaced apart from each other in the functional layer; and,

[0020] The functional layer is etched along a second direction intersecting the first direction to form a plurality of second grooves arranged at intervals in the functional layer, wherein the first grooves and the second grooves separate the functional layer into a plurality of active pillars arranged in an array.

[0021] In some embodiments of the present disclosure, the following steps are also included:

[0022] Preparing a bit line in the substrate between adjacent first trenches, wherein the bit line is located at a side of the source region away from the drain region and the bit line is electrically connected to the source region;

[0023] preparing a word line structure disposed on a sidewall of the trench in the second trench; and,

[0024] A capacitor is fabricated on a side of the drain region away from the source region.

[0025] In the vertical channel transistor of the conventional technology, the doping concentration in the channel is usually relatively uniform or symmetrically arranged along the center line of the channel. The semiconductor structure provided in the present disclosure includes an active column. Among them, the active column includes a source region, a channel and a drain region, and there is a doping peak region in the channel, and the doping concentration of the doping peak region is higher than the doping concentration of other regions in the channel, and the doping peak region is located on the side of the center line between the source end and the drain end close to the source end. By controlling the doping peak region to be away from the drain end and offset toward the source end, the gate induced drain leakage current in the vertical channel transistor can be effectively reduced, the problem of gate induced drain leakage current can be improved, and the channel performance of the vertical channel transistor can be improved.

[0026] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0028] Figure 1 is a schematic cross-sectional view of a semiconductor structure along the channel axis;

[0029] Figure 2 for Figure 1 Schematic diagram of the change of doping concentration of the channel from the source end to the drain end;

[0030] Figure 3A Schematic diagram of a top view structure of a substrate and a functional layer. Figure 3B For along Figure 3A Schematic diagram of the cross-sectional structure at BB' in the figure. Figure 3C For along Figure 3A Schematic diagram of the cross-sectional structure at CC' in FIG.

[0031] Figure 4A For Figure 3AA schematic diagram of a top view of the structure of the first isolation layer prepared on the basis of the structure shown in FIG. Figure 4B For along Figure 4A Schematic diagram of the cross-sectional structure at BB' in the figure. Figure 4C For along Figure 4A Schematic diagram of the cross-sectional structure at CC' in FIG.

[0032] Figure 5A Shown in Figure 4A A schematic diagram of a top view of the structure of the source region, drain region and channel prepared on the basis of the structure shown in FIG. Figure 5B For along Figure 5A Schematic diagram of the cross-sectional structure at BB' in the figure. Figure 5C For along Figure 5A Schematic diagram of the cross-sectional structure at CC' in FIG.

[0033] Figure 6 For Figure 5B A schematic diagram of the structure after a single ion implantation based on the structure shown;

[0034] Fig. 7A For Figure 5B A schematic diagram of the structure after the first ion implantation process is performed on the structure shown in FIG. Figure 7B For Fig. 7A A schematic diagram of the structure after the second ion implantation process is performed on the structure shown in FIG. Figure 7C For Figure 7B A schematic diagram of a structure after a third ion implantation process is performed on the structure shown;

[0035] Figure 8 For Figure 5B A schematic diagram of a cross-sectional structure of performing tilted ion implantation based on the structure shown;

[0036] Fig. 9A Shown in Figure 5A Schematic diagram of the top view of the structure of preparing the second isolation layer based on the structure shown. Fig. 9B For along Fig. 9A Schematic diagram of the cross-sectional structure at BB' in the figure. Fig. 9C For along Fig. 9A Schematic diagram of the cross-sectional structure at CC' in FIG.

[0037] The reference numerals and their meanings are as follows:

[0038] 10. Substrate; 100. Functional layer; 101. First groove; 110. Channel; 111. Doping peak region; 1111. Single injection region; 1121. First injection region; 1122. Second injection region; 1123. Third injection region; 1131. Inclined injection region; 120. Source region; 130. Drain region; 200. Bit line; 300. Capacitor; 400. Word line structure; 410. Gate dielectric layer; 420. Gate; 510. First isolation layer; 520. Second isolation layer. DETAILED DESCRIPTION

[0039] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0041] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0042] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] The disclosed embodiments are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing, and the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

[0045] The present disclosure Figure 1 is a schematic cross-sectional view of a semiconductor structure along the channel axis, referring to Figure 1 As shown, the semiconductor structure includes an active column, which includes a source region 120, a channel 110 and a drain region 130 arranged in sequence from bottom to top, and the channel 110 has a source end and a drain end arranged oppositely, the source end is arranged close to the source region 120, and the drain end is arranged close to the drain region 130. It can be understood that in Figure 1 In the embodiment, the bottom end of the channel 110 is the source end, and the top end of the channel 110 is the drain end. Figure 2 for Figure 1 Schematic diagram of the change of doping concentration of the channel 110 from the source end to the drain end, Figure 2The horizontal axis represents the radial cross-sectional area between the source end and the drain end, and the vertical axis represents the doping concentration of the corresponding area. Figure 1 and Figure 2 As shown, the channel 110 has a doping peak region 111, the doping concentration of the doping peak region 111 is higher than the doping concentration of other regions in the channel 110, and the distance between the doping peak region 111 and the source end is smaller than the distance between the doping peak region 111 and the drain end, that is, the doping peak region 111 is offset toward the source end. Figure 1 and Figure 2 As shown, the doping peak region 111 is located on the side of the midline between the source terminal and the drain terminal close to the source terminal. In the channel 110, other regions refer to regions other than the doping peak region 111, and the doping peak region 111 has the highest doping concentration, while the doping concentrations of other regions are lower than the doping concentration of the doping peak region 111, which means that the doping concentrations of other regions are not equal to the doping concentration of the doping peak region 111.

[0046] In the vertical channel transistor of the conventional technology, the doping concentration in the channel is usually relatively uniform or symmetrically arranged along the center line of the channel. The semiconductor structure provided in the present disclosure includes an active column. Among them, the active column includes a source region 120, a channel 110 and a drain region 130, and the channel 110 has a doping peak region 111, and the doping concentration of the doping peak region 111 is higher than the doping concentration of other regions in the channel 110, and the doping peak region 111 is located on the side of the center line between the source terminal and the drain terminal close to the source terminal. By controlling the doping peak region 111 to be away from the drain terminal and offset toward the source terminal, the gate induced drain leakage current in the vertical channel transistor can be effectively reduced, the problem of gate induced drain leakage current can be improved, and the channel 110 performance of the vertical channel transistor can be improved.

[0047] In some examples of this embodiment, the doping concentration of the channel 110 gradually decreases between the doping peak region 111 and the drain terminal. The doping concentration of the channel 110 is controlled to gradually decrease, that is, the doping concentration presents a gradient change, which can ensure that the overall doping concentration distribution of the channel 110 is relatively uniform, and the conduction performance of the channel 110 is guaranteed while improving the gate induced drain current leakage.

[0048] It can be understood that the doping concentration between the doping peak region 111 and the drain terminal may be gradually reduced in a discontinuous manner or in a continuous manner.

[0049] For example, in the discontinuous reduction method, multiple intervals can be formed between the doping peak region 111 and the drain end according to the doping concentration, the doping concentration in each interval is constant, and the doping concentration in the later interval is lower than the doping concentration in the previous interval. In addition, adjacent intervals can be adjacent, or there can be a transition interval between adjacent intervals, and the doping concentration in the transition interval can be continuously reduced in the direction from the doping peak region 111 toward the drain end.

[0050] For example, in a continuously decreasing manner, between the doping peak region 111 and the drain terminal, the doping concentration of the region closer to the drain terminal is always lower than the doping concentration of the region farther from the drain terminal. Further, the variation trend of the doping concentration may be linear or nonlinear, for example, the variation trend may conform to the trend of Gaussian distribution.

[0051] Reference Figure 2 As shown, in this embodiment, the doping concentration decreases continuously from the doping peak region 111 toward the drain end.

[0052] Further, in some examples of this embodiment, in the channel 110, the doping concentration of the source terminal is higher than the doping concentration of the drain terminal. Setting the doping concentration of the source terminal higher than the doping concentration of the drain terminal is beneficial to further improve the overall conductivity performance of the channel 110 while reducing the gate induced drain leakage current.

[0053] In some examples of this embodiment, the doping type of the channel 110 is different from the doping type of the source region 120, and the doping type of the channel 110 is different from the doping type of the drain region 130. For example, the doping type of the channel 110 may be P-type, and the doping types of the source region 120 and the drain region 130 may be N-type.

[0054] In some examples of this embodiment, the doping concentration of the source terminal is 10 13 Pieces / cm 3 ~10 15 Pieces / cm 3 For example, the doping concentration of the source is 10 13 Pieces / cm 3 , 2×10 13 Pieces / cm 3 , 5×10 13 Pieces / cm 3 , 10 14 Pieces / cm 3 , 2×10 14 Pieces / cm 3 , 5×10 14 Pieces / cm 3 or 10 15 Pieces / cm 3Alternatively, the doping concentration of the source end may also be in the range between any two of the above doping concentrations.

[0055] In some examples of this embodiment, the doping concentration of the drain terminal is 10 13 Pieces / cm 3 ~10 15 Pieces / cm 3 For example, the doping concentration of the drain terminal is 10 13 Pieces / cm 3 , 2×10 13 Pieces / cm 3 , 5×10 13 Pieces / cm 3 , 10 14 Pieces / cm 3 , 2×10 14 Pieces / cm 3 , 5×10 14 Pieces / cm 3 or 10 15 Pieces / cm 3 Alternatively, the doping concentration of the drain terminal may also be in the range between any two of the above doping concentrations. Controlling the doping concentrations of the source terminal and the drain terminal within the above doping concentration range can ensure that the channel 110 has good conductivity performance and threshold voltage performance.

[0056] In some examples of this embodiment, the doping concentration of the doping peak region 111 may be 10 14 Pieces / cm 3 ~10 15 Pieces / cm 3 The maximum doping concentration in the doping concentration variation section is controlled to be 10 14 Pieces / cm 3 ~10 15 Pieces / cm 3 , which can make the overall doping concentration change of the doping concentration change portion relatively flat, so that the current distribution is also relatively uniform, thereby improving the durability of the channel 110.

[0057] In some examples of this embodiment, the ratio of the distance between the doping peak region 111 and the drain end to the length of the channel 110 is (85-95):100. It can be understood that the distance between the doping peak region 111 and the drain end is mainly determined by the position of the doping peak region 111 in the channel 110. The closer the doping peak region 111 is to the source end, the larger the distance between the doping peak region 111 and the drain end, and the larger the ratio of the distance between the doping peak region 111 and the length of the channel 110. Figure 2As shown, the distance between the doping peak region 111 and the drain end is d1, the length of the channel 110 is d2, and the ratio of d1 to d2 is (85-95): 100. By controlling the ratio of the distance between the doping peak region 111 and the drain end to the length of the channel 110 to be (85-95): 100, the gate induced drain leakage current of the channel 110 can be significantly improved.

[0058] In some examples of this embodiment, the ratio of the spacing between the doping peak region 111 and the drain terminal to the length of the channel 110 can be 85:100, 88:100, 90:100, 92:100 or 95:100. The ratio of the spacing between the doping peak region 111 and the drain terminal to the length of the channel 110 can also be within the range of the ratio of any two lengths mentioned above.

[0059] Reference Figure 1 As shown, in some examples of this embodiment, the semiconductor structure may further include a bit line 200, a word line structure 400 and a capacitor 300. The bit line 200 is electrically connected to the source region 120, the capacitor 300 is electrically connected to the drain region 130, and the word line structure 400 is disposed on the side wall of the active column. Among them, the word line structure 400 may include a gate 420 and a gate dielectric layer 410, and the gate dielectric layer 410 is disposed between the gate 420 and the active column. It can be understood that the word line structure 400 is used to control the on-off of the electrical signal of the channel 110 in the active column, and then control the on-off of the electrical signal between the bit line 200 and the capacitor 300. Combining the design of the active column, the bit line 200, the word line structure 400 and the capacitor 300, a storage unit capable of storing information can be formed.

[0060] The present disclosure also provides a method for preparing the above semiconductor structure, which includes steps S1 to S4, as follows.

[0061] Step S1 : preparing a functional layer 100 on a substrate 10 .

[0062] Figure 3A FIG. 1 is a schematic diagram of a top view of a substrate 10 and a functional layer 100. Figure 3A As shown, the functional layer 100 is disposed on the substrate 10 .

[0063] In some examples of this embodiment, the material of the substrate 10 may be a semiconductor material, for example, the material of the substrate 10 may be one or more of silicon, germanium, silicon-germanium alloy, gallium nitride, gallium arsenide or silicon carbide.

[0064] In some examples of this embodiment, the step of preparing the functional layer 100 on the substrate 10 may further include: etching the functional layer 100 along the first direction to form a plurality of first grooves 101 extending along the first direction in the functional layer 100 .

[0065] Reference Figure 3A For ease of explanation, Figure 3A There are shown a first direction and a second direction intersecting each other, the first direction is Figure 3A The y direction in the second direction is Figure 3A In some examples of this embodiment, the first direction and the second direction may be perpendicular to each other. Figure 3B For along Figure 3A Schematic diagram of the cross-sectional structure at BB' in the figure. Figure 3C For along Figure 3A Schematic diagram of the cross-sectional structure at CC' in FIG. Figure 3A to Figure 3C As shown, a plurality of first grooves 101 extending along a first direction may be provided in the functional layer 100 , and the plurality of first grooves 101 are arranged in parallel and at intervals.

[0066] In some examples of this embodiment, after the functional layer 100 is prepared on the substrate 10 , the following step is further included: preparing a first isolation layer 510 in the first trench 101 . Figure 4A For Figure 3A A schematic top view of the structure of the first isolation layer 510 is prepared based on the structure shown. Figure 4B For along Figure 4A Schematic diagram of the cross-sectional structure at BB' in the figure. Figure 4C For along Figure 4A Schematic diagram of the cross-sectional structure at CC' in FIG.

[0067] Reference Figure 4A to Figure 4C As shown, the first isolation layer 510 is disposed in the first trench 101 . The first isolation layer 510 is used to block the implanted ions during the subsequent process of preparing the channel 110 , so as to ensure that the ions are not implanted into the substrate 10 as much as possible.

[0068] In some examples of this embodiment, the material of the first isolation layer 510 may be an insulating material. For example, the material of the first isolation layer 510 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the first isolation layer 510 may include silicon oxide.

[0069] Reference Figure 4A to Figure 4C As shown, in some examples of this embodiment, in the step of preparing the first isolation layer 510 in the first groove 101, the first isolation layer 510 can also cover the functional layer 100. Further, the spacing between the top surface of the first isolation layer 510 and the top surface of the functional layer 100 is less than 10nm. For example, the spacing between the top surface of the first isolation layer 510 and the top surface of the functional layer 100 can be 2nm, 3nm, 5nm, 7nm or 10nm. Further, the spacing between the top surface of the first isolation layer 510 and the top surface of the functional layer 100 can also be a range between any two of the above spacings.

[0070] Step S2 , preparing a source region 120 and a drain region 130 in the functional layer 100 , and performing ion implantation and annealing on the functional layer 100 to form a channel 110 between the source region 120 and the drain region 130 .

[0071] In some examples of this embodiment, the step of preparing the source region 120 and the drain region 130 in the functional layer 100 may include: doping the functional layer 100 so that the functional layer 100 has a first doping type, and forming the source region 120 and the drain region 130 respectively. It can be understood that since the source region 120 and the drain region 130 have the same doping type, the source region 120 and the drain region 130 can be formed at the same time in this step. In addition, the functional layer 100 located between the source region 120 and the drain region 130 may also have the first doping type, but this part of the functional layer 100 can form the channel 110 after ion implantation and annealing.

[0072] Figure 5A Shown in Figure 4A A schematic diagram of a top view of the structure of the source region 120, the drain region 130 and the channel 110 is prepared on the basis of the structure shown. Figure 5B For along Figure 5A Schematic diagram of the cross-sectional structure at BB' in the figure. Figure 5C For along Figure 5A Schematic diagram of the cross-sectional structure at CC' in FIG.

[0073] Reference Figure 5A to Figure 5C As shown, the channel 110 is located between the source region 120 and the drain region 130. Further, in this embodiment, the channel 110 has a source terminal and a drain terminal that are arranged opposite to each other, the source terminal is arranged close to the source region 120, and the drain terminal is arranged close to the drain region 130, and the channel 110 has a doping peak region 111, the doping concentration of the doping peak region 111 is higher than the doping concentration of other regions in the channel 110, and the distance between the doping peak region 111 and the source terminal is smaller than the distance between the doping peak region 111 and the drain terminal.

[0074] It can be understood that the ion implantation process is used to implant ions at a specific dose into a specific depth of the functional layer 100, and the annealing process is used to diffuse the implanted ions into the lattice of the functional layer 100 to achieve doping. In a relatively ideal case, after the ion implantation process and the annealing process, the doping concentration obeys a Gaussian distribution. The doping type depends on the type of ions implanted, and therefore, the corresponding doping type can be obtained by selecting the type of ions implanted. For example, in this embodiment, the functional layer 100 can have N-type doping, and the implanted ions can include boron ions to form a P-type channel 110 region between the source region 120 and the drain region 130.

[0075] When preparing the channel 110 with conventional technology, during ion implantation, the implantation region is usually the midline between the source region 120 and the drain region 130. Through annealing, the doping ions diffuse to both ends, thereby forming the channel 110. In the channel 110, the doping peak region 111 is located at the midline between the source end and the drain end. The present disclosure combines the characteristics of the vertical channel, and by controlling the specific method of ion implantation, the doping peak region 111 can be offset toward the source end, so that the distance between the doping peak region 111 and the source end is smaller than the distance between the doping peak region 111 and the drain end. This can more effectively improve the problem of gate-induced drain leakage current in the vertical channel.

[0076] The present disclosure provides three methods for preparing the above-mentioned channel 110, which can refer to the following step S2.1, step S2.2 and step S2.3 respectively.

[0077] Step S2 . 1 , performing a single ion implantation on the functional layer 100 , during which the implantation region is controlled to be closer to the source region 120 , so that the doping peak region 111 in the channel 110 is offset toward the source region 120 .

[0078] Figure 6 For Figure 5B Schematic diagram of the structure after a single ion implantation based on the structure shown in FIG. Figure 6 The arrow in the figure indicates the direction of ion implantation. Figure 6 As shown, after a single ion implantation, a single implantation region 1111 is formed in the functional layer 100 .

[0079] It can be understood that during the ion implantation process, the energy of the ion implantation can be controlled so that the single implantation region 1111 is closer to the source region 120. The single implantation region 1111 is closer to the source region 120 means that the distance between the single implantation region 1111 and the source region 120 is smaller than the distance between the single implantation region 1111 and the drain region 130. The doping peak region 111 is offset toward the source region 120 means that the doping peak region 111 is offset toward the source region 120 relative to the center line between the source region 120 and the drain region 130, so that the distance between the doping peak region 111 and the source region 120 is smaller than the distance between the doping peak region 111 and the drain region 130.

[0080] After the ion implantation, annealing is performed to allow the doped atoms in the single implantation region 1111 to diffuse toward the source region 120 and the drain region 130, respectively. It can be understood that during the annealing process, the injected atoms are driven by the concentration difference to diffuse toward both sides. With the single implantation region 1111 as the center, the farther away from the single implantation region 1111, the lower the concentration of the doped atoms, so the doping peak region 1111 is located in the single implantation region 1111. Furthermore, in the formed channel 110, the doping concentration gradually decreases from the doping peak region 111 toward the drain end, and since the single implantation region 1111 is closer to the source region 120, the doping concentration at the source end is also higher than the doping concentration at the drain end.

[0081] It can be understood that in the ion implantation step, the implantation energy can be adjusted accordingly according to the actual thickness of the functional layer 100 and the position of the required single implantation region 1111, and the implantation dose can be adjusted according to the actual required doping concentration.

[0082] In some examples of this embodiment, the annealing process can be performed after the multiple ion implantation processes are completed. During the annealing process, the annealing temperature can be controlled to be 500° C. to 700° C., and the annealing time can be controlled to be 30 min to 240 min.

[0083] Through step S2.1, the channel 110 in the semiconductor structure of the present disclosure can be formed to improve the problem of drain leakage current induced by the gate 420. In addition, the doping concentration after annealing obeys the Gaussian distribution, which makes the doping concentration from the doping peak region 111 to the drain end vary greatly, limiting the further improvement of the performance of the channel 110.

[0084] In step S2.2, multiple ion implantations are performed on the functional layer 100 . The energy and implantation dose of each ion implantation process are different, and the implantation dose in the ion implantation process where the implantation area is closer to the source region 120 is larger, so that the doping peak region 111 in the channel 110 is offset toward the source region 120 .

[0085] It can be understood that, during the ion implantation process, the greater the implantation energy, the deeper the ion implantation region, and the greater the implantation dose, the higher the doping concentration of the implantation region after annealing. The implantation region refers to the region where the ions are located after being implanted into the functional layer 100. In this embodiment, the source region 120 is located below the drain region 130. During the ion implantation process, the greater the implantation energy, the closer the ion implantation region is to the source region 120. Conversely, the smaller the implantation energy, the closer the ion implantation region is to the source region 120. It can be understood that in other embodiments, the source region 120 can be located above the drain region 130. At this time, the smaller the implantation energy, the closer the ion implantation region is to the source region 120.

[0086] In the above-mentioned multiple ion implantation processes, the ion implantation process with a larger implantation energy can be set to also have a larger implantation dose, so that the implantation dose in the ion implantation process where the implantation region is closer to the source region 120 is larger. In the multiple ion implantation processes, the distance between the implantation region closest to the source region 120 and the source region 120 is smaller than the distance between the implantation region and the drain region 130.

[0087] In some examples of this embodiment, an ion implantation process with a larger implantation energy may be performed before an ion implantation process with a smaller implantation energy, that is, multiple implantation processes are performed sequentially from deep to shallow to avoid as much as possible the impact of the previously implanted ions on the subsequently implanted ions.

[0088] Further, in some examples of this embodiment, the step of performing multiple ion implantation on the functional area may include more than three ion implantation processes. For example, in this embodiment, the step of performing multiple ion implantation on the functional area includes a first ion implantation process, a second ion implantation process, and a third ion implantation process.

[0089] Fig. 7A For Figure 5B A schematic diagram of the structure after the first ion implantation process is performed on the structure shown in FIG. Figure 7B For Fig. 7A A schematic diagram of the structure after the second ion implantation process is performed on the structure shown in FIG. Figure 7C For Figure 7B Schematic diagram of the structure after the third ion implantation process is performed on the structure shown. Figure 7A to Figure 7C The arrows in the figure indicate the direction of ion implantation.

[0090] The implantation energy of the first ion implantation process is 23keV to 26keV, and the implantation dose of the first ion implantation process is 10 15 Pieces / cm 3 ~10 16 Pieces / cm 3 The injection energy of the second ion injection process is 21keV to 23keV, and the injection dose of the second ion injection process is 10 14 Pieces / cm 3 ~10 15 Pieces / cm 3 The implantation energy of the third ion implantation process may be 18keV to 21keV, and the implantation dose of the third ion implantation process may be 10 13 Pieces / cm 3 ~10 14 Pieces / cm 3 .

[0091] Reference Figure 7A to Figure 7CAs shown, after the first ion implantation process, a first implantation region 1121 is formed in the functional layer 100, after the second ion implantation process, a second implantation region 1122 is formed in the functional layer 100, and after the third ion implantation process, a third implantation region 1123 is formed in the functional layer 100. Due to the difference in implantation energy, the first implantation region 1121 is closest to the source region 120, the second implantation region 1122 is second, and the third implantation region 1123 is farthest from the source region 120. In addition, the implantation dose of the first implantation region 1121 is the largest, and after annealing, the doping peak region 111 is also located in the first implantation region 1121. In addition, due to the introduction of the second implantation region 1122 and the third implantation region 1123, the doping concentration change from the doping peak region 111 to the drain end is more gentle, which also makes the channel 110 have better conductivity.

[0092] It can be understood that during the annealing process, the injected ions can diffuse under the drive of the concentration difference. Therefore, although the ion implantation is performed in multiple times, in the doping concentration variation portion finally formed, the doping concentration can be continuously reduced in the direction from the source region 120 to the drain region 130. By controlling the dose and depth of the second implantation region 1122 and the third implantation region 1123, or introducing more implantation processes, it is possible to achieve a more precise adjustment of the doping concentration between the doping peak region 111 and the drain end.

[0093] In some examples of this embodiment, the annealing process can be performed after the multiple ion implantation processes are completed. During the annealing process, the annealing temperature can be controlled to be 500° C. to 700° C., and the annealing time can be controlled to be 30 min to 240 min.

[0094] Step S2.3, performing tilted ion implantation on the functional layer, during which the implantation direction is controlled to be tilted relative to the channel direction, and the ion source is controlled to rotate around the channel direction relative to the functional layer, so that the doping peak region in the channel is offset toward the source region.

[0095] The direction of the channel 110 is the direction determined by the source region 120 and the drain region 130. In this embodiment, the direction of the channel 110 may be vertical. It is understood that the source region 120 is located below the drain region 130. During the tilted ion implantation, the implantation direction is controlled to be tilted downward.

[0096] Figure 8 For Figure 5BA schematic diagram of a cross-sectional structure of an inclined ion implantation based on the structure shown, wherein the arrow indicates the implantation direction, which is inclined relative to the vertical direction (i.e., the direction of the channel 110). During the ion implantation process, the ion source is controlled to rotate around the vertical direction relative to the functional layer 100. The direction of the ion implantation is controlled to be inclined relative to the direction of the channel 110, so that an inclined implantation region 1131 closer to the source region 120 can be formed. The ion source is controlled to rotate around the direction of the channel 110 relative to the functional layer 100, so that the ion implantation dose on the plane perpendicular to the direction of the channel 110 is uniform. Thus, in the step of performing the annealing treatment, a doping peak region 111 offset toward the source region 120 can be formed.

[0097] In some examples of this embodiment, in the step of performing tilted ion implantation on the functional layer 100, the acute angle between the implantation direction and the direction of the channel 110 is controlled to be 4° to 9°. Further, the acute angle between the implantation direction and the direction of the channel 110 can be controlled to be 4°, 5°, 6°, 7°, 8° or 9°. The acute angle between the implantation direction and the direction of the channel 110 can also be a range between any two of the above angles.

[0098] In some examples of this embodiment, in the step of performing tilted ion implantation on the functional layer 100, the implantation energy is controlled to be 18keV to 25keV, and the implantation dose is 10 13 Pieces / cm 3 ~10 16 Pieces / cm 3 .

[0099] In some examples of this embodiment, the annealing process can be performed after the inclined ion implantation is completed. During the annealing process, the annealing temperature can be controlled to be 500° C. to 700° C., and the annealing time can be controlled to be 30 min to 240 min.

[0100] It can be understood that by controlling the angle between the injection direction and the direction of the channel 110, the length of the doping concentration variation portion can be well controlled. By controlling the injection energy and the injection dose, the doping concentration variation of the channel 110 can be further controlled, thereby obtaining a channel 110 that better meets actual needs. In addition, compared with a single ion injection, the use of an inclined ion injection method can make the doping concentration of the channel 110 change more uniformly and smoothly, thereby making the channel 110 have better electrical properties.

[0101] It can be understood that the preparation of the channel 110 in step S2 can be completed through the above step S2.1, step S2.2 or step S2.3.

[0102] Step S3, etching the functional layer 100 along the second direction to form a plurality of second trenches extending along the second direction, and preparing a second isolation layer 520 in the second trenches.

[0103] The first isolation layer 510 and the second isolation layer 520 together separate the functional layer 100 into a plurality of active pillars arranged in an array.

[0104] In some examples of this embodiment, after the ion implantation and annealing, the functional layer 100 is etched along the second direction to form a plurality of second grooves extending along the second direction, and then a second isolation layer 520 is prepared in the second groove. The first isolation layer 510 and the second isolation layer 520 together separate the functional layer 100 into a plurality of active pillars arranged in an array.

[0105] Fig. 9A Shown in Figure 5A A schematic top view of the structure of the second isolation layer 520 is prepared based on the structure shown. Fig. 9B For along Fig. 9A Schematic diagram of the cross-sectional structure at BB' in the figure. Fig. 9C For along Fig. 9A Schematic diagram of the cross-sectional structure at CC' in FIG.

[0106] Reference Figures 9A to 9C As shown, a plurality of second trenches extend along the second direction, a second isolation layer 520 is disposed in the second trench, and the first isolation layer 510 and the second isolation layer 520 together separate the functional layer 100 into a plurality of active pillars. Each active pillar includes a source region 120, a drain region 130 and a channel 110, the channel 110 is located between the source region 120 and the drain region 130, the channel 110 has a source end and a drain end that are disposed oppositely, the source end is disposed close to the source region 120, and the drain end is disposed close to the drain region 130. There is a doping peak region 111 in the channel 110, the doping concentration of the doping peak region 111 is higher than the doping concentration of other regions in the channel 110, and the distance between the doping peak region 111 and the source end is smaller than the distance between the doping peak region 111 and the drain end.

[0107] In some examples of this embodiment, the following step may be further included: preparing a bit line 200 in the substrate 10 between adjacent first trenches 101 , the bit line 200 being located on a side of the source region 120 away from the drain region 130 and electrically connected to the source region 120 .

[0108] In some examples of this embodiment, the following step may be further included: preparing a word line structure 400 disposed on the sidewall of the trench 110 in the second trench.

[0109] In some examples of this embodiment, the following step may be further included: preparing a capacitor 300 on a side of the drain region 130 away from the source region 120 .

[0110] It can be understood that through steps S1 to S3, the semiconductor structure provided by the present disclosure can be prepared.

[0111] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0112] It should be understood that, unless otherwise specified herein, the execution of the steps described is not strictly limited in order, and the steps may be executed in other orders. Moreover, at least a portion of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0113] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0114] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A semiconductor structure, characterized in that: It includes an active column; the active column includes a source region, a channel and a drain region which are stacked in sequence, the channel has a source end and a drain end which are relatively arranged, the source end is arranged close to the source region, the drain end is arranged close to the drain region, the channel has a doping peak region, the doping concentration of the doping peak region is higher than the doping concentration of other regions in the channel, and the distance between the doping peak region and the source end is smaller than the distance between the doping peak region and the drain end.

2. The semiconductor structure according to claim 1, characterized in that: The doping concentration in the channel gradually decreases from the peak region of the doping concentration toward the drain end.

3. The semiconductor structure according to claim 1, characterized in that: The doping concentration of the source terminal is higher than the doping concentration of the drain terminal.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The ratio of the distance between the doping peak region and the drain end to the length of the channel is (85-95):

100.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: It also includes a bit line, a word line structure and a capacitor, wherein the bit line is electrically connected to the source region, the word line structure is arranged on the side wall of the channel region, and the capacitor is electrically connected to the drain region.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 5, characterized in that: The steps include: preparing a functional layer on a substrate; The source region and the drain region are prepared in the functional layer, and the functional layer is subjected to ion implantation and annealing to form the channel between the source region and the drain region. The step of ion implantation includes: Performing multiple ion implantations on the functional layer, wherein the implantation energy and implantation dose of each ion implantation process are different, and the implantation dose of the ion implantation process in the implantation area closer to the source region is larger, so that the doping peak region in the channel is shifted toward the source region; or, Performing a single ion implantation on the functional layer, during which the implantation region is controlled to be closer to the source region, so that the doping peak region in the channel is shifted toward the source region; or, The functional layer is subjected to tilted ion implantation. During the tilted ion implantation, the implantation direction is controlled to be tilted relative to the channel direction, and the ion source is controlled to rotate around the channel direction relative to the functional area, so that the doping peak area in the channel is offset toward the source area.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The step of performing multiple ion implantation on the functional area includes more than three ion implantation processes.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that: In the step of performing inclined ion implantation on the functional area, the angle between the implantation direction and the channel direction is controlled to be 4° to 9°; and / or, The implantation energy is controlled to be 18keV to 25keV, and the implantation dose is 10E13 / cm 3 ~10E16 pieces / cm 3 .

9. The method for preparing a semiconductor structure according to any one of claims 6 to 8, characterized in that: The following steps are also included: Etching the functional layer along a first direction to form a plurality of first grooves spaced apart from each other in the functional layer; and, The functional layer is etched along a second direction intersecting the first direction to form a plurality of second grooves arranged at intervals in the functional layer, wherein the first grooves and the second grooves separate the functional layer into a plurality of active pillars arranged in an array.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The following steps are also included: Preparing a bit line in the substrate between adjacent first trenches, wherein the bit line is located at a side of the source region away from the drain region and the bit line is electrically connected to the source region; preparing a word line structure disposed on a sidewall of the trench in the second trench; and, A capacitor is fabricated on a side of the drain region away from the source region.

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