Semiconductor devices and transistors

Abstract

The present application provides a semiconductor device and a transistor. The semiconductor device includes: a substrate; an epitaxial layer, located on the surface of the substrate; a first injection region, located in the epitaxial layer, the surface of the first injection region away from the substrate overlaps with the partial surface of the epitaxial layer away from the substrate; an angled channel region, located in the first injection region, the conductivity type of the angled channel region is different from the conductivity type of the first injection region, and the angle between the surface of the angled channel region away from the substrate and the surface of the first injection region away from the substrate is not 0°; a gate structure, located on the partial surface of the epitaxial layer away from the substrate, the orthographic projection of the angled channel region on the substrate is located in the orthographic projection of the gate structure on the substrate. The present application at least solves the problem of low channel mobility of semiconductor devices in the prior art.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a transistor. Background Art

[0002] Silicon carbide (SiC) is a typical representative of the third generation of semiconductor materials. It has excellent material properties such as wide bandgap, high critical breakdown field strength, high saturation drift velocity, and high thermal conductivity, making it an ideal material for manufacturing high-voltage and high-power power electronic devices. Silicon carbide can be directly thermally oxidized to grow SiO 2 , providing a good process technology foundation for the preparation of silicon carbide gate-controlled transistors. When a certain voltage is applied to the gate, the electric field between the gate dielectric layer and silicon carbide will attract free carriers to form a conductive channel. However, SiC / SiO 2 The actual process quality of the interface limits the performance of SiC gate-controlled transistors. For example, thermal oxidation, ion implantation, and high-temperature annealing processes can cause SiC / SiO 2 The interface has a high interface state density and large interface roughness, which produces a strong scattering effect on the channel carriers, resulting in low channel mobility and large on-resistance, and the energy conversion efficiency of the device is severely limited. Therefore, how to improve the channel carrier mobility has become a key technical problem that needs to be solved in the development of silicon carbide gate-controlled transistors. Summary of the invention

[0003] The main purpose of the present application is to provide a semiconductor device and a transistor to at least solve the problem of low channel mobility of semiconductor devices in the prior art.

[0004] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a semiconductor device is provided, comprising: a substrate; an epitaxial layer located on the surface of the substrate; a first injection region located in the epitaxial layer, the surface of the first injection region away from the substrate overlaps with the partial surface of the epitaxial layer away from the substrate; an angled channel region located in the first injection region, the conductivity type of the angled channel region is different from the conductivity type of the first injection region, and the angle between the surface of the angled channel region away from the substrate and the surface of the first injection region away from the substrate is not 0°; a gate structure located on the partial surface of the epitaxial layer away from the substrate, the orthographic projection of the angled channel region on the substrate is located in the orthographic projection of the gate structure on the substrate.

[0005] Optionally, a portion of a surface of the oblique channel region away from the substrate overlaps with a surface of the first implantation region away from the substrate.

[0006] Optionally, the gate structure includes: a gate dielectric layer located on a portion of the surface of the epitaxial layer away from the substrate and a portion of the surface of the first injection region away from the substrate; and a gate located at least on a surface of the gate dielectric layer away from the epitaxial layer.

[0007] Optionally, when the threshold voltage of the semiconductor device is a first voltage, the target parameter of the gate structure is a first value, and the distance between the gate dielectric layer and the bevel channel region is a first distance; when the threshold voltage of the semiconductor device is a second voltage, the target parameter is a second value, and the distance between the gate dielectric layer and the bevel channel region is a second distance; the first voltage is greater than the second voltage, the first value is greater than the second value, the first distance is less than the second distance, and the target parameter is the thickness of the gate dielectric layer or the work function of the gate.

[0008] Optionally, there are two bevel channel regions and two first injection regions respectively, and the bevel channel regions are located one-to-one in the first injection region, the gate dielectric layer includes a first part and a second part located on both sides of the first part, the bevel channel regions are located one-to-one in the orthographic projection of the substrate and the second part in the orthographic projection of the substrate, the distance from the side of the bevel channel region close to the first part to the surface of the first injection region away from the substrate is a third distance, the distance from the side of the bevel channel region away from the first part to the surface of the first injection region away from the substrate is a fourth distance, the third distance is smaller than the fourth distance, and the thickness of the first part is greater than the thickness of the second part.

[0009] Optionally, there are two bevel channel regions and two first injection regions respectively, and the bevel channel regions are located one-to-one in the first injection region, the gate dielectric layer includes a first part and a second part located on both sides of the first part, the bevel channel regions are located one-to-one in the orthographic projection of the substrate and the second part in the orthographic projection of the substrate, the distance from the side of the bevel channel region close to the first part to the surface of the first injection region away from the substrate is a third distance, the distance from the side of the bevel channel region away from the first part to the surface of the first injection region away from the substrate is a fourth distance, the third distance is greater than the fourth distance, and the thickness of the first part is less than the thickness of the second part.

[0010] Optionally, the semiconductor device also includes: a second injection region, located in the first injection region, the surface of the second injection region away from the substrate overlaps with a portion of the surface of the first injection region away from the substrate, one side of the bevel channel region contacts the epitaxial layer, and the other side of the bevel channel region contacts one side of the second injection region; a third injection region, located in the first injection region, located on a side of the second injection region away from the bevel channel region and in contact with another side of the second injection region, the surface of the third injection region away from the substrate overlaps with a portion of the surface of the first injection region away from the substrate.

[0011] Optionally, the conductivity type of the epitaxial layer is different from the conductivity type of the first injection region, the conductivity type of the second injection region is different from the conductivity type of the first injection region, and the conductivity type of the third injection region is the same as the conductivity type of the first injection region.

[0012] Optionally, the semiconductor device also includes: a first electrode, located on a portion of the surface of the epitaxial layer away from the substrate, and the first electrode is in contact with the second injection region and the third injection region respectively; a second electrode, located on a surface of the substrate away from the epitaxial layer; and an interlayer dielectric layer, located on the surface of the gate structure away from the substrate and on the side of the gate structure.

[0013] Optionally, the thickness of the oblique channel region is 10 nm to 0.5 μm, and the doping concentration of the oblique channel region is 1e17 cm -3 -1e20cm -3 .

[0014] Optionally, the thickness of the epitaxial layer is 5-200 μm, and the doping concentration of the epitaxial layer is 1e14 cm -3 -1e16cm -3 .

[0015] Optionally, the thickness of the first injection region is 0.5 μm-3 μm, and the doping concentration of the first injection region is 1e17 cm -3 -1e19cm -3 .

[0016] Optionally, the angle is less than or equal to 60°, or the angle is greater than or equal to 120°.

[0017] Optionally, materials of the substrate and the epitaxial layer both include silicon carbide.

[0018] According to another aspect of the present application, a transistor is provided, comprising: any one of the semiconductor devices described above.

[0019] The technical solution of the present application is applied to provide a semiconductor device including a substrate, an epitaxial layer located on the surface of the substrate, a first injection region located in the epitaxial layer, an oblique channel region located in the first injection region, and a gate structure located on the epitaxial layer, wherein the surface of the first injection region away from the substrate overlaps with the partial surface of the epitaxial layer away from the substrate, the conductivity type of the oblique channel region is different from that of the first injection region, an angle not equal to 0° is formed between the surface of the oblique channel region away from the substrate and the surface of the first injection region away from the substrate, and the gate structure covers the oblique channel region along the thickness direction of the semiconductor device. By arranging an oblique channel region in the first injection region of the epitaxial layer below the gate structure, the oblique channel region has a conductivity type opposite to that of the first injection region, and the contact interface between the gate structure and the epitaxial layer has a certain inclination angle with the surface of the oblique channel region, so that the conductive channel of the semiconductor device is away from the contact interface, the influence of the device interface state density and surface roughness on the conductive channel is reduced, and the channel carrier mobility of the device is ensured to be high, so that the on-resistance of the semiconductor device is low, the conduction efficiency of the semiconductor device is improved, and the energy conversion efficiency of the semiconductor device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0021] Figure 1 A schematic structural diagram of a semiconductor device provided in an embodiment of the present application is shown;

[0022] Figure 2 A schematic structural diagram of another semiconductor device provided according to an embodiment of the present application is shown;

[0023] Figure 3 A schematic structural diagram of another semiconductor device provided according to an embodiment of the present application is shown;

[0024] Figure 4 A schematic diagram of output characteristic curves of a conventional silicon carbide gate-controlled transistor provided according to an embodiment of the present application and a silicon carbide gate-controlled transistor including a bevel channel region of the present application is shown;

[0025] Figure 5 A schematic diagram of transfer characteristic curves of a conventional silicon carbide gate-controlled transistor provided according to an embodiment of the present application and a silicon carbide gate-controlled transistor including a bevel channel region of the present application is shown;

[0026] Figure 6 A schematic structural diagram of a semiconductor device manufacturing method according to an embodiment of the present application obtained after process step S1 is shown;

[0027] Figure 7 A schematic diagram of the structure obtained after process step S2 of the method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0028] Figure 8 A schematic diagram of the structure obtained after process step S3 of the method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0029] Fig. 9 A schematic diagram of the structure obtained after process step S4 of the method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0030] Fig.10 A schematic diagram of the structure obtained after process step S5 of the method for manufacturing a semiconductor device provided in an embodiment of the present application is shown;

[0031] Fig.11 A schematic structural diagram of the semiconductor device manufacturing method provided in an embodiment of the present application after process step S6 is shown.

[0032] The above drawings include the following reference numerals:

[0033] 10. Substrate; 11. Epitaxial layer; 12. First injection region; 13. Bevel channel region; 14. Gate structure; 141. Gate dielectric layer; 1411. First portion; 1412. Second portion; 142. Gate; 15. Second injection region; 16. Third injection region; 17. First electrode; 18. Second electrode; 19. Interlayer dielectric layer. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] As introduced in the background technology, there is a technical problem in the prior art that the channel mobility of semiconductor devices is low. To solve this technical problem, the embodiments of the present application provide a semiconductor device and a transistor.

[0038] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0039] An embodiment of the present application provides a semiconductor device. Figure 1 The structure diagram of the semiconductor device according to the embodiment of the present application is exemplarily shown. Figure 1 As shown, the semiconductor device comprises:

[0040] Substrate 10;

[0041] Specifically, the substrate 10 of the present application can be selected according to the actual requirements of the semiconductor device, and may include a silicon substrate, a silicon carbide substrate, a silicon germanium substrate, an SOI substrate or a GOI substrate, etc. The conductivity type of the substrate 10 may be P type or N type.

[0042] An epitaxial layer 11 is located on the surface of the substrate 10;

[0043] Specifically, the material of the epitaxial layer 11 may include silicon, silicon germanium, silicon carbide, gallium nitride, etc. The conductivity type of the epitaxial layer 11 may be the same as or different from the conductivity type of the substrate 10 .

[0044] A first injection region 12 is located in the epitaxial layer 11, and a surface of the first injection region 12 away from the substrate 10 overlaps with a portion of a surface of the epitaxial layer 11 away from the substrate 10;

[0045] Specifically, the first injection region 12 mainly functions to control the flow of electrons, and the conductivity type of the first injection region 12 is different from the conductivity type of the epitaxial layer 11 .

[0046] an oblique channel region 13 located in the first implantation region 12, wherein the conductivity type of the oblique channel region 13 is different from the conductivity type of the first implantation region 12, and an angle between a surface of the oblique channel region 13 away from the substrate 10 and a surface of the first implantation region 12 away from the substrate 10 is not 0°;

[0047] Specifically, the surface of the angled channel region 13 away from the substrate 10 is inclined at an angle, ie, the angle, relative to the surface of the first implantation region 12 away from the substrate 10. Those skilled in the art can flexibly set the angle according to actual needs.

[0048] The gate structure 14 is located on a portion of the surface of the epitaxial layer 11 away from the substrate 10 , and the orthographic projection of the bevel channel region 13 on the substrate 10 is located in the orthographic projection of the gate structure 14 on the substrate 10 .

[0049] Through the above embodiments, a semiconductor device is provided, comprising a substrate, an epitaxial layer located on the surface of the substrate, a first injection region located in the epitaxial layer, an oblique channel region located in the first injection region, and a gate structure located on the epitaxial layer, wherein the surface of the first injection region away from the substrate overlaps with the partial surface of the epitaxial layer away from the substrate, the conductivity type of the oblique channel region is different from that of the first injection region, an angle not equal to 0° is formed between the surface of the oblique channel region away from the substrate and the surface of the first injection region away from the substrate, and the gate structure covers the oblique channel region along the thickness direction of the semiconductor device. By arranging the oblique channel region in the first injection region of the epitaxial layer below the gate structure, the oblique channel region has a conductivity type opposite to that of the first injection region, and the contact interface between the gate structure and the epitaxial layer has a certain inclination angle with the surface of the oblique channel region, so that the conductive channel of the semiconductor device is away from the contact interface, the influence of the device interface state density and surface roughness on the conductive channel is reduced, and the channel carrier mobility of the device is ensured to be high, so that the on-resistance of the semiconductor device is low, the conduction efficiency of the semiconductor device is improved, and the energy conversion efficiency of the semiconductor device is improved.

[0050] The bevel channel region and the first injection region have different conductivity types, and a PN junction depletion region is formed between the two. The built-in electric field of the PN junction formed by the bevel channel region and the first injection region, the gate structure and the gate voltage are used together to adjust the depletion layer width of the PN junction depletion region to achieve the switching control of the device. When the gate voltage is zero, the bevel channel region forms self-depletion to achieve the normally closed state of the device; when the gate voltage is greater than the threshold voltage, the bevel channel region is no longer completely depleted to achieve the conduction of the device. When the gate voltage is zero, the bevel channel region forms self-depletion to achieve the normally closed state of the semiconductor device; when the gate voltage is greater than the threshold voltage, the bevel channel region is no longer completely depleted to achieve the conduction of the semiconductor device. The bevel channel region makes the carrier path when the semiconductor device is turned on away from the contact interface between the gate structure and the epitaxial layer, reducing the scattering and capture effect of the contact interface defects on the carriers, thereby improving the channel carrier mobility.

[0051] In addition, the surface of the angled channel region and the surface of the first injection region have a certain inclination angle. The angled channel region and the first injection region have different conductivity types, and a PN junction depletion region is formed between the two. The inclination angle makes the width of the depletion region at each position different, thereby achieving the effect of regulating the width of the depletion layer and realizing the control of the device threshold voltage.

[0052] Specifically, the angle is not 90°, that is, the angle is an acute angle or an obtuse angle.

[0053] In this embodiment, when the semiconductor device is a unipolar transistor (such as MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the conductivity type of the substrate is the same as the conductivity type of the epitaxial layer; when the semiconductor device is a bipolar transistor (such as IGBT (Insulated Gate Bipolar Transistor), the conductivity type of the substrate is different from the conductivity type of the epitaxial layer.

[0054] Optionally, the materials of the substrate and the epitaxial layer include silicon carbide. Silicon carbide has excellent material properties such as wide bandgap, high critical breakdown field strength, high saturation drift velocity, and high thermal conductivity. Semiconductor devices using silicon carbide can meet the design requirements of high-voltage and high-power devices.

[0055] More specifically, the materials of the substrate and the epitaxial layer are both silicon carbide, that is, the semiconductor device is a silicon carbide device.

[0056] In an optional solution, a portion of the surface of the above-mentioned bevel channel region away from the above-mentioned substrate overlaps with the surface of the above-mentioned first injection region away from the above-mentioned substrate. In other words, the above-mentioned bevel channel region can be located inside the above-mentioned first injection region, or can be located on the surface of the above-mentioned first injection region. Those skilled in the art can flexibly set the position of the above-mentioned bevel channel region in the above-mentioned first injection region according to the actual process.

[0057] Alternatively, if Figures 1 to 3 As shown, the gate structure 14 includes: a gate dielectric layer 141, which is located on a portion of the surface of the epitaxial layer 11 away from the substrate 10 and a portion of the surface of the first injection region 12 away from the substrate 10, that is, the gate dielectric layer 141 covers a portion of the surface of the first injection region 12 and also covers a portion of the surface of the epitaxial layer 11 that does not overlap with the first injection region 12, and the orthographic projection of the gate dielectric layer 141 on the substrate 10 covers the orthographic projection of the angled channel region 13 on the substrate 10; and a gate 142, which is at least located on a surface of the gate dielectric layer 141 away from the epitaxial layer 11. In this embodiment, a gate dielectric layer is provided between the epitaxial layer and the gate to achieve isolation and insulation between the gate and the substrate, to ensure that current does not flow directly between the gate and the substrate, to prevent direct current conduction between the two, and to ensure normal operation of the semiconductor device.

[0058] Those skilled in the art may select any suitable material as the material of the gate dielectric layer and the gate. The material of the gate dielectric layer may include silicon dioxide, high-k dielectric material, etc. The material of the gate may include polysilicon, metal material, etc. Those skilled in the art may also flexibly set the thickness of the gate dielectric layer and the thickness of the gate according to actual needs, and this application does not impose specific restrictions on this. In one embodiment, the thickness of the gate dielectric layer is 10nm-100nm.

[0059] According to some other optional schemes of the present application, when the threshold voltage of the semiconductor device is a first voltage, the target parameter of the gate structure is a first value, the distance between the gate dielectric layer and the bevel channel region is a first distance, when the threshold voltage of the semiconductor device is a second voltage, the target parameter is a second value, the distance between the gate dielectric layer and the bevel channel region is a second distance, the first voltage is greater than the second voltage, the first value is greater than the second value, the first distance is less than the second distance, and the target parameter is the thickness of the gate dielectric layer or the work function of the gate. In this embodiment, semiconductor devices with different threshold voltages can be obtained by adjusting the thickness of the gate dielectric layer or the work function of the gate to meet the design requirements of the threshold voltage of different devices. At the same time, by adjusting the distance between the gate dielectric layer and the bevel channel region, the on-resistance of the semiconductor device can be ensured to be low while meeting the threshold voltage design requirements.

[0060] Specifically, a gate dielectric layer with a specific structural shape or a gate electrode with a specific work function size is used, and the depletion width of the bevel channel region is regulated by changing the electric field between the gate electrode and the bevel channel region to meet the design requirements of different device threshold voltages. When a device with a larger threshold voltage is required, the thickness of the gate dielectric layer or the work function of the gate is set to be larger, the electric field formed is smaller, the reaction to the mobility is smaller, and the threshold voltage of the obtained semiconductor device is larger, but at this time the width of the depletion layer is also smaller, and the on-resistance is larger. By reducing the distance between the gate dielectric layer and the bevel channel region, that is, setting the distance to a smaller value, the on-resistance can be reduced. Similarly, when a device with a smaller threshold voltage is required, the thickness of the gate dielectric layer or the work function of the gate is set to be smaller, and the influence of the thickness of the gate dielectric layer or the work function of the gate on the mobility is reduced by increasing the distance between the gate dielectric layer and the bevel channel region.

[0061] It should be noted that the above-mentioned gate is a single material or a composite material. The work function of the gate will change the electric field between the gate and the bevel channel region, adjust the depletion region width of the bevel channel region, and meet the design requirements of different threshold voltages. For example, under zero bias conditions, the bevel channel region forms self-depletion to realize a normally closed device. According to formula (1), by changing the work function of the gate or the thickness of the gate dielectric layer, the device threshold voltage can be effectively controlled.

[0062] (1)

[0063] in, is the threshold voltage, is the work function difference between the gate and epitaxial layer, is the capacitance related to the thickness of the gate dielectric layer, is the body potential, is the interface state charge density, is the fixed charge density, is the dielectric constant of SiC, is the charge, Doping for semiconductors.

[0064] The size adjustment of the work function can be achieved by adjusting the material composition of the gate. By selecting a single material with a specific work function size, or a single material that introduces specific elements to achieve effective work function regulation, or a composite material with a specific atomic ratio to achieve effective work function regulation, as the constituent material of the gate, the electric field between the gate and the bevel channel region can be regulated to meet the design requirements of different device threshold voltages.

[0065] A PN junction depletion region is formed between the above-mentioned bevel channel region and the first injection region. When the gate voltage is zero, the bevel channel region forms self-depletion by utilizing the controllability of the gate dielectric layer shape and the gate work function, and the first injection region and the epitaxial layer are blocked, thereby realizing the normally closed state of the semiconductor device. The gate voltage affects the depletion region width of the bevel channel region, and the switching control of the semiconductor device can be realized by changing the gate voltage. When the gate voltage is greater than the threshold voltage, the vertical electric field introduced by the gate is offset, and the bevel channel region is no longer completely depleted, which can provide a current channel for the semiconductor device (specifically, a current channel from the first electrode to the second electrode) to realize the conduction of the semiconductor device. The bevel channel region can make the carrier path of the semiconductor device away from the gate dielectric layer when it is turned on, reduce the scattering and capture effect of interface defects on carriers, and improve the channel carrier mobility. According to formula (2), the channel resistance is determined by the carrier mobility and the carrier concentration.

[0066] (2)

[0067] Where q is the charge, L is the length of the bevel channel region, and W is the width of the bevel channel region. is the carrier mobility in the oblique channel region, is the carrier concentration in the oblique channel region.

[0068] In some other optional solutions, the work function of the gate is 3eV-7eV. In this embodiment, the work function of the gate is 3eV-7eV, which can further regulate the electric field between the gate dielectric layer and the angled channel region, and thus further control the threshold voltage of the device.

[0069] The distance between the gate dielectric layer and the oblique channel region may be a minimum distance between a surface of the gate dielectric layer close to the substrate and a surface of the oblique channel region far from the substrate.

[0070] The above-mentioned oblique angle channel region and first implantation region structures of the present application may be only one or more. The oblique angle channel region may be inclined in a direction of high on the left and low on the right, or in a direction of low on the left and high on the right.

[0071] In some exemplary embodiments of the present application, Figure 2 As shown, there are two oblique channel regions 13 and two first injection regions 12, respectively. The two first injection regions 12 are arranged in the epitaxial layer 11 at intervals. The oblique channel regions 13 are located in the first injection regions 12 one by one. The gate dielectric layer 141 includes a first portion 1411 and second portions 1412 located on both sides of the first portion 1411. The orthographic projections of the oblique channel regions 13 on the substrate 10 are located in the orthographic projections of the second portions 1412 on the substrate 10 one by one. That is, as shown in FIG. Figure 2 As shown, the two oblique channel regions 13 are respectively located below the two ends of the gate dielectric layer 141; the oblique channel region 13 includes two sides close to and away from the first part 1411 in addition to the two surfaces close to and away from the substrate 10, wherein the distance from the side of the oblique channel region 13 close to the first part 1411 to the surface of the first injection region 12 away from the substrate 10 is a third distance, and the distance from the side of the oblique channel region 13 away from the first part 1411 to the surface of the first injection region 12 away from the substrate 10 is a fourth distance, and the third distance is less than the fourth distance, that is, the two oblique channel regions 13 are regular octaves, and the thickness of the first part 1411 is greater than the thickness of the second part 1412. The thickness of different regions of the gate dielectric layer is set to different thickness values ​​according to the inclination direction of the two oblique channel regions, thereby further realizing the control of the electric field between the gate dielectric layer and the oblique channel region, and further realizing the design requirements of different threshold voltages.

[0072] In some other exemplary embodiments of the present application, Figure 3 As shown, there are two oblique channel regions 13 and two first injection regions 12, respectively. The two first injection regions 12 are arranged in the epitaxial layer 11 at intervals. The oblique channel regions 13 are located in the first injection regions 12 one by one. The gate dielectric layer 141 includes a first portion 1411 and second portions 1412 located on both sides of the first portion 1411. The orthographic projections of the oblique channel regions 13 on the substrate 10 are located in the orthographic projections of the second portions 1412 on the substrate one by one. That is, as shown in FIG. Figure 3As shown, the two oblique channel regions 13 are respectively located below the two ends of the gate dielectric layer 141; the oblique channel region 13 includes two sides close to and away from the first part 1411 in addition to the two surfaces close to and away from the substrate 10, wherein the distance from the side of the oblique channel region 13 close to the first part 1411 to the surface of the first injection region 12 away from the substrate 10 is a third distance, and the distance from the side of the oblique channel region 13 away from the first part 1411 to the surface of the first injection region 12 away from the substrate 10 is a fourth distance, and the third distance is greater than the fourth distance, that is, the two oblique channel regions 13 are inverted eight shapes, and the thickness of the first part 1411 is less than the thickness of the second part 1412. The thickness of different regions of the gate dielectric layer is set to different thickness values ​​according to the inclination direction of the two oblique channel regions, thereby further realizing the control of the electric field between the gate dielectric layer and the oblique channel region, and further realizing the design requirements of different threshold voltages.

[0073] like Figure 2 and Figure 3 As shown, the two first injection regions 12 are spaced apart in the epitaxial layer 11 , and the gate structure is located between the two first injection regions 12 and is in contact with the partial surfaces of the two first injection regions 12 away from the substrate 10 .

[0074] In order to further ensure the good device performance of the semiconductor device, specifically, Figure 2 and Figure 3 As shown, the semiconductor device further includes: a second injection region 15, located in the first injection region 12, the surface of the second injection region 15 away from the substrate 10 overlaps with a partial surface of the first injection region 12 away from the substrate 10, one side of the bevel channel region 13 contacts the epitaxial layer 11, and the other side of the bevel channel region 13 contacts one side of the second injection region 15; a third injection region 16, located in the first injection region 12, located on a side of the second injection region 15 away from the bevel channel region 13, and contacts with another side of the second injection region 15, the surface of the third injection region 16 away from the substrate 10 overlaps with a partial surface of the first injection region 12 away from the substrate 10. In this embodiment, a second injection region and a third injection region are formed in the first injection region. The second injection region serves as the source region of the device to provide electrons and holes. When an external voltage is applied to the gate, the electrons or holes in the second injection region will be affected by the gate electric field and move to cause a change in current, thereby controlling the conduction and cutoff of the device. The third injection region serves as the ohmic contact region of the device to ensure that the current can flow smoothly without generating significant additional impedance.

[0075] Furthermore, the conductivity type of the epitaxial layer is different from the conductivity type of the first injection region, the conductivity type of the second injection region is different from the conductivity type of the first injection region, and the conductivity type of the third injection region is the same as the conductivity type of the first injection region, that is, the conductivity type of the second injection region and the third injection region are different.

[0076] In actual application, those skilled in the art can flexibly set the thickness and doping concentration of the second injection region according to actual needs, and this application does not impose specific restrictions on this. For example, the thickness of the second injection region is 0.1 μm-0.3 μm, and the doping concentration of the second injection region is 1e19 cm -3 -1e21cm -3 The thickness of the third injection region is 0.1 μm-0.3 μm, and the doping concentration of the third injection region is 1e19 cm -3 -1e21cm -3 .

[0077] like Figure 2 and Figure 3 As shown, the gate dielectric layer 141 is also located on a portion of the surface of the second implantation region 15 that is away from the substrate 10 .

[0078] Alternatively, if Figure 2 and Figure 3 As shown, the semiconductor device further includes: a first electrode 17, which is located on a surface of the epitaxial layer 11 away from the substrate 10, and the first electrode 17 is in contact with the second injection region 15 and the third injection region 16 respectively; a second electrode 18, which is located on a surface of the substrate 10 away from the epitaxial layer 11; and an interlayer dielectric layer 19, which is located on a surface of the gate structure 14 away from the substrate 10 and on the side of the gate structure 14. In this embodiment, the first electrode is formed on a surface of the epitaxial layer away from the substrate, and the second electrode is formed on a surface of the substrate away from the epitaxial layer, and the input and output of the current of the semiconductor device are realized through the first electrode and the second electrode; the gate structure is isolated from the first electrode by the interlayer dielectric layer to avoid short circuit between the gate structure and the first electrode.

[0079] In one embodiment, the first electrode serves as a source or collector of the semiconductor device, and the second electrode serves as a drain or emitter of the semiconductor device.

[0080] In the exemplary embodiment of the present application, Figure 2 and Figure 3As shown, there are two of the second injection region 15 , the third injection region 16 and the first electrode 17 . The second injection region 15 and the third injection region 16 are located in the first injection region 12 in a one-to-one correspondence, and the first electrode 17 is located at both sides of the gate structure 14 .

[0081] In practical applications, technicians in this field can flexibly set the thickness of the above-mentioned substrate, the thickness and doping concentration of the above-mentioned epitaxial layer, the thickness and doping concentration of the above-mentioned first injection region, the thickness and doping concentration of the above-mentioned angled channel region, and the thickness of the above-mentioned gate structure according to actual needs, and the present application does not impose specific restrictions on this.

[0082] In an exemplary embodiment, the thickness of the epitaxial layer is 5 μm-200 μm, and the doping concentration of the epitaxial layer is 1e14 cm -3 -1e16cm -3 The thickness of the first injection region is 0.5 μm-3 μm, and the doping concentration of the first injection region is 1e17 cm -3 -1e19cm -3 The thickness of the above-mentioned oblique angle channel region is 10nm-0.5μm, and the doping concentration of the above-mentioned oblique angle channel region is 1e17cm -3 -1e20cm -3 .

[0083] In order to take into account the device performance and miniaturization design requirements of semiconductor devices, in some exemplary schemes, the above angle is less than or equal to 60°, or the above angle is greater than or equal to 120°. Since the angle between the two surfaces ranges from [0°, 180°], the angle between the surface of the oblique channel region away from the substrate and the surface of the first injection region away from the substrate of the present application can be an angle less than or equal to 60° in the clockwise (or counterclockwise) direction, or can be an angle greater than or equal to 120° in the clockwise (or counterclockwise) direction, that is, the above oblique channel region is inclined relative to the surface of the first injection region, but the inclination angle is not large, which can further reduce the impact of the device interface state density and surface roughness on the conductive channel, and further ensure that the overall space occupied by the oblique channel region in the semiconductor device is small.

[0084] According to another aspect of the present application, a transistor is provided, comprising: any one of the above-mentioned semiconductor devices.

[0085] The above-mentioned transistor includes any one of the above-mentioned semiconductor devices, which sets an angled channel region in the first injection region of the epitaxial layer below the gate structure. The angled channel region has a conductivity type opposite to that of the first injection region, and the contact interface between the gate structure and the epitaxial layer has a certain inclination angle with the surface of the angled channel region, so that the conductive channel of the semiconductor device is away from the contact interface, reducing the influence of the device interface state density and surface roughness on the conductive channel, ensuring that the channel carrier mobility of the device is high, thereby making the on-resistance of the semiconductor device low, improving the conduction efficiency of the transistor, and improving the energy conversion efficiency of the transistor.

[0086] Specifically, the above transistor may be a silicon carbide transistor. Figure 4 The output characteristic curves of the conventional silicon carbide gate-controlled transistor and the silicon carbide gate-controlled transistor including the bevel channel region of the present application are shown. Figure 4 The horizontal axis represents the drain voltage, and the vertical axis represents the output current of the transistor. Figure 5 The transfer characteristic curves of a conventional silicon carbide gate-controlled transistor and a silicon carbide gate-controlled transistor including an angled channel region of the present application are shown, wherein the abscissa represents the gate voltage and the ordinate represents the output current of the transistor. Figure 4 and Figure 5 It can be seen that the slope of the output characteristic curve and the slope of the transfer characteristic curve of the silicon carbide gate-controlled transistor including the bevel channel region of the present application are both increased, the channel resistance is reduced, and the conduction loss of the device is reduced, indicating that the silicon carbide gate-controlled transistor including the bevel channel region of the present application can improve the channel carrier mobility.

[0087] In addition, by adjusting the gate work function and the characteristics of the gate dielectric layer shape, a normally-off silicon carbide gate-controlled transistor with controllable threshold voltage is realized.

[0088] The embodiment of the present application also provides a method for manufacturing the above-mentioned semiconductor device, comprising the following steps:

[0089] Step S1: epitaxially grow an epitaxial layer 11 on a surface of a substrate 10, and determine the doping concentration and thickness of the epitaxial layer 11 according to the blocking voltage requirement, so as to obtain Figure 6 The structural diagram shown;

[0090] Step S2: Patterning is performed on the surface of the epitaxial layer 11 away from the substrate 10 (hereinafter referred to as the upper surface) by photolithography, and a first implantation region 12 and an oblique channel region 13 having a certain doping concentration distribution are formed in a specific region of the epitaxial layer 11 by high-temperature ion implantation, so as to obtain Figure 7The structure shown in the figure, wherein the first implantation region 12 and the bevel channel region 13 have opposite conductivity types, and the bevel channel region 13 can be arranged on the surface or inside of the first implantation region 12 by changing the implantation energy of the ion implantation, and the doping concentration and thickness of the bevel channel region 13 can be controlled by changing the implantation dose of the ion implantation;

[0091] Step S3: Patterning is performed on the upper surface of the epitaxial layer 11 by a photolithography process, and ion implantation is performed in a specific area of ​​the first implantation region 12 by a high-temperature ion implantation process to form a second implantation region 15. Figure 8 ;

[0092] Step S4: Patterning is performed on the upper surface of the epitaxial layer 11 by a photolithography process, ion implantation is performed in a specific area of ​​the first implantation region 12 by a high temperature ion implantation process to form a third implantation region 16, and high temperature annealing is performed to activate the impurity atoms and repair the lattice damage, referring to Fig. 9 ;

[0093] Step S5: Patterning the upper surface of the epitaxial layer 11 by photolithography, and growing a gate dielectric layer 141 in a specific area of ​​the upper surface of the epitaxial layer 11 by thermal oxidation, physical vapor deposition, chemical vapor deposition, etc. Fig.10 ;

[0094] Step S6: growing a gate material on the upper surface of the gate dielectric layer 141 to form a gate 142, growing an interlayer dielectric layer 19 on the outer side of the gate 142 to isolate the gate 142 from the first electrode 17, and patterning the interlayer dielectric layer 19 by photolithography, referring to Fig.11 The gate dielectric layer 141 can be formed by an etching process; the gate dielectric layer 141 with a specific structural shape and tilt angle is formed by adjusting the photolithography mask design and the selection ratio of the etching process. The gate dielectric layer 141 can also be formed by a deposition process. The gate dielectric layer 141 with a certain angle and a gradual width is formed by multiple deposition processes, so that the thickness of the gate dielectric layer 141 can be effectively regulated; the gate 142 can be formed by a deposition and annealing process; the process conditions of the gate 142 such as the growth rate, growth temperature, and growth atmosphere are controlled, or special process treatments of the gate 142 such as ionizing radiation and specific atmosphere annealing are used, or a composite material gate 142 with a specific atomic ratio is formed by a multi-step deposition process, so as to effectively regulate the work function of the gate 142;

[0095] Step S7: growing an ohmic contact layer on specific areas of the upper and lower surfaces of the epitaxial layer 11, performing heat treatment by annealing to form an ohmic contact, growing an electrode layer on the upper surface of the ohmic contact to form a first electrode 17 and a second electrode 18, respectively, to prepare a semiconductor device with an oblique channel, referring to Figure 2 .

[0096] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0097] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0098] The present application provides a semiconductor device, comprising a substrate, an epitaxial layer located on the surface of the substrate, a first injection region located in the epitaxial layer, an oblique channel region located in the first injection region, and a gate structure located on the epitaxial layer, wherein the surface of the first injection region away from the substrate overlaps with the partial surface of the epitaxial layer away from the substrate, the conductivity type of the oblique channel region is different from that of the first injection region, an angle not equal to 0° is formed between the surface of the oblique channel region away from the substrate and the surface of the first injection region away from the substrate, and the gate structure covers the oblique channel region along the thickness direction of the semiconductor device. By arranging an oblique channel region in the first injection region of the epitaxial layer below the gate structure, the oblique channel region has a conductivity type opposite to that of the first injection region, and the contact interface between the gate structure and the epitaxial layer has a certain inclination angle with the surface of the oblique channel region, so that the conductive channel of the semiconductor device is away from the contact interface, the influence of the device interface state density and surface roughness on the conductive channel is reduced, and the channel carrier mobility of the device is ensured to be high, so that the on-resistance of the semiconductor device is low, the conduction efficiency of the semiconductor device is improved, and the energy conversion efficiency of the semiconductor device is improved.

[0099] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: substrate; an epitaxial layer located on the surface of the substrate; A first injection region is located in the epitaxial layer, wherein a surface of the first injection region away from the substrate overlaps a portion of a surface of the epitaxial layer away from the substrate; an oblique channel region located in the first implantation region, the conductivity type of the oblique channel region being different from the conductivity type of the first implantation region, and an angle between a surface of the oblique channel region away from the substrate and a surface of the first implantation region away from the substrate is not 0°; A gate structure is located on a portion of the surface of the epitaxial layer away from the substrate, and the orthographic projection of the oblique channel region on the substrate is located in the orthographic projection of the gate structure on the substrate. The gate structure comprises: a gate dielectric layer, located on a portion of the surface of the epitaxial layer away from the substrate and a portion of the surface of the first implantation region away from the substrate; a gate, at least located on a surface of the gate dielectric layer away from the epitaxial layer, There are two bevel channel regions and two first injection regions respectively, the bevel channel regions are located in the first injection region in a one-to-one correspondence, the gate dielectric layer includes a first portion and a second portion located on both sides of the first portion, the bevel channel regions are located in a one-to-one correspondence in the orthographic projection of the substrate in the orthographic projection of the second portion in the substrate, the distance from the side of the bevel channel region close to the first portion to the surface of the first injection region away from the substrate is a third distance, and the distance from the side of the bevel channel region away from the first portion to the surface of the first injection region away from the substrate is a fourth distance, and one of the following is satisfied: The third distance is smaller than the fourth distance, and the thickness of the first portion is larger than the thickness of the second portion; The third distance is greater than the fourth distance, and the thickness of the first portion is less than the thickness of the second portion.

2. The semiconductor device according to claim 1, wherein: A portion of a surface of the oblique channel region that is remote from the substrate overlaps with a surface of the first implant region that is remote from the substrate.

3. The semiconductor device according to claim 1, wherein: When the threshold voltage of the semiconductor device is a first voltage, the target parameter of the gate structure is a first value, and the distance between the gate dielectric layer and the bevel channel region is a first distance; when the threshold voltage of the semiconductor device is a second voltage, the target parameter is a second value, and the distance between the gate dielectric layer and the bevel channel region is a second distance; the first voltage is greater than the second voltage, the first value is greater than the second value, the first distance is less than the second distance, and the target parameter is the thickness of the gate dielectric layer or the work function of the gate.

4. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: A second implantation region is located in the first implantation region, a surface of the second implantation region away from the substrate overlaps with a portion of a surface of the first implantation region away from the substrate, one side surface of the bevel channel region contacts the epitaxial layer, and another side surface of the bevel channel region contacts one side surface of the second implantation region; The third injection region is located in the first injection region, on a side of the second injection region away from the angled channel region, and in contact with another side surface of the second injection region, and the surface of the third injection region away from the substrate overlaps with a portion of the surface of the first injection region away from the substrate.

5. The semiconductor device according to claim 4, characterized in that The conductivity type of the epitaxial layer is different from that of the first injection region, the conductivity type of the second injection region is different from that of the first injection region, and the conductivity type of the third injection region is the same as that of the first injection region.

6. The semiconductor device according to claim 4, characterized in that The semiconductor device further comprises: A first electrode is located on a portion of the surface of the epitaxial layer away from the substrate, and the first electrode is in contact with the second injection region and the third injection region respectively; A second electrode is located on a surface of the substrate away from the epitaxial layer; The interlayer dielectric layer is located on the surface of the gate structure away from the substrate and on the side surface of the gate structure.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that The thickness of the oblique channel region is 10 nm to 0.5 μm, and the doping concentration of the oblique channel region is 1e17 cm -3 -1e20cm -3 .

8. The semiconductor device according to any one of claims 1 to 6, characterized in that: The thickness of the epitaxial layer is 5-200 μm, and the doping concentration of the epitaxial layer is 1e14 cm -3 -1e16cm -3 .

9. The semiconductor device according to any one of claims 1 to 6, characterized in that: The thickness of the first injection region is 0.5 μm-3 μm, and the doping concentration of the first injection region is 1e17 cm -3 -1e19cm -3 .

10. The semiconductor device according to any one of claims 1 to 6, characterized in that The angle is less than or equal to 60°, or the angle is greater than or equal to 120°.

11. The semiconductor device according to any one of claims 1 to 6, characterized in that: The materials of the substrate and the epitaxial layer both include silicon carbide.

12. A transistor, characterized in that: include: The semiconductor device according to any one of claims 1 to 11.

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