Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming a first initial gate material layer on the surface of a substrate through a first low-pressure chemical vapor deposition technology, and enabling the first initial gate material layer to be made of polycrystalline silicon; a second initial gate material layer is formed on the surface of the first initial gate material layer through a second low-pressure chemical vapor deposition process, the second initial gate material layer is made of polycrystalline silicon, and the grain size of the second initial gate material layer is larger than that of the first initial gate material layer; the gate material layer comprises a first initial gate material layer and a second initial gate material layer; doping ions are injected into the gate material layer by adopting an ion injection process, the first initial gate material layer has a first doping concentration, and the second initial gate material layer has a second doping concentration; and performing annealing treatment on the gate material layer to reduce defects in the gate material layer, and enabling the first doping concentration to be greater than the second doping concentration, thereby facilitating suppression of a polycrystal depletion effect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] The continuous reduction of transistor manufacturing costs and the continuous improvement of transistor performance are two major trends in the development of integrated circuit manufacturing technology. Reducing the geometric size of transistors is the most effective way to reduce transistor manufacturing costs and improve transistor performance. However, this brings a huge challenge to the proportional reduction of the gate.

[0003] Depletion of charge carriers at or near the interface between the gate oxide and the polysilicon gate (poly depletion effect) has severely impacted the performance of complementary metal oxide semiconductor (CMOS) devices. The poly depletion effect results in a substantial increase in the gate dielectric thickness, thereby negatively affecting device performance. As the gate oxide thickness decreases, the impact of the poly depletion effect becomes increasingly important.

[0004] Therefore, the performance of the polysilicon gate formed by the existing technology needs to be improved urgently. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, comprising: a substrate; a gate layer located on a portion of the surface of the substrate, the gate layer comprising a first gate material layer and a second gate material layer located on the surface of the first gate material layer, the materials of the first gate material layer and the second gate material layer are both polycrystalline silicon, the grain size of the first gate material layer is smaller than the grain size of the second gate material layer, the first gate material layer has a first doping concentration, the second gate material layer has a second doping concentration, and the first doping concentration is greater than the second doping concentration.

[0007] Optionally, the gate layer also includes: a third gate material layer located on the surface of the substrate, the first gate material layer is located on the surface of the third gate material layer, the material of the third gate material layer is polysilicon, and the grain size of the third gate material layer is smaller than the grain size of the first gate material layer, and the third gate material layer has a third doping concentration, and the third doping concentration is greater than the first doping concentration.

[0008] Optionally, it also includes: a gate oxide layer located between the substrate surface and the gate layer.

[0009] Correspondingly, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; using a first low-pressure chemical vapor deposition process to form a first initial gate material layer on the surface of the substrate, the material of the first initial gate material layer is polycrystalline silicon; using a second low-pressure chemical vapor deposition process to form a second initial gate material layer on the surface of the first initial gate material layer, the material of the second initial gate material layer is polycrystalline silicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, and the gate material layer includes the first initial gate material layer and the second initial gate material layer; using an ion implantation process to implant doping ions into the gate material layer, the first initial gate material layer has a first doping concentration, and the second initial gate material layer has a second doping concentration; annealing the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration; patterning the gate material layer to form a gate layer, the gate layer includes the first gate material layer and the second gate material layer, the first gate material layer is formed with the first initial gate material layer, and the second gate material layer is formed with the second initial gate material layer.

[0010] Optionally, the first low-pressure chemical vapor deposition process has a first process temperature; the second low-pressure chemical vapor deposition process has a second process temperature, and the second process temperature is greater than the first process temperature.

[0011] Optionally, the first process temperature ranges from 610°C to 620°C; and the second process temperature ranges from 615°C to 625°C.

[0012] Optionally, before forming the first initial gate material layer, it also includes: using a third low-pressure chemical vapor deposition process to form a third initial gate material layer on the surface of the substrate, the material of the third initial gate material layer is amorphous silicon, the gate material layer also includes the third initial gate material layer, and the first initial gate material layer is formed on the surface of the third initial gate material layer; the ion implantation process also makes the third initial gate material layer have a third doping concentration; the annealing treatment also makes the material of the third initial gate material layer change from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer, so that the third doping concentration is greater than the first doping concentration; the gate layer also includes a third gate material layer, and the third gate material layer is formed with the third initial gate material layer.

[0013] Optionally, the third low pressure chemical vapor deposition process has a third process temperature, and the third process temperature is lower than the first process temperature.

[0014] Optionally, the third process temperature ranges from 500°C to 610°C.

[0015] Optionally, the process parameters of the ion implantation process include: the ions include N-type or P-type conductive ions.

[0016] Optionally, before forming the first initial gate material layer, a gate oxide material layer is further formed on the surface of the substrate; the gate oxide material layer under the gate layer is used as the gate oxide layer.

[0017] Correspondingly, the technical solution of the present invention also provides another method for forming a semiconductor structure, including: providing a substrate; using a first low-pressure chemical vapor deposition process and a first in-situ doping process to form a first initial gate material layer on the surface of the substrate, the material of the first initial gate material layer is polycrystalline silicon, and the first initial gate material layer has a first doping concentration; using a second low-pressure chemical vapor deposition process and a second in-situ doping process to form a second initial gate material layer on the surface of the first initial gate material layer, the material of the second initial gate material layer is polycrystalline silicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, and the second initial gate material layer has a second doping concentration, and the gate material layer includes the first initial gate material layer and the second initial gate material layer; annealing the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration; patterning the gate material layer to form a gate layer, the gate layer includes a first gate material layer and a second gate material layer, the first gate material layer is formed with the first initial gate material layer, and the second gate material layer is formed with the second initial gate material layer.

[0018] Optionally, the first low-pressure chemical vapor deposition process has a first process temperature; the second low-pressure chemical vapor deposition process has a second process temperature, and the second process temperature is greater than the first process temperature.

[0019] Optionally, the first process temperature ranges from 610°C to 620°C; and the second process temperature ranges from 615°C to 625°C.

[0020] Optionally, before forming the first initial gate material layer, it also includes: using a third low-pressure chemical vapor deposition process and a third in-situ doping process to form a third initial gate material layer on the surface of the substrate, the material of the third initial gate material layer is amorphous silicon, the gate material layer also includes the third initial gate material layer, the third initial gate material layer has a third doping concentration, and the first initial gate material layer is formed on the surface of the third initial gate material layer; the annealing treatment also causes the material of the third initial gate material layer to be transformed from amorphous silicon to polycrystalline silicon, and causes the grain size of the third initial gate material layer to be smaller than the grain size of the first initial gate material layer, so that the third doping concentration is greater than the first doping concentration; the gate layer also includes a third gate material layer, and the third gate material layer is formed with the third initial gate material layer.

[0021] Optionally, the third low-pressure chemical vapor deposition process has a third process temperature, and the third process temperature is lower than the first process temperature.

[0022] Optionally, the third process temperature ranges from 500°C to 610°C.

[0023] Optionally, before forming the first initial gate material layer, a gate oxide material layer is further formed on the surface of the substrate; and a gate oxide layer is formed with the gate oxide material layer under the gate layer.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the formed gate material layer includes a first initial gate material layer and a second initial gate material layer, the grain size of the first initial gate material layer is smaller than the grain size of the second initial gate material layer, the gate material layer is patterned to form a gate layer, so that in the finally formed gate layer, the first doping concentration of the first gate material layer is greater than the second doping concentration of the second gate material layer. Since the first gate material layer is closer to the gate oxide layer than the second gate material layer, it is beneficial to suppress the polycrystalline depletion effect when the total content of doped ions in the gate layer does not change.

[0026] Furthermore, a third initial gate material layer is formed on the surface of the substrate, and the material of the third initial gate material layer is amorphous silicon. The annealing treatment also transforms the material of the third initial gate material layer from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer, thereby making the third doping concentration of the third gate material layer greater than the first doping concentration of the first gate material layer. Since the third gate material layer is closer to the gate oxide layer than the first gate material layer, it is beneficial to further suppress the polycrystalline depletion effect when the total content of doped ions in the gate layer does not change.

[0027] In the semiconductor structure provided by the technical solution of the present invention, the grain size of the first gate material layer is smaller than the grain size of the second gate material layer, and the first doping concentration of the first gate material layer is greater than the second doping concentration of the second gate material layer. Since the first gate material layer is closer to the gate oxide layer than the second gate material layer, it is beneficial to suppress the polycrystalline depletion effect when the total content of doped ions in the gate layer does not change.

[0028] Furthermore, the grain size of the third gate material layer is smaller than the grain size of the first gate material layer, and the third doping concentration of the third gate material layer is greater than the first doping concentration of the first gate material layer. Since the third gate material layer is closer to the gate oxide layer than the first gate material layer, when the total content of doped ions in the gate layer does not change, it is further beneficial to suppress the polycrystalline depletion effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a flow chart of steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0030] Figures 2 to 8 is a structural schematic diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0031] Fig. 9 is a curve diagram showing the relationship between process temperature and grain size of a low pressure chemical vapor deposition process;

[0032] Fig.10 is a flow chart of steps of a method for forming a semiconductor structure according to another embodiment of the present invention;

[0033] Figures 11 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor structure according to another embodiment of the present invention. DETAILED DESCRIPTION

[0034] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0035] As described in the background art, the performance of the polysilicon gate formed by the prior art needs to be improved urgently.

[0036] Specifically, for MOS devices using polysilicon gates, the voltage applied to the gate will attract minority carriers to the interface between the dielectric and the channel, forming an inversion carrier distribution. At this time, carriers will accumulate near the interface between the dielectric and the polysilicon gate to maintain electrical neutrality, which will inevitably deplete the charge of the nearby semiconductor. When the charge of the semiconductor is completely depleted, the semiconductor is equivalent to an insulator, which is equivalent to increasing the effective thickness of the gate dielectric. Although the depletion layer thickness is only a few angstroms of SiO2, when the gate dielectric thickness is reduced to more than a dozen angstroms, the impact of this thickness becomes very significant, and the impact of the polycrystalline depletion effect cannot be ignored.

[0037] In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, in which a gate material layer is formed, including a first initial gate material layer and a second initial gate material layer, the grain size of the first initial gate material layer is smaller than the grain size of the second initial gate material layer, and the gate material layer is patterned to form a gate layer, so that in the finally formed gate layer, the first doping concentration of the first gate material layer is greater than the second doping concentration of the second gate material layer. Since the first gate material layer is closer to the gate oxide layer than the second gate material layer, it is beneficial to suppress the polycrystalline depletion effect when the total content of doped ions in the gate layer does not change.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figure 1 is a flow chart of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 1 , the method for forming the semiconductor structure comprises the following steps:

[0041] Step S101, providing a substrate;

[0042] Step S103, using a first low-pressure chemical vapor deposition process to form a first initial gate material layer on the surface of the substrate, wherein the material of the first initial gate material layer is polysilicon;

[0043] Step S104, using a second low-pressure chemical vapor deposition process to form a second initial gate material layer on the surface of the first initial gate material layer, wherein the material of the second initial gate material layer is polysilicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, and the gate material layer includes the first initial gate material layer and the second initial gate material layer;

[0044] Step S105, implanting doping ions into the gate material layer using an ion implantation process, wherein the first initial gate material layer has a first doping concentration, and the second initial gate material layer has a second doping concentration;

[0045] Step S106, performing annealing treatment on the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration;

[0046] Step S107 , patterning the gate material layer to form a gate layer, wherein the gate layer includes a first gate material layer and a second gate material layer, wherein the first initial gate material layer is used to form the first gate material layer, and the second initial gate material layer is used to form the second gate material layer.

[0047] In this embodiment, before executing step S103, that is, before forming the first initial gate material layer, the following steps are also included:

[0048] Step S102, using a third low-pressure chemical vapor deposition process to form a third initial gate material layer on the surface of the substrate, the material of the third initial gate material layer is amorphous silicon, the gate material layer also includes the third initial gate material layer, and the first initial gate material layer is formed on the surface of the third initial gate material layer.

[0049] In another embodiment, step S102 may not be included.

[0050] The following is a detailed description with reference to the accompanying drawings.

[0051] Figures 2 to 8 It is a structural schematic diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0052] Execute step S101, please refer to Figure 2 , providing a substrate 200.

[0053] In this embodiment, before forming the first initial gate material layer, a gate oxide material layer 201 is further formed on the surface of the substrate 200. The gate oxide material layer 201 is used to form a gate oxide layer.

[0054] In this embodiment, the material of the substrate 200 is silicon.

[0055] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0056] In this embodiment, before executing step S103, that is, before forming the first initial gate material layer, step S102 is also executed. For details, please refer to Figure 3 .

[0057] Please refer to Figure 3 A third low-pressure chemical vapor deposition process is used to form a third initial gate material layer 202 on the surface of the substrate 200 , and the material of the third initial gate material layer 202 is amorphous silicon.

[0058] Specifically, the third initial gate material layer 202 is formed on the surface of the gate oxide material layer 201 .

[0059] In this embodiment, the third low pressure chemical vapor deposition process has a third process temperature.

[0060] In this embodiment, the third process temperature ranges from 500°C to 610°C.

[0061] It should be noted here that the first low-pressure chemical vapor deposition process, the second low-pressure chemical vapor deposition process and the third low-pressure chemical vapor deposition process described in this article are all LPCVD (Low Pressure Chemical Vapor Deposition) processes.

[0062] Here, we will combine Fig. 9 , the process temperature of the low pressure chemical vapor deposition process and the size of the polysilicon grains finally formed are explained.

[0063] Fig. 9 This is a curve diagram showing the relationship between process temperature and grain size in a low pressure chemical vapor deposition process.

[0064] Depend on Fig. 9 It can be seen that within the third process temperature range, i.e., 500° C. to 610° C., the material of the third initial gate material layer 202 formed is amorphous silicon. By subsequently annealing the third initial gate material layer 202, the material of the third initial gate material layer 202 will be transformed from amorphous silicon to polycrystalline silicon, and the higher the third process temperature, the smaller the grains of the polycrystalline silicon finally formed. The grain size of the third gate material layer finally formed can be adjusted by controlling the third process temperature.

[0065] Execute step S103, please refer to Figure 4 A first low-pressure chemical vapor deposition process is used to form a first initial gate material layer 203 on the surface of the substrate 200 , wherein the material of the first initial gate material layer 203 is polycrystalline silicon.

[0066] More specifically, the first initial gate material layer 203 is formed on the surface of the third initial gate material layer 202 .

[0067] The first initial gate material layer 203 is used to form a first gate material layer.

[0068] In this embodiment, the first low pressure chemical vapor deposition process has a first process temperature, and the third process temperature is lower than the first process temperature.

[0069] In this embodiment, the first process temperature ranges from 610°C to 620°C.

[0070] Continue to refer Fig. 9 It can be seen that within the first process temperature range, i.e. 610° C. to 620° C., the material of the first initial gate material layer 202 formed is polysilicon, and the grain size of the first gate material layer finally formed can be adjusted by controlling the first process temperature.

[0071] Execute step S104, please refer to Figure 4 A second low-pressure chemical vapor deposition process is used to form a second initial gate material layer 204 on the surface of the first initial gate material layer 203. The material of the second initial gate material layer 204 is polysilicon. The grain size of the second initial gate material layer 204 is larger than the grain size of the first initial gate material layer 203. The gate material layer includes the first initial gate material layer 203 and the second initial gate material layer 204.

[0072] The second initial gate material layer 204 is used to form a second gate material layer.

[0073] In this embodiment, the gate material layer further includes the third initial gate material layer 202. In another embodiment, the gate material layer includes the first initial gate material layer and the second initial gate material layer, but does not include the third initial gate material layer.

[0074] In this embodiment, the second low pressure chemical vapor deposition process has a second process temperature, and the second process temperature is greater than the first process temperature.

[0075] In this embodiment, the second process temperature ranges from 615°C to 625°C.

[0076] Continue to refer Fig. 9 It can be seen that: within the second process temperature range, i.e., 615°C to 625°C, the material of the second initial gate material layer 204 formed is polysilicon, and the higher the second process temperature, the larger the grains of the polysilicon finally formed. The grain size of the second gate material layer finally formed can be adjusted by controlling the second process temperature.

[0077] Here, by controlling the second process temperature to be greater than the first process temperature, the grain size of the second initial gate material layer 204 can be made greater than the grain size of the first initial gate material layer 203 , thereby making the grain size of the second gate material layer greater than the grain size of the first gate material layer.

[0078] Execute step S105, please refer to Figure 6 , an ion implantation process is used to implant doping ions into the gate material layer, the first initial gate material layer 203 has a first doping concentration, and the second initial gate material layer 204 has a second doping concentration.

[0079] In this embodiment, the ion implantation process further enables the third initial gate material layer 202 to have a third doping concentration.

[0080] The process parameters of the ion implantation process include: the doping ions include N-type or P-type conductive ions. In this embodiment, the doping ions are P-type conductive ions, and specifically, the doping ions are boron.

[0081] Execute step S106, please refer to Figure 7 , performing annealing treatment on the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration.

[0082] Here, it should be noted that since the grain size of the formed first initial gate material layer 203 is smaller than the grain size of the second initial gate material layer 204, the doped ions are easily gathered at the grain boundaries, thereby achieving the purpose of making the first doping concentration greater than the second doping concentration.

[0083] In this embodiment, the annealing treatment also transforms the material of the third initial gate material layer 202 from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer 202 smaller than the grain size of the first initial gate material layer 203, so that the third doping concentration is greater than the first doping concentration.

[0084] Here, it should be noted that the grain size of the obtained third initial gate material layer 202 is smaller than the grain size of the first initial gate material layer 203. Since doped ions tend to aggregate at grain boundaries, the third doping concentration can be made greater than the first doping concentration.

[0085] To execute S107, refer to Figure 8 , patterning the gate material layer to form a gate layer, the gate layer including a first gate material layer 206 and a second gate material layer 207, the first gate material layer 206 is formed by the first initial gate material layer 203, and the second gate material layer 207 is formed by the second initial gate material layer 204.

[0086] At this point, the first gate material layer 206 is formed by the first initial gate material layer 203, and the first gate material layer 206 also has the first doping concentration. The second gate material layer 207 is formed by the second initial gate material layer 203, and the second gate material layer 207 also has the second doping concentration. Since the first doping concentration is greater than the second doping concentration, the first gate material layer 206 is closer to the gate oxide layer than the second gate material layer 207, which is beneficial to suppressing the polycrystalline depletion effect when the total content of doped ions in the gate layer does not change.

[0087] In this embodiment, the gate layer further includes a third gate material layer 205 , and the third gate material layer 205 is formed by using the third initial gate material layer 202 .

[0088] Here, the third gate material layer 205 is formed by the third initial gate material layer 202, and the third gate material layer 205 also has the third doping concentration. Since the third doping concentration is greater than the first doping concentration, the third gate material layer 205 is closer to the gate oxide layer 208 than the first gate material layer 206. When the total content of doped ions in the gate layer does not change, it is further beneficial to suppress the polycrystalline depletion effect.

[0089] In this embodiment, the method of patterning the gate material layer to form the gate layer includes: forming a patterned photoresist layer on a portion of the surface of the gate material layer; using the photoresist layer as a mask, etching the gate material layer until the surface of the substrate 200 is exposed to form the gate layer.

[0090] In this embodiment, the gate oxide layer 208 is further formed by the gate oxide material layer 201 under the gate layer.

[0091] Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 8 , including: a substrate 200; a gate layer located on a surface of part of the substrate 200, the gate layer including a first gate material layer 206 and a second gate material layer 207 located on the surface of the first gate material layer 206, the first gate material layer 206 and the second gate material layer 207 are both polysilicon, the grain size of the first gate material layer 206 is smaller than the grain size of the second gate material layer 207, the first gate material layer 206 has a first doping concentration, the second gate material layer 207 has a second doping concentration, and the first doping concentration is greater than the second doping concentration.

[0092] Here, the grain size of the first gate material layer 206 is smaller than the grain size of the second gate material layer 207, and the first doping concentration of the first gate material layer 206 is greater than the second doping concentration of the second gate material layer 207. Since the first gate material layer 206 is closer to the gate oxide layer than the second gate material layer 207, it is beneficial to suppress the polycrystalline depletion effect when the total content of doped ions in the gate layer does not change.

[0093] In this embodiment, the gate layer also includes: a third gate material layer 205 located on the surface of the substrate 200, the first gate material layer 206 is located on the surface of the third gate material layer 205, the material of the third gate material layer 205 is polycrystalline silicon, and the grain size of the third gate material layer 205 is smaller than the grain size of the first gate material layer 206, and the third gate material layer 205 has a third doping concentration, and the third doping concentration is greater than the first doping concentration.

[0094] Here, the grain size of the third gate material layer 205 is smaller than the grain size of the first gate material layer 206, and the third doping concentration of the third gate material layer 205 is greater than the first doping concentration of the first gate material layer 206. Since the third gate material layer 205 is closer to the gate oxide layer 208 than the first gate material layer 206, when the total content of doped ions in the gate layer does not change, it is further beneficial to suppress the polycrystalline depletion effect.

[0095] In this embodiment, the semiconductor structure further includes: a gate oxide layer 208 located between the surface of the substrate 200 and the gate layer.

[0096] Specifically, the gate oxide layer 208 is located between the surface of the substrate 200 and the third gate material layer 205 .

[0097] Fig.10 is a flow chart of steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0098] The main difference between this embodiment and the previous embodiment is that the doping method of the doped ions in the gate material layer is different.

[0099] Fig.10 is a flow chart of steps of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0100] Please refer to Fig.10 , the method for forming the semiconductor structure comprises the following steps:

[0101] Step S301, providing a substrate;

[0102] Step S303, using a first low-pressure chemical vapor deposition process and a first in-situ doping process to form a first initial gate material layer on the surface of the substrate, wherein the material of the first initial gate material layer is polysilicon, and the first initial gate material layer has a first doping concentration;

[0103] Step S304, using a second low-pressure chemical vapor deposition process and a second in-situ doping process to form a second initial gate material layer on the surface of the first initial gate material layer, wherein the material of the second initial gate material layer is polysilicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, and the second initial gate material layer has a second doping concentration, and the gate material layer includes the first initial gate material layer and the second initial gate material layer;

[0104] Step S305, performing annealing treatment on the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration;

[0105] Step S306, patterning the gate material layer to form a gate layer, wherein the gate layer includes a first gate material layer and a second gate material layer, wherein the first initial gate material layer is used to form the first gate material layer, and the second initial gate material layer is used to form the second gate material layer.

[0106] In this embodiment, before executing step S303, that is, before forming the first initial gate material layer, the following steps are also included:

[0107] Step S302, using a third low-pressure chemical vapor deposition process and a third in-situ doping process to form a third initial gate material layer on the surface of the substrate, the material of the third initial gate material layer is amorphous silicon, the gate material layer also includes the third initial gate material layer, the third initial gate material layer has a third doping concentration, and the first initial gate material layer is formed on the surface of the third initial gate material layer.

[0108] In another embodiment, step S302 may not be included.

[0109] The following is a detailed description with reference to the accompanying drawings.

[0110] Figures 11 to 16 It is a structural schematic diagram of each step of a method for forming a semiconductor structure according to another embodiment of the present invention.

[0111] Execute step S301, please refer to Fig.11 , providing a substrate 400.

[0112] In this embodiment, before forming the first initial gate material layer, a gate oxide material layer 401 is further formed on the surface of the substrate 400. The gate oxide material layer 401 is used to form a gate oxide layer.

[0113] In this embodiment, before executing step S303, that is, before forming the first initial gate material layer, step S302 is also executed. For details, please refer to Fig.12 .

[0114] Please refer to Fig.12 A third low-pressure chemical vapor deposition process and a third in-situ doping process are used to form a third initial gate material layer 402 on the surface of the substrate 400. The material of the third initial gate material layer 402 is amorphous silicon, and the third initial gate material layer 402 has a third doping concentration.

[0115] Specifically, the third initial gate material layer 402 is formed on the surface of the gate oxide material layer 401 .

[0116] In this embodiment, the third low pressure chemical vapor deposition process has a third process temperature.

[0117] In this embodiment, the third process temperature ranges from 500°C to 610°C.

[0118] Execute step S303, please refer to Fig.13 A first low-pressure chemical vapor deposition process and a first in-situ doping process are used to form a first initial gate material layer 403 on the surface of the substrate 400 . The material of the first initial gate material layer 403 is polysilicon, and the first initial gate material layer 403 has a first doping concentration.

[0119] Specifically, the first initial gate material layer 403 is formed on the surface of the third initial gate material layer 402 .

[0120] In this embodiment, the first low pressure chemical vapor deposition process has a first process temperature, and the third process temperature is lower than the first process temperature.

[0121] In this embodiment, the first process temperature ranges from 610°C to 620°C.

[0122] Execute step S104, please refer to Fig.14 A second initial gate material layer 404 is formed on the surface of the first initial gate material layer 403 by a second low-pressure chemical vapor deposition process and a second in-situ doping process. The material of the second initial gate material layer 404 is polycrystalline silicon. The grain size of the second initial gate material layer 404 is larger than the grain size of the first initial gate material layer 403, and the second initial gate material layer 404 has a second doping concentration. The gate material layer includes the first initial gate material layer 403 and the second initial gate material layer 404.

[0123] In this embodiment, the second low pressure chemical vapor deposition process has a second process temperature, and the second process temperature is greater than the first process temperature.

[0124] In this embodiment, the second process temperature ranges from 615°C to 625°C.

[0125] In this embodiment, the gate material layer further includes the third initial gate material layer 402 .

[0126] Execute step S305, please refer to Fig.15 , performing annealing treatment on the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration.

[0127] The annealing process also transforms the material of the third initial gate material layer 402 from amorphous silicon to polysilicon, and makes the grain size of the third initial gate material layer 402 smaller than the grain size of the first initial gate material layer 403, and makes the third doping concentration greater than the first doping concentration.

[0128] Execute step S306, please refer to Fig.16 , patterning the gate material layer to form a gate layer, the gate layer including a first gate material layer 406 and a second gate material layer 407, the first gate material layer 406 is formed by the first initial gate material layer 403, and the second gate material layer 407 is formed by the second initial gate material layer 404.

[0129] At this point, the first gate material layer 406 is formed by the first initial gate material layer 403, and the first gate material layer 406 also has the first doping concentration. The second gate material layer 407 is formed by the second initial gate material layer 403, and the second gate material layer 407 also has the second doping concentration. Since the first doping concentration is greater than the second doping concentration, the first gate material layer 406 is closer to the gate oxide layer than the second gate material layer 407, which is beneficial to suppressing the polycrystalline depletion effect when the total content of doped ions in the gate layer does not change.

[0130] In this embodiment, the gate layer further includes a third gate material layer 405 , and the third gate material layer 405 is formed by using the third initial gate material layer 402 .

[0131] Here, the third gate material layer 405 is formed by the third initial gate material layer 402, and the third gate material layer 405 also has the third doping concentration. Since the third doping concentration is greater than the first doping concentration, the third gate material layer 405 is closer to the gate oxide layer 408 than the first gate material layer 406. When the total content of doped ions in the gate layer does not change, it is further beneficial to suppress the polycrystalline depletion effect.

[0132] In this embodiment, a gate oxide layer 408 is formed by using the gate oxide material layer 401 under the gate layer.

[0133] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A gate layer is located on a portion of the surface of the substrate, the gate layer includes a first gate material layer and a second gate material layer located on the surface of the first gate material layer, the materials of the first gate material layer and the second gate material layer are both polysilicon, the grain size of the first gate material layer is smaller than the grain size of the second gate material layer, the first gate material layer has a first doping concentration, the second gate material layer has a second doping concentration, and the first doping concentration is greater than the second doping concentration.

2. The semiconductor structure according to claim 1, wherein: The gate layer also includes: a third gate material layer located on the surface of the substrate, the first gate material layer is located on the surface of the third gate material layer, the material of the third gate material layer is polysilicon, and the grain size of the third gate material layer is smaller than the grain size of the first gate material layer, and the third gate material layer has a third doping concentration, and the third doping concentration is greater than the first doping concentration.

3. The semiconductor structure according to claim 1, wherein: Also includes: A gate oxide layer is located between the substrate surface and the gate layer.

4. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Using a first low-pressure chemical vapor deposition process, forming a first initial gate material layer on the surface of the substrate, wherein the material of the first initial gate material layer is polycrystalline silicon; Using a second low-pressure chemical vapor deposition process, forming a second initial gate material layer on the surface of the first initial gate material layer, wherein the material of the second initial gate material layer is polysilicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, and the gate material layer includes the first initial gate material layer and the second initial gate material layer; Injecting doping ions into the gate material layer using an ion implantation process, wherein the first initial gate material layer has a first doping concentration, and the second initial gate material layer has a second doping concentration; performing an annealing treatment on the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration; The gate material layer is patterned to form a gate layer, wherein the gate layer includes a first gate material layer and a second gate material layer. The first gate material layer is formed by using the first initial gate material layer, and the second gate material layer is formed by using the second initial gate material layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: The first low pressure chemical vapor deposition process has a first process temperature; The second LPCVD process has a second process temperature, and the second process temperature is greater than the first process temperature.

6. The method for forming a semiconductor structure according to claim 5, wherein: The first process temperature ranges from 610°C to 620°C; the second process temperature ranges from 615°C to 625°C.

7. The method for forming a semiconductor structure according to claim 5, before forming the first initial gate material layer, further comprising: A third low-pressure chemical vapor deposition process is adopted to form a third initial gate material layer on the surface of the substrate, wherein the material of the third initial gate material layer is amorphous silicon, and the gate material layer also includes the third initial gate material layer, and the first initial gate material layer is formed on the surface of the third initial gate material layer; the ion implantation process also makes the third initial gate material layer have a third doping concentration; the annealing treatment also makes the material of the third initial gate material layer change from amorphous silicon to polycrystalline silicon, and makes the grain size of the third initial gate material layer smaller than the grain size of the first initial gate material layer, so that the third doping concentration is greater than the first doping concentration; the gate layer also includes a third gate material layer, and the third gate material layer is formed by the third initial gate material layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: The third LPCVD process has a third process temperature, and the third process temperature is lower than the first process temperature.

9. The method for forming a semiconductor structure according to claim 8, wherein: The third process temperature ranges from 500°C to 610°C.

10. The method for forming a semiconductor structure according to claim 4, wherein: The process parameters of the ion implantation process include: the ions include N-type or P-type conductive ions.

11. The method for forming a semiconductor structure according to claim 4, wherein: Before forming the first initial gate material layer, a gate oxide material layer is formed on the surface of the substrate; the gate oxide material layer under the gate layer is used as the gate oxide layer.

12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; Using a first low-pressure chemical vapor deposition process and a first in-situ doping process, a first initial gate material layer is formed on the surface of the substrate, wherein the material of the first initial gate material layer is polysilicon, and the first initial gate material layer has a first doping concentration; A second low-pressure chemical vapor deposition process and a second in-situ doping process are used to form a second initial gate material layer on the surface of the first initial gate material layer, wherein the material of the second initial gate material layer is polysilicon, the grain size of the second initial gate material layer is larger than the grain size of the first initial gate material layer, and the second initial gate material layer has a second doping concentration, and the gate material layer includes the first initial gate material layer and the second initial gate material layer; Performing annealing treatment on the gate material layer to reduce defects in the gate material layer and make the first doping concentration greater than the second doping concentration; The gate material layer is patterned to form a gate layer, wherein the gate layer includes a first gate material layer and a second gate material layer. The first gate material layer is formed by using the first initial gate material layer, and the second gate material layer is formed by using the second initial gate material layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The first low pressure chemical vapor deposition process has a first process temperature; The second LPCVD process has a second process temperature, and the second process temperature is greater than the first process temperature.

14. The method for forming a semiconductor structure according to claim 13, wherein: The first process temperature ranges from 610°C to 620°C; the second process temperature ranges from 615°C to 625°C.

15. The method for forming a semiconductor structure according to claim 13, before forming the first initial gate material layer, further comprising: A third low-pressure chemical vapor deposition process and a third in-situ doping process are used to form a third initial gate material layer on the surface of the substrate, wherein the material of the third initial gate material layer is amorphous silicon, and the gate material layer also includes the third initial gate material layer, wherein the third initial gate material layer has a third doping concentration, and the first initial gate material layer is formed on the surface of the third initial gate material layer; the annealing treatment also causes the material of the third initial gate material layer to be transformed from amorphous silicon to polycrystalline silicon, and causes the grain size of the third initial gate material layer to be smaller than the grain size of the first initial gate material layer, and causes the third doping concentration to be greater than the first doping concentration; the gate layer also includes a third gate material layer, and the third gate material layer is formed by using the third initial gate material layer.

16. The method for forming a semiconductor structure according to claim 15, wherein: The third LPCVD process has a third process temperature, and the third process temperature is lower than the first process temperature.

17. The method for forming a semiconductor structure according to claim 16, wherein: The third process temperature ranges from 500°C to 610°C.

18. The method for forming a semiconductor structure according to claim 15, wherein: Before forming the first initial gate material layer, a gate oxide material layer is formed on the surface of the substrate; and a gate oxide layer is formed by using the gate oxide material layer under the gate layer.

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