Gate interconnection method of flip-chip stacked transistor, transistor, device and equipment

Abstract

The invention provides a gate interconnection method of an inverted stacked transistor, a transistor, a device and equipment. The grid interconnection method comprises the following steps: forming an active structure comprising a first active structure and a second active structure on a substrate; forming a first transistor including a first gate structure based on the first active structure; reversing and exposing the second active structure; forming a second transistor including a second gate structure based on the second active structure; before the second transistor is formed, forming a first insulating layer based on the first gate structure, and selectively etching the first insulating layer and the first gate structure through a material to form an interconnection structure; and / or, after the second gate structure is formed, a second insulating layer is formed based on the second gate structure, the second insulating layer and the second gate structure are selectively etched through the material, an interconnection structure is formed, and the interconnection structure is used for connecting the first gate structure and the second gate structure. According to the invention, the requirement of grid interconnection on photoetching can be reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a gate interconnection method, transistor, device and equipment of a flip-chip stacked transistor. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Flip-chip stacked transistors integrate two or more layers of transistors in a vertical space to further increase transistor integration density, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In the related art, when preparing the gate interconnection structure of the upper and lower layers of transistors in a flip-chip stacked transistor, the gate area is usually etched by photolithography to form a groove for the gate interconnection structure, and then metal is filled in the groove to form the gate interconnection structure, but this method has high requirements on the photolithography accuracy. Summary of the invention

[0004] The present application provides a gate interconnection method of a flip-chip stacked transistor, a flip-chip stacked transistor, a device and an apparatus, which can reduce the requirements of the gate interconnection on the photolithography accuracy.

[0005] In a first aspect, an embodiment of the present application provides a gate interconnection method for a flip-chip stacked transistor, the method comprising: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, the first active structure being away from the substrate relative to the second active structure; forming a first transistor based on the first active structure, the first transistor comprising a first gate structure; flipping the first transistor and exposing the second active structure; forming a second transistor based on the second active structure, the second transistor comprising a second gate structure; before forming the second transistor, forming a first insulating layer based on the first gate structure, and forming an interconnection structure by selectively etching the first insulating layer and the first gate structure in a first region; and / or, after forming the second gate structure, forming a second insulating layer based on the second gate structure, and forming an interconnection structure by selectively etching the second insulating layer and the second gate structure in the first region, the interconnection structure being used to connect the first gate structure with the second gate structure, the first region being located between a boundary on one side of the active structure and the gate region.

[0006] In one possible embodiment, before forming the first transistor, the method also includes: forming an isolation structure surrounding the second active structure on the substrate to expose the first active structure; selectively etching the first insulating layer and the first gate structure in the first region to form an interconnection structure, including: forming a first mask on the first insulating layer, the first mask exposing the first region; based on the first mask, selectively etching the first insulating layer, the first gate structure and a portion of the isolation structure to form a first groove; filling the first groove with metal material to form an interconnection structure.

[0007] In one possible embodiment, before forming the first transistor, the method also includes: forming an isolation structure surrounding the second active structure on the substrate to expose the first active structure; exposing the second active structure, including: removing the substrate; thinning the isolation structure to a preset height to expose the second active structure; in the first region, selectively etching the second insulating layer and the second gate structure by material to form an interconnection structure, including: forming a second mask on the second insulating layer, the second mask exposing the first region; based on the second mask, selectively etching the second insulating layer, the second gate structure and the retained isolation structure to the first gate structure by material to form a second groove; filling the second groove with metal material to form an interconnection structure.

[0008] In one possible embodiment, a first insulating layer is formed based on the first gate structure, including: etching the first gate structure to a preset height and forming a first insulating layer on the etched first gate structure; and a second insulating layer is formed based on the second gate structure, including: etching the second gate structure to a preset height and forming a second insulating layer on the etched second gate structure.

[0009] In one possible embodiment, a first insulating layer is formed on the etched first gate structure, comprising: depositing an insulating material on the etched first gate structure to form a first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of the first side wall, and the first side wall is located on both sides of the first gate structure; and a second insulating layer is formed on the etched second gate structure, comprising: depositing an insulating material on the etched second gate structure to form a second insulating layer, wherein the upper surface of the second insulating layer is flush with the upper surface of the second side wall, and the second side wall is located on both sides of the second gate structure.

[0010] In a possible implementation, the method further includes: forming a gate cutoff structure on both sides of the first gate structure and / or the second gate structure, the gate cutoff structure being used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

[0011] In a second aspect, an embodiment of the present application provides a flip-chip stacked transistor, which is manufactured using a method as described in the first aspect and any one of its embodiments, and includes: a first transistor; a second transistor, the first transistor and the second transistor are arranged back to back; and an interconnection structure, the interconnection structure is used to connect a first gate structure of the first transistor with a second gate structure of the second transistor.

[0012] In a possible implementation, the flip-chip stacked transistor further includes: a gate cut-off structure, which is located on both sides of the first gate structure and / or the second gate structure and is used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, comprising: a flip-chip stacked transistor as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] The technical solution provided by this application may have the following beneficial effects:

[0016] In an embodiment of the present application, an active structure including a first active structure and a second active structure is formed on a substrate, a first transistor is formed based on the first active structure, the first transistor is flipped, and a second transistor is formed based on the exposed second active structure. Before forming the second transistor, a first insulating layer is formed based on the first gate structure of the first transistor, and the first insulating layer and the first gate structure are selectively etched in the first region to form an interconnection structure, and / or, after forming the second gate structure of the second transistor, a second insulating layer is formed based on the second gate structure, and the second insulating layer and the second gate structure are selectively etched in the first region to form an interconnection structure. Therefore, in an embodiment of the present application, an interconnection structure is formed after the front and back transistors are formed, which can reduce the metal blockage problem during the filling process and reduce the resistance of the interconnection structure inside the flip-chip stacked transistor. At the same time, the insulating layer and the gate structure are etched on the front and / or back of the transistor by the selectivity of the material to form an interconnection structure, and the gate region does not need to be etched by photolithography, which can reduce the requirements of photolithography for gate interconnection.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 A schematic diagram of an implementation process of a gate interconnection method of a flip-chip stacked transistor in an embodiment of the present application;

[0020] Figure 2 A schematic top view of a flip-chip stacked transistor in an embodiment of the present application;

[0021] Figures 3 to 16 A schematic diagram of a flip-chip stacked transistor in the process of manufacturing in an embodiment of the present application;

[0022] Fig.17 It is a structural schematic diagram of a flip-chip stacked transistor in an embodiment of the present application.

[0023] The above pictures:

[0024] 10. Flip-chip stacked transistor; 11. First transistor (front transistor); 111. First fin structure (first active structure); 112. First source-drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source-drain metal; 116. First metal interconnect layer; 12. Second transistor (back transistor); 121. Second fin structure (second active structure); 122. Second source-drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 125. Second source-drain metal; 126. Second metal interconnection layer; 20. Substrate; 21. Fin structure (active structure); 22. Isolation structure; 23. First side wall; 24. First insulating layer; 25. Third insulating layer; 26. Carrier wafer; 27. Second dummy gate structure; 28. Second side wall; 29. ​​Second insulating layer; 30. Second mask; 31. Groove formed by etching the insulating layer; 32. Second groove; 33. Interconnection structure. DETAILED DESCRIPTION

[0025] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0026] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Flip-chip stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies to continue the miniaturization of integrated circuit size.

[0027] In one embodiment, there are two schemes for the manufacturing process of the flip-chip stack transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0028] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using substrate bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0029] The second solution is based on substrate bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the substrate on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to substrate bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance. This solution currently has the following technical challenges: (1) Preparation of high-quality upper transistor active layer; (2) Thinning and defect control of the upper bonding substrate; (3) There is an alignment error between the upper and lower transistors, which requires extremely high lithography accuracy.

[0030] However, in some schemes for preparing flip-chip stacked transistors, when forming the gate interconnection structure of the upper and lower layers of transistors, a groove for the gate interconnection structure is usually formed before the gate structure of the back transistor is formed, and then a metal material is filled in the groove to form the gate interconnection structure. However, this method may have the problem of metal clogging during the filling process, and the gate interconnection structure formed by this method has a large resistance. In addition, this method relies on photolithography to achieve self-alignment of the gate region and the source and drain region, and requires high photolithography alignment accuracy.

[0031] Based on the above problems, an embodiment of the present application provides a gate interconnection method for a flip-chip stacked transistor, which can solve the problem of metal blockage, reduce the resistance of the internal gate interconnection structure of the flip-chip stacked transistor, and reduce the requirements for lithography accuracy.

[0032] In the embodiments of the present application, the flip-chip stacked transistor can be applied to semiconductor devices such as memory and processor.

[0033] In one embodiment, the flip-stacked transistor may include at least two transistors. Taking the first transistor and the second transistor as an example, the first transistor and the second transistor are stacked, the first transistor is formed based on the first active structure, and the second transistor is formed based on the second active structure. The first active structure and the second active structure are actually formed by the same process, so it can be understood that the first transistor and the second transistor are self-aligned. In addition, the flip-stacked transistor also includes an interconnection structure formed in the gate region, and the interconnection structure is used to connect the first gate structure of the first transistor and the second gate structure of the second transistor to achieve gate interconnection between the upper and lower layers of transistors.

[0034] In one embodiment, the flip-chip stacked transistor may further include a gate cut-off structure, which is located on both sides of the first gate structure and / or the second gate structure and is used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

[0035] In an embodiment of the present application, the first transistor and the second transistor in the flip-chip stacked transistor may be transistors of the same type, and the types of the transistors may include but are not limited to: fin field effect transistor (FinFET), gate-all-around field effect transistor (GAAFET), planar transistor, vertical field effect transistor (VFET), forksheet transistor, etc.

[0036] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a gate interconnection method of a flip-chip stacked transistor in an embodiment of the present application. Figure 1 As shown, the gate interconnection method of the flip-chip stacked transistor includes the following steps.

[0037] Step S110: forming an active structure on the substrate structure.

[0038] The active structure includes a first active structure and a second active structure, and the first active structure is farther away from the substrate than the second active structure.

[0039] In some embodiments, the implementation process of step S110 may be: providing a substrate; etching the substrate to form an active structure, wherein the active structure includes a first active structure and a second active structure, and the first active structure is farther from the substrate than the second active structure.

[0040] In some embodiments, the substrate may be any semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate.

[0041] In some embodiments, the SOI substrate includes a three-layer structure: a thin top silicon layer, a buried oxide (BOX) layer, and a supporting base silicon layer. That is, a BOX layer is provided between the top silicon layer and the bottom silicon substrate, and the SOI substrate can achieve dielectric isolation of components in the integrated circuit and eliminate the parasitic latch effect in the bulk silicon CMOS circuit. The integrated circuit prepared using the SOI substrate also has the advantages of small parasitic capacitance, high integration density, high speed, simple process, small short channel effect, and is particularly suitable for low-voltage and low-power circuits.

[0042] After providing the substrate, the substrate may be etched to form a plurality of active structures standing upright on the substrate. In one example, the active structures may be obtained by anisotropically etching the substrate. The etching process may be, for example, at least one of dry etching, wet etching, reactive ion etching, and chemical oxide removal processes.

[0043] In the case where the transistor is a fin field effect transistor, the active structure is a fin structure. In the case where the transistor is a full-surround gate transistor, the active structure is a nanosheet. In the case where the transistor is a planar transistor, the active structure is a block planar structure.

[0044] In some embodiments, the active structure may be multiple. In one example, the multiple active structures may be arranged in parallel. In other words, the multiple active structures may extend in the same direction. In one example, the multiple active structures may include a first active structure and a second active structure in a vertical direction of the substrate, and the first active structure is farther away from the substrate than the second active structure.

[0045] It can be understood that in the embodiment of the present application, since the upper and lower layers of transistors in the flip-chip stacked transistor share an active structure, that is, the first active structure of the upper transistor (front transistor) and the second active structure of the lower transistor (back transistor) are formed by the same etching process, a larger etching depth can be used when forming the active structure on the substrate to obtain an active structure with a higher height. For example, the height of the active structure obtained by etching can be greater than 100 nanometers (nm).

[0046] In some embodiments, after forming the active structure, an isolation structure surrounding the second active structure may be formed on the substrate to expose the first active structure.

[0047] In some embodiments, after etching the substrate, a trench may be formed at the etched position, and an oxide may be filled in the trench to form an isolation structure. By way of example, the isolation structure may also be referred to as a shallow trench isolation (STI) structure. The oxide forming the isolation structure may be, by way of example, silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc.

[0048] In some embodiments, in order to facilitate subsequent processing, after the isolation structure is formed, the isolation structure can be polished or chemical-mechanical planarization (CMP) is performed, so that when the isolation structure is subsequently etched, different areas of the isolation structure have the same etching depth, thereby making the top height of the exposed active structure the same.

[0049] In some embodiments, a portion of the isolation structure may be etched first to expose the first active structure, wherein the solvent used to etch the isolation structure may be, for example, a dilute hydrofluoric acid (DHF) solution or a buffered oxide etch (BOE) solution.

[0050] It can be understood that after etching a portion of the isolation structure, the remaining isolation structure surrounds the second active structure to expose the first active structure.

[0051] Step S120: forming a first transistor based on the first active structure.

[0052] A front transistor, ie, a first transistor, in a flip-chip stack transistor can be prepared by using the first active structure in the active structure.

[0053] In some embodiments, the implementation process of step S120 may be: epitaxially growing a first source-drain structure on the first active structure; forming a first gate structure based on the first active structure; and forming a first source-drain metal on the first source-drain structure.

[0054] It is understandable that after forming the shallow trench isolation structure, a semiconductor material can also be deposited in the gate region of the first transistor in the flip-chip stacked transistor to form a first dummy gate structure; a first spacer is formed on both sides of the first dummy gate structure; and a first source-drain structure is formed on the first active structure on both sides of the first dummy gate structure and the first spacer. The first spacer is used to isolate the first source-drain structure from the first gate structure. The structure of the first spacer can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0055] In some embodiments, the semiconductor material forming the first dummy gate structure may be polysilicon, amorphous silicon, etc. Exemplarily, the first spacer may have a single-layer structure, and the entire structure may be made of the same material, such as porous silicon carbon oxyhydride (SiCOH).

[0056] In some embodiments, the implementation process of forming the first source-drain structure on the first dummy gate structure and the first active structure on both sides of the first sidewall may be: etching the first active structure of the first transistor in the source-drain region to form a first source-drain groove, performing source-drain epitaxial growth at the first source-drain groove to form the first source-drain structure.

[0057] For example, strained materials such as silicon germanium or silicon carbide may be formed in the source-drain grooves by selective epitaxial growth to fill the source-drain grooves of the first transistor, and then a first source-drain structure is formed on the strained material by a heavy doping process.

[0058] In some embodiments, after the first source-drain structure is formed, an interlayer dielectric may be deposited on the first source-drain structure and thinned to the top of the first source-drain structure to form a first interlayer dielectric layer.

[0059] For example, an insulating material (such as silicon dioxide SiO2) may be deposited on the first source-drain structure and the first active structure and planarized to form a first interlayer dielectric layer, and the first interlayer dielectric layer may cover the first source-drain structure and the first active structure.

[0060] After the first source-drain structure is formed, a gate structure of the first transistor, that is, a first gate structure, may be formed.

[0061] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to obtain a first gate groove, an insulating material can be deposited at the first gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute the first gate structure. In some embodiments, the first gate electrode layer can also be referred to as a first gate metal layer.

[0062] For example, the first gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide).

[0063] After forming the first gate structure, a metal material may be deposited on the first source-drain structure formed above to form a first source-drain metal.

[0064] In some embodiments, when the first interlayer dielectric layer is formed after the first source-drain structure is formed, the first interlayer dielectric layer can be etched to expose the first source-drain structure, and a metal material is filled on the first source-drain structure to form a first source-drain metal.

[0065] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the first source-drain metal, the first source-drain groove, the second source-drain structure, the second source-drain metal, the second source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0066] It should be noted that the first source-drain structure, the first interlayer dielectric layer, the first gate structure, and the first source-drain metal can all be formed through standard steps of a semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0067] In some embodiments, after the first transistor is manufactured, a first metal interconnection layer may be formed on the first transistor.

[0068] It can be understood that a first metal interconnection layer can be formed by performing back-end processes (such as dielectric deposition between interconnection lines, metal line formation, lead pad formation, etc.) on the first transistor.

[0069] Step S130: flipping the first transistor and exposing the second active structure.

[0070] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer formed above to form a third insulating layer, and the third insulating layer may be bonded to a carrier wafer. The first transistor is then flipped over and the substrate is placed on top.

[0071] In some embodiments, the process of exposing the second active structure in step S130 may be: removing the substrate; thinning the isolation structure to a preset height to expose the second active structure, and the thinned shallow trench isolation structure is used to isolate the first transistor and the second transistor.

[0072] In one example, after flipping, the substrate may be removed by polishing or chemical mechanical planarization.

[0073] It is understandable that after removing the substrate, the top of the second active structure is flush with the top of the isolation structure, so the isolation structure can be thinned to a preset height to expose the peripheral side of the second active structure, so that the second transistor can be formed later based on the second active structure exposed on the peripheral side. The preset height can be set according to actual needs, and the embodiment of the present application is not limited to this.

[0074] Step S140: forming a second transistor based on the second active structure.

[0075] After the front transistor is flipped over, a back transistor, ie, a second transistor, in the flip-stack transistor can be prepared based on the exposed second active structure.

[0076] In some embodiments, the implementation process of step S140 may be: epitaxially growing a second source-drain structure on the second active structure; forming a second gate structure based on the second active structure; and forming a second source-drain metal on the second source-drain structure.

[0077] In some embodiments, after forming the second source-drain structure, an interlayer dielectric may be deposited on the second source-drain structure, thinned to the top layer of the second source-drain structure to form a second interlayer dielectric layer, and then a second source-drain metal may be formed in the second interlayer dielectric layer.

[0078] In some embodiments, the preparation method of the second source-drain structure, the second interlayer dielectric layer, the second gate structure, and the second source-drain metal of the second transistor is the same as the preparation method of the first source-drain structure, the first interlayer dielectric layer, the first gate structure, and the first source-drain metal in the first transistor, and will not be repeated here.

[0079] It should be noted that since the second source-drain structure is epitaxially grown based on the second active structure, the first source-drain structure is epitaxially grown based on the first active structure, and the first active structure and the second active structure are self-aligned structures, the second source-drain structure and the first source-drain structure are self-aligned structures, which effectively improves the symmetry of the flip-chip stacked transistor structure.

[0080] In addition, in some embodiments, the embodiment of the present application may not form the second source-drain metal first in step S140, and then form the second source-drain metal after the interconnect structure is formed based on step S150.

[0081] Step S150: before forming the second transistor, a first insulating layer is formed based on the first gate structure, and the first insulating layer and the first gate structure are selectively etched by materials in the first region to form an interconnection structure; and / or, after forming the second gate structure, a second insulating layer is formed based on the second gate structure, and the second insulating layer and the second gate structure are selectively etched by materials in the first region to form an interconnection structure.

[0082] In some embodiments, the interconnect structure is used to connect the first gate structure and the second gate structure, and the first region is located between the active structure and a boundary of one side of the flip-chip stack transistor.

[0083] It should be noted that the interconnection structure in the embodiment of the present application can be formed once on the back transistor, or it can be formed once on the front transistor, and the interconnection structure can also be formed on both the front transistor and the back transistor, and the gate structure of the front transistor can be connected to the gate structure of the back transistor through the interconnection structure on the front and back sides.

[0084] The following first introduces a method for forming an interconnection structure at the front transistor.

[0085] In some embodiments, after forming the first gate structure and before forming the second transistor, a first insulating layer may be formed based on the first gate structure, wherein the first insulating layer is used to protect the first gate structure, and the first insulating layer may also be referred to as a gate cap.

[0086] In some embodiments, based on the first gate structure, the process of forming the first insulating layer may be: etching the first gate structure to a preset height, and forming the first insulating layer on the etched first gate structure. The preset height may be pre-set, and the embodiment of the present application does not limit this.

[0087] It can be understood that a portion of the first gate structure can be selectively etched so that the upper surface of the first gate structure is slightly lower than the upper surface of the first spacer.

[0088] In some embodiments, the process of forming the first insulating layer on the etched first gate structure may be: depositing an insulating material on the etched first gate structure to form the first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of the first sidewall. The insulating material may be nitride, which is not limited in the embodiments of the present application.

[0089] It can be understood that after the first insulating layer is formed, the first insulating layer and the first gate structure may be selectively etched in the first region to form an interconnection structure.

[0090] In some embodiments, the process of forming an interconnect structure by selectively etching the first insulating layer and the first gate structure in the first region may be: forming a first mask on the first insulating layer, the first mask exposing the first region; based on the first mask, selectively etching the first insulating layer, the first gate structure and a portion of the isolation structure to form a first groove; filling the first groove with metal material to form an interconnect structure.

[0091] It can be understood that a mask can be first formed on the gate region of the first transistor, that is, a gate merge groove is first photoetched, and then based on the groove, the area exposed by the first mask is selectively etched. In the embodiment of the present application, the etching material can be pre-set to be an insulating material forming the first insulating layer, so that only the first insulating layer will be etched during etching, and the first sidewall and source and drain regions will not be etched, that is, the etched groove will automatically align with the gate region and will not affect the source and drain regions next to it.

[0092] In some embodiments, the first region exposed by the gate merge groove may have a larger range, and may expose the first sidewall spacers and the source and drain regions on both sides of the first insulating layer.

[0093] It can be understood that the interconnection structure is formed after the front transistor is formed. At this time, the back transistor has not yet been formed. There is an isolation structure below the front transistor. Therefore, after the first insulating layer is removed by selective etching of the material, the first gate structure and a part of the isolation structure located below the original first insulating layer can be anisotropically etched to form a first groove, and a metal material is filled in the first groove to form an interconnection structure. In this way, after the back transistor is subsequently prepared, the bottom of the interconnection structure contacts the surface or inside of the gate metal of the back transistor. Therefore, the gate structure of the front transistor can be connected to the gate structure of the back transistor through the interconnection structure.

[0094] In some embodiments, an interconnect structure may be formed on the front side before forming the first metal interconnect layer. After forming the interconnect structure, the first metal interconnect layer may be formed on the first transistor and the interconnect structure, and then the operations of step S130 and step S140 are sequentially performed.

[0095] In addition, in some embodiments, before forming the first source-drain metal of the first transistor, an interconnect structure may be formed first, and then the first source-drain metal and the first metal interconnect layer may be formed in sequence.

[0096] The following describes a method for forming an interconnection structure on the back side after forming the second transistor.

[0097] In some embodiments, after forming the second gate structure, a second insulating layer may be formed based on the second gate structure. In some embodiments, based on the second gate structure, the second insulating layer may be formed by etching the second gate structure to a preset height, and forming the second insulating layer on the etched second gate structure. The preset height may be pre-set, and the embodiment of the present application is not limited thereto.

[0098] It can be understood that a portion of the second gate structure can be selectively etched so that the upper surface of the second gate structure is slightly lower than the upper surface of the second spacer.

[0099] In some embodiments, the process of forming the second insulating layer on the etched second gate structure may be: depositing an insulating material on the etched second gate structure to form the second insulating layer, wherein the upper surface of the second insulating layer is flush with the upper surface of the second sidewall. The insulating material may be nitride, which is not limited in the embodiments of the present application.

[0100] It can be understood that after the second insulating layer is formed, the second insulating layer and the second gate structure can be selectively etched in the first region to form an interconnection structure.

[0101] It can be understood that a groove can be etched in the gate area between the active structure and the boundary on one side of the semiconductor structure, and the groove runs through the gate structure of the back transistor and the isolation structure between the front and back transistors, and the etching stops on the surface or inside of the gate metal of the front transistor.

[0102] In some embodiments, the process of forming an interconnect structure by selectively etching a second insulating layer and a second gate structure in a first region may be as follows: forming a second mask on the second insulating layer, the second mask exposing the first region; based on the second mask, selectively etching the second insulating layer, the second gate structure and the retained isolation structure to the first gate structure to form a second groove; and filling the second groove with metal material to form an interconnect structure.

[0103] It can be understood that a mask can be first formed on the gate region of the second transistor, that is, a gate merge groove is first photolithographically formed, and then based on the groove, the area exposed by the second mask is selectively etched by the material. In the embodiment of the present application, the etching material can be pre-set to be an insulating material forming a second insulating layer, so that only the second insulating layer will be etched during etching, and the second sidewall and source and drain regions will not be etched, that is, the etched groove will automatically align with the gate region and will not affect the source and drain regions next to it.

[0104] In some embodiments, the first region exposed by the gate merge groove may have a larger range, and may expose the second sidewall spacers and the source and drain regions on both sides of the second insulating layer.

[0105] It can be understood that after the second insulating layer is removed by selective etching of the material, the second gate structure, the retained isolation structure and the gate dielectric layer of the first gate structure located below the original second insulating layer can be anisotropically etched, and the etching stops at the gate electrode layer of the front transistor, that is, the etching stops at the gate metal surface of the front transistor. The second gate structure, the retained isolation structure and the first gate structure can also be anisotropically etched, and the etching stops inside the gate metal of the front transistor. Therefore, the gate structure of the front transistor can be connected to the gate structure of the back transistor through the interconnection structure.

[0106] In some embodiments, after forming the interconnect structure, a second metal interconnect layer may be formed on the second transistor and the interconnect structure.

[0107] In addition, in some embodiments, before forming the second source-drain metal of the second transistor, an interconnect structure may be formed first, and then the second source-drain metal and the second metal interconnect layer may be formed in sequence.

[0108] A method of forming interconnect structures on both the front and back sides is described below.

[0109] In some embodiments, before forming the second transistor, a first insulating layer is formed based on the first gate structure, and a first interconnection structure is formed by selectively etching the first insulating layer and the first gate structure in the first region; after forming the second gate structure, a second insulating layer is formed based on the second gate structure, and a second interconnection structure is formed by selectively etching the second insulating layer and the first gate structure in the first region, and the first interconnection structure and the second interconnection structure constitute an interconnection structure.

[0110] In some embodiments, the process of forming the first interconnect structure may be: forming a first mask on the first insulating layer, the first mask exposing the first region; based on the first mask, selectively etching the first insulating layer, the first gate structure, and a portion of the isolation structure to form a first groove; filling the first groove with a metal material to form the first interconnect structure. The method of forming the first interconnect structure may refer to the above-mentioned content related to forming the interconnect structure on the front side, which will not be repeated here.

[0111] In some embodiments, the process of forming the second interconnect structure may be: forming a second mask on the second insulating layer, the second mask exposing the first region; based on the second mask, selectively etching the second insulating layer, the second gate structure and the retained isolation structure to form a second groove; filling the second groove with a metal material to form the second interconnect structure. The method of forming the second interconnect structure may refer to the above-mentioned content related to forming the interconnect structure on the back side, which will not be described in detail here.

[0112] In some embodiments, the first interconnect structure may contact the second interconnect structure at the isolation structure, so when etching to form the first interconnect structure and / or the second interconnect structure, the isolation structure between the first gate structure and the second gate structure may be etched to make the first interconnect structure contact the second interconnect structure. For example, when forming the first interconnect structure, the first gate structure and the isolation structure may be etched, or when forming the second interconnect structure, the second gate structure and the isolation structure may be etched, or when forming the first interconnect structure and forming the second interconnect structure, a portion of the isolation structure may be etched to make the finally formed first interconnect structure contact the second interconnect structure at the isolation structure, and the embodiments of the present application do not specifically limit this.

[0113] In some embodiments, after forming the first interconnect structure, the operations of step S130 and step S140 may be performed, and then before forming the second metal interconnect layer, the second interconnect structure may be formed, and then the second metal interconnect layer may be formed on the second interconnect structure and the second transistor.

[0114] In addition, the embodiment of the present application can also achieve isolation between flip-chip stacked transistors through a gate cut structure, that is, perform gate cut processing on the flip-chip stacked transistors.

[0115] In some embodiments, after forming a first gate structure of a first transistor and / or forming a second gate structure of a second transistor, a gate cut-off structure can be formed on both sides of the first gate structure and / or the second gate structure, and the gate cut-off structure is used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

[0116] It can be understood that the gate cut-off structure can be formed on the back transistor at one time, that is, after forming the gate structure of the back transistor, the first gate structure and the second gate structure are gate-cut to form the gate cut-off structure. It can also be formed on the front transistor at one time, that is, after forming the gate structure of the front transistor, the first gate structure and the isolation structure under the first gate structure are gate-cut to form the gate cut-off structure. It is also possible to gate-cut the gate structure of the front transistor and the gate structure of the back transistor after they are formed, respectively, to form the first gate cut-off structure and the second gate cut-off structure, and the first gate cut-off structure and the second gate cut-off structure constitute the gate cut-off structure.

[0117] In some embodiments, after forming the gate structure, the gate structure may be cut off at both ends along the extension direction to form two grooves, and then the two grooves are filled with insulating material to form a gate cut-off structure, and the gate cut-off structure is located on both sides of the active structure. In the case where there is an insulating layer (a first insulating layer and a second insulating layer), the gate cut-off structure is also located on both side edges of the insulating layer.

[0118] In an embodiment of the present application, an active structure including a first active structure and a second active structure is formed on a substrate, a first transistor is formed based on the first active structure, the first transistor is flipped, and a second transistor is formed based on the exposed second active structure. Before forming the second transistor, a first insulating layer is formed based on the first gate structure of the first transistor, and the first insulating layer and the first gate structure are selectively etched in the first region to form an interconnection structure, and / or, after forming the second gate structure of the second transistor, a second insulating layer is formed based on the second gate structure, and the second insulating layer and the second gate structure are selectively etched in the first region to form an interconnection structure. Therefore, in an embodiment of the present application, an interconnection structure is formed after the front and back transistors are formed, which can reduce the metal blockage problem during the filling process and reduce the resistance of the interconnection structure inside the flip-chip stacked transistor. At the same time, the insulating layer and the gate structure are etched on the front and / or back of the transistor by the selectivity of the material to form an interconnection structure, and the gate region does not need to be etched by photolithography, which can reduce the requirements of photolithography for gate interconnection.

[0119] The gate interconnection method of the flip-chip stacked transistor provided in the embodiment of the present application is described below by taking the active structure in the flip-chip stacked transistor as a fin structure as an example. Figure 2This is a schematic top view of the flip-stacked transistor in the embodiment of the present application. It should be noted that, for ease of understanding, the top view only shows the fin structure, the gate structure, the source-drain structure and the first region, and the first region is the region where the interconnection structure is located. Among them, the A-A' direction is the cross-sectional direction of the flip-stacked transistor along the gate structure; the B-B' direction is the cross-sectional direction of the flip-stacked transistor along the source-drain structure; the C-C' direction is the cross-sectional direction of the flip-stacked transistor along the fin structure, and the D-D' direction is the cross-sectional direction of the flip-stacked transistor along the first region.

[0120] The following describes the preparation process of forming the interconnect structure on the back side transistor in one step. Figures 3 to 16 is a schematic diagram of a flip-chip stacked transistor during the preparation process in an embodiment of the present application, Fig.17 It is a structural diagram of a flip-chip stacked transistor in an embodiment of the present application. It should be noted that the different steps (i.e., different processes) in the following examples can be respectively represented by the A-A' direction, the B-B' direction, the C-C' direction, the D-D' direction, or different combinations of the above four directions according to the changes in the structure to demonstrate the preparation process of the flip-chip stacked transistor 10.

[0121] In one example, the process of preparing the flip-chip stack transistor 10 may include the following steps:

[0122] Step 1: Prepare the front transistor 11 according to the standard process flow to obtain Figure 3 The structure shown.

[0123] It can be understood that first, the fin is formed on the substrate 20 by a standard method to form a fin structure 21, and then an oxide material is deposited on the substrate 20 to form an isolation structure 22. The isolation structure 22 wraps the portion of the fin structure close to the substrate 20, that is, the second fin structure 121 (the second active structure), and exposes the portion of the fin structure away from the substrate 20, that is, the first fin structure 111 (the first active structure). Then, polysilicon material is deposited in the gate region of the substrate 20 to form a first dummy gate structure, and a first sidewall (spacer) 23 is formed on the sidewall of the first dummy gate structure, and a first source and drain structure 112 is formed based on the epitaxial growth of the first fin structure at the source and drain region, and an interlayer dielectric is deposited on the first source and drain structure 112 to form a first interlayer dielectric layer 113. Then, the first dummy gate structure is removed, a first gate structure 114 is formed in the gate region, and a first source and drain metal 115 is formed on the first source and drain structure 112. Among them, the first gate structure 114 includes a first gate dielectric layer and a first gate electrode layer formed on the first fin structure.

[0124] Step 2: Selectively etch the first gate structure 114 to a preset height so that the upper surface of the first gate structure 114 is slightly lower than the first spacer 23, and the following is obtained: Figure 4The structure shown.

[0125] Step 3: Deposit an insulating material on the etched first gate structure 114 and perform CMP to form a first insulating layer 24. Figure 5 The structure shown.

[0126] In some embodiments, the insulating material forming the first insulating layer is different from the material forming the first interlayer dielectric layer. For example, the insulating material forming the first insulating layer may be SiN.

[0127] Step 4: Complete the back-end process of the front transistor to form the first metal interconnect layer 116, and obtain Figure 6 The structure shown.

[0128] It can be understood that the first metal interconnection layer can be formed by performing back-end processes (such as dielectric deposition between interconnection lines, metal line formation, lead pad formation, etc.) on the front transistor.

[0129] Step 5: Deposit oxide on the first metal interconnect layer 116 to form a third insulating layer 25. Bond the carrier wafer 26 to the third insulating layer 25 above the third insulating layer 25, and then flip the wafer to obtain the following: Figure 7 The structure shown.

[0130] Step 6: deposit polysilicon material in the exposed gate region, and form a second dummy gate structure 27 by photolithography and etching, so as to obtain Figure 8 The structure shown.

[0131] It is understandable that before forming the second dummy gate structure 27, the Figure 7 In the structure shown, the substrate 20 and the isolation structure 22 are exposed to a certain depth to expose the second fin structure 121 (second active structure), and then a second dummy gate structure 27 is formed on the exposed gate region.

[0132] Step 7: forming a second spacer 28 on the sidewall of the second dummy gate structure 27, and forming a second source-drain structure 122 based on the second fin-shaped structure at the source-drain region, and depositing an interlayer dielectric on the second source-drain structure 122 to form a second interlayer dielectric layer 123, so as to obtain Fig. 9 The structure shown.

[0133] Step 8: Remove the second dummy gate structure 27 and form a second gate structure 124 in the gate region to obtain Fig.10 The structure shown.

[0134] It can be understood that the second gate structure 124 includes a second gate dielectric layer and a second gate metal layer formed on the second fin structure.

[0135] Step 9: Selectively etch the second gate structure 124 to a preset height so that the upper surface of the second gate structure 124 is slightly lower than the second sidewall 28, and the following is obtained: Fig.11 The structure shown.

[0136] Step 10: Deposit an insulating material on the etched second gate structure 124 and perform CMP to form a second insulating layer 29. Fig.12 The structure shown.

[0137] Step 11: Form a second mask 30 on the second transistor, the second mask exposes the area where the interconnection structure is located (the first area), that is, photolithography forms a gate merge groove, and then selectively etches the second insulating layer 29 of the material, the gatemerge groove is automatically aligned to the gate area, so as to obtain a groove 31 formed by etching the insulating layer, and obtain the following Fig.13 The structure shown.

[0138] like Fig.13 As shown in (c), due to the selectivity of the material, etching will only etch the second insulating layer, and will not etch the second sidewall and source / drain region next to the second insulating layer. Therefore, the first region exposed by the second mask 30 can be set larger.

[0139] Step 12: Etch the second gate structure 124 and the isolation structure 22 and a portion of the first gate structure 114 to form a second groove 32, and obtain Fig.14 The structure shown.

[0140] like Fig.14 As shown in (a) and (c), the etching stops at the inside of the gate metal of the first transistor. In some embodiments, the etching can also stop at the surface of the gate metal of the first transistor.

[0141] Step 13: Remove the second mask 30 to obtain Fig.15 The structure shown.

[0142] Step 14: Fill the etched second groove 32 with metal material to form an interconnection structure 33, and obtain Fig.16 The structure shown.

[0143] It can be understood that the interconnect structure 33 connects the gate structure of the back transistor with the gate structure of the front transistor.

[0144] Step 15: Form the second source-drain metal 125 and the second metal interconnection layer 126 to obtain Fig.17 The structure shown.

[0145] It should be noted that the above is an introduction to the structure of the flip-chip stacked transistor provided by the present application by taking the fin field effect transistor as an example. The preparation method in the embodiment of the present application can also be applied to the stacking of transistors in various forms such as full-surround gate transistors, planar transistors, vertical field effect transistors, fork-shaped transistors, etc., which are not shown in the drawings in the embodiment of the present application.

[0146] In an embodiment of the present application, an active structure including a first active structure and a second active structure is formed on a substrate, a first transistor is formed based on the first active structure, the first transistor is flipped, and a second transistor is formed based on the exposed second active structure, and then an interconnection structure is formed in a first region between the active structure and a boundary on one side of the flip-chip stacked transistor to connect the first gate structure of the first transistor with the second gate structure of the second transistor. Therefore, in an embodiment of the present application, an interconnection structure is formed after the front and back transistors are formed, which can reduce the metal blockage problem during the filling process and reduce the resistance of the interconnection structure inside the flip-chip stacked transistor.

[0147] Furthermore, the flip-chip stacked transistor provided in the embodiment of the present application can be detected using a detection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscope (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the structure of the flip-chip stacked transistor.

[0148] The present application provides a semiconductor device, including: a flip-chip stacked transistor as in the above embodiment. The specific definition of the flip-chip stacked transistor can be found in the above flip-chip stacked transistor, which will not be described in detail here.

[0149] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device being arranged on the circuit board. The semiconductor device includes the above flip-chip stacked transistor. The specific definition of the flip-chip stacked transistor can be referred to the above flip-chip stacked transistor, which will not be described in detail here.

[0150] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0151] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A gate interconnection method for flip-chip stacked transistors, characterized in that: include: forming an active structure on a substrate, the active structure comprising a first active structure and a second active structure, wherein the first active structure is farther away from the substrate than the second active structure; Based on the first active structure, forming a first transistor, wherein the first transistor includes a first gate structure; Flipping the first transistor and exposing the second active structure; Based on the second active structure, forming a second transistor, wherein the second transistor includes a second gate structure; Before forming the second transistor, a first insulating layer is formed based on the first gate structure, and the first insulating layer and the first gate structure are selectively etched in the first region to form an interconnection structure; And / or, after forming the second gate structure, a second insulating layer is formed based on the second gate structure, and the second insulating layer and the second gate structure are selectively etched by material in the first region to form an interconnection structure, wherein the interconnection structure is used to connect the first gate structure and the second gate structure, and the first region is located between the active structure and the boundary on one side of the gate region.

2. The method according to claim 1, characterized in that Before forming the first transistor, the method further includes: forming an isolation structure surrounding the second active structure on the substrate to expose the first active structure; The method of forming an interconnect structure by selectively etching the first insulating layer and the first gate structure in the first region includes: forming a first mask on the first insulating layer, wherein the first mask exposes the first region; Based on a first mask, the first insulating layer, the first gate structure, and a portion of the isolation structure are selectively etched to form a first groove; The first groove is filled with metal material to form the interconnection structure.

3. The method according to claim 1, characterized in that Before forming the first transistor, the method further includes: forming an isolation structure surrounding the second active structure on the substrate to expose the first active structure; The exposing the second active structure comprises: removing the substrate; Thinning the isolation structure to a predetermined height to expose the second active structure; The method of forming an interconnect structure by selectively etching the second insulating layer and the second gate structure in the first region includes: forming a second mask on the second insulating layer, wherein the second mask exposes the first region; Based on the second mask, the second insulating layer, the second gate structure and the reserved isolation structure are etched to the first gate structure by material selectivity to form a second groove; The second groove is filled with metal material to form the interconnection structure.

4. The method according to claim 1, characterized in that: The step of forming a first insulating layer based on the first gate structure includes: Etching the first gate structure to a preset height, and forming the first insulating layer on the etched first gate structure; The forming of a second insulating layer based on the second gate structure includes: The second gate structure is etched to a preset height, and the second insulating layer is formed on the etched second gate structure.

5. The method according to claim 4, characterized in that The forming of the first insulating layer on the etched first gate structure comprises: Depositing an insulating material on the etched first gate structure to form the first insulating layer, wherein the upper surface of the first insulating layer is flush with the upper surface of the first sidewall spacer, and the first sidewall spacer is located on both sides of the first gate structure; The forming of the second insulating layer on the etched second gate structure comprises: An insulating material is deposited on the etched second gate structure to form the second insulating layer, wherein the upper surface of the second insulating layer is flush with the upper surface of the second sidewall spacer, and the second sidewall spacer is located on both sides of the second gate structure.

6. The method according to claim 1, characterized in that The method further comprises: A gate cut-off structure is formed on both sides of the first gate structure and / or the second gate structure, and the gate cut-off structure is used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

7. A flip-chip stack transistor, manufactured using the gate interconnection method according to any one of claims 1 to 6, characterized in that: include: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged opposite to each other; An interconnect structure is used to connect a first gate structure of the first transistor and a second gate structure of the second transistor.

8. The flip-chip stack transistor according to claim 7, characterized in that: The flip-chip stack transistor further comprises: A gate cut-off structure, located at both sides of the first gate structure and / or the second gate structure, is used to isolate the gate region of the flip-chip stacked transistor from the gate region of an adjacent flip-chip stacked transistor.

9. A semiconductor device, characterized in that: include: A flip-chip stack transistor as claimed in claim 7 or 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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