Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method thereof. The preparation method comprises the following steps: S1, cleaning and polishing a substrate silicon wafer; s2, forming a dielectric region and a polycrystalline silicon layer; s3, forming a dopant source layer of the first conductive type impurities; s4, one-step co-doping of impurities of different conductive types; s5, forming a dielectric layer; s6, metallization is carried out; the thickness of the dopant source layer of the first conductive type impurities is 10 nm to 100 nm. According to the invention, the dopant source layer of the first conductive type impurities is formed firstly, so that the high-temperature doping times and cleaning times are reduced, the doping temperature is reduced, the process time is shortened, the process flow is simplified, the equipment investment cost is reduced, and the internal composite action of the solar cell is reduced, thereby improving the photoelectric conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] TOPCon (Tunnel Oxide Passivated Contact) is a solar cell technology based on the principle of selective carriers and tunnel oxide passivation contact. Its cell structure is an N-type or P-type silicon substrate cell. An ultra-thin oxide layer is prepared on the back, and then a thin layer of doped silicon is formed. The two together form a passivation contact structure, which effectively reduces surface recombination and metal contact recombination.

[0003] There are currently two main production technology routes for TOPCon cells, namely LPCVD (Low Pressure Chemical Vapor Deposition) and PECVD (Plasma Enhanced Chemical Vapor Deposition). The conventional process preparation route for TOPCon cells includes the following steps: texturing - boron doping - removal of BSG (borosilicate glass) and alkali polishing - use LPCVD or PECVD to form a tunneling oxide layer and a Ploy layer - phosphorus doping - removal of BSG, PSG (phosphosilicate glass) and RCA (industry standard wet cleaning process) cleaning - ALD (atomic layer formation) - front and back anti-reflection film - metallization. The conventional process preparation routes of TOPCon batteries are limited by the different doping sources, temperatures and times of the P and N regions. Usually, boron doping is chosen before phosphorus doping. However, such a preparation route has the following shortcomings: 1. It is necessary to grow a thicker BSG before phosphorus doping, usually with a thickness greater than 100nm, to block alkali polishing and the alkali washing tank in the RCA. Then the thicker BSG will make the silicon wafer have a higher oxygen content and serious BO recombination, resulting in a decrease in photoelectric conversion efficiency and photoinduced degradation; 2. It needs to go through two high-temperature processes (phosphorus doping process and boron doping process) and two removal plating processes during the battery preparation process. The process is cumbersome, the process time is long, and the equipment investment cost is high; 3. Most of them adopt a single-insertion form, which reduces production capacity. Summary of the invention

[0004] The present invention aims at the above problems, makes up for the deficiencies of the prior art, and provides a solar cell and a preparation method to solve the problems arising from the above background technology.

[0005] A first aspect of the present invention provides a method for preparing a solar cell, comprising the following steps: S1 cleans and polishes the substrate silicon wafer; S2 forms a dielectric region and a polysilicon layer; S3 forming a dopant source layer of first conductivity type impurities; S4 co-doping of impurities of different conductivity types in one step; S5 forms a dielectric layer; S6 metallization; The thickness of the dopant source layer of the first conductive type impurities is 10 nm-100 nm.

[0006] Preferably, the thickness of the dopant source layer of the first conductive type impurities is 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm. More preferably, the thickness of the dopant source layer of the first conductive type impurities is 50nm-100nm.

[0007] In the present invention, the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm. When the thickness is less than 10nm, it cannot serve as a barrier layer for the second conductive type impurities, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency. When the thickness is greater than 100nm, the oxygen content of the silicon wafer will be high, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency and photoinduced degradation.

[0008] The dopant source layer of the first conductive type impurity needs to have a certain thickness, in order to ensure that the first doped region has sufficient doping concentration after a one-step co-doping, and to act as a mask layer to prevent the dopant material of the second conductive type impurity from being doped into the first doped region, while blocking the damage to polysilicon or c-Si caused by film opening; and the complete removal of the dopant source layer of the first doped conductive type impurity and the dopant source layer of the second doped conductive type impurity will be completely removed in the subsequent RCA cleaning step.

[0009] Preferably, the solar cell includes a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the back side of the substrate silicon wafer being sequentially provided with the dielectric region and the polysilicon layer in a direction away from the substrate silicon wafer, and the dopant source layer of the first conductive type impurities being located outside the polysilicon layer.

[0010] Preferably, the preparation method further includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer, or the texturing step forms a front texturing surface on the front side of the substrate silicon wafer and a back partial texturing surface on the back side, and the morphology and size of the front texturing surface and the back partial texturing surface are the same or different.

[0011] Preferably, the texturing step is performed before the dielectric region and the polysilicon layer are formed in S2, and the texturing step also includes a mask preparation step before the texturing step, and the mask step forms a mask layer on the back side of the substrate silicon wafer; or, the texturing step is performed after the dopant source layer of the first conductive type impurities is formed in S3.

[0012] Preferably, the substrate silicon wafer in S1 is N-type or P-type.

[0013] Preferably, the dopant source layer of the first conductive type impurity formed in S3 is formed by CVD at a temperature of 300°C-800°C for 1 min-90 min, and the raw materials include a boron source gas or a phosphorus source gas, and the boron source gas is BH 3 , TMB, BCl 3 , BBr 3 At least one of the above, the phosphorus source gas is PH 3 POCl 3 At least one of them.

[0014] Preferably, the forming raw material further comprises other gases, and the other gases are SiH 4 、N 2 O、NH 3 , Ar or more gases.

[0015] Preferably, in the step S3 of forming a dopant source layer of first conductive type impurities, the dopant source layer of the first conductive type impurities is a silicon-containing compound layer containing first conductive type impurities, and the first conductive type impurities are boron, gallium or phosphorus.

[0016] Preferably, in the one-step co-doping of different conductive type impurities in S4, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the one-step co-doping of different conductive type impurities is performed at least once.

[0017] Preferably, the doping source of the second conductive type impurity is a boron source gas or a phosphorus source gas, and the boron source gas is BH 3 , TMB, BCl 3 , BBr 3 At least one of the above, the phosphorus source gas is PH 3 POCl 3 At least one of them.

[0018] Preferably, the doping temperature of the S4 different conductive type impurities co-doped in one step is 600°C-1000°C, more preferably, the doping temperature is 600°C-980°C, and the doping time is 5min-180min, and the doping time does not include the time required for heating and cooling.

[0019] Preferably, after the S4 is co-doped with impurities of different conductive types in one step, it also includes laser selective doping, the wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, the frequency is 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped region of the conductive type impurity region.

[0020] Preferably, after the laser selective doping, the process further includes removing the dopant source layer of the first conductive type impurities, wherein the dopant source layer of the first conductive type impurities is removed by pickling with hydrofluoric acid having a concentration of 0.5%-50% for a pickling time of 10s-1200s.

[0021] The second aspect of the present invention further provides a solar cell, comprising a substrate silicon wafer; the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer and a front metal electrode; the back side of the substrate silicon wafer is provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer and a back metal electrode; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm; The second conductive type impurity region and the first conductive type impurity region are simultaneously formed in one or more different conductive type impurity one-step co-doping steps; In the step of co-doping impurities of different conductivity types, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the local area of ​​the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0022] Preferably, a second dielectric region is provided on the upper edge of the front velvet surface in a direction away from the substrate silicon wafer; a back local velvet surface and an edge velvet surface are provided on the lower edge of the first dielectric region in a direction close to the substrate silicon wafer, and a heavily doped region is also provided in the first conductive type impurity region and / or the second conductive type impurity region.

[0023] Preferably, the c-Si region is formed by film opening and cleaning, and the film opening method is at least one of laser, etching slurry, and photolithography; the polysilicon layer is formed by CVD (Chemical Vapor Deposition) deposition.

[0024] A second aspect of the present invention provides another solar cell, the solar cell comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer being provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside; the back side of the substrate silicon wafer being provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside; The local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity region; the local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0025] Compared with the prior art, the present invention has the following beneficial effects: The present invention reduces the number of high-temperature doping and cleaning times, lowers the doping temperature, shortens the process time, simplifies the process flow, reduces equipment investment costs, and reduces the internal recombination of solar cells, thereby improving the photoelectric conversion efficiency. Specifically, the present invention forms a doping source layer of the first conductive type impurity first, and when different conductive types of impurities are co-doped in one step, the formed doping source layer of the first conductive type impurity can be used as a doping source and also as a barrier layer when another element is doped, so that different conductive types of impurities are doped at high temperature in one step to form a first conductive type impurity region. Only one high-temperature doping is required for the second conductive type impurity region, thereby reducing the number of high-temperature doping times; since the present invention only has one step of co-doping, there is no need to form a thicker BSG layer to block alkali polishing and the alkali washing tank in the RCA before phosphorus doping, so the oxygen content of the silicon wafer is reduced, reducing the internal recombination of the solar cell and thus improving the photoelectric conversion efficiency; since the conventional production line route is boron doping first and then phosphorus doping, the boron doping temperature is as high as 1000°C, and high temperature is required to grow a thicker oxide layer and promote boron doping, while the preparation route of the present invention does not require the growth of a thicker oxide layer, eliminates the high-temperature boron doping process, simplifies the process flow, and reduces equipment investment costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of the TOPCon battery structure in Example 1; Figure 2 This is a process flow chart of TOPCon battery preparation in Example 1; Figure 3 This is a schematic diagram of the TOPCon battery structure in Example 9; Figure 4 This is a process flow chart of TOPCon battery preparation in Example 9 and Examples 15-16; Figure 5 This is a schematic diagram of the TOPCon battery structure in Example 15; Figure 6 Schematic diagram of the TOPCon battery structure in Example 16.

[0027] In the figure: 1-front metal electrode, 2-second dielectric layer, 3-second conductivity type impurity polysilicon layer, 4-N-type silicon wafer, 5-first tunneling oxide layer, 6-first conductivity type impurity polysilicon layer, 7-first dielectric layer, 8-back metal electrode, 9-second conductivity type impurity polysilicon layer heavily doped region, 10-second tunneling oxide layer, 11-second conductivity type impurity c-Si region, 12-first conductivity type impurity c-Si region, 13-first conductivity type impurity polysilicon layer heavily doped region. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0029] This embodiment provides a method for preparing a solar cell, comprising the following steps: S1 cleans and polishes the substrate silicon wafer; S2 forms a dielectric region and a polysilicon layer; S3 forming a dopant source layer of first conductivity type impurities; S4 co-doping of impurities of different conductivity types in one step; S5 forms a dielectric layer; S6 metallization; The thickness of the dopant source layer of the first conductive type impurities is 10 nm-100 nm.

[0030] The present invention reduces the number of high-temperature doping and cleaning times, lowers the doping temperature, shortens the process time, simplifies the process flow, reduces equipment investment costs, and reduces the internal recombination of solar cells, thereby improving the photoelectric conversion efficiency. Specifically, the present invention forms a doping source layer of the first conductive type impurity first, and when different conductive types of impurities are co-doped in one step, the formed doping source layer of the first conductive type impurity can be used as a doping source and also as a barrier layer when another element is doped, so that different conductive types of impurities are doped at high temperature in one step to form a first conductive type impurity region. and the second conductive type impurity region, only one high-temperature doping is performed, thereby reducing the number of high-temperature doping times; since the present invention only has one step of co-doping, there is no need to form a thicker BSG layer to block alkali polishing and the alkali washing tank in the RCA before phosphorus doping, so the oxygen content of the silicon wafer is reduced, reducing the internal recombination of the solar cell and thus improving the photoelectric conversion efficiency; since the conventional production line route is to dope boron first and then dope phosphorus, the boron doping temperature is as high as 1000°C, and high temperature is required to grow a thicker oxide layer and promote boron doping, while the preparation route of the present invention does not require the growth of a thicker oxide layer, thereby eliminating the high-temperature boron doping process, simplifying the process flow, and reducing equipment investment costs.

[0031] As a preferred embodiment, the thickness of the dopant source layer of the first conductive type impurity is 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm. More preferably, the thickness of the dopant source layer of the first conductive type impurity is 50nm-100nm.

[0032] In the present invention, the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm. When the thickness is less than 10nm, it cannot serve as a barrier layer for the second conductive type impurities, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency. When the thickness is greater than 100nm, the oxygen content of the silicon wafer will be high, and serious recombination will occur, resulting in a decrease in photoelectric conversion efficiency and photoinduced degradation.

[0033] The dopant source layer of the first conductive type impurity needs to have a certain thickness, in order to ensure that the first doped region has sufficient doping concentration after a one-step co-doping, and to act as a mask layer to prevent the dopant material of the second conductive type impurity from being doped into the first doped region, while blocking the damage to polysilicon or c-Si caused by film opening; and the complete removal of the dopant source layer of the first doped conductive type impurity and the dopant source layer of the second doped conductive type impurity will be completely removed in the subsequent RCA cleaning step.

[0034] As a preferred embodiment, the solar cell includes a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the back side of the substrate silicon wafer being sequentially provided with the dielectric region and the polysilicon layer in a direction away from the substrate silicon wafer, and the dopant source layer of the first conductive type impurities being located outside the polysilicon layer.

[0035] As a preferred embodiment, the preparation method also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer, or the texturing step forms a front texturing surface on the front side of the substrate silicon wafer and a back partial texturing surface on the back side, and the morphology and size of the front texturing surface and the back partial texturing surface are the same or different.

[0036] As a preferred embodiment, the texturing step is performed before the dielectric region and the polysilicon layer are formed in S2, and the texturing step also includes a mask preparation step before the texturing step, and the mask step forms a mask layer on the back side of the substrate silicon wafer; or, the texturing step is performed after the dopant source layer of the first conductive type impurities is formed in S3.

[0037] As a preferred embodiment, a mask layer is formed by CVD. In a CVD furnace tube, a mask layer is formed on the back of a silicon wafer through chemical reaction and plasma reaction. The mask layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and its thickness is 10nm-100nm.

[0038] As a preferred embodiment, the texturing is performed by etching with one or more of 0.5 wt%-2wt% KOH and NaOH, and the etching time is 400s-600s.

[0039] As a preferred embodiment, the texturing step further includes a film opening step, and the film opening adopts at least one of laser, etching slurry, and photolithography. More preferably, laser film opening is adopted, and the parameters of laser film opening are set as follows: wavelength 355nm-1064nm, power ≥1W, scanning speed 5m / s-50m / s, frequency 200kHz-2000kHz, and the film opening step forms a c-Si region.

[0040] As a preferred implementation, the substrate silicon wafer in S1 is N-type or P-type, has a resistivity of 0.1 Ωcm-3.0 Ωcm, and a thickness of 100 μm-200 μm.

[0041] As a preferred implementation, the cleaning and polishing in S1 utilizes acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and performs etching and polishing on the surface of the single crystal silicon wafer.

[0042] As a preferred embodiment, the dielectric region and the polysilicon layer are formed by CVD in S2. 2 O is used as the oxidant, the oxidation temperature is 300℃-650℃, the time is 60s-600s, and a tunneling oxide layer is formed with a thickness of 1 nm-3nm; SiH 4 The reaction gas is Ar and the diluent gas is Ar. The formation temperature is 300-650°C and the time is 300s-3600s. A polysilicon layer with a thickness of 50 nm-400nm is formed on the surface of the tunnel oxide layer. The CVD method is PECVD or LPCVD.

[0043] As a preferred embodiment, the dopant source layer of the first conductive type impurity is formed by CVD at a temperature of 300°C-800°C for 1 min-90 min, and the raw materials include a boron source gas or a phosphorus source gas, wherein the boron source gas is BH 3 , TMB, BCl 3 , BBr 3 At least one of the above, the phosphorus source gas is PH 3 POCl 3 At least one of the CVD methods is PECVD or LPCVD.

[0044] As a preferred embodiment, the forming raw material further comprises other gases, and the other gases are SiH 4 、N 2 O、NH 3 , Ar or more gases.

[0045] As a preferred implementation, the dopant source layer of the first conductive type impurity in S3 is a silicon-containing compound layer containing first conductive impurities, and the first conductive impurities are boron, gallium or phosphorus.

[0046] As a preferred embodiment, the S4 different conductive type impurities are co-doped in one step, the silicon wafer is placed in a doping tube for doping, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used, and the doping temperature is 600℃-1000℃. As a more preferred embodiment, the doping temperature is 600℃-980℃, and the doping time is 5min-180min. The doping source layer of the first conductive type impurity formed on the back of the silicon wafer can be used as a doping source and as a barrier layer for doping with another element during doping, so that the first conductive type impurities and the second conductive type impurity regions are doped at high temperature in one step to form a first conductive type impurity region and a second conductive type impurity region. The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the number of times the different conductive type impurities are co-doped in one step is at least once.

[0047] As a preferred embodiment, the doping source of the second conductive type impurity is a boron source gas or a phosphorus source gas, and the boron source gas is BH 3 , TMB, BCl 3 , BBr 3 At least one of the above, the phosphorus source gas is PH 3 POCl 3 At least one of them.

[0048] As a preferred embodiment, after the S4 is co-doped with impurities of different conductive types in one step, it also includes laser selective doping, and the wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, and the frequency is 200kHz-2000kHz. The laser selective doping obtains a local heavily doped area of ​​the conductive type impurity area.

[0049] As a preferred embodiment, after the laser selective doping, the process also includes removing the dopant source layer of the first conductive type impurities, wherein the dopant source layer of the first conductive type impurities is removed by pickling with hydrofluoric acid at a concentration of 0.5%-50% for a pickling time of 10s-1200s; and then the silicon wafer is cleaned according to RCA standards to remove surface contaminants.

[0050] As a preferred embodiment, S5 forms a dielectric layer, which is at least composed of an anti-reflection film, and a 50 nm-120 nm anti-reflection film layer is formed by CVD. The reflective film layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0051] As a preferred implementation, the dielectric layer further includes a passivation film layer, the thickness of the passivation film layer is 2-15 nm, and the passivation film layer is aluminum oxide.

[0052] As a preferred implementation, the S6 metallization is to provide a front metal electrode and a back metal electrode on the silicon wafer, wherein the metal electrode is preferably a silver electrode, to obtain the solar cell structure.

[0053] As a preferred implementation, the forming of the polysilicon layer in S2, the forming of the dopant source layer of the first conductive type impurities in S3, the doping in S4 and the forming of the dielectric layer in S5 are dual insertion mode.

[0054] Since many working sections of the present invention are changed from a single-insertion mode to a double-insertion mode, production costs are saved, output is increased, and large-scale production is facilitated.

[0055] This embodiment also provides a solar cell, comprising a substrate silicon wafer; the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer and a front metal electrode; the back side of the substrate silicon wafer is provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer and a back metal electrode; The first dielectric region is a first tunneling oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm; The second conductive type impurity region and the first conductive type impurity region are simultaneously formed in one or more different conductive type impurity one-step co-doping steps; In the step of co-doping impurities of different conductivity types, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the local area of ​​the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0056] As a preferred embodiment, a second dielectric region is further arranged on the upper edge of the front velvet surface in a direction away from the substrate silicon wafer; a back local velvet surface and an edge velvet surface are further arranged on the lower edge of the first dielectric region in a direction close to the substrate silicon wafer, and a heavily doped region is also arranged in the first conductive type impurity region and / or the second conductive type impurity region.

[0057] As a preferred embodiment, the c-Si region is formed by film opening and cleaning, and the film opening method is at least one of laser, etching slurry, and photolithography; the polysilicon layer is formed by CVD deposition.

[0058] This embodiment also provides another solar cell structure, the solar cell includes a substrate silicon wafer, the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is sequentially provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer, and a front metal electrode from the inside to the outside; the back side of the substrate silicon wafer is sequentially provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer, and a back metal electrode from the inside to the outside; The local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity region; the local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0059] The solar cell and the preparation method thereof of the present invention are further described below through specific examples and comparative examples.

[0060] Example 1 like Figure 1 As shown, an N-type TOPCon battery includes an N-type silicon wafer 4, the N-type silicon wafer 4 is a substrate silicon wafer, and the front side of the N-type silicon wafer 4 is sequentially provided with a second conductive type impurity polysilicon layer 3, a second dielectric layer 2, and a front metal electrode 1 from the inside to the outside; the back side of the N-type silicon wafer 4 is sequentially provided with a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer 6, a first dielectric layer 7, and a back metal electrode 8 from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0061] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0062] like Figure 2 As shown, the method for preparing the N-type TOPCon battery in this embodiment includes the following steps: ① Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0063] ② In the PECVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 500°C, the time was 300s, and the first tunneling oxide layer with a thickness of 3nm was formed on the back of the silicon wafer; SiH 4 As the reaction gas, Ar as the diluent gas, the formation temperature is 500°C, the time is 1800s, and a polysilicon layer with a thickness of 250nm is formed on the surface of the first tunnel oxide layer.

[0064] ③ In the PECVD furnace tube, PH 3 、SiH 4 、N 2 O, Ar, NH 3 As raw material, the forming temperature is 600°C, the time is 50min, and a phosphorus-containing silicon oxide layer with a thickness of 50nm is formed on the polysilicon layer.

[0065] ④ Use 1.3% NaOH solution for etching for 500s to form a front pyramid velvet surface on the front side of the silicon wafer (not shown in the figure).

[0066] ⑤ Place the silicon wafer into a boron doping tube for boron-phosphorus co-doping. The doping temperature is 800°C, the doping time is 100 minutes, and the boron doping source is BBr 3 The second conductive type impurity polysilicon layer is formed on the front side of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back side can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a barrier layer for boron doping. The number of boron and phosphorus co-doping in one step is 2 times.

[0067] ⑥ Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0068] ⑦ Using ALD atomic layer formation method, TMA is used as a precursor, and the reaction temperature is controlled at 300℃ to form a dense Al layer on the front and back of the silicon wafer. 2 O 3The passivation layer has a thickness of 8 nm, and an 80 nm SiNx anti-reflection layer is formed on the front and back surfaces of the silicon wafer by LPCVD. The passivation layer and the anti-reflection layer form a dielectric layer.

[0069] ⑧ Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0070] Example 2 An N-type TOPCon battery, comprising an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a heavily doped region of the second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0071] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0072] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: ① Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0073] ② In the LPCVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 500°C, the time was 300s, and the first tunneling oxide layer with a thickness of 3nm was formed on the back of the silicon wafer; SiH 4 As the reaction gas, Ar as the diluent gas, the formation temperature is 500°C, the time is 1800s, and a polysilicon layer with a thickness of 250nm is formed on the surface of the first tunnel oxide layer.

[0074] ③ In the LPCVD furnace tube, PH 3 、SiH 4 、N 2 O, Ar, NH 3 As raw material, the forming temperature is 600°C, the time is 50min, and a phosphorus-containing silicon oxide layer with a thickness of 50nm is formed on the polysilicon layer.

[0075] ④ Use 1.3% NaOH solution for etching for 500s to form a front pyramid velvet surface on the front side of the silicon wafer (not shown in the figure).

[0076] ⑤ Place the silicon wafer into a boron doping tube for boron-phosphorus co-doping. The doping temperature is 950°C, the doping time is 100 minutes, and the boron doping source is BBr 3 , a second conductive type impurity polysilicon layer is formed on the front of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a boron-doped barrier layer. The number of boron-phosphorus co-doping steps is 2 times. During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms the second conductive type impurity polysilicon.

[0077] ⑥ Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0078] ⑦ Using ALD atomic layer formation method, TMA is used as a precursor, and the reaction temperature is controlled at 300℃ to form a dense Al layer on the front and back of the silicon wafer. 2 O 3 The passivation layer has a thickness of 8 nm, and an 80 nm SiNx anti-reflection layer is formed on the front and back surfaces of the silicon wafer by LPCVD. The passivation layer and the anti-reflection layer form a dielectric layer.

[0079] ⑧ Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0080] Example 3 An N-type TOPCon battery, comprising a polished N-type silicon wafer, wherein a front velvet surface, a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the polished N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the polished N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0081] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0082] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: ① Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0083] ②In the LPCVD furnace, a mask layer is formed on the back of the silicon wafer through chemical reaction and plasma reaction; the mask layer is SiO 2 , and its thickness is 100nm.

[0084] ③ Use 1.3% NaOH solution for etching for 500s to form a front pyramid velvet surface on the front of the silicon wafer.

[0085] ④ In the PECVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 500°C, the time was 300s, and the first tunneling oxide layer with a thickness of 3nm was formed on the back of the silicon wafer; SiH 4 As the reaction gas, Ar as the diluent gas, the formation temperature is 500°C, the time is 1800s, and a polysilicon layer with a thickness of 250nm is formed on the surface of the first tunnel oxide layer.

[0086] ⑤ In the LPCVD furnace tube, PH 3 、SiH 4 、N 2 O, Ar, NH 3 As raw material, the forming temperature is 600°C, the time is 50min, and a phosphorus-containing silicon oxide layer with a thickness of 50nm is formed on the polysilicon layer.

[0087] ⑥ Place the silicon wafer into a boron doping tube for boron-phosphorus co-doping. The doping temperature is 800°C, the doping time is 100 minutes, and the boron doping source is BBr 3 The second conductive type impurity polysilicon layer is formed on the front side of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back side can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a barrier layer for boron doping. The number of boron and phosphorus co-doping in one step is 2 times.

[0088] ⑦ Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0089] ⑧ Use LPCVD to form an 80nm SiNx anti-reflection layer on the front and back of the silicon wafer, and the passivation layer and the anti-reflection layer form a dielectric layer.

[0090] ⑨ Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0091] Example 4 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0092] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 10 nm.

[0093] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: ① Select a P-doped N-type silicon wafer with a resistivity of 0.1Ωcm and a thickness of 100μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0094] ② In the PECVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 300°C, the time was 600s, and the first tunneling oxide layer with a thickness of 2nm was formed on the back of the silicon wafer; SiH 4 As the reaction gas, Ar as the diluent gas, the formation temperature is 300°C, the time is 3600s, and a polysilicon layer with a thickness of 50nm is formed on the surface of the first tunnel oxide layer.

[0095] ③In the PECVD furnace tube, POCl, SiH 4 、N 2 O, Ar, NH 3 As raw material, the forming temperature is 300°C, the time is 5 minutes, and a phosphorus-containing silicon oxide compound layer with a thickness of 10nm is formed on the polysilicon layer.

[0096] ④ Use 0.5% NaOH solution for etching for 600s to form a pyramid velvet surface on the front side of the silicon wafer.

[0097] ⑤ Place the silicon wafer into a boron doping tube for boron-phosphorus co-doping. The doping temperature is 600°C, the doping time is 180 minutes, and the boron doping source is BBr 3The second conductive type impurity polysilicon layer is formed on the front side of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back side can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a barrier layer for boron doping. The number of boron-phosphorus co-doping in one step is 4 times.

[0098] ⑥ Place the silicon wafer in 0.5% HF for pickling for 1200s to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0099] ⑦ Using ALD atomic layer formation method, TMA is used as a precursor, and the reaction temperature is controlled at 300℃ to form a dense Al layer on the front and back of the silicon wafer. 2 O 3 The passivation layer has a thickness of 2 nm, and a 50 nm SiNx anti-reflection layer is formed on the front and back surfaces of the silicon wafer by LPCVD. The passivation layer and the anti-reflection layer form a dielectric layer.

[0100] ⑧ Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0101] Example 5 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0102] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 100 nm.

[0103] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: ① Select a P-doped N-type single crystal silicon wafer with a resistivity of 3Ωcm and a thickness of 200μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0104] ② In the LPCVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 650°C, the time was 60s, and the first tunneling oxide layer with a thickness of 4nm was formed on the back of the silicon wafer; SiH 4As the reaction gas, Ar as the diluent gas, the formation temperature is 650°C, the time is 300s, and a polysilicon layer with a thickness of 400nm is formed on the surface of the first tunnel oxide layer.

[0105] ③ In the LPCVD furnace tube, PH 3 、SiH 4 、N 2 O, Ar, NH 3 As raw material, the forming temperature is 800°C, the time is 90min, and a phosphorus-containing silicon oxide compound layer with a thickness of 100nm is formed on the polycrystalline silicon layer.

[0106] ④ Use 2% NaOH solution for etching for 400s to prepare a pyramid velvet surface on the front side of the silicon wafer.

[0107] ⑤ Place the silicon wafer into a boron doping tube for boron-phosphorus co-doping. The doping temperature is 1000°C, the doping time is 5 minutes, and the boron doping source is BBr 3 The second conductive type impurity polysilicon layer is formed on the front side of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back side can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a barrier layer for boron doping. The number of boron-phosphorus co-doping in one step is 1.

[0108] ⑥ Place the silicon wafer in 50% HF for pickling for 10 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0109] ⑦ Using ALD atomic layer formation method, TMA is used as a precursor, and the reaction temperature is controlled at 300℃ to form a dense Al layer on the front and back of the silicon wafer. 2 O 3 The passivation layer has a thickness of 15 nm, and a 120 nm SiNx anti-reflection layer is formed on the front and back surfaces of the silicon wafer by LPCVD. The passivation layer and the anti-reflection layer form a dielectric layer.

[0110] ⑧ Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0111] Example 6 A P-type TOPCon cell, comprising a P-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the P-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the P-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0112] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0113] The preparation method of this embodiment is different from that of embodiment 1 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③BH 3 、SiH 4 、N 2 O, Ar, NH 3 As raw materials, a boron-containing silicon oxide layer with a thickness of 50nm is formed; ⑤ Place the silicon wafer into a phosphorus-doped tube for boron-phosphorus co-doping. The doping temperature is 800°C, the doping time is 100 minutes, and the phosphorus doping source is POCl 3 , forming a second conductive type impurity polysilicon layer on the front side of the silicon wafer; the boron-containing silicon oxide compound layer on the back side can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a phosphorus-doped barrier layer; The rest are the same.

[0114] Example 7 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0115] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 8 nm.

[0116] The preparation method of this embodiment is different from that of embodiment 4 in that: ③ A phosphorus-containing silicon oxide layer with a thickness of 8 nm formed; The rest are the same.

[0117] Example 8 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0118] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 103 nm.

[0119] The preparation method of this embodiment is different from that of embodiment 5 in that: ③ The phosphorus-containing silicon oxide layer formed in the step has a thickness of 103 nm; The rest are the same.

[0120] Example 9 like Figure 3 As shown, an N-type TOPCon battery includes an N-type silicon wafer 4, wherein a second conductive type impurity c-Si region 11, a second dielectric layer 2, a second tunneling oxide layer 10, a second conductive type impurity polysilicon layer heavily doped region 9, and a front metal electrode 1 are sequentially arranged on the front side of the N-type silicon wafer 4 from the inside to the outside; a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer 6, a first dielectric layer 7, and a back metal electrode 8 are sequentially arranged on the back side of the N-type silicon wafer 4 from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0121] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0122] like Figure 4 As shown, the preparation method of this embodiment is different from that of embodiment 1 in that: ② In the PECVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 500°C, the time was 300s, and the second tunneling oxide layer and the first tunneling oxide layer were formed on the front and back of the silicon wafer, respectively, with a thickness of 3nm; SiH 4As the reaction gas, Ar as the diluent gas, the formation temperature is 500°C, the time is 1800s, and a polysilicon layer with a thickness of 250nm is formed on the surface of the tunnel oxide layer; ④ In the process of laser film opening and then texturing, the non-metal contact area on the front side of the silicon wafer is laser opened to form a c-Si area. The parameters of laser film opening are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz; ⑤ During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si area; The rest are the same.

[0123] Example 10 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0124] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 10 nm.

[0125] The preparation method of this embodiment is different from that of embodiment 4 in that: ② In the PECVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 300°C, and the time was 600s. The second tunneling oxide layer and the first tunneling oxide layer were formed on the front and back of the silicon wafer, respectively, with a thickness of 2nm. SiH 4 The reaction gas is Ar, the diluent gas is Ar, the formation temperature is 300°C, the time is 3600s, and a polysilicon layer with a thickness of 50nm is formed on the surface of the tunnel oxide layer; ④ In the process of laser film opening and then texturing, the non-metal contact area on the front side of the silicon wafer is laser opened to form a c-Si area. The parameters of laser film opening are set as follows: wavelength 355nm, power ≥1W, scanning speed 5m / s, frequency 2000kHz; ⑤ During laser selective doping, the wavelength is set to 1064nm, the scanning speed is 50m / s, and the frequency is 2000kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si area; The rest are the same.

[0126] Embodiment 11 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0127] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 100 nm.

[0128] The preparation method of this embodiment is different from that of embodiment 5 in that: ② In the PECVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 650°C, the oxidation time was 60s, and the second tunneling oxide layer and the first tunneling oxide layer were formed on the front and back of the silicon wafer, respectively, with a thickness of 4nm; SiH 4 As the reaction gas, Ar as the diluent gas, the formation temperature is 650°C, the time is 300s, and a polysilicon layer with a thickness of 400nm is formed on the surface of the tunnel oxide layer; ④ In the process of laser film opening and then texturing, the non-metal contact area on the front side of the silicon wafer is laser opened to form a c-Si area. The parameters of laser film opening are set as follows: wavelength 1064nm, power ≥1W, scanning speed 50m / s, frequency 200kHz; ⑤ During laser selective doping, the wavelength is set to 200nm, the scanning speed is 5m / s, and the frequency is 200kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si area; The rest are the same.

[0129] Example 12 A P-type TOPCon battery comprises a P-type silicon wafer, wherein the front side of the P-type silicon wafer is provided with a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode in sequence from the inside to the outside; and the back side of the P-type silicon wafer is provided with a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0130] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0131] The preparation method of this embodiment is different from that of embodiment 9 in that: ① The single crystal silicon wafer is a B-doped P-type single crystal silicon wafer; ③BH 3 、SiH 4 、N 2 O, Ar, NH 3 As raw materials, a boron-containing silicon-oxygen compound layer with a thickness of 50 nm is formed; The doping source in ⑤ is POCl 3 During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si area; The rest are the same.

[0132] Example 13 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0133] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 8 nm.

[0134] The preparation method of this embodiment is different from that of embodiment 10 in that: The thickness of the phosphorus-containing silicon oxide compound layer formed in ③ is 8nm; The rest are the same.

[0135] Embodiment 14 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0136] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 103 nm.

[0137] The preparation method of this embodiment is different from that of embodiment 11 in that: The thickness of the phosphorus-containing silicon oxide compound layer formed in ③ is 103nm; The rest are the same.

[0138] Embodiment 15 like Figure 5 As shown, an N-type TOPCon battery comprises an N-type silicon wafer 4, wherein a second conductive type impurity polysilicon layer 3, a second dielectric layer 2, and a front metal electrode 1 are sequentially arranged on the front side of the N-type silicon wafer 4 from the inside to the outside; and a first conductive type impurity c-Si region 12, a first dielectric layer 7, a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer heavily doped region 13, and a back metal electrode 8 are sequentially arranged on the back side of the N-type silicon wafer 4 from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the first conductive type impurity polysilicon layer.

[0139] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0140] The preparation method of this embodiment is different from that of embodiment 9 in that: In ④, laser film opening is first used followed by texturing. The non-metallic contact area on the back of the silicon wafer is laser opened to form a c-Si area. The parameters of laser film opening are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz; then, a 1.3% NaOH solution is used for etching, and the etching time is 500s to form a front pyramid velvet surface on the front and back of the silicon wafer (not shown in the figure), and then the local pyramid velvet surface on the back is polished with an acid-base solution to make the local pyramid velvet surface on the back smooth and flat.

[0141] ⑤ During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area on the back of the silicon wafer forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the film-opening area on the back of the silicon wafer with non-metallic contact forms a second conductive type impurity c-Si area; The rest are the same.

[0142] Example 16 like Figure 6 As shown, an N-type TOPCon battery comprises an N-type silicon wafer 4, wherein the front side of the N-type silicon wafer 4 is provided with a second conductive type impurity c-Si region 11, a second dielectric layer 2, a second tunneling oxide layer 10, a second conductive type impurity polysilicon layer heavily doped region 9, and a front metal electrode 1 in sequence from the inside to the outside; the back side of the N-type silicon wafer 4 is provided with a first conductive type impurity c-Si region 12, a first dielectric layer 7, a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer heavily doped region 13, and a back metal electrode 8 in sequence from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the first conductive type impurity polysilicon layer.

[0143] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 50 nm.

[0144] The preparation method of this embodiment is different from that of embodiment 15 in that: In ④, laser film opening is first used followed by texturing. The non-metallic contact areas on the front and back sides of the silicon wafer are laser opened to form c-Si areas. The parameters of laser film opening are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz; then, a 1.3% NaOH solution is used for etching, and the etching time is 500s to form a front pyramid velvet surface on the front and back sides of the silicon wafer (not shown in the figure), and then the local pyramid velvet surface on the back side is polished with an acid-base solution to make the local pyramid velvet surface on the back side smooth and flat.

[0145] ⑤ During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact areas on the front and back sides of the silicon wafer respectively form a heavily doped area of ​​the second conductive type impurity polysilicon layer and a heavily doped area of ​​the first conductive type impurity polysilicon layer. The film opening areas on the front and back sides of the silicon wafer that are in non-metallic contact form a second conductive type impurity c-Si area and a first conductive type impurity c-Si area respectively. Comparative Example 1 This comparative example is a conventional method for preparing a TOPCon battery: ① Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer; ② Use 1.3% NaOH solution for etching for 60 minutes to prepare a velvet surface on the front side of the silicon wafer; ③Put the silicon wafer into the boron doping tube for boron doping. The doping temperature is 1000℃, the doping time is 180min, and the boron doping source is BBr. 3 , forming a 150nm BSG layer on the silicon wafer; ④ Etch the silicon wafer on one side to remove the BSG on the front side and retain the BSG barrier layer on the back side; perform corrosion polishing on the surface of the single crystal silicon wafer for 60 minutes; ⑤ In the LPCVD furnace tube, N 2 O was used as the oxidant, the oxidation temperature was 600°C, the time was 3 min, and a tunneling oxide layer with a thickness of 3 nm was formed on the back of the silicon wafer. 4 As the reaction gas, Ar as the diluent gas, the formation temperature is 600 ℃, the time is 90min, and a polysilicon layer with a thickness of 250nm is formed on the surface of the tunnel oxide layer; ⑥Put the silicon wafer into the phosphorus doping tube for phosphorus doping. The doping temperature is 1000℃, the doping time is 150min, and the boron doping source is BBr 3 ; ⑦ Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0146] ⑧ Using ALD atomic layer formation method, TMA is used as a precursor, and the reaction temperature is controlled at 300℃ to form a dense Al layer on the front and back of the silicon wafer 2 O 3 The passivation layer has a thickness of 10 nm, and a 100 nm SiNx anti-reflection layer is formed on the front and back surfaces of the silicon wafer by PECVD. The passivation layer and the anti-reflection layer form a dielectric layer.

[0147] ⑨ Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0148] The batteries in Examples 1-16 and Comparative Example 1 were tested under the same conditions. The test results are shown in Table 1.

[0149] Table 1 Test results of battery of embodiment and comparative example

[0150] As can be seen from Table 1, from the comparison of the test data of Examples 1-16 and Comparative Example 1, it can be seen that when the solar cell adopts a dopant source layer of the first conductive type impurity to be formed first, the open circuit voltage, short circuit current, and fill factor of the battery are improved, thereby improving the conversion efficiency of the battery; the process time of battery preparation is also shortened. From the test data of Examples 1-6 and Examples 7-8, it can be seen that when the thickness of the dopant source layer of the first conductive type impurity is 10nm-100nm, the open circuit voltage, short circuit current, fill factor, and conversion efficiency of the battery are better; from the test data of Examples 9-12 and Examples 13-14, it can be seen that when the thickness of the dopant source layer of the first conductive type impurity is 10nm-100nm, the open circuit voltage, short circuit current, fill factor, and conversion efficiency of the battery are better.

[0151] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: S1 cleans and polishes the substrate silicon wafer; S2 forms a dielectric region and a polysilicon layer; S3 forming a dopant source layer of first conductivity type impurities; S4 co-doping of impurities of different conductivity types in one step; S5 forms a dielectric layer; S6 metallization; The thickness of the dopant source layer of the first conductive type impurities is 10 nm-100 nm.

2. The method for preparing a solar cell according to claim 1, characterized in that: The solar cell includes a substrate silicon wafer, which has a front side facing the sun during normal operation and a back side opposite to the front side, the back side of the substrate silicon wafer being sequentially provided with the dielectric region and the polysilicon layer in a direction away from the substrate silicon wafer, and the dopant source layer of the first conductive type impurities being outside the polysilicon layer.

3. The method for preparing a solar cell according to claim 2, characterized in that: It also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer, or the texturing step forms a front texturing surface on the front side of the substrate silicon wafer and a partial back texturing surface on the back side, and the morphology and size of the front texturing surface and the partial back texturing surface are the same or different.

4. The method for preparing a solar cell according to claim 3, characterized in that: The texturing step is performed before the dielectric region and the polysilicon layer are formed in S2, and the texturing step also includes a mask preparation step before the texturing step, and the mask step forms a mask layer on the back side of the substrate silicon wafer; or, the texturing step is performed after the dopant source layer of the first conductive type impurities is formed in S3.

5. The method for preparing a solar cell according to claim 1, characterized in that: In the step S3, the dopant source layer of the first conductive type impurities is formed by CVD at a temperature of 300° C. to 800° C. and the raw materials include a boron source gas or a phosphorus source gas; The boron source gas is at least one of BH3, TMB, BCl3, and BBr3; The phosphorus source gas is at least one of PH3 and POCl3.

6. The method for preparing a solar cell according to claim 1, characterized in that: In the step S3 of forming a dopant source layer of first conductivity type impurities, the dopant source layer of the first conductivity type impurities is a silicon compound layer containing first conductivity type impurities, and the first conductivity type impurities are boron, gallium or phosphorus.

7. The method for preparing a solar cell according to claim 1, characterized in that: In the S4 one-step co-doping of different conductive type impurities, a doping source of a second conductive type impurity with electrical properties opposite to those of the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the one-step co-doping of different conductive type impurities is performed at least once.

8. The method for preparing a solar cell according to claim 1, characterized in that: The doping temperature of the S4 different conductivity type impurities co-doped in one step is 600° C.-1000° C., and the doping time is 5 min-180 min.

9. The method for preparing a solar cell according to claim 1, characterized in that: After the S4 co-doping of different conductive type impurities in one step, it also includes a laser selective doping step, the wavelength of the laser selective doping step is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, the frequency is 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped area of ​​the conductive type impurity area.

10. The method for preparing a solar cell according to claim 9, characterized in that: After the laser selective doping, the method further includes removing the dopant source layer of the first conductive type impurities, wherein the dopant source layer of the first conductive type impurities is removed by pickling with hydrofluoric acid having a concentration of 0.5%-50% for a pickling time of 10s-1200s.

11. A solar cell prepared by the method for preparing a solar cell according to any one of claims 1 to 10, characterized in that: The invention comprises a substrate silicon wafer; the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer and a front metal electrode; the back side of the substrate silicon wafer is provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer and a back metal electrode; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 10nm-100nm; The second conductive type impurity region and the first conductive type impurity region are simultaneously formed in one or more different conductive type impurity one-step co-doping steps; In the step of co-doping impurities of different conductivity types, at least once, a doping source having impurities of a second conductivity type opposite to the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the local area of ​​the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

12. A solar cell according to claim 11, characterized in that: A second dielectric region is also arranged on the upper edge of the front velvet surface in a direction away from the substrate silicon wafer; a back local velvet surface and an edge velvet surface are also arranged on the lower edge of the first dielectric region close to the substrate silicon wafer, and a heavily doped region is also arranged in the first conductive type impurity region and / or the second conductive type impurity region.

13. The solar cell according to claim 11, characterized in that: The c-Si region is formed by film opening and cleaning, and the film opening method is at least one of laser, etching slurry, and photolithography; the polysilicon layer is formed by CVD deposition.

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