Pulsed voltage source for plasma processing applications

Abstract

Embodiments provided herein generally include an apparatus, such as a plasma processing system, and a method for plasma processing of a substrate in a processing chamber. Some embodiments relate to a waveform generator. The waveform generator generally includes a first voltage stage having: a first voltage source; a first switch; a ground reference point; a transformer having a first transformation ratio, the first transformer comprising: a primary winding coupled to the first voltage source and the ground reference point; and a secondary winding having a first end and a second end, where the first end is coupled to the ground reference point and the second end is configured to be coupled to a load through a common node; and a first diode coupled in parallel with the primary winding of the first transformer. The waveform generator generally also includes one or more additional voltage stages coupled to a load through the common node.

Description

Background Art Technical Field

[0001] Embodiments of the present disclosure generally relate to systems used in the manufacture of semiconductor devices. More specifically, embodiments of the present disclosure relate to plasma processing systems for processing substrates. Related technical notes

[0002] One of the key technical challenges for next generation semiconductor devices is to reliably fabricate high aspect ratio features. One method of forming high aspect ratio features utilizes a plasma assisted etching process to bombard material formed on the surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface.

[0003] As technology nodes advance toward 2nm, the fabrication of smaller features with larger aspect ratios requires atomic-level precision for plasma processing. For etching processes in which plasma plays a major role, ion energy control has always been a challenge for the semiconductor equipment industry. In a typical plasma-assisted etching process, a substrate is positioned on an electrostatic chuck (ESC) disposed in a processing chamber, a plasma is formed above the substrate, and ions are accelerated from the plasma toward the substrate across the plasma sheath (i.e., the electron depletion region formed between the plasma and the substrate surface). Traditionally, radio frequency (RF) substrate bias methods (which utilize a sinusoidal RF waveform to excite the plasma and form the plasma sheath) have been unable to form these smaller device feature sizes as expected. Recently, it has been discovered that utilizing a pulsed plasma source to deliver high voltage direct current (DC) pulses to one or more electrodes within a processing chamber may be useful in controlling the plasma sheath formed above the substrate surface as expected.

[0004] Traditionally, a pulsed power source provides a pulsed DC bias to a cathode (known as a metal plate that can be coupled to a plasma using capacitive coupling through a dielectric layer). While designing such a pulsed power source, switching frequency, and power consumption capability are some of the main design considerations. To facilitate high switching speeds, MOSFETs are primarily used in pulsed power sources. However, despite significant advances in the field of SiC and GaN MOSFETs, the maximum operating switching frequency of these MOSFETs is limited to tens of kHz to hundreds of kHz. As device dimensions in the semiconductor industry shrink to below 10 nm, a pulsed DC bias source with a switching frequency in the upper half of the hundreds of kHz range can be a powerful tool to further control critical high aspect ratio features such as etch selectivity and uniformity.

[0005] Therefore, there is a need in the art for a pulsed voltage source and bias method that can enable a desired plasma-assisted process to be performed on a substrate. Summary of the invention

[0006]

[0013] Embodiments provided herein generally include apparatus (eg, plasma processing systems) and methods for plasma processing of substrates in a processing chamber.

[0007] Some embodiments relate to a waveform generator. The waveform generator generally includes a first voltage stage having: a first voltage source; a first switch, wherein a first terminal of the first voltage source is coupled to a first terminal of the first switch; a ground reference point, wherein a second terminal of the first switch is coupled to the ground reference point; a transformer having a first transformation ratio, wherein the first transformer includes: a primary winding, wherein the primary winding is coupled to the second terminal of the first voltage source and the ground reference point; and a secondary winding, wherein the secondary winding has a first end and a second end, wherein the first end is coupled to the ground reference point; and a first diode, wherein the first diode is coupled in parallel with the primary winding of the first transformer. The waveform generator generally also includes a second voltage stage having: a second voltage source; a second switch, wherein a first terminal of the second voltage source is coupled to a first terminal of the second switch; a second ground reference point, wherein a second terminal of the second switch is coupled to the second ground reference point; a second transformer having a second transformation ratio, the second transformer comprising: a primary winding, the primary winding being coupled to a second terminal of the second voltage source and the second ground reference point; and a secondary winding, the secondary winding having a first end and a second end, wherein the first end is coupled to the second end of the secondary winding of the first transformer, and the second end is configured to be coupled to a load via a common node; and a second diode, the second diode being coupled in parallel with the primary winding of the second transformer.

[0008] Some embodiments relate to a method for waveform generation. The method generally includes generating a first voltage pulse at a common node by closing a first switch, the first switch having a first terminal and a second terminal, wherein: the first terminal of the first switch is coupled to a first terminal of a first voltage source; the second terminal of the first voltage source is coupled to a first terminal of a primary winding of a first transformer, the first transformer having a first transformation ratio; the second terminal of the first switch is coupled to a second terminal of the primary winding of the first transformer and ground; and the common node is coupled to a first terminal of a secondary winding of the first transformer. The method for waveform generation generally also includes generating a second voltage pulse at the common node by closing a second switch, the second switch having a first terminal and a second terminal, wherein: the first terminal of the second switch is coupled to the first terminal of the second voltage source; the second terminal of the second voltage source is coupled to the first terminal of the primary winding of the second transformer, the second transformer having a second transformation ratio; the second terminal of the first switch is coupled to the second terminal of the primary winding of the second transformer and ground; a second bias voltage is generated between the first terminal and the second terminal of the second voltage source by the second voltage source; and the first terminal of the secondary winding of the second transformer is coupled to the second terminal of the secondary winding of the first transformer, wherein the common node is set between the first terminal of the secondary winding of the first transformer and the load.

[0009] Some embodiments relate to a non-transitory computer-readable medium for generating a waveform, the non-transitory computer-readable medium including instructions executable by one or more processors. The instructions generally include generating a first voltage pulse at a common node by closing a first switch, the first switch having a first terminal and a second terminal, wherein: the first terminal of the first switch is coupled to a first terminal of a first voltage source; the second terminal of the first voltage source is coupled to a first terminal of a primary winding of a first transformer, the first transformer having a first transformation ratio; the second terminal of the first switch is coupled to a second terminal of the primary winding of the first transformer and ground; and the common node is coupled to a first terminal of a secondary winding of the first transformer. The instructions generally also include generating a second voltage pulse at the common node by closing a second switch, the second switch having a first terminal and a second terminal, wherein: the first terminal of the second switch is coupled to the first terminal of the second voltage source; the second terminal of the second voltage source is coupled to the first terminal of the primary winding of the second transformer, the second transformer having a second transformation ratio; the second terminal of the first switch is coupled to the second terminal of the primary winding of the second transformer and ground; a second bias voltage is generated between the first terminal and the second terminal of the second voltage source by the second voltage source; and the first terminal of the secondary winding of the second transformer is coupled to the second terminal of the secondary winding of the first transformer, wherein the common node is set between the first terminal of the secondary winding of the first transformer and the load. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Therefore, in order to understand the above-mentioned features of the present disclosure in detail, a more particular description of the present disclosure (which has been briefly summarized above) may be obtained by reference to the embodiments, some of which are depicted in the accompanying drawings. However, it will be noted that the drawings only illustrate exemplary embodiments and therefore should not be considered to limit its scope and other equally effective embodiments may be recognized.

[0011] Figure 1 is a schematic cross-sectional view of a processing system configured to implement the methods set forth herein, according to one or more embodiments.

[0012] Figure 2 Stray capacitance associated with the processing chamber and substrate support capacitance are illustrated.

[0013] Figure 3A , Figure 3B ,and Figure 3C Examples of voltage waveforms that may be provided during plasma processing are illustrated.

[0014] Figure 4 A schematic diagram of a pulser according to certain embodiments of the present disclosure is illustrated.

[0015] Figure 5A is a diagram showing the states of switches of a pulser during various operating modes according to certain embodiments of the present disclosure.

[0016] Figure 5B According to a specific embodiment of the present disclosure, Figure 5A A diagram depicting the output provided by the pulser during the operating mode.

[0017] Figure 6 Depicted is a simplified schematic representation of the operating mode of a pulser according to certain embodiments of the present disclosure.

[0018] Fig. 7A is a diagram showing the states of switches of a pulser during various operating modes according to certain embodiments of the present disclosure.

[0019] Figure 7B According to a specific embodiment of the present disclosure, Fig. 7A A diagram depicting the output provided by the pulser during the operating mode.

[0020] Fig. 8A is a diagram showing the states of switches of a pulser during various operating modes according to certain embodiments of the present disclosure.

[0021] Figure 8B According to a specific embodiment of the present disclosure, Fig. 8A A diagram depicting the output provided by the pulser during the operating mode.

[0022] Fig.9A is a diagram showing the states of switches of a pulser during various operating modes according to certain embodiments of the present disclosure.

[0023] Fig. 9B According to a specific embodiment of the present disclosure, Fig.9A A diagram depicting the output provided by the pulser during the operating mode.

[0024] Fig. 10A is a diagram showing the states of switches of a pulser during various operating modes according to certain embodiments of the present disclosure.

[0025] Fig. 10B According to a specific embodiment of the present disclosure, Fig. 10A A diagram depicting the output provided by the pulser during the operating mode.

[0026] Fig.11A is a diagram showing the states of switches of a pulser during various operating modes according to certain embodiments of the present disclosure.

[0027] Fig. 11B According to a specific embodiment of the present disclosure, Fig.11A A diagram depicting the output provided by the pulser during the operating mode.

[0028] Fig. 11C is a diagram showing the states of switches of a pulser during various operating modes according to certain embodiments of the present disclosure.

[0029] Fig.11D According to a specific embodiment of the present disclosure, Fig. 11C A diagram depicting the output provided by the pulser during the operating mode.

[0030] Fig.12 A charging circuit for charging a capacitive element according to certain aspects of the present disclosure is illustrated.

[0031] Fig.13 is a process flow diagram illustrating a waveform generation method according to a specific embodiment of the present disclosure.

[0032] To facilitate understanding, identical reference numerals have been used, where practicable, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0033] Certain aspects of the present disclosure are generally directed to techniques for generating voltage waveforms for plasma processing systems. Traditionally, a pulsed power source provides a pulsed direct current (DC) bias to a cathode (a metal plate that is coupled to a plasma through a dielectric layer). While designing such pulsed power sources, switching frequency, and power consumption capabilities are some of the main design considerations. To facilitate high switching speeds, MOSFETs are primarily used in pulsed power sources. However, despite significant advances in the field of SiC and GaN MOSFETs, the maximum operating switching frequency of these MOSFETs is limited to tens of kHz to hundreds of kHz. As device dimensions in the semiconductor industry shrink to below 10 nm, a pulsed DC bias source with a switching frequency in the upper half of the hundreds of kHz range can be a powerful tool to further control key high aspect ratio features such as etch selectivity and uniformity.

[0034] In aspects of the present disclosure, a pulsed power source (e.g., a waveform generator) may include several stacked modules that allow for greater flexibility in different characteristics of the generated waveform. In some embodiments, the waveform generator can be adjusted to generate configurable output voltage waveforms for various applications and their individual requirements, which may include varying characteristics such as current, voltage, switching frequency (e.g., pulse frequency), pulse width, peak amplitude, pulse shape, and other requirements. In this way, the waveform generator can better control key high depth and width features, including etch selectivity and uniformity. In some embodiments, the waveform generator can mask limitations on specific components (such as, for example, maximum operating switching frequency or maximum voltage of transistors typically available in semiconductor switches typically used in waveform generation) in order to better control key high depth and width features, including increased etch selectivity, uniformity, and throughput in the processing system 10. Therefore, the waveform generator can achieve voltage waveform generation with a desired energy distribution function (IEDF) at the substrate surface. Plasma Processing System Examples

[0035] Figure 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as a reactive ion etching (RIE) plasma process. However, it should be noted that the embodiments described herein may also be used with a processing system configured for use in other plasma-assisted processes, such as a plasma-enhanced deposition process, for example, a plasma-enhanced chemical vapor deposition (PECVD) process, a plasma-enhanced physical vapor deposition (PEPVD) process, a plasma-enhanced atomic layer deposition (PEALD) process, a plasma treatment process, or a plasma-based ion implantation process (e.g., a plasma doping (PLAD) process).

[0036] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP) while the processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed in the processing volume 129, which faces a lower electrode (e.g., substrate support assembly 136) also disposed in the processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator 118) is electrically coupled to one of the upper electrode or the lower electrode and delivers an RF signal configured to ignite and maintain a plasma (e.g., plasma 101). In this configuration, the plasma is capacitively coupled to each of the upper electrode or the lower electrode and is disposed in a processing region therebetween. Typically, the other of the upper electrode or the lower electrode is coupled to ground or to a second RF power source. One or more components of the substrate support assembly 136 (such as the support pedestal 107) are electrically coupled to the plasma generator assembly 163 (which includes the RF generator 118), and the chamber lid 123 is electrically coupled to ground. As shown, the processing system 10 includes a processing chamber 100, a substrate support assembly 136, and a system controller 126.

[0037] The processing chamber 100 typically includes a chamber body 113 including a chamber lid 123, one or more sidewalls 122, and a chamber seat 124, all of which define a processing volume 129. The one or more sidewalls 122 and the chamber seat 124 generally include materials that are sized and shaped to form structural supports for elements of the processing chamber 100 and are configured to withstand pressure and increased energy applied to the materials while generating the plasma 101 within a vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber seat 124 are formed of a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0038] A gas inlet 128 provided through the chamber lid 123 is used to deliver one or more process gases from a process gas source 119 in fluid communication with the gas inlet to the processing volume 129. The substrate 103 is loaded into and removed from the processing volume 129 through openings (not shown) in the sidewalls of one or more sidewalls 122, which are sealed during plasma processing of the substrate 103 using a slit valve (not shown).

[0039] The system controller 126 (also referred to herein as a processing chamber controller) includes a central processing unit (CPU) 133, a memory 134, and support circuits 135. The system controller 126 is used to control the process sequence used to process the substrate 103, including the substrate biasing method described herein. The CPU 133 is a general purpose computer processor that is configured for use in an industrial setting to control a processing chamber and its associated subprocessors. The memory 134 (generally a non-volatile memory) described herein may include random access memory, read-only memory, a floppy disk drive or hard disk drive, or other suitable form of digital storage (local or remote). The support circuits 135 are conventionally coupled to the CPU 133 and include caches, clock circuits, input / output subsystems, power supplies, and the like, as well as combinations thereof. Software instructions (programs) and data can be encoded and stored in the memory 134 for instructing the processor within the CPU 133. A software program (or computer instructions) readable by the CPU 133 in the system controller 126 determines which tasks are performable by the components in the processing system 10 .

[0040] Typically, the program (which can be read by the CPU 133 in the system controller 126) includes code that, when executed by the CPU 133, performs tasks related to the plasma processing schemes described herein. The program may include instructions used to control various hardware and electrical components within the processing system 10 to perform various different program tasks and various program sequences to implement the methods described herein. In an embodiment, the program includes instructions to perform the following related to Fig.13 One or more of the operations described.

[0041] The processing system may include a plasma generator assembly 163, a first pulsed voltage (PV) source assembly 196 for establishing a first PV waveform at the bias electrode 104, and a second PV source assembly 197 for establishing a second PV waveform at the edge control electrode 115. Figure 4-Figure 1 1 to generate the first PV waveform or the second PV waveform. In some embodiments, the plasma generator assembly 163 delivers an RF signal to the support base 107 (e.g., a power electrode or cathode), which can be used to generate (maintain and / or ignite) the plasma 101 in the processing region disposed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to deliver an RF signal having a frequency of greater than 1 MHz or more, or about 2 MHz or more (such as about 13.56 MHz or more).

[0042] As discussed above, in some embodiments, the plasma generator assembly 163 (which includes the RF generator 118 and the RF generator assembly 160) is generally configured to deliver a desired amount of continuous wave (CW) or pulsed RF power to the support pedestal 107 of the substrate support assembly 136 at a desirably substantially fixed sinusoidal waveform frequency based on control signals provided from the system controller 126. During processing, the plasma generator assembly 163 is configured to deliver RF power (e.g., an RF signal) to the support pedestal 107 disposed proximate to the substrate support 105 and within the substrate support assembly 136. The RF power delivered to the support pedestal 107 is configured to ignite and maintain a plasma 101 of a process gas disposed within the processing volume 129.

[0043] In some embodiments, the support base 107 is electrically coupled to the RF electrode of the RF generator 118 via the RF matching circuit 162 and the first filter assembly 161, both of which are disposed within the RF generator assembly 160. The first filter assembly 161 includes one or more electrical components configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power delivery line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator P1 within the PV waveform generator 150, thereby inhibiting current flow to the RF matching circuit 162 and the RF generator 118.

[0044] In some embodiments, the RF generator assembly 160 and the RF generator 118 are used to ignite and maintain the plasma 101 using process gases disposed in the processing volume 129 and in the field generated by the RF power (RF signal) delivered by the RF generator 118 to the support pedestal 107. The processing volume 129 is fluidly coupled to one or more dedicated vacuum pumps through a vacuum outlet 120, which maintains the processing volume 129 at a sub-atmospheric pressure state and evacuates process and / or other gases therefrom. In some embodiments, the substrate support assembly 136 disposed in the processing volume 129 is disposed on a support shaft 138 that is grounded and extends through the chamber pedestal 124. However, in some embodiments, the RF generator assembly 160 is configured to deliver RF power to a bias electrode 104 disposed in the substrate support 105 relative to the support pedestal 107.

[0045] As briefly discussed above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support pedestal 107. In some embodiments, the substrate support assembly 136 can additionally include an insulator plate 111 and a ground plate 112, as discussed further below. The support pedestal 107 is electrically isolated from the chamber pedestal 124 by the insulator plate 111, and the ground plate 112 is interposed between the insulator plate 111 and the chamber pedestal 124. The substrate support 105 is thermally coupled to and disposed on the support pedestal 107. In some embodiments, the support pedestal 107 is configured to regulate the temperature of the substrate support 105 (and the substrate 103 disposed on the substrate support 105) during substrate processing.

[0046] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion resistant metal oxide or metal nitride material (e.g., aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof). In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing region above the bias electrode 104 are determined and / or monitored by measuring the RF waveform established at the bias electrode 104.

[0047] In one configuration, the bias electrode 104 is a pole that is used to secure (i.e., attach) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 relative to the plasma 101 using one or more of the pulsed voltage biasing schemes described herein. Typically, the bias electrode 104 is formed of one or more electrically conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0048] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network 116 that provides a clamping voltage (such as a static DC voltage between about -5000 V and about 5000 V) to the bias electrode 104 using an electrical conductor (such as a coaxial power delivery line 106 (e.g., a coaxial cable)). As will be discussed further below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power source 155, and a bias compensation module blocking capacitor (also referred to herein as a blocking capacitor C5). The blocking capacitor C5 is disposed between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0049] The substrate support assembly 136 may further include an edge control electrode 115 positioned below the edge ring 114 and surrounding the bias electrode 104 and / or disposed at a distance from the center of the bias electrode 104. Generally, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is round in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments (such as Figure 1 ), the edge control electrode 115 is positioned within the region of the substrate support 105. In some embodiments (such as Figure 1 ), the edge control electrode 115 comprises a conductive grid, foil, and / or plate that is disposed at a similar distance (i.e., in the Z direction) from the substrate supporting surface 105A of the substrate support 105 as the bias electrode 104. In some other embodiments, the edge control electrode 115 comprises a conductive grid, foil, and / or plate that is positioned on or within a region of the quartz tube 110 surrounding at least a portion of the bias electrode 104 and / or the substrate support 105. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is positioned within or coupled to an edge ring 114 that is positioned on or adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed of a semiconductor or dielectric material (e.g., AlN, etc.).

[0050] The edge control electrode 115 may be biased by utilizing a PV waveform generator that is different from the PV waveform generator 150 used to bias the bias electrode 104. In some embodiments, by splitting a portion of the power to the edge control electrode 115, the edge control electrode 115 can be biased by utilizing the PV waveform generator 150 that is also used to bias the bias electrode 104. In one configuration, the first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the bias electrode 104, while the second PV waveform generator 150 of the second PV source assembly 197 is configured to bias the edge control electrode 115.

[0051] The power delivery line 157 electrically connects the output of the PV waveform generator 150 of the first PV source assembly 196 to the optional filter assembly 151 and the bias electrode 104. Although the following discussion focuses on the power delivery line 157 of the first PV source assembly 196 (which is used to couple the PV waveform generator 150 to the bias electrode 104), the power delivery line 158 of the second PV source assembly 197 (which couples the PV waveform generator 150 to the edge control electrode 115) will include the same or similar components. The electrical conductors in the various components of the power delivery line 157 may include: (a) a coaxial cable or a combination of coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable, (b) an insulated high voltage corona resistant hookup wire, (c) bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical components in (a)-(e). The optional filter assembly 151 includes one or more electrical components configured to substantially prevent current generated by the output of the RF generator 118 from flowing through the power delivery line 157 and damaging the PV waveform generator 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118, thereby inhibiting current flow to the PV waveform generator 150.

[0052] The second PV source assembly 197 includes a clamping network 116 so that the bias applied to the edge control electrode 115 can be configured similarly to the bias applied to the bias electrode 104 by the clamping network 116 coupled within the first PV source assembly 196. Applying similarly configured PV waveforms and clamping voltages to the bias electrode 104 and the edge control electrode 115 can help improve plasma uniformity across the substrate surface during processing, thereby improving the results of the plasma processing process.

[0053] In some embodiments, the processing chamber 100 further includes a quartz tube 110 (or column) that at least partially surrounds a portion of the substrate support assembly 136 to prevent the substrate support 105 and / or the support pedestal 107 from contacting the corrosive process gas or plasma, the cleaning gas or plasma, or their byproducts. Typically, the quartz tube 110, the insulator plate 111, and the ground plate 112 are surrounded by the cathode liner 108. In some embodiments, the plasma shield 109 is positioned between the cathode liner 108 and the sidewalls 122 to prevent plasma from forming in the volume below the plasma shield 109 between the cathode liner 108 and one or more sidewalls 122. Example Representative Circuitry for a Processing Chamber

[0054] Figure 2 The diagram shows the stray capacitance and escape capacitance associated with the processing chamber.stray ) represents the capacitance between the electrode of the processing chamber and ground, and the substrate support capacitance 202 (also referred to herein as the electrostatic chuck capacitance (C esc )) represents the capacitance between the bias electrode 104 and the substrate support surface 105A. As shown in the figure, C esc Generated at the output node (labeled as U out ) and a composite load (e.g., a plasma load), which is represented by only the resistor element 206. load The voltage pulse at the point is square-shaped. esc The voltage and cross Cstray Voltage (eg U out The slope is implemented by the voltage at C as will be described in more detail below. stray Current (such as compensation current (I comp )) can be equal to span C esc The load current (I load ) multiplied by C stray The capacitance and C esc The output current (I out ) can be equal to I load with I comp The sum of , which can be expressed by the following equation: Example voltage waveforms for a process chamber

[0055] Figure 3A An example of a voltage waveform that may be delivered to an electrode (such as Figure 1 The waveform generally includes two main phases, the ion current phase and the sheath collapse phase. At the beginning of the ion current phase, the chip voltage drops to create a high voltage sheath above the substrate, thereby accelerating positive ions toward the substrate 103. The positive ions deposit positive charges on the substrate surface and tend to gradually increase the substrate voltage in a positive direction. If a square wave is applied, the ion current toward the substrate creates a positive slope of the substrate voltage (e.g. Figure 2 U shown in load In order to make Figure 3C As shown in (for example, U load The voltage pulse on the load at the position of the ion current is square, and the voltage pulse on the load at the position of the ion current is square. out (like Figure 3A The voltage at ) implements a negative slope, which is used to form a capacitive element C across the electrostatic chuck. esc The voltage, such as Figure 3B as shown in . Figure 3CAn example of a desired voltage waveform that may be established at a substrate disposed on a substrate support assembly 136 disposed within a processing chamber 100 is shown. The bias electrode 104 and the electrostatic chuck capacitor C are implemented during the ion current phase. esc The slope at is generally referred to as current compensation, which is used to form U during this phase. load The constant voltage seen at . The voltage difference between the beginning and the end of the ion current phase determines the width of the ion energy distribution function (IEDF). The larger the voltage difference, the wider the distribution of ion energies and therefore the wider the IEDF width. To achieve single energy ions and narrow IEDF width, a current compensation operation is performed to flatten the substrate voltage waveform during the ion current period. In some embodiments, the voltage waveform can be adjusted at a frequency (1 / T) between about 50 kHz and 1000 kHz. P In some embodiments, the voltage waveform established at the electrode has an on-time, which is defined as the time period of the ion current (e.g., the length of the ion current phase) and the waveform period T P (e.g., the length of the sheath disintegration phase + the length of the ion current phase), the start-up time is greater than 50%, or greater than 70%, such as between 80% and 95%. In some embodiments, the waveform period is T P The voltage waveform of (e.g., about 2.5 μs) is continuously repeated within a waveform short pulse having a short pulse period of between about 100 microseconds (μs) and about 10 milliseconds (ms). The short pulse of the PV waveform can have a short pulse duty cycle of between about 5%-100% (such as between about 50% and about 95%), where the duty cycle is the ratio of the short pulse period divided by the short pulse period plus the non-short pulse period (i.e., no PV waveform is generated) separating the short pulse periods. As shown, the sheath collapse phase may have a duration T SH , which may be approximately 200ns. Waveform Generator Example

[0056] Figure 4A pulser 400 (also referred to herein as a waveform generator) is illustrated in accordance with a particular embodiment of the present disclosure. In some embodiments, the pulser 400 may be included in a power supply (e.g., the PV waveform generator 150). As shown, the pulser 400 includes a plurality of stacked inductive adder modules (e.g., 440, 442, 444) and may include pulse capacitor elements 402, 404, and 406 (labeled as C1, C2, C3, and C4) and transistors 410, 412, and 414 (labeled as Q1, Q2, and Q3). The transistors 410, 412, and 414 may be power transistors (e.g., metal oxide semiconductor field effect transistors (MOSFETs)) with parallel diodes (e.g., body diodes D1, D2, and D3). Each transistor 410, 412, 414 may act as a switch and may be referred to herein as a switch. In some embodiments, the transistors 410, 412, 414 may be implemented on a printed circuit board. Capacitive elements 402, 404, and 406 may be used as charging circuits (such as those depicted in FIG. Fig.12 In some embodiments, transistors 410, 412, and 414 may each be coupled to a gate drive circuit 418, 420, 422. Each gate drive circuit 418, 420, 422 may have a trigger that receives a signal from the system controller 126 to be enabled or disabled to set the state of the gate within the respective transistor 410, 412, 414. Figure 4 , Figure 6 and Fig.12 The capacitive element shown in operatively acts as a voltage source. Although the example pulser 400 shows a capacitive element to facilitate understanding, any suitable voltage source may be used.

[0057] Resistive element 424 (labeled R1) represents the internal series resistance element of the pulser coupled to load 426. Composite load 426 (which may be formed by plasma formed in the plasma processing chamber) may be represented by capacitive element 428 (labeled C4) and resistive element 430 (labeled R2). As shown, capacitive element 406 and transistor 414 form a first voltage stage 444 (e.g., module), while capacitive element 404 and transistor 412 form a second voltage stage 442 (e.g., module). Pulser 400 also includes a third voltage stage 440 (e.g., module) having capacitive element 402 and transistor 410. The output of pulser 400 is coupled to a common node 480, which is coupled (e.g., capacitively coupled) to composite load 426. Although pulser 400 is implemented with three voltage stages, aspects of the present disclosure may be implemented with one, two, or more than three voltage stages. In some embodiments of the pulser 400 , one or more of the voltage levels may be replicated one or more times, such as a configuration including a first voltage level 444 , two or more second voltage levels 442 , and a third voltage level 440 .

[0058] In some embodiments, common node 480 and load 426 are configured to be capacitively coupled to support base 107 due to the delivery of RF power provided to support base 107 by RF generator 118. In some embodiments, common node 480 can be configured to be capacitively coupled to the load 426 via node 190 ( Figure 1 ) provides a cathode RF feed. During plasma processing, the plasma 101 will act as a composite load 426.

[0059] In some embodiments, and as Figure 4As shown in , the pulser 400 may include a first voltage stage 444. The first voltage stage 444 has a first switch (e.g., a combination of a transistor 414, a gate drive circuit 422, and a trigger), the first terminal of the first switch is coupled to the first terminal of a first voltage source (e.g., a capacitor 406) at a node N9. The second terminal of the first switch is coupled to a ground reference point at a node N11. The first voltage stage 444 may further include a first transformer 470 having a core 476, a primary winding 472 coupled to the second terminal of the first voltage source 406 at a node N10, and a secondary winding 474 whose first end is coupled to the first ground reference point via a node N12. The primary winding of the first transformer is also coupled to the ground reference point at a node N11. The first voltage stage 444 may further include a first diode D3, the first diode D3 being connected in parallel with the primary winding 472 of the first transformer 470. The first end of the diode D3 may be coupled to the second terminal of the first voltage source 406 and the primary winding at a node N10, and the second end of the diode D3 may be coupled to the first terminal of the first switch 414 and the primary winding via a node N12. The first transformer may have a first transformation ratio. The ratio of the transformer is the ratio between the number of primary turns (Wp) in the primary winding 472 and the number of secondary turns (Ws) in the secondary winding 474 relative to each other. The transformation ratio (i.e., Wp:Ws) produces a step-up transformer (i.e., Ws>Wp) or a step-down transformer (i.e., Ws>Ws). <Wp)。

[0060] In some embodiments, and as Figure 4As shown in , the pulser 400 may include a second voltage stage 442. The second voltage stage 442 has a second switch (e.g., a combination of a transistor 412, a gate drive circuit 420, and a trigger), the first terminal of the second switch is coupled to the first terminal of a second voltage source (e.g., a capacitor element 404) at a node N5. The second terminal of the second switch is coupled to a second ground reference point at a node N7. The second voltage stage 442 may further include a second transformer 460 having a core 466, a primary winding 462 coupled to the second terminal of the second voltage source 404 at a node N6, and a secondary winding 464, the first end of the secondary winding 464 is coupled to the second end of the secondary winding 474 of the first transformer 470. The primary winding of the second transformer 460 is also coupled to the ground reference point at a node N7. The second voltage stage 442 may further include a second diode D2, the second diode D2 is connected in parallel with the primary winding 462 of the second transformer 460. The first end of the diode D2 may be coupled to the second terminal of the second voltage source 404 and the primary winding at a node N6, and the second end of the diode D2 may be coupled to the first terminal of the second switch 412 and the primary winding via a node N8. The second transformer 460 may have a second transformation ratio as described above. In some embodiments of the pulser 400, such as a configuration in which there are only two voltage levels (i.e., voltage levels 442 and 444), the second end of the secondary winding 464 of the second transformer 460 may be configured to be coupled to an electrode disposed within the processing chamber 100, such as the bias electrode 104, via a common node 480.

[0061] In some embodiments, and as Figure 4As shown in , the pulser 400 may include a third voltage stage 440. The third voltage stage 440 has a third switch (e.g., a combination of a transistor 410, a gate drive circuit 418, and a trigger), the first terminal of the third switch being coupled to the first terminal of a third voltage source (e.g., a capacitor 402) at a node N1. The second terminal of the third switch is coupled to a third ground reference point at a node N3. The third voltage stage 440 may further include a third transformer 450 having a core 456, a primary winding 452 coupled to the second terminal of the third voltage source 402 at a node N2, and a secondary winding 454, the first end of the secondary winding 454 being coupled to the second end of the secondary winding 464 of the second transformer 460. The primary winding of the third transformer is also coupled to the ground reference point at a node N3. The third voltage stage 440 may further include a third diode D1, the third diode D1 being connected in parallel with the primary winding 452 of the third transformer 450. The first end of the diode D1 may be coupled to the second terminal of the third voltage source 402 and the primary winding at the node N2, and the second end of the diode D1 may be coupled to the first terminal of the third switch 410 and the primary winding via the node N4. The third transformer may have a third transformation ratio as described above. In some embodiments of the pulser 400 (e.g. Figure 4 ), the second end of the secondary winding 454 of the third transformer 450 may be configured to be coupled to an electrode disposed in the processing chamber 100, such as the bias electrode 104, through the common node 480.

[0062] In some embodiments, the cores (e.g., 456, 466, 476) in the transformers 450, 460, 470 of the modules 440, 442, 444 of the pulser 400 are used to adjust the output waveforms that are feasible for the pulser 400. The characteristics of the cores (e.g., 456, 466, 476) indicate the maximum allowable switching frequency and pulse width of the output waveform that the pulser 400 can produce. Some of the characteristics of the cores (e.g., 456, 466, 476) that can affect the output waveform produced by the pulser 400 include magnetic saturation flux density, magnetic flux swing, residual flux density, cross-sectional area, volume, and weight. In some embodiments, each of the cores (e.g., 456, 466, 476) has at least one of the following: magnetic saturation flux density between 1.4 Tesla (T) and 1.8 T, magnetic flux swing between 2.4 T and 3.6 T, residual flux density between 0.2 T and 0.8 T, and a cross-sectional area of ​​6 square centimeters (cm 2 ) and 9cm 2 A cross-sectional area between 2 kg and 4 kg, a weight between 700 cubic centimeters (cm 3 ) and 1500cm 3 The volume between.

[0063] In some embodiments, different cores (e.g., 456, 466, 476) may be used in different modules 440, 442, 444 of the pulser 400 to customize the characteristics of the output waveform. In some embodiments, each module 440, 442, 444 has its own ground reference point. In some embodiments, the first, second, and third transformation ratios in each of the transformers 450, 460, 470 are the same. In other embodiments, one or more of the transformers of the pulser 400 have different transformation ratios than other transformers in other stages within the pulser 400. In addition, ground referencing each module may also reduce isolation breakdown (e.g., arcing) between gate drive circuits at higher voltages, which can prove problematic in certain conventional pulser designs. In some embodiments, the output of each module 440, 442, 444 is tied to the same ground reference point as the gate drive circuit input, so that the pulser 400 may be subject to less electromagnetic interference during operation.

[0064] In some embodiments, the transformation ratio of the first transformer (i.e., the first transformation ratio) may be the same as the transformation ratio of the second transformer (i.e., the second transformation ratio). In other embodiments, the transformation ratio of the first transformer may be different from the transformation ratio of the second transformer. For example, the first transformation ratio may be less than the second transformation ratio, or greater than the second transformation ratio. In some embodiments, the transformation ratio of the third transformer (i.e., the third transformation ratio) may be the same as the transformation ratio of the first transformer and the second transformer. In other embodiments, the transformation ratio of the third transformer may be different from the transformation ratio of the first transformer and the second transformer. There may be any combination of transformation ratios among the transformers for each voltage level 440, 442, 444 (e.g., module). The transformation ratio of the transformer may be modified to customize the output voltage waveform of the pulser 400 using different voltages and different pulse widths. Each module 440, 442, 444 can deliver pulses, and each pulse seen at the common node 480 depends on the voltage and transformation ratio stored in the capacitors 402, 404, 406 of the corresponding module. Utilizing different transformation ratios to trigger multiple modules of the pulser 400 can allow the output signal shape and pulse width generated in the secondary winding of the module to be modified to fit the desired IEDF. In some embodiments, the transformers (e.g., 450, 460, 470) of each of the voltage stages 440, 442, 444 (e.g., modules) are connected in series.

[0065] As shown, each of the capacitor elements 402, 404, and 406 can be charged to a specific voltage according to the characteristics of the waveform implemented. The transistors, gate drive circuits, and triggers in each module 440, 442, 444 can be operated as switches controlled by the system controller 126. For example, when the gate drive circuits and triggers (such as transistors 410, 412, 414) in each module 440, 442, 444 are operated as closed switches, each of the capacitor elements 402, 404, and 406 is charged to 800 volts. In some embodiments, the capacitor elements 402, 404, and 406 can be charged to higher or lower voltages to implement different voltage levels to obtain waveforms suitable for different embodiments. In some embodiments, each of the voltage levels 440, 442, and 444 can have a modular design, which facilitates simple replacement in the event of a failure. For generating Figure 3A The operation of the pulser 400 shown in the waveform will be for Figure 6-Figure 1 1 for more detailed description. Example of the generated voltage waveform

[0066] In some embodiments, transistors 410, 412, and 414 can be triggered by gate signals at different time instances to increase the switching frequency and address the switching frequency limitations of commercial transistors in the delivery of voltage pulses in various processing applications (such as plasma etching applications). In this way, output voltages can be obtained at different time stamps, thereby increasing the effective switching frequency at the output terminal (e.g., common node 480) and effectively addressing the switching frequency limitations of typical commercial transistors. In some embodiments, some parameters of the gate signals applied to transistors 410, 412, and 414 can be changed. For example, the trigger gate signal start time and / or the trigger gate signal width can be modified to produce output voltages with different waveform characteristics, as depicted and described herein. In some embodiments, multiple different DC power modules capable of having output voltages of different amplitudes at electrodes within processing chamber 100 can be coupled to modules 440, 442, and 444 capacitively coupled to composite load 426, for example, at common node 480, which is coupled to bias electrode 104. In some embodiments, different duty cycle ratios among modules 440, 442, and 444 can result in output voltages with different peak amplitudes in the pulses. Additionally, the gate signals applied to modules 440, 442, and 444 can be triggered to create overlap in the generated voltage waveforms, which can help achieve better IEDF of the output waveform.

[0067] Figure 5A 5- is a diagram showing the state of switches (eg, transistors 410, 412, 414) and the voltage generated by the pulser 400 during an operating mode according to certain embodiments of the present disclosure. Fig.11D The voltage amplitudes associated with the various operating modes and circuit elements depicted in are intended to provide examples of voltages that may be established during the generation of the pulse waveform and are not intended to limit the scope of the disclosure herein. Figure 500A is a diagram showing the state of each of transistors 410, 412, and 414 (e.g., Q1, Q2, Q3) when a gate signal (e.g., trigger) is simultaneously applied to each of the corresponding gate drive circuits 418, 420, 422 of transistors 410, 412, and 414 (e.g., Q1, Q2, Q3) (e.g., gate drive 418 triggers transistor 410, gate drive 420 triggers transistor 412, and gate drive 422 triggers transistor 414). The applied gate signal may be a transistor-to-transistor logic (TTL) signal and may be between 1.5V and 5V. In some embodiments, the system controller 126 may control the application of gate signals to the gate drive circuits 418, 420, 422 to enable the transistors 410, 412, and 414 of the modules 440, 442, and 444. Figure 5A In the diagram 500A in FIG. 1 , a gate signal (e.g., V1) is applied to each of the modules 440, 442, and 444 simultaneously (e.g., between time T1 and T2), and each module generates a pulse trigger TR1, TR2, and TR3. The module 440 generates a pulse TR1, the module 442 generates a pulse TR2, and the module 444 generates a pulse TR3. Figure 5B Graph 500B shown in illustrative embodiment depicts the voltage (e.g., V2) visible at common node 480 as a result of pulses P1, P2, P3 generated between time T1 and T2. The pulses may be repeated during intervals T3 and T4 as depicted. Simultaneously triggering multiple modules of the pulser 400 may allow the output voltage at common node 480 (e.g., the voltage at load 426) to be increased. For example, if each module of the pulser generates a 1200V pulse at the secondary winding portion of each transformer 450, 460, 470, then the electrode coupled to common node 480 will reach 3600V because the voltage of each of the simultaneous pulses P1, P2, P3 will be added together.

[0068] Figure 6 Depicted in Figure 4 0 is a further simplified schematic diagram of the pulser 400 depicted in , and depicts an example of an operating mode of the pulser 400 according to a specific embodiment of the present disclosure. Figure 6The operating modes and circuit elements shown in show examples of how different voltages may be established during different times during the generation of the pulsed waveform, and are thus not intended to limit the scope of the disclosure provided herein. Other embodiments may include other combinations of modules 440, 442, and 444 being triggered simultaneously or at different times by their corresponding gate drive circuits 418, 420, and 422 in order to produce a desired voltage at the common node 480 at different times during the process. Figure 6 In the example shown in FIG. 1 , transistors 410, 412, and 414 are represented by switches and are functionally operated as switches. In this example, only the gate drive 418 of the module 440 is triggered by the gate signal command provided by the system controller 126, and thus the switch representing the transistor 410 is closed. In this example, the gate drive circuit 420 of the second module 442 and the gate drive circuit 422 of the third module 444 are not triggered by the gate signal command provided by the system controller 126, and thus the switches representing the transistors 412 and 414 remain open.

[0069] According to certain embodiments of the present disclosure, Fig. 7A It is displayed in Figure 6 FIG. 4 is a diagram of the state of transistor 410 (eg, Q1) of pulser 400 during the operating mode illustrated in the schematic configuration depicted in FIG. Figure 5A , Figure 5B ,and Figures 7A-9B , V1 represents a gate signal, which may be a TTL signal (e.g., between 1.5V and 5V), and V2 represents an output voltage, which may be adjusted as described herein. As described above, applying a switch signal (e.g., a gate signal) closes a switch (e.g., transistor 410) to achieve pulse generation. Fig. 7A Graph 700A in FIG. 700B depicts the state of transistor 410 when a gate signal is applied to the transistor by gate driver circuit 418 (e.g., between time T1 and T2). In graph 700A, a gate signal (e.g., V1) is applied to gate driver circuit 418 in module 440 as a trigger pulse TR1, and thus only the triggered module 440 generates pulse P1, which is depicted in graph 700B. Figure 7BThe graph 700B shown in depicts the voltage (e.g., V2) visible at the common node 480 caused by the pulse P1 generated by the module 440 between time T1 and T2. In contrast to the above example, when multiple modules of the pulser 400 are triggered simultaneously, triggering only a single module produces a smaller output voltage because the other modules are not generating a pulse voltage at the same time. When more than one module is generating a pulse voltage at the same time, the pulses generated will be added together because of the series connection of the secondary windings of each module (which extend from the ground connected at node N11 to the common node 480). Therefore, in some embodiments, a pulser using multiple modules simultaneously can generate higher pulses than a pulser using only a single module. As shown in FIG. Figure 7B As shown in , the pulses can be repeated during intervals T3 and T4. For example, if each module of the pulser is configured to generate a 1200V pulse in the secondary winding connected to each module, the common node 480 in this example will only reach 1200V because only one module (e.g., module 440) is commanded to generate a pulse.

[0070] Fig. 8A 800A is a diagram showing the state of switches (e.g., transistors 410, 412, 414) during another example operating mode as a function of the time used to generate voltage pulses from the pulser 400 according to certain embodiments of the present disclosure. Graph 800A is a diagram showing the state of each of the transistors 410, 412, and 414 when gate signals are applied to each of the transistors 410, 412, and 414 (e.g., Q1, Q2, Q3) and their corresponding gate drive circuits 418, 420, 422 at different times. In some embodiments, the system controller 126 can control the application of the gate signals to the gate drive circuits 418, 420, 422 to enable the transistors 410, 412, and 414 of each of the modules 440, 442, and 444 at desired time points within the pulse sequence. In diagram 800A, the gate signal (e.g., V1) is first applied to module 440 between time T1 and T2 to generate pulse trigger TR1, then applied to module 442 between time T3 and T4 to generate pulse trigger TR2, and finally applied to module 444 between time T5 and T6 to generate trigger TR3. Figure 8B ) depicts the voltage (e.g., V2) reached at the common node 480 due to the voltage pulses P1, P2, P3 generated during each corresponding time interval. Continuously triggering multiple modules of the pulse generator 400 can allow the frequency of the output voltage to be increased. The pulses can be repeated in intervals T7-T8, T9-T10 as shown. 10 , and T 11 -T 12In some embodiments, due to the sequential pulse delivery from each module within the pulser, the provided pulse frequency (F1) provided by the pulser 400 can achieve an output pulse frequency that masks the switching hardware frequency (F2) limitations visible in each module, because the hardware in each module only needs to deliver pulses at its own position within the pulse sequence (e.g., at Figure 8B ), thereby preventing each module from exceeding its ability to reliably deliver pulses at a frequency (F1) that exceeds the functional limits of the hardware (e.g., voltage limits, switching frequency limits, and other limits of transistors 410, 412, and 414). During the pulse, the voltage waveform may experience some degree of ringing (e.g., 802) due to the long wires and associated stray inductance. The degree of ringing can be adjusted and / or minimized through the design of the pulser 400 and the processing system 10 utilized.

[0071] Fig.9A 900A is a diagram showing the states of switches (e.g., transistors 410, 412, 414) of the pulser 400 during another example mode of operation according to a particular embodiment of the present disclosure. FIG. 900A is a diagram showing the states of each transistor 410, 412, and 414 (e.g., Q1, Q2, Q3) when a gate signal is applied to each of the corresponding gate drive circuits 418, 420, 422 at different times. In some embodiments, the system controller 126 may control the application of the gate signal to the gate drive circuits 418, 420, 422 to enable the transistors 410, 412, and 414 of the modules 440, 442, and 444. As shown in FIG. Fig.9A As shown in , the system controller 126 can send gate signals with different pulse widths to the gate drive circuits 418, 420, and 422. In Figure 900A, a gate signal (e.g., V1) is first applied to the module 440 between time T1 and T2 to generate a trigger pulse TR1. Another gate signal (e.g., V1) is applied to the module 442 between time T3 and T4 to generate a trigger pulse TR2. A third gate signal (e.g., V1) is applied to the module 444 between time T5 and T6 to generate a trigger pulse TR3. Figure 900B (e.g., Fig. 9B) depicts the voltage (e.g., V2) reached at the common node 480 as a result of the voltage pulses P1, P2, P3 generated during each respective time interval defined by the signal provided by the system controller 126. Because of the different pulse widths of the applied gate signals, the widths of the pulses P1, P2, and P3 provided to the common node 480 are different. In this way, the output waveform can include pulses generated with different pulse widths, which are provided at desired time points within the pulse sequence. Using different gate signals with different pulse widths to trigger multiple modules of the pulser 400 allows the output signal shape and pulse width to be modified to suit the desired IEDF. The pulses can be repeated in intervals T7-T8, T9-T10 as shown. 10 , and T 11 -T 12 period.

[0072] Fig. 10A is a diagram showing states of switches (eg, transistors 410 , 412 , 414 ) of the pulser 400 during another example mode of operation in accordance with certain embodiments of the present disclosure. Fig. 10A and Fig. 10B , V1 represents a gate signal, which may be a TTL signal (e.g., between 1.5V and 5V), and V2, V3, and V4 represent output voltages (e.g., 1000V, 2000V, and 3000V). FIG. 1000A is a diagram showing the state of each of transistors 410, 412, and 414 (e.g., Q1, Q2, and Q3) when a gate signal is applied to each of the corresponding gate drive circuits 418, 420, and 422 at different times. In some embodiments, the system controller 126 may control the application of the gate signal to the gate drive circuits 418, 420, and 422 to enable the transistors 410, 412, and 414 of the modules 440, 442, and 444. The system controller 126 may send gate signals with different pulse widths to the gate drive circuits 418, 420, and 422. In Figure 1000A, a gate signal (e.g., V1) is first applied to module 440 between time T1 and T2 to generate a trigger pulse TR1. Another gate signal (e.g., V1) is applied to module 442 between time T3 and T4 to generate a trigger pulse TR2. A third gate signal is applied to module 444 between time T5 and T6 to generate a trigger pulse TR3. Figure 1000B (shown in Fig. 10B ) depicts the voltage generated at the common node 480 due to the pulses P1, P2, P3 generated by each module 440, 442, and 444 during their respective time intervals. During the time interval between time T1 and T2, pulse P1 includes a voltage V3 because the voltage (V s1) to the primary winding 452, which generates a voltage V3 at the secondary winding 454 due to the first transformation ratio of the transformer 450. During the time interval between times T3 and T4, the pulse P2 includes a voltage V4 because the voltage (V s2 ) is delivered to primary winding 462, which produces voltage V4 at secondary winding 464 due to the second transformation ratio of transformer 460. During the time interval between times T5 and T6, pulse P3 includes voltage V2 due to the delivery of voltage (Vs3) stored in capacitive element 406 (e.g., voltage source) to primary winding 472, which produces voltage V2 at secondary winding 474 due to the first transformation ratio of first transformer 470. The width and amplitude of each pulse P1, P2, and P3 are different due to the different pulse widths applied and the different transformation ratios and / or input voltages applied through the use of transformers 450, 460, and 470, respectively. In this way, output waveforms with different voltages and different pulse widths can be generated, which can enable better IEDF of the output waveforms. In one example, the modules can include transformers each having the same transformation ratio, while the voltage input sources are configured to provide different peak input voltages, so that different peak voltage levels can be generated in the output voltage waveform pulses P1, P2, and P3. In another example, the modules include transformers each having different transformation ratios, while the voltage input sources are each configured to provide the same peak input voltage, so that different peak voltage levels can be generated in the output voltage waveform pulses P1, P2, and P3. Using input voltages and different gate signals with different pulse widths to trigger multiple modules of the pulser 400 allows the output signal shape and pulse width to be modified to suit the desired IEDF. The pulses can be repeated in intervals T7-T8, T9-T10 as shown. 10 , and T 11 -T 12 period.

[0073] Fig.11A 4 is a diagram showing the states of switches (e.g., transistors 410, 412, 414) of the pulser 400 during another example of an operating mode according to certain embodiments of the present disclosure. Figures 11A-11D, V1 and V5 each represent a gate signal, which may be a TTL signal (e.g., between 1.5V and 5V), and V2, V3, V4, V6, and V7 represent output voltages (e.g., 1000V, 2000V, and 3000V). FIG. 1100A is a diagram showing the state of each of transistors 410, 412, and 414 (e.g., Q1, Q2, and Q3) when a gate signal is applied to each of the corresponding gate drive circuits 418, 420, and 422 so that the gate signals overlap. In some embodiments, the system controller 126 delivers a gate signal to the gate drive circuits 418, 420, and 422 to enable the transistors 410, 412, and 414 of the modules 440, 442, and 444 to generate Fig. 11B The pulse sequence shown in . The system controller 126 may send gate signals including temporally overlapping pulses to the gate drive circuits 418, 420, 422. In FIG. 1100A, a gate signal (e.g., V1) is first applied to module 440 between time T1 and T2 to generate a trigger pulse TR1. Another gate signal is applied to module 442 between time T1 and T3 to generate a trigger pulse TR2. A third gate signal is applied to module 444 between time T1 and T4 to generate a trigger TR3. Here, the time interval between time T1 and T2 includes overlapping gate signals (e.g., V1) provided to the gate drive circuits 418, 420, 422, continuing to provide overlapping gate signals (e.g., V1) between time T2 and T3 to the gate drive circuits 420, 422, and continuing to provide gate signals (e.g., V1) to the gate drive circuit 422 during the time interval between T3 and T4. FIG. 1100B (as shown in FIG. 1100B) Fig. 11B The voltage pulses P1, P2, P3 generated at Fig.11A During the time interval between time T1 and T2, a first portion of pulses is generated, which includes pulses P1, P2 and P3 generated by modules 440, 442, 444, to produce a portion of a pulse having a voltage V2. During the time interval between time T2 and T3, a second portion of pulses is generated, which includes pulses P2 and P3 generated by modules 442 and 444, to produce a portion of a pulse having a voltage V3. During the time interval between time T3 and T4, a third portion of pulses is generated, which includes pulse P3 generated by module 444, to produce a portion of a pulse having a voltage V4. As shown in FIG. Fig. 11BAs shown in , portions of the pulse may repeat during time intervals T5 and T6, T6 and T7, and T7 and T8. In some embodiments, the pulses P1, P2, P3 provided to the gate drive circuits 418, 420, 422 are generated by the system controller such that at least portions of two or more pulses overlap in time. As described herein, the transformation ratios of the transformers in the modules 440, 442, 444 may be modified to customize the output voltage waveform of the pulser 400 to have different voltages and different pulse widths. Triggering multiple modules of the pulser 400 with different transformation ratios may allow the output signal shapes and pulse widths to overlap, which may allow the generation of waveforms that achieve a desired IEDF distribution during plasma processing.

[0074] Fig. 11C 1100D ( Fig.11D ) depicts an example of a voltage waveform resulting from the applied trigger pulses TR4, TR5, TR6 at time T 10 At time T 11 1100D is a diagram showing the states of transistors 410, 412, and 414 (e.g., Q1, Q2, Q3) when different gate signals are applied to each of the corresponding gate drive circuits 418, 420, 422 so that the gate signals overlap. In some embodiments, the system controller 126 may control the application of gate signals to the gate drive circuits 418, 420, 422 to enable the transistors 410, 412, and 414 of the modules 440, 442, and 444. The gate drive circuits 418, 420, 422 may apply gate signals so that the pulses overlap. In FIG. 1100C, the gate signal (e.g., V5) is first applied at time T9 and T 10 is applied to the module 440 to generate a trigger pulse TR4, and then at time T 10 With T 11 is applied to module 442 to generate a trigger pulse TR5, and finally at time T 11 With T12 is applied to module 444 to generate trigger pulse TR6. 10 The interval between the time T 10 With T 11 The intervals between them overlap, and at time T 10 With T 11 The interval between the time T 11 With T 12 1100D depicts the voltage seen at common node 480 as a result of the generated pulses P1, P2, P3 during their respective intervals. 10 During the interval between , pulse P1 generates voltage V6. 10 With T 11 During the interval between , pulse P2 generates voltage V7. 11 With T 12 During the interval between T and V, pulse P3 generates voltage V6. 13 -T 14 , T 14 -T 15 , and T 15 -T 16 In this example, pulses P4 and P6 both include a higher voltage (e.g., V6) than the voltage included in pulse P5 (e.g., V7), as shown. Triggering multiple modules of the pulser 400 where the modules are capable of generating different voltages can allow for the generation of various waveforms that achieve a desired IEDF distribution.

[0075] Fig.12 A charging circuit 1200 is depicted for charging a capacitive element 1212 according to certain aspects of the present disclosure. Capacitive element 1212 may correspond to any of capacitive elements 402, 404, and 406. In other words, a charging circuit (e.g., similar to charging circuit 1200) may be implemented for each of capacitive elements 402, 404, and 406 to charge the capacitive element to its corresponding voltage, as described herein. Charging circuit 1200 may include an inverter 1202 for converting a DC voltage into an alternating current (AC) voltage. The AC voltage may be provided to a primary winding 1206 of a transformer 1204. The transformer may generate an AC voltage at a secondary winding 1208 that is higher than the AC voltage at the primary winding 1206. For example, to charge inverter 1202, the AC voltage at the secondary winding 1208 may have a peak voltage of 1200 volts. The AC voltage at the secondary winding 1208 may be provided to a rectifier 1210 to generate a DC signal used to charge the capacitive element 1212 . Voltage waveform generation example

[0076] Fig.13 1 is a process flow diagram depicting a waveform generation method 1300 according to certain embodiments of the present disclosure. The method 1300 may be performed by a waveform generation system including a waveform generator such as the pulser 400 and / or a control circuit system such as the system controller 126. The following discussion of the method 1300 is in conjunction with Figure 4 As discussed above, in some embodiments, Figure 4 Common node 480 is shown configured to be coupled to an electrode within plasma processing system 10 .

[0077] At activity 1302, a waveform generator (e.g., pulser 400) delivers a first pulse from a first voltage level 444 at a first time. Delivering the first pulse from the first voltage level will include generating a first voltage pulse at a common node 480 by closing a first switch (e.g., transistor 414) coupled to a first voltage source 406 and a first transformer 470. The first voltage source 406 is configured to provide a first voltage V P1 to the primary winding 472 of the first transformer 470. The first transformer has a first transformation ratio, so that the second voltage V T2 is formed in the secondary winding 474 of the first transformer, wherein the second voltage V T2 Equal to the first voltage V P1 The common node 480 (which is coupled to the first terminal of the secondary winding 474) will then reach the formed first pulse, which includes the provided second voltage V T2 .

[0078] At activity 1304, the waveform generator (e.g., pulser 400) delivers a second pulse from the second voltage level 442 at a second time. Delivering the second pulse from the second voltage level 442 will include generating a second voltage pulse at the common node 480 by closing a second switch (e.g., transistor 412) coupled to the second voltage source 404 and the second transformer 460. The second voltage source 404 is configured to provide a third voltage V P3 to the primary winding 462 of the second transformer 460. The second transformer has a second transformation ratio, so that the fourth voltage V T4 is formed in the secondary winding 464 of the second transformer, wherein the fourth voltage V T4 Equal to the third voltage V P3 The common node 480 coupled to the first terminal of the secondary winding 464 will then realize the formed second pulse, which includes the provided fourth voltage V T4 When the second module 442 delivers the second pulse, the second pulse may be combined with the first pulse generated as desired provided in activity 1302, such as described above. Figures 5A-11DOne or more of the pulse configurations discussed.

[0079] At activity 1306, the waveform generator (e.g., pulser 400) delivers a third pulse from the third voltage level 440 at a third time. Delivering the third pulse from the third voltage level 440 will include generating a third voltage pulse at the common node 480 by closing a third switch (e.g., transistor 410) coupled to the third voltage source 402 and the third transformer 450. The third voltage source 402 is configured to provide a fifth voltage V P5 to the primary winding 452 of the third transformer 450. The third transformer has a third transformation ratio, so that the sixth voltage V T6 is formed in the secondary winding 464 of the second transformer, wherein the sixth voltage V T6 Equal to the fifth voltage V P5 The common node 480 coupled to the first terminal of the secondary winding 454 will then realize the formed third pulse, which includes the provided sixth voltage V T6 When the third module 442 delivers the third pulse, the third pulse may be combined with the first and / or second pulses generated as desired in activities 1302 and 1304, such as described above. Figures 5A-11D One or more of the pulse configurations discussed.

[0080] In some embodiments of method 1300, activities 1302, 1304, 1306 may each be separated by a time interval. In other embodiments of method 1300, the delivery of pulses provided during activities 1302, 1304, 1306 may be at least partially overlapping, as described above. As described herein, Figure 5A-Figure 5B and Figures 7A-11D The method 1300 mentioned in may involve triggering multiple modules of the pulser 400 with different transformation ratios during plasma processing to customize the output voltage waveform of the pulser 400 to have different voltages and different pulse widths so as to achieve waveform generation that can achieve a desired IEDF distribution during plasma processing.

[0081] In some embodiments, the third transformation ratio may be the same as the first transformation ratio or the second transformation ratio. In other embodiments, the third transformation ratio may be different from the first transformation ratio and the second transformation ratio. As described above, in some embodiments, the first transformation ratio, the second transformation ratio, and the third transformation ratio are all the same or all different from each other. In one example, the transformation ratio may be in a range between 1:1 and 1:4, such as between 1:1.5 and 1:4. In an alternative example, the transformation ratio may be in a range between 4:1 and 1:1, such as between 2:1 and 1.5:1.

[0082] In some embodiments, the first voltage V provided by the first voltage source 406, the second voltage source 404, and the third voltage source 402 are P1 , the third voltage V P3 , and the fifth voltage V P5 All are set to the same voltage level (eg, +100 volts to +800 volts). In some embodiments, the first voltage V P1 , the third voltage V P3 , and the fifth voltage V P5 One or more of the first voltage V P1 , the third voltage V P3 , and the fifth voltage V P5 is set to a voltage level ranging from +100 volts to +800 volts. In another example, the first voltage V P1 , the third voltage V P3 , and the fifth voltage V P5 is set to a voltage level ranging from 100 volts to 10,000 volts, such as 100 volts to 1,000 volts. In some embodiments, the polarity of the output voltage reached at common node 480 may be negative, and may be changed so that the voltage polarity is positive.

[0083] The processing chamber 100 includes a system controller 126, which includes a CPU 133, a memory 134, and support circuits 135, as described above. In some embodiments, the memory 134 may be a computer-readable medium memory configured to store instructions (e.g., computer executable code) that, when executed by the CPU 133, cause the processing chamber 100 to perform the operations depicted in FIG. Fig.13 The operations described above, or other operations for performing the various techniques discussed herein to provide voltage waveforms.

[0084] In some embodiments, CPU 133 has circuitry configured to implement code stored in a computer-readable medium, such as memory 134. For example, the circuitry includes circuitry for delivering a first pulse from a first voltage level (e.g., 444) at a first time and a second pulse from a second voltage level (e.g., 442) at a second time. In some embodiments, the circuitry includes circuitry for delivering a third pulse from a third voltage level (e.g., 440) at a third time. Additional Considerations

[0085] The term "coupled" is used herein to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B and object B contacts object C, objects A and C may still be considered coupled to each other—even if objects A and C are not in direct physical contact with each other. For example, a first object may be coupled to a second object even if the first object has never been in direct physical contact with the second object.

[0086] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, the scope of which is determined by the following claims.

Claims

1. A waveform generator, comprising: A first voltage level, the first voltage level having: a first voltage source; a first switch, wherein a first terminal of the first voltage source is coupled to a first terminal of the first switch; a ground reference point, wherein the second terminal of the first switch is coupled to the ground reference point; A transformer having a first transformation ratio, wherein the first transformer comprises: a primary winding coupled to a second terminal of the first voltage source and to the ground reference point; and a secondary winding having a first end and a second end, wherein the first end is coupled to the ground reference point; as well as A second voltage level, the second voltage level having: a second voltage source; a second switch, wherein a first terminal of the second voltage source is coupled to a first terminal of the second switch; a second ground reference point, wherein the second terminal of the second switch is coupled to the second ground reference point; A second transformer, the second transformer having a second transformation ratio, the second transformer comprising: a primary winding coupled to a second terminal of the second voltage source and the second ground reference point; and A secondary winding has a first end and a second end, wherein the first end is coupled to the second end of the secondary winding of the first transformer, and the second end is configured to be coupled to a load through a common node.

2. The waveform generator of claim 1, wherein The first voltage stage further comprises a first diode coupled in parallel with the primary winding of the first transformer, and The second voltage stage further includes a second diode coupled in parallel with the primary winding of the second transformer.

3. The waveform generator of claim 2, wherein the first diode is coupled to a first node and a second node, wherein the first node is between the second terminal of the voltage source and the first terminal of the primary winding, and the second node is between the first terminal of the first switch and the second terminal of the primary winding.

4. The waveform generator of claim 2, wherein the first diode comprises a body diode of the first switch, or the second diode comprises a body diode of the second switch.

5. The waveform generator of claim 1, wherein the first transformation ratio is different from the second transformation ratio.

6. The waveform generator of claim 5, wherein the first transformation ratio is smaller than the second transformation ratio.

7. The waveform generator of claim 5, wherein the first transformation ratio is greater than the second transformation ratio.

8. The waveform generator of claim 1, wherein the first switch comprises: a transistor, the transistor being a metal oxide semiconductor field effect transistor (MOSFET); and Gate drive circuit.

9. The waveform generator of claim 1, wherein the first voltage source comprises a capacitive element.

10. The waveform generator of claim 1, wherein the common node is configured to be capacitively coupled to a plasma formed in a processing region of a plasma processing system.

11. The waveform generator of claim 10, wherein the common node is coupled to a bias electrode disposed within a substrate support disposed within the plasma processing system.

12. The waveform generator of claim 1, further comprising a third voltage level, the third voltage level having: a third voltage source; a third switch, wherein the first terminal of the third voltage source is coupled to the first terminal of the third switch; a third ground reference point, wherein the second terminal of the third switch is coupled to the third ground reference point; A third transformer, the third transformer having a third transformation ratio, the third transformer comprising: a primary winding coupled to a second terminal of the third voltage source and the third ground reference point; and a secondary winding having a first end and a second end, the first end being coupled to the second end of the secondary winding of the second transformer, and the second end of the third transformer being configured to be coupled to the load through the common node; as well as A third diode is coupled in parallel with the primary winding of the second transformer.

13. A method for generating a voltage waveform, comprising the following steps: At a first time, a first voltage pulse is generated at a common node by closing a first switch having a first terminal and a second terminal, wherein: The first terminal of the first switch is coupled to a first terminal of the first voltage source; The second terminal of the first voltage source is coupled to a first terminal of a primary winding of a first transformer, the first transformer having a first transformation ratio; the second terminal of the first switch is coupled to the second terminal of the primary winding of the first transformer and to ground; as well as The common node is coupled to a first terminal of a secondary winding of the first transformer; as well as At a second time, a second voltage pulse is generated at the common node by closing a second switch having a first terminal and a second terminal, wherein: The first terminal of the second switch is coupled to the first terminal of the second voltage source; A second terminal of the second voltage source is coupled to a first terminal of a primary winding of a second transformer, the second transformer having a second transformation ratio; the second terminal of the first switch is coupled to the second terminal of the primary winding of the second transformer and to ground; generating, by the second voltage source, a second bias voltage between the first terminal and the second terminal of the second voltage source; and a first terminal of the secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer, The common node is arranged between the first terminal of the secondary winding of the first transformer and a load.

14. The method of claim 13, wherein the first voltage pulse overlaps with the second voltage pulse in time.

15. The method of claim 13, wherein the common node is coupled to a bias electrode disposed within a substrate support disposed within a plasma processing system.

16. The method of claim 13, wherein the first transformation ratio is different from the second transformation ratio. The method of claim 13 , wherein the first time overlaps with the second time.

18. The method of claim 13, further comprising the steps of: At a third time, a third voltage pulse is generated at the common node by closing a third switch having a first terminal and a second terminal, wherein: The first terminal of the third switch is coupled to a first terminal of a third voltage source; The second terminal of the third voltage source is coupled to a first terminal of a primary winding of a third transformer, and the third transformer has a third transformation ratio; The second terminal of the third switch is coupled to the second terminal of the primary winding of the third transformer and to ground; generating, by the third voltage source, a third bias voltage between the first terminal and the second terminal of the third voltage source; as well as A first terminal of the secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer.

19. The method of claim 18, wherein the third transformation ratio is different from the first transformation ratio and the second transformation ratio.

20. A non-transitory computer readable medium for generating a waveform, the non-transitory computer readable medium comprising instructions executable by one or more processors to: At a first time, a first voltage pulse is generated at a common node by closing a first switch having a first terminal and a second terminal, wherein: The first terminal of the first switch is coupled to a first terminal of the first voltage source; The second terminal of the first voltage source is coupled to a first terminal of a primary winding of a first transformer, the first transformer having a first transformation ratio; the second terminal of the first switch is coupled to the second terminal of the primary winding of the first transformer and to ground; as well as The common node is coupled to a first terminal of a secondary winding of the first transformer; as well as At a second time, a second voltage pulse is generated at the common node by closing a second switch having a first terminal and a second terminal, wherein: The first terminal of the second switch is coupled to the first terminal of the second voltage source; A second terminal of the second voltage source is coupled to a first terminal of a primary winding of a second transformer, the second transformer having a second transformation ratio; the second terminal of the first switch is coupled to the second terminal of the primary winding of the second transformer and to ground; generating, by the second voltage source, a second bias voltage between the first terminal and the second terminal of the second voltage source; and a first terminal of the secondary winding of the second transformer is coupled to a second terminal of the secondary winding of the first transformer, The common node is arranged between the first terminal of the secondary winding of the first transformer and a load.

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