Semiconductor device and electronic apparatus

Abstract

The invention provides a semiconductor device. The semiconductor device can easily inspect bonding between a cooler of a semiconductor element such as a Peltier element and a substrate in a PGA package. And an electronic apparatus including the semiconductor device. A semiconductor device according to the present disclosure has a configuration including: a semiconductor element; a cooler having a top surface bonded to the semiconductor element, and conducting heat generated by the semiconductor element to the heat dissipation portion; a semiconductor package having a cavity for accommodating the semiconductor element and the cooler; an electrode formed on the heat dissipation portion of the cooler; a terminal formed on a bottom surface of the cavity to face the electrode; a conductive resin through which the electrode is bonded to the terminal; and at least one conductive inspection pattern portion for detecting wet diffusion of the conductive resin interposed between the electrode and the terminal. An electronic device includes a semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device configured to cool a semiconductor element by using a cooling device for the semiconductor element provided in a semiconductor package with the cooling device for the semiconductor element such as a Peltier element interposed therebetween, and an electronic device including the semiconductor device. Background Art

[0002] In the past, with the miniaturization of semiconductor processes and the speed of semiconductor elements, the high integration of semiconductor elements has been promoted. With the high integration of semiconductor elements, various semiconductor structures and packages have emerged. In addition, with the high integration, the power consumption of semiconductor elements has also increased, and suppressing the temperature increase associated with this has become a problem.

[0003] As a structure for suppressing the temperature rise of a semiconductor device, for example, a packaging structure in which a heat sink or a Peltier element is mounted as a cooling device in the semiconductor device is known. However, when such an element is incorporated, the packaging structure of the semiconductor device becomes complicated, so there are problems such as that capital investment in the inspection process such as welding becomes expensive and that, for example, the production time becomes longer.

[0004] Patent document 1 discloses a semiconductor device, which includes: a semiconductor module; a heat sink base having a first surface to which the semiconductor module is attached and a second surface arranged on the opposite side of the semiconductor module relative to the first surface; and a heat sink including a plurality of heat sink portions arranged on the opposite side of the semiconductor module relative to the heat sink base, wherein the plurality of heat sink portions of the heat sink are joined to the second surface.

[0005] Specifically, in the semiconductor device, the semiconductor module is bonded to the first surface, which is the upper surface of the fin having a substantially rectangular shape and a substantially flat plate shape in a plan view, through a first welding portion. In addition, a plurality of fin portions are vertically arranged on a second surface, which is the lower surface of the fin base, each of the plurality of fin portions having a substantially truncated cone-shaped root portion and a substantially cylindrical shaft portion connected to the root portion.

[0006] The process configuration in which a plurality of heat sink portions are vertically arranged on the second surface of the heat sink base is as follows. That is, the semiconductor module is joined to the first surface, which is the upper surface of the fin plate, by the first welding portion. After that, the presence of defective solder, etc., is checked by an X-ray inspection device. Next, the plurality of heat sink portions are joined to the second surface, which is the lower surface of the heat sink base, which is a good product, by rotational friction welding. That is, first, the semiconductor module is welded to the heat sink base, and after the welding is checked, a plurality of heat sink portions are arranged in the vertical direction. The semiconductor device is formed by the above process.

[0007] As described above, since the semiconductor device is formed, it is not necessary to form projections and depressions such as a press-fit structure on the fin substrate, and it is not necessary to attach and detach the protective cover when attaching the semiconductor module to the first surface of the fin substrate. In addition, since the heat capacity and surface area of ​​the heat sink base are smaller than those in the case where the heat sink base is provided with a plurality of heat sink portions, the time required for bonding by the first solder portion is reduced.

[0008] Furthermore, when the bonding state of the semiconductor module is inspected by X-ray, the plurality of fins are not reflected, so that the time required for analyzing the X-ray inspection can be shortened and the cost can be reduced. As a result, a method for manufacturing a semiconductor device with high productivity and a semiconductor device can be provided.

[0009] Reference List

[0010] Patent Literature

[0011] Patent Document 1: Japanese Patent Application Publication No. 2021-158255 Summary of the invention

[0012] Problems to be solved by the present invention

[0013] As described above, in the semiconductor device described in Patent Document 1, after the semiconductor module is solder-joined to the first surface of a roughly flat heat sink base using a first solder portion, an X-ray inspection is performed, and after the X-ray inspection is completed, a plurality of heat sink portions are joined to the second surface by rotational friction welding to form a heat sink.

[0014] However, in the X-ray inspection, the inspection equipment is expensive, and it takes time to set up the X-ray inspection and the like.

[0015] In addition, when the semiconductor element or semiconductor module is fixed by soldering, there is a problem that the position and tilt cannot be controlled with high precision, which affects the tilt angle. In addition, when the semiconductor module as a heat source is soldered to the first surface of the heat sink base, the thermal conductivity of the solder is not necessarily high, so there is a problem of heat generation and voltage drop at the solder joint.

[0016] The present invention has been made in view of the above-mentioned problems, and its object is to provide a semiconductor device and an electronic device including the semiconductor device that can easily perform bonding inspection between a cooling device of a semiconductor element such as a Peltier element and a substrate in a semiconductor package such as a PGA package.

[0017] Solution to the problem

[0018] The present disclosure has been made to solve the above-mentioned problems, and a first aspect thereof is:

[0019] A semiconductor device, the semiconductor device comprising:

[0020] Semiconductor components;

[0021] a cooling device on which the semiconductor element is bonded to an upper surface to transfer heat generated by the semiconductor element to a heat dissipation portion;

[0022] A semiconductor package including a cavity for housing a semiconductor element and a cooling device;

[0023] an electrode formed in a heat dissipation portion of the cooling device;

[0024] a terminal formed on a bottom surface of the cavity to face the electrode;

[0025] Conductive resin that joins the electrodes and terminals together; and

[0026] At least one or more detection pattern parts have conductivity and are used to detect wet diffusion of the conductive resin between the electrode and the terminal.

[0027] In the first aspect, the detection pattern portion may be insulated and arranged on a surface where the terminal is formed, and wet spread of the conductive resin may be detected based on a capacitance value between the detection pattern portion and the terminal.

[0028] Furthermore, in the first aspect, the detection pattern portion may be arranged in a non-insulated manner on a surface on which the terminal is formed, and may be configured to detect wet diffusion of the conductive resin based on a resistance value between the detection pattern portion and the terminal.

[0029] In the first aspect, the detection pattern portion may be insulated and arranged on a surface on which the electrode is formed, and wet spread of the conductive resin may be detected based on a capacitance value between the detection pattern portion and the electrode.

[0030] Furthermore, in the first aspect, the detection pattern portion may be arranged in a non-insulated manner on a surface where the electrode is formed, and may be configured to detect wet spreading of the conductive resin based on a resistance value between the detection pattern portion and the electrode.

[0031] In the first aspect, the detection pattern portion may be insulated and arranged on a surface on which the electrode is formed, and wet spread of the conductive resin may be detected based on a capacitance value between the detection pattern portion and the terminal.

[0032] Furthermore, in the first aspect, the detection pattern portion may be arranged in a non-insulated manner on the surface where the electrode is formed, and may be configured to detect wet diffusion of the conductive resin based on a resistance value between the detection pattern portion and the terminal.

[0033] In the first aspect, the detection pattern portion may be insulated and arranged on a surface where the terminal is formed, and wet spread of the conductive resin may be detected based on a capacitance value between the detection pattern portion and the electrode.

[0034] Furthermore, in the first aspect, the detection pattern portion may be arranged in a non-insulated manner on the surface where the terminal is formed, and may be configured to detect wet diffusion of the conductive resin based on a resistance value between the detection pattern portion and the electrode.

[0035] In addition, in the first aspect, the detection pattern portion may be formed in a linear shape, and at least one detection pattern portion may be arranged between the plurality of terminals and between the terminal and the inner wall of the cavity.

[0036] In addition, in the first aspect, the detection pattern portion may be formed as a plurality of small detection pattern portions, and the plurality of detection pattern portions may be arranged between the plurality of terminals and between the terminals and the inner wall of the cavity.

[0037] In addition, in the first aspect, the detection pattern portion may be formed in a linear shape, and at least one detection pattern portion may be provided between the plurality of electrodes and between the electrode and the inner wall of the cavity.

[0038] In addition, in the first aspect, the detection pattern portion may be formed as a plurality of small detection pattern portions, and the plurality of detection pattern portions may be arranged between a plurality of electrodes and between the electrodes and an inner wall of the cavity.

[0039] Furthermore, in the first aspect, the small detection pattern portion may be formed in a substantially short straight line shape, a substantially rectangular shape, a substantially triangular shape, or a substantially circular shape in a plan view.

[0040] In the first aspect, the insulating material of the detection pattern portion may be aluminum oxide (Al 2 O 3 ).

[0041] Furthermore, in the first aspect, the insulating material of the detection pattern portion may be an insulating resin.

[0042] Furthermore, in the first aspect, the cooling device may include a Peltier element.

[0043] The second aspect of the present disclosure is

[0044] Electronic equipment, the electronic equipment including a semiconductor device, the semiconductor device including:

[0045] Semiconductor components;

[0046] a cooling device on which the semiconductor element is bonded to an upper surface to transfer heat generated by the semiconductor element to a heat dissipation portion;

[0047] A semiconductor package including a cavity for housing a semiconductor element and a cooling device;

[0048] an electrode formed in a heat dissipation portion of the cooling device;

[0049] a terminal formed on a bottom surface of the cavity to face the electrode;

[0050] Conductive resin that joins the electrodes and terminals together; and

[0051] At least one or more detection pattern parts have conductivity and are used to detect wet diffusion of the conductive resin between the electrode and the terminal.

[0052] By adopting the above aspect, it is possible to provide a semiconductor device capable of easily performing a bonding inspection between a cooling device for a semiconductor element such as a Peltier element bonded to the semiconductor element and a semiconductor package, and an electronic device having the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is an exploded perspective view of a semiconductor device according to the present disclosure.

[0054] Figure 2 is a plan view of a first embodiment of a semiconductor device according to the present disclosure.

[0055] Figure 3 XX is a cut end view of the semiconductor device according to the first embodiment of the present disclosure.

[0056] Figure 4 It is an explanatory diagram of the inspection method when there is no wet diffusion in the first embodiment of the semiconductor device according to the present disclosure.

[0057] Figure 5 It is an explanatory diagram of an inspection method when wet diffusion occurs in the first embodiment of the semiconductor device according to the present disclosure.

[0058] Figure 6 It is an explanatory diagram of the manufacturing process of the first embodiment of the semiconductor device according to the present disclosure (part 1).

[0059] Figure 7 It is a figure (part 2) explaining the manufacturing process of the semiconductor device of this first embodiment.

[0060] Figure 8 It is an explanatory diagram of the manufacturing process of the first embodiment of the semiconductor device according to the present disclosure (Part 3).

[0061] Fig. 9 It is an explanatory diagram of the manufacturing process of the first embodiment of the semiconductor device according to the present disclosure (Part 4).

[0062] Fig.10 It is a diagram for explaining the manufacturing process of the semiconductor device according to the first embodiment (part 5).

[0063] Fig.11 It is an explanatory diagram of the manufacturing process of the first embodiment of the semiconductor device according to the present disclosure (Part 6).

[0064] Fig.12 It is an explanatory diagram of the manufacturing process of the first embodiment of the semiconductor device according to the present disclosure (Part 7).

[0065] Fig.13 It is a diagram (part 8) for explaining the manufacturing process of the semiconductor device according to the first embodiment.

[0066] Fig.14 It is an explanatory diagram of the manufacturing process of the first embodiment of the semiconductor device according to the present disclosure (Part 9).

[0067] Fig.15 is a plan view of a second embodiment of a semiconductor device according to the present disclosure.

[0068] Fig.16 XX is a cut end view of the second embodiment of the semiconductor device according to the present disclosure.

[0069] Fig.17 It is a diagram for explaining an inspection method when there is no wet diffusion in the second embodiment of the semiconductor device of the present disclosure.

[0070] Fig.18 It is a diagram for explaining an inspection method when wet diffusion occurs in the second embodiment of the semiconductor device according to the present disclosure.

[0071] Fig.19 is a plan view of a third embodiment of a semiconductor device according to the present disclosure.

[0072] Fig. 20 XX is a cut end view of the third embodiment of the semiconductor device according to the present disclosure.

[0073] Fig.21 It is a diagram for explaining an inspection method when there is no wet diffusion in the semiconductor device according to the third embodiment of the present disclosure.

[0074] Fig. 22 It is a diagram for explaining an inspection method when wet diffusion occurs in the semiconductor device according to the third embodiment of the present disclosure.

[0075] Fig.23 is a plan view of a fourth embodiment of a semiconductor device according to the present disclosure.

[0076] Fig.24 XX is a cut end view of the fourth embodiment of the semiconductor device according to the present disclosure.

[0077] Fig.25 It is an explanatory diagram of an inspection method when there is no wet diffusion in the semiconductor device according to the fourth embodiment of the present disclosure.

[0078] Fig.26 It is an explanatory diagram of an inspection method when wet diffusion occurs in the fourth embodiment of the semiconductor device according to the present disclosure.

[0079] Fig. 27 It is an explanatory diagram of an inspection method when there is no wet diffusion in the fifth embodiment of the semiconductor device according to the present disclosure.

[0080] Fig.28 It is an explanatory diagram of an inspection method when wet diffusion occurs in a semiconductor device according to a fifth embodiment of the present disclosure.

[0081] Fig.29 It is an explanatory diagram of an inspection method when there is no wet diffusion in the sixth embodiment of the semiconductor device according to the present disclosure.

[0082] Fig.30 1 is an explanatory diagram of an inspection method when wet diffusion occurs in the sixth embodiment of the semiconductor device according to the present disclosure.

[0083] Fig.31 It is a plan view of a first modification example of the first embodiment or the second embodiment of the semiconductor device according to the present disclosure.

[0084] Fig.32 It is a plan view of a second modification example of the first embodiment or the second embodiment of the semiconductor device according to the present disclosure.

[0085] Fig.33 1 is a plan view of a first modified example of the third to sixth embodiments of the semiconductor device according to the present disclosure.

[0086] Fig.34 1 is a Y1 - Y1 line cut end view of a first modified example of the semiconductor device according to the third embodiment to the sixth embodiment of the present disclosure.

[0087] Fig.35 1 is a Y2 - Y2 line cut end view of a first modified example of the third to sixth embodiments of the semiconductor device according to the present disclosure.

[0088] Fig.361 is a plan view of a second modification example of the third to sixth embodiments of the semiconductor device according to the present disclosure.

[0089] Fig.37 1 is a Y3 - Y3 line cut end view of the second modified example of the semiconductor device according to the third embodiment to the sixth embodiment of the present disclosure.

[0090] Fig.38 is a block diagram of an electronic device including a semiconductor device according to the present disclosure. DETAILED DESCRIPTION

[0091] Next, the modes for implementing the semiconductor device according to the present disclosure (hereinafter, they are referred to as "embodiments") will be described in the following order with reference to the accompanying drawings. In the following drawings, the same or similar parts are represented by the same or similar reference numerals. However, the drawings are schematic, and the size ratios of the parts are not necessarily consistent with the actual size ratios. In addition, in the description of the drawings, of course, parts with different size relationships and ratios are also included.

[0092] 1. First Embodiment of Semiconductor Device According to the Present Disclosure

[0093] 2. Manufacturing process of the first embodiment of the semiconductor device according to the present disclosure

[0094] 3. Second Embodiment of Semiconductor Device According to the Present Disclosure

[0095] 4. Third Embodiment of Semiconductor Device According to the Present Disclosure

[0096] 5. Fourth Embodiment of Semiconductor Device According to the Present Disclosure

[0097] 6. Fifth Embodiment of Semiconductor Device According to the Present Disclosure

[0098] 7. Sixth Embodiment of Semiconductor Device According to the Present Disclosure

[0099] 8. Modification of the first embodiment of the semiconductor device according to the present disclosure

[0100] 9. Modification of the Second Embodiment of the Semiconductor Device According to the Present Disclosure

[0101] 10. First Modification Example of First Embodiment or Second Embodiment of Semiconductor Device According to the Present Disclosure

[0102] 11. Second Modification Example of First Embodiment or Second Embodiment of Semiconductor Device According to the Present Disclosure

[0103] 12. First Modification of the Third to Sixth Embodiments of the Semiconductor Device According to the Present Disclosure

[0104] 13. Second Modification of the Third to Sixth Embodiments of the Semiconductor Device According to the Present Disclosure

[0105] 14. Electronic equipment including the semiconductor device according to the present disclosure

[0106] <1. First Embodiment of Semiconductor Device According to the Present Disclosure>

[0107] [Basic Configuration of First Embodiment]

[0108] Figure 1 1 is an exploded perspective view of a first embodiment of a semiconductor device 101 according to the present disclosure. The semiconductor device 101 is configured such that a semiconductor element 10 is bonded to the upper surface of a Peltier element 20 as a cooling device through a die bonding material 11, the Peltier element 20 is bonded to terminals 61, 62 on a substrate 50 provided in a cavity 35 of a PGA package 30 through conductive resins 71, 72, and a glass cover 32 is placed on the cavity 35. Here, the cooling device of the semiconductor element 10 is not limited to the Peltier element 20, and may be other cooling devices.

[0109] The pin grid array (PGA) package 30 is a type of semiconductor package and includes a glass cover 32. The PGA package 30 has the following functions: accommodating a semiconductor element 10 inside, supplying power to the semiconductor element 10, etc., inputting and outputting signals from an external device, protecting the semiconductor element 10 from the external environment, dissipating the heat generated by the semiconductor element 10 to the outside, and cooling the semiconductor element. Therefore, the PGA package 30 includes a package frame body 31, the outer periphery of which has a substantially square shape, and in which a cavity 35 having a square shape and a step is formed in the center portion. Then, a plurality of pins 34 for external connection are vertically arranged on the lower surface of the package frame body 31. The cavity 35 is a storage space for the semiconductor element 10 and a cooling device, etc. On the substrate 50 as the bottom of the cavity 35, the Peltier element 20 having the semiconductor element 10 bonded to the upper surface is bonded via conductive resins 71 and 72.

[0110] Then, if Figure 1 As shown, a glass cover 32 is placed and welded on the upper surface of the PGA package 30 so as to cover the cavity 35 , thereby protecting the semiconductor element 10 and the like from the external environment.

[0111] The first embodiment of the semiconductor device 101 according to the present disclosure is generally configured as described above.

[0112] Hereinafter, the basic configuration of the first embodiment will be described in more detail with reference to the drawings.

[0113] Figure 2 1 is a plan view of the PGA package 30 before the Peltier element 20 is bonded to the substrate 50 in the first embodiment. Figure 3 yes Figure 2 The XX line cutting end view in FIG. 1 (hereinafter, the drawings may be referred to as "X end view" and "plan view" respectively). The same applies to the following.

[0114] In addition, for example, the direction of the cutting line parallel to the XX line cutting end surface is referred to as the "X direction", the right direction in the drawings is referred to as the "right side", and the left direction in the drawings is referred to as the "left side". In addition, the direction orthogonal to the "X direction" is referred to as the "Y direction", and the upward direction and the downward direction in the drawings are referred to as the "upper side" and the "lower side", respectively.

[0115] In the following description, although not shown in the drawings, the electrodes 21 and 22 and the conductive wire portions such as the terminals 61 and 62 are electrically insulated from other electrodes or conductive portions.

[0116] On the lower surface of the PGA package 30, as Figure 3 As shown, in order to supply power to the semiconductor element 10 or the Peltier element 20 and input and output signals from an external device to an external device, a plurality of predetermined metal pins 34 are vertically arranged by copper welding or the like. Here, the semiconductor element 10 is an integrated circuit chip formed on a silicon substrate, and is, for example, a solid-state imaging element, a microprocessor, a memory, a logic circuit, a power element, or the like.

[0117] The wiring between the semiconductor element 10 and each lead 34 is specifically as follows. First, Figure 3 As shown, a connection terminal 10a is arranged on the periphery of the upper surface of the semiconductor element 10. A step is formed on the inner peripheral surface of the cavity 35, and a connection terminal 31a is arranged on the step. Then, the connection terminal 10a and the connection terminal 31a are connected to each other by wire bonding such as gold wire (Au) 33. The connection terminal 31a in the cavity 35 is connected to the pin 34 through the wiring 31b, the via 31c and the pad 31d formed inside the package frame body 31 and the substrate 50.

[0118] As described above, the electrical connection between the semiconductor element 10 and the pins 34 is formed. However, the wiring 31b, the via 31c, and the pad 31d shown in the figure are part of them, and the connection state of the other pins 34 is omitted. Figure 3 In other drawings, the connection terminals 10a and 31a forming the above-mentioned electrical connection, the gold wire (Au) 33 for wire bonding connection, the wiring 31b, the via 31c, the pad 31d, etc. are omitted to avoid complication.

[0119] The Peltier element 20 is a cooling device utilizing the Peltier effect. Specifically, when the P-type semiconductor 26 and the N-type semiconductor 25 are connected in series, and, for example, a DC current is caused to flow from the N-type semiconductor 25 in a direction toward the P-type semiconductor 26, heat is absorbed (cooled) at the connection portion between the P-type semiconductor 26 and the N-type semiconductor 25, and heat is dissipated (generated) on each side of the anode side of the N-type semiconductor 25 and the cathode side of the P-type semiconductor 26.

[0120] In a first embodiment of a semiconductor device 101 according to the present disclosure, as Figure 2 As shown, terminals 61 and 62 having a roughly rectangular shape in the Y direction are arranged side by side at a roughly central portion of the upper surface of a substrate 50 having a roughly square shape in a plan view. Then, between the terminals 61 and 62, a detection pattern portion 51 is arranged in the Y direction at intervals roughly equal to the terminals 61 and 62. In addition, on the right side of the terminal 61, a detection pattern portion 52 is arranged along the right side in the Y direction. Similarly, on the left side of the terminal 62, a detection pattern portion 53 is arranged in the Y direction along the left side. That is, the detection pattern portion 52, the terminal 61, the detection pattern portion 51, the terminal 62, and the detection pattern portion 53 are arranged in parallel in sequence from the right side in the figure.

[0121] The detection pattern portions 51 , 52 , and 53 have conductivity and serve as sensors for detecting the wet diffusion of the conductive resins 71 and 72 when the Peltier element 20 is bonded.

[0122] The detection pattern portions 51, 52, 53 are covered with insulators 51b, 52b, 53b, respectively, and are electrically insulated. The insulators 51b, 52b, and 53b include, for example, alumina (Al2O3) or insulating resin.

[0123] like Figure 2 As shown, the detection pattern portion 52 extends obliquely from its upper end to the upper right, and the inspection terminal 52a is connected to the extended end. As shown in the figure, the detection pattern portion 53 extends obliquely from its upper end to the upper left, and the inspection terminal 53a is connected to the extended end. In addition, as shown in the figure, the detection pattern portion 51 extends linearly from the lower end toward the lower side, and the inspection terminal 51a is connected to the extended end.

[0124] like Figure 2As shown, in terminal 61, wiring pattern 61d is led out obliquely from its lower right corner to the lower right side, and inspection terminal 61a is connected to the lead-out terminal. In addition, as shown in the figure, in terminal 62, wiring pattern 62d is led out obliquely from its lower left corner to the lower left side, and inspection terminal 62a is connected to the lead-out terminal. Inspection terminals 51a, 52a, 53a, 61a and 62a are terminals for connecting probes of flight inspection instruments, etc., and are used to check the wet diffusion of conductive resins 71 and 72 by contact, etc.

[0125] like Figure 1 or Figure 2 As shown in FIG. 1 , conductive resins 71 and 72 are applied to the upper surfaces of the terminals 61 and 62, respectively. Figure 1 or Figure 3 As shown, Peltier element 20 bonded with semiconductor element 10 is arranged on conductive resins 71, 72 and bonded to substrate 50. As a result, electrodes 21, 22 on the lower surface of Peltier element 20 are electrically connected to terminals 61, 62 on substrate 50 through conductive resins 71, 72, respectively.

[0126] exist Figure 3 In the figure, the Peltier element 20 has a structure in which a plurality of N-type semiconductors 25 and a plurality of P-type semiconductors 26 having a substantially rectangular shape are arranged on the upper surface on the heat dissipation side of a ceramic substrate 24 (hereinafter, referred to as a "heat dissipation plate 24") and on the upper surface thereof, a ceramic substrate 23 (hereinafter, referred to as a "heat absorption plate 23") is placed on the heat absorption side bonded to the semiconductor element 10, and the N-type semiconductors 25 and the P-type semiconductors 26 are sandwiched between the heat dissipation plate 24 and the heat absorption plate 23. Then, the N-type semiconductors 25 and the P-type semiconductors 26 are connected together in series to form a cooling circuit (in the figure, a circuit diagram is not shown).

[0127] Specifically, the circuit including the N-type semiconductor 25 and the P-type semiconductor 26 is configured such that one end of the N-type semiconductor 25 and one end of the P-type semiconductor 26 are connected together, the other end of the N-type semiconductor 25 is connected to the electrode 22 serving as an anode, the other end of the P-type semiconductor 26 is connected to the electrode 21 serving as a cathode, and a DC voltage is applied between the electrodes 22 and 21 to flow a DC current. That is, a DC circuit is formed by the terminal 62, the conductive resin 72, the electrode 22, the N-type semiconductor 25, the P-type semiconductor 26, the electrode 21, the conductive resin 71, and the terminal 61.

[0128] When a DC current is caused to flow through the circuit configured as described above, the connection side between one end of the N-type semiconductor 25 and one end of the P-type semiconductor 26 absorbs heat generated by the semiconductor element 10 through the heat absorbing plate 23 as a heat absorbing portion. On the other hand, the electrode 22 side to which the other end of the N-type semiconductor 25 is connected and the electrode 21 side to which the other end of the P-type semiconductor 26 is connected transfer heat to the heat dissipation plate 24 as a heat dissipation portion.

[0129] The heat dissipation plate 24 transfers heat to the PGA package 30 via the electrodes 21, 22, the conductive resins 71, 72, and the terminals 61, 62. Since the PGA package 30 includes, for example, ceramics having excellent thermal conductivity, the PGA package 30 itself dissipates heat to the atmosphere to cool the semiconductor element 10. Alternatively, in the case where the PGA package 30 includes a heat sink (not shown), the heat is transferred to the heat sink, and the heat sink dissipates the heat to the atmosphere to cool the semiconductor element 10. That is, the heat generated by the semiconductor element 10 is dissipated to the atmosphere. Figure 3 The structure of cooling the semiconductor element 10 by using the Peltier element 20 is as described above.

[0130] Note that a circuit formed by a combination of the N-type semiconductor 25 and the P-type semiconductor 26 can be further connected in series, or a circuit formed by the N-type semiconductor 25 and the P-type semiconductor 26 can be connected in parallel by appropriately performing insulation treatment on the heat absorbing plate 23 and the heat dissipating plate 24. Such a DC circuit can be formed by arranging a desired number of N-type semiconductors 25 and P-type semiconductors 26.

[0131] Here, as described above, the terminals 61, 62 of the substrate 50 and the electrodes 21, 22 of the Peltier element 20 are electrically and thermally connected respectively by the conductive resins 71, 72. The conductive resins 71, 72 are, for example, silver (Ag) paste, sintered copper solder paste, or diamond paste, etc., which have excellent adhesion and thermal conductivity compared to silver paste. Silver paste is, for example, a conductive bonding material in which conductive silver (Ag) particles are dispersed in a resin paste such as epoxy resin or polyurethane.

[0132] In recent years, in the solid-state imaging device 100, the requirement for tilt accuracy has become serious due to the increase in resolution and the increase in optical size. In the case where the semiconductor element 10 of the solid-state imaging device 100 is fixed by welding, the position and tilt of the component are determined by self-alignment. On the other hand, in the case of fixing with the conductive resins 71 and 72, it is determined by the posture at the time of installation. Then, in the case of fixing with the conductive resins 71 and 72, it can be strictly controlled. Therefore, the conductive resins 71 and 72 can cope with the accuracy requirement of tilt accuracy higher than welding.

[0133] In addition, in the case of the conductive resins 71 and 72, materials having excellent thermal conductivity have appeared in recent years. For example, sintered copper solder paste has a thermal conductivity of 180 W / (m·K), and has a sufficiently high thermal conductivity relative to the thermal conductivity of 30 W / (m·K) of a general high-lead solder. For this reason, it can be said that the conductive resins 71 and 72 are the best die bonding materials for counteracting the temperature increase of the semiconductor device 101 compared to solder.

[0134] However, since the conductive resins 71 and 72 are liquid immediately after being applied, when the Peltier element 20 is bonded to the substrate 50, moisture diffusion may occur between the electrode 21 of the heat sink 24 and the terminal 61 of the substrate 50, or between the electrode 22 and the terminal 62. As a result, there is a problem of short circuit between the terminals 61 and 62 or between the electrodes 21 and 22 due to moisture diffusion.

[0135] Furthermore, when the Peltier element 20 is bonded to the substrate 50, the conductive resins 71 and 72 are hidden under the lower surface of the Peltier element 20, and therefore, there is no simple method for nondestructively confirming the wet state thereof. For example, a configuration can be made in which X-rays or the like can be used and confirmation is performed, but there is a problem that it takes time to set up and confirm, and expensive inspection equipment is required.

[0136] In addition, as the package becomes smaller, the gap between the peripheral portion of the Peltier element 20 or substrate 50 and the side wall of the resonant cavity 35 becomes narrower, and the conductive resin 71, 72 protruding from the lower surface of the Peltier element 20 reaches the side wall of the resonant cavity 35. In extreme cases, the conductive resin may climb up the side wall.

[0137] Therefore, in the first embodiment of the semiconductor device 101 according to the present disclosure, as Figure 2 As shown in the figure, the detection pattern portion 51 is arranged between the terminals 61 and 62, the detection pattern portion 52 is arranged on the right side surface of the terminal 61, and the detection pattern portion 53 is arranged on the left side surface of the terminal 62. Moreover, the inspection terminals 51a, 52a, 53a are connected to the detection pattern portions 51, 52, 53 respectively. In addition, as shown in the figure, the inspection terminals 61a and 62a are connected to the terminals 61 and 62 respectively.

[0138] As described above, according to the first embodiment of the semiconductor device 101 of the present embodiment, the bonding inspection between the Peltier element 20 and the substrate 50 provided in the cavity 35 of the PGA package 30 can be easily performed using the inspection terminals 51 a , 52 a , 53 a , 61 a , and 62 a .

[0139] [Wet Diffusion Inspection Method of First Embodiment]

[0140] Next, an inspection method for inspecting wet diffusion of the conductive resins 71 and 72 through the inspection terminals 51 a , 52 a , and 53 a connected to the detection pattern portions 51 , 52 , and 53 and the inspection terminals 61 a and 62 a connected to the terminals 61 and 62 will be described below.

[0141] Figure 4 It means in Figure 3 The X-end view shown is a partially enlarged explanatory view of the bonding state when no wet diffusion of the conductive resin 71, 72 occurs between the terminals 61, 62 of the substrate 50 and the electrodes 21, 22 of the Peltier element 20. Figure 4 In the illustrated embodiment, an appropriate amount of conductive resin 72 is applied between the electrode 22 and the terminal 62. Similarly, an appropriate amount of conductive resin 71 is also applied between the electrode 21 and the terminal 61. For this reason, wet diffusion of the conductive resins 72 and 71 does not occur between the electrode 22 and the terminal 62 and between the electrode 21 and the terminal 61.

[0142] In this state, the capacitance Cx is measured between the terminal 62 and the detection pattern portion 53 on the substrate 50. The capacitance Cx is measured, for example, by applying a measurement probe (not shown, the same below) to the inspection terminal 62a connected to the terminal 62 and the inspection terminal 53a connected to the detection pattern portion 53, respectively, by a flying inspector (not shown, the same below).

[0143] Here, the flying inspector refers to an inspection jig (hereinafter, referred to as "inspector") that applies a probe (a needle that contacts or is inserted into an object to be measured, tested, or inspected) to determine open / short of a mounted component such as a substrate.

[0144] exist Figure 4 In the illustrated example, since wet diffusion of the conductive resin 72 does not occur between the terminal 62 and the detection pattern portion 53 , the value of the capacitance Cx between the terminal 62 and the detection pattern portion 53 is substantially zero (0).

[0145] Similarly, the capacitance Cy is measured between the terminal 62 and the detection pattern portion 51 on the substrate 50. The capacitance Cy is measured by the inspector by applying a measurement probe to the inspection terminal 62a connected to the terminal 62 and the inspection terminal 51a connected to the detection pattern portion 51. Figure 4 In the illustrated example, since wet diffusion of the conductive resin 72 does not occur between the terminal 62 and the detection pattern portion 51 , the value of the capacitance Cy between the terminal 62 and the detection pattern portion 51 is substantially zero (0).

[0146] Likewise, the capacitance Cx between the terminal 61 on the substrate 50 and the detection pattern portion 52 and the capacitance Cy between the terminal 61 and the detection pattern portion 51 are measured. The method of measuring the capacitances Cx and Cy is similar to the above-described measurement method, and thus a description thereof will be omitted.

[0147] exist Figure 4 In the illustrated embodiment, since no wet diffusion of the conductive resin 71 occurs between the terminal 61 and the detection pattern portion 52 and between the terminal 61 and the detection pattern portion 51, the value of the capacitance Cx between the terminal 61 and the detection pattern portion 52 and the value of the capacitance Cy between the terminal 61 and the detection pattern portion 51 are substantially zero (0).

[0148] Figure 5 It means in Figure 3 FIG. 1 is an explanatory diagram of a partially enlarged view of a bonding state when wet diffusion of the conductive resin 72 occurs between the substrate 50 and the Peltier element 20 in the X-end view shown. Figure 5 In the illustrated embodiment, an appropriate amount of conductive resin 71 is applied between the electrode 21 and the terminal 61. However, a large amount of conductive resin 72 is applied between the electrode 22 and the terminal 62. For this reason, wet diffusion of the conductive resin 72 occurs between the electrode 22 and the terminal 62.

[0149] In this state, the capacitance Cx is measured between the terminal 62 and the detection pattern portion 53 on the substrate 50. Figure 4 The measurement of capacitance Cx is performed similarly to the description. Figure 5 In the illustrated embodiment, since wet diffusion of the conductive resin 72 occurs between the terminal 62 and the detection pattern portion 53 , the value of the capacitance Cx between the terminal 62 and the detection pattern portion 53 is not zero (0).

[0150] Specifically, the conductive resin 72 reaches the insulator 53b covering the detection pattern portion 53 due to wet diffusion, and covers the insulator 53b. Thus, a structure is formed in which the insulator 53b as a dielectric is sandwiched between the detection pattern portion 53 as a conductor and the conductive resin 72. Thus, a capacitor C1 is formed between the conductive resin 72 and the detection pattern portion 53.

[0151] Thus, when the capacitance Cx is measured between the inspection terminal 62a and the inspection terminal 53a, the capacitance C1 formed between the conductive resin 72 and the detection pattern portion 53 can be obtained. As a result, it can be known that the conductive resin 72 wet-spreads and reaches the detection pattern portion 53.

[0152] Likewise, the capacitance Cy is measured between the terminal 62 and the detection pattern portion 51. The capacitance Cy is measured similarly to that described in Figure 4 proceed as described. Figure 5In the illustrated example, since wet diffusion of the conductive resin 72 occurs between the terminal 62 and the detection pattern portion 51 , the value of the capacitance Cy between the terminal 62 and the detection pattern portion 51 is not zero (0).

[0153] That is, the conductive resin 72 reaches the insulator 51b covering the detection pattern portion 51 due to wet diffusion and covers the insulator 51b. Therefore, a structure is formed in which the insulator 51b as a dielectric is sandwiched between the detection pattern portion 51 as a conductor and the conductive resin 72, and a capacitor C2 is formed between the conductive resin 72 and the detection pattern portion 51.

[0154] Thus, when the capacitance Cy is measured between the inspection terminal 62a and the inspection terminal 51a, the capacitance C2 formed between the conductive resin 72 and the detection pattern portion 51 can be obtained. As a result, it can be known that the conductive resin 72 wet-spreads and reaches the detection pattern portion 51.

[0155] Note that Figure 5 In the illustrated embodiment, since no wet diffusion of the conductive resin 71 occurs between the terminal 61 and the detection pattern portion 52 and between the terminal 61 and the detection pattern portion 51, the value of the capacitance Cx between the terminal 61 and the detection pattern portion 52 and the value of the capacitance Cy between the terminal 61 and the detection pattern portion 51 are substantially zero (0).

[0156] <2. Manufacturing Process of First Embodiment of Semiconductor Device According to the Present Disclosure>

[0157] Next, a description will be given of a manufacturing process of the first embodiment of the semiconductor device 101 according to the present disclosure. Figures 6 to 14 It is an X-end view for explaining the manufacturing process of the semiconductor device 101 in the first embodiment.

[0158] First, if Figure 6 As shown, a green sheet 90 is prepared. The green sheet 90 is obtained by mixing ceramic raw material powder with a binder and the like to form a paste, thinly stretching the paste on a plastic carrier film to form a sheet, and drying the sheet.

[0159] Then, if Figure 7 As shown, a paste-like conductive material is printed on a green sheet 90 according to the shapes of the terminals 61, 62, the detection pattern portions 51, 52, 53, etc. Note that, although not shown in the figure, this also applies to the inspection terminals 51a, 52a, 53a, 61a and 62a. In addition, the conductive material is, for example, a conductive metal material such as tungsten (W).

[0160] Next, if Figure 8As shown, an alumina coating for forming insulators 51b, 52b, and 53b is applied on the detection pattern portions 51, 52, and 53. In this way, a laminated body including the green sheets 90 is formed.

[0161] Then, if Fig. 9 As shown, the laminated body including the green sheet 90 is sintered. As a result, the ceramic material on the green sheet 90 forms the ceramic substrate 50. In addition, the conductive material on the substrate 50 forms the terminals 61, 62, the detection pattern portions 51, 52, 53, the inspection terminals 51a, 52a, 53a, 61a, 62a, etc. (not shown). In addition, the alumina coating on the detection pattern portions 51, 52, and 53 forms the insulators 51b, 52b, and 53b including alumina (Al2O3) covering the detection pattern portions 51, 52, and 53 by a sintering process.

[0162] The plastic carrier film forming the green sheet 90 is burned, and the substrate 50, the terminals 61, 62 and the detection pattern portions 51, 52, 53 on the substrate 50 including sintered ceramics remain. In addition, the inspection terminals 51a, 52a, 53a, 61a, 62a, etc. (not shown) remain.

[0163] In addition, the insulators 51b, 52b, and 53b may include insulating resin. In this case, Figure 8 The process of forming the aluminum oxide coating shown is not necessary. Instead, it is only necessary to provide a process of forming an insulating resin on the upper surfaces of the detection pattern parts 51, 52, and 53.

[0164] Notice, Fig. 9 The sintering process shown is not actually Figure 8 The laminated body including one green sheet 90 shown is performed in a single state, but in the state described later Fig.11 The packaging frame body 31 is shown in the state of being stacked. That is, the packaging frame body 31 is formed by sequentially stacking a plurality of green sheets 90 of a plurality of types. Thus, when a plurality of green sheets 90 of a plurality of types are sequentially stacked to form the packaging frame body 31, Figure 8 The stacked body including the green sheets 90 shown is stacked together with other green sheets 90. Then, after stacking, the formed package frame body 31 is sintered, thereby also forming a cavity 35 in the package frame body 31. Fig. 9 The substrate 50 is shown in FIG.

[0165] Then, if Fig.10As shown, the terminals 61 and 62 and the inspection terminals 51a, 52a, 53a, 61a, and 62a formed by sintering with a conductive metal 65 such as gold (Au) are subjected to electroplating. That is, the conductor parts (such as the terminals 61 and 62 including tungsten (W) formed by sintering) are covered with a conductive metal 65 such as gold (Au). Note that Fig. 9 The process is similar to that described later. Fig.12 The electroplating process is actually performed in the electroplating process of the entire package frame body 31 shown in FIG.

[0166] Next, an embodiment of forming the package frame body 31 will be described in detail. Among the plurality of raw sheets 90 forming the package frame body 31, in the raw sheet 90 forming the cavity 35, a square hole as the cavity 35, a small hole as the via 31c, etc. are drilled by punching or the like. In addition, on the raw sheet 90 that becomes the wiring layer, a prescribed conductive material is printed in the shape of the pattern of the wiring 31b. Similarly, on the raw sheet 90 on which the pin 34 is vertically arranged, a predetermined conductive material is printed in the shape of the pattern of the pad 31d. In addition, in the raw sheet 90 for ensuring the thickness, a small hole as the via 31c, etc. is drilled. Then, a plurality of raw sheets 90 of multiple types are sequentially stacked in a predetermined order to have a predetermined thickness.

[0167] In this lamination process, Figure 8 The stacked body including the green sheets 90 formed in the illustrated process is stacked at the uppermost position of the bottom of the cavity 35 .

[0168] The plurality of green sheets 90 of various types stacked as described above are formed into a predetermined package frame body 31. Then, the formed package frame body 31 is sintered. As a result, a package frame body 31 is formed as shown in FIG. Fig.11 The package frame body 31 is shown. In the cavity 35, the connection terminal 31a, the wiring 31b, the via 31c, the pad 31d, etc. are formed to be connected to the reference numeral 31 through the wire bonding, etc. (none of which is shown in the figure). Figure 3 The semiconductor element 10 is described. In addition, Fig. 9 The terminals 61 and 62 , the detection pattern portions 51 , 52 , and 53 , the insulators 51 b , 52 b , and 53 b , and the like described in FIG. 5 are formed on the substrate 50 which is the bottom of the cavity 35 .

[0169] Then, if Fig.12 As shown, a plurality of metal pins 34 for supplying power to the semiconductor element 10 and the Peltier element 20 and inputting and outputting signals from external devices are vertically arranged on the pads 31d formed on the lower surface of the package frame body 31 by copper welding or the like. Then, a predetermined plating process or the like is performed.

[0170] In this process, as mentioned above Fig.10As depicted, these conductor portions (eg, terminals 61 and 62) are also covered with a conductive metal 65 (eg, gold (Au)).

[0171] Then, if Fig.13 As shown, appropriate amounts of conductive resins 71 and 72 are applied to the upper surfaces of the terminals 61 and 62, respectively.

[0172] Then, if Fig.14 As shown in FIG. 1 , the Peltier element 20 bonded with the semiconductor element 10 is arranged on the upper surface of the applied conductive resins 71 and 72, and they are bonded, and the conductive resins 71 and 72 are thermally cured. As a result, the electrodes 21 and 22 and the terminals 61 and 62 are electrically connected to each other through the conductive resins 71 and 72, respectively. When the bonding by thermal curing is completed, the Peltier element 20 is bonded with the semiconductor element 10 by using an inspector as described above. Figure 4 and Figure 5 The described method measures the capacitances Cx and Cy, and performs a wet diffusion inspection of the conductive resins 71 and 72 .

[0173] The inspection result is that when the values ​​of the capacitors Cx and Cy are both approximately zero (0), the product is judged as a qualified product and enters the next process. When the values ​​of the capacitors Cx and Cy are not substantially zero (0), the product is judged as a defective product and sent to the defective product processing process. In the following, a similar process is performed in the manufacturing process of other embodiments.

[0174] By having the manufacturing process as described above, it is possible to manufacture the following assembly process, final inspection process, etc. Figure 2 and Figure 3 A semiconductor device 101 according to a first embodiment of the present disclosure is shown in FIG.

[0175] [Effects of the First Embodiment]

[0176] As described above, according to the first embodiment of the semiconductor device 101 of the present embodiment, the bonding between the Peltier element 20 as the cooling device of the semiconductor element 10 and the substrate 50 can be inspected easily and quickly by a simple inspector.

[0177] <3. Second Embodiment of Semiconductor Device According to the Present Disclosure>

[0178] [Basic Configuration of Second Embodiment]

[0179] Next, a description will be given of a second embodiment of the semiconductor device 101 according to the present disclosure.

[0180] Fig.15 1 is a plan view of the PGA package 30 before the Peltier element 20 is bonded to the substrate 50 in the second embodiment.

[0181] In the second embodiment, as shown in the figure, the arrangement of the terminals 61, 62, the detection pattern portions 51, 52, 53 and the inspection terminals 51a, 52a, 53a, 61a, 62a is similar to Figure 2 The same is true for the first embodiment shown.

[0182] However, in the second embodiment, if Figures 15 to 18 As shown, the detection pattern portions 51, 52 and 53 are not covered by the insulators 51b, 52b and 53b, respectively, as in the first embodiment. That is, in the second embodiment, the detection pattern portions 51, 52 and 53 are not covered by the insulators 51b, 52b and 53b, respectively, and are plated with a conductive metal 65 such as gold (Au), for example, to expose the conductor portion.

[0183] The structure other than this is the same as that of the first embodiment, and thus the description thereof will be omitted.

[0184] [Wet Diffusion Inspection Method of Second Embodiment]

[0185] Next, an inspection method for inspecting wet diffusion of the conductive resins 71 and 72 through the inspection terminals 51 a , 52 a , and 53 a connected to the detection pattern portions 51 , 52 , and 53 and the inspection terminals 61 a and 62 a connected to the terminals 61 and 62 will be described below.

[0186] Fig.17 It means in Fig.16 The X-end view shown is a partially enlarged explanatory view of the bonding state when wet diffusion of the conductive resins 71 and 72 does not occur between the substrate 50 and the Peltier element 20. Fig.17 In the illustrated embodiment, an appropriate amount of conductive resin 72 is applied between the electrode 22 and the terminal 62. Similarly, an appropriate amount of conductive resin 72 is also applied between the electrode 21 and the terminal 61. For this reason, as shown in the figure, wet diffusion of the conductive resins 71 and 72 does not occur between the electrode 22 and the terminal 62 and between the electrode 21 and the terminal 61.

[0187] In this state, the resistance Rx is measured between the terminal 62 and the detection pattern portion 53 on the substrate 50. The tester measures the resistance Rx by applying a measurement probe to the inspection terminal 62a connected to the terminal 62 and the inspection terminal 53a connected to the detection pattern portion 53, respectively. Fig.17 In the illustrated embodiment, since wet diffusion of the conductive resin 72 does not occur between the terminal 62 and the detection pattern portion 53 , the value of the resistance Rx is substantially infinite (∞) between the terminal 62 and the detection pattern portion 53 .

[0188] Similarly, the resistance Ry is measured between the terminal 62 on the substrate 50 and the detection pattern portion 51. The resistance Ry is measured by the inspector applying a measurement probe to the inspection terminal 62a connected to the terminal 62 and the inspection terminal 51a connected to the detection pattern portion 51, respectively. Fig.17 In the illustrated embodiment, since wet diffusion of the conductive resin 72 does not occur between the terminal 62 and the detection pattern portion 51 , the value of the resistance Ry is substantially infinite (∞) between the terminal 62 and the detection pattern portion 51 .

[0189] Likewise, the resistance Rx between the terminal 61 and the detection pattern portion 52 on the substrate 50 and the resistance Ry between the terminal 61 and the detection pattern portion 51 are measured. The method of measuring the resistances Rx and Ry is similar to the above-described measurement method, and thus a description thereof will be omitted.

[0190] exist Fig.17 In the illustrated embodiment, since there is no wet diffusion of the conductive resin 71 between the terminal 61 and the detection pattern portion 52 and between the terminal 61 and the detection pattern portion 51, the value of the resistance Rx between the terminal 61 and the detection pattern portion 52 and the value of the resistance Ry between the terminal 61 and the detection pattern portion 51 are both substantially infinite (∞).

[0191] Fig.18 It means in Fig.16 This is an explanatory diagram of a partially enlarged view of the bonding state when wet diffusion of the conductive resin 72 occurs between the substrate 50 and the Peltier element 20 in the X-end view of FIG. Fig.18 In the illustrated embodiment, an appropriate amount of conductive resin 71 is applied between the electrode 21 and the terminal 61. However, a large amount of conductive resin 72 is applied between the electrode 22 and the terminal 62. For this reason, wet diffusion of the conductive resin 72 occurs between the electrode 22 and the terminal 62.

[0192] In this state, the resistance Rx is measured between the terminal 62 and the detection pattern portion 53 on the substrate 50. Fig.17 The measurement of the resistance Rx is performed similarly to that described. Fig.18 In the illustrated embodiment, since wet diffusion of the conductive resin 72 occurs between the terminal 62 and the detection pattern portion 53 , the value of the resistance Rx is not infinite (∞) between the terminal 62 and the detection pattern portion 53 .

[0193] Specifically, the conductive resin 72 reaches the detection pattern portion 53 due to wet diffusion. However, the detection pattern portion 53 is not covered by the insulator 53b, and the conductor portion is exposed. Therefore, the conductive resin 72 and the detection pattern portion 53 are electrically connected to each other and are in a so-called short-circuit state.

[0194] Therefore, when the resistance Rx between the inspection terminal 62a and the inspection terminal 53a is measured, the value of the resistance Rx between the conductive resin 72 and the detection pattern portion 53 is substantially zero ohm (0Ω). As a result, it can be known that the conductive resin 72 wet-spreads and reaches the detection pattern portion 53.

[0195] Similarly, the resistance Ry is measured between the terminal 62 and the detection pattern portion 51. The measurement of the resistance Ry is similar to that of Fig.17 Proceed similarly as described. Fig.18 In the illustrated embodiment, since wet diffusion of the conductive resin 72 occurs between the terminal 62 and the detection pattern portion 51 , similarly, the value of the resistance Ry is substantially zero ohm (0Ω) between the terminal 62 and the detection pattern portion 51 .

[0196] That is, the conductive resin 72 reaches the detection pattern portion 51 due to wet diffusion, thereby causing a short circuit. As a result, it can be known that the conductive resin 72 wet diffuses and reaches the detection pattern portion 51.

[0197] Note that Fig.18 In the illustrated embodiment, since there is no wet diffusion of the conductive resin 71 between the terminal 61 and the detection pattern portion 52 and between the terminal 61 and the detection pattern portion 51, the value of the resistance Rx between the terminal 61 and the detection pattern portion 52 and the value of the resistance Ry between the terminal 61 and the detection pattern portion 51 are both substantially infinite (∞).

[0198] [Manufacturing process of the second embodiment]

[0199] In the manufacturing process of the second embodiment of the semiconductor device 101, as shown in FIG. Figure 8 As shown, it is not necessary to apply an alumina coating for forming the insulators 51b, 52b and 53b on the detection pattern portions 51, 52 and 53. That is, in the manufacturing process of the second embodiment, Figure 8 The process shown is not necessary. Fig.10 In the illustrated plating process, the detection pattern parts 51 , 52 , and 53 may be plated with a conductive metal 65 such as gold (Au).

[0200] Except for the above, the manufacturing process is similar to that of reference Figures 6 to 14 The manufacturing process described herein is not described, and thus its description will be omitted.

[0201] [Effects of the Second Embodiment]

[0202] Since the second embodiment of the semiconductor device 101 according to the present disclosure is configured as described above, it is not necessary to Figure 8The detection pattern portions 51, 52, and 53 shown in FIG. 5 are subjected to a process for forming an alumina coating of the insulators 51b, 52, and 53b. In addition, the bonding inspection of the Peltier element 20 and the substrate 50 can be performed simply and quickly by a simple inspection device.

[0203] Furthermore, since the wet diffusion inspection of the conductive resins 71 and 72 can be realized by simply measuring the resistance, there is no need to use expensive inspection equipment, a simple inspector for conductivity inspection is sufficient, and the investment amount of the inspection equipment is small.

[0204] <4. Third Embodiment of Semiconductor Device According to the Present Disclosure>

[0205] [Basic Configuration of the Third Embodiment]

[0206] Next, a description will be given of a third embodiment of the semiconductor device 101 according to the present disclosure.

[0207] Fig.19 3 is a plan view of the PGA package 30 in a state where the Peltier element 20 is bonded to the substrate 50 in the third embodiment, and is a plan view of the heat sink 24 of the Peltier element 20. Fig. 20 yes Fig.19 X-end view of the .

[0208] In a third embodiment, if Fig. 20 As shown, the heat dissipation plate 24 is formed to be wider than the heat absorption plate 23 , and the periphery of the heat dissipation plate 24 protrudes more than the heat absorption plate 23 .

[0209] In addition, if Fig.19 As shown, the terminals 61 and 62 are arranged on the substrate 50, but the detection pattern portions 51, 52, 53 and the inspection terminals 51a, 52a, 53a, 61a, 62a are not arranged.

[0210] like Fig.19 and Fig. 20 As shown, the detection pattern portions 51, 52, 53 are arranged on the lower surface of the heat sink 24 as the heat sink of the Peltier element 20. In addition, on the upper surface of the heat sink 24, the inspection terminals 51a, 52a, 53a, 21a, 22a are arranged.

[0211] Moreover, the detection pattern portions 51, 52, 53 arranged on the lower surface of the heat sink 24 and the inspection terminals 51a, 52a, 53a arranged on the upper surface of the heat sink 24 are connected via through holes 51c, 52c, 53c, respectively. Similarly, the electrodes 21 and 22 and the inspection terminals 21a and 22a are connected to each other via through holes 21c and 22c, respectively.

[0212] Specifically, if Figures 19 to 22 As shown in FIG. 1 , one end of the detection pattern portions 51, 52, 53 disposed on the lower surface of the heat sink 24 is connected to the lower ends of the through holes 51c, 52c, 53c, respectively. In addition, the upper ends of the through holes 51c, 52c, 53c are connected to the inspection terminals 51a, 52a, 53a disposed on the upper surface of the heat sink 24, respectively. Thus, the detection pattern portions 51, 52, 53 disposed on the lower surface of the heat sink 24 are electrically connected to the inspection terminals 51a, 52a, 53a disposed on the upper surface of the heat sink 24, respectively.

[0213] The electrodes 21 and 22 , the detection pattern portions 51 , 52 and 53 , the through holes 51 c , 52 c and 53 c , and the inspection terminals 51 a , 52 a , 53 a , 21 a and 22 a are electrically insulated from the heat sink 24 in a predetermined manner (the same applies hereinafter).

[0214] Except for the above, the configuration is similar to that in the first embodiment. Figure 2 and Figure 3 The configuration in this case is not described, so its description will be omitted.

[0215] [Wet Diffusion Inspection Method of Third Embodiment]

[0216] Next, an inspection method for inspecting wet diffusion of the conductive resins 71 and 72 through the inspection terminals 51 a , 52 a , and 53 a connected to the detection pattern portions 51 , 52 , and 53 and the inspection terminals 61 a and 62 a connected to the terminals 61 and 62 will be described below.

[0217] Fig.21 is Fig. 20 The X-end view shown is a partially enlarged explanatory diagram of the bonding state when wet diffusion of the conductive resin 71, 72 does not occur between the substrate 50 and the Peltier element 20. An appropriate amount of the conductive resin 72 is applied between the electrode 22 and the terminal 62. Similarly, an appropriate amount of the conductive resin 72 is also applied between the electrode 21 and the terminal 61. For this reason, wet diffusion of the conductive resin 71 and 72 does not occur between the electrode 22 and the terminal 62 and between the electrode 21 and the terminal 61.

[0218] In this state, the capacitance Cx between the electrode 22 and the detection pattern portion 53 on the lower surface of the heat sink 24 is measured. The capacitance Cx is measured in a state where the inspection terminal 22a and the inspection terminal 53a are arranged on the upper surface of the heat sink 24. Except for the above, this method is similar to that in the first embodiment described above. Figure 4 In this case, the value of the capacitance Cx between the electrode 22 and the detection pattern portion 53 is substantially zero (0).

[0219] Likewise, the capacitance Cy is measured between the electrode 22 and the detection pattern portion 51 on the lower surface of the heat sink 24. In this case, the value of the capacitance Cy is substantially zero (0).

[0220] Likewise, the capacitance Cx between the electrode 21 and the detection pattern portion 52 and the capacitance Cy between the electrode 21 and the detection pattern portion 51 are measured. In this case, the value of the capacitance Cx and the value of the capacitance Cy are substantially zero (0).

[0221] Fig. 22 is Fig. 20 The X-end view shown is an explanatory diagram showing a partially enlarged view of a bonding state when wet diffusion of the conductive resin 72 occurs between the substrate 50 and the Peltier element 20. An appropriate amount of the conductive resin 71 is applied between the electrode 21 and the terminal 61. However, a large amount of the conductive resin 72 is applied between the electrode 22 and the terminal 62. For this reason, wet diffusion of the conductive resin 72 occurs between the electrode 22 and the terminal 62.

[0222] In this state, the capacitance Cx between the electrode 22 and the detection pattern portion 53 on the lower surface of the heat sink 24 is measured. Since the method of measuring the capacitance Cx is the same as that in the first embodiment described above, Figure 5 In this case, the value of the capacitance Cx is not zero (0) between the electrode 22 and the detection pattern portion 53, but is as in the first embodiment described above. Figure 5 As a result, it can be known that the conductive resin 72 wet-spreads and reaches the detection pattern section 53 .

[0223] Likewise, the capacitance Cy is measured between the electrode 22 and the detection pattern portion 51. Fig. 22 In the embodiment shown, since wet diffusion of the conductive resin 72 occurs between the electrode 22 and the detection pattern portion 51, the value of the capacitance Cy between the electrode 22 and the detection pattern portion 51 is not zero (0), but is Figure 5 As a result, it can be known that the conductive resin 72 wet-spreads and reaches the detection pattern section 51 .

[0224] Note that Fig. 22 In the illustrated embodiment, since no wet diffusion of the conductive resin 71 occurs between the electrode 21 and the detection pattern portion 52 and between the electrode 21 and the detection pattern portion 51, the value of the capacitance Cx between the electrode 21 and the detection pattern portion 52 and the value of the capacitance Cy between the electrode 21 and the detection pattern portion 51 are substantially zero (0).

[0225] [Manufacturing process of the third embodiment]

[0226] In the manufacturing process of the third embodiment of the semiconductor device 101, as shown in FIG. Figures 6 to 10 As shown, it is not necessary to form the detection pattern parts 51, 52, 53, the insulators 51b, 52b, 53b, and the inspection terminals 61a, 62a (not shown) on the green sheet 90. For this reason, in the manufacturing process of the third embodiment, Figure 8 The process shown for applying the aluminum oxide coating is not necessary.

[0227] In the manufacturing process (not shown) of the Peltier element 20, the detection pattern portions 51, 52, 53 are formed on the lower surface of the heat sink 24 of the Peltier element 20 and covered with insulators 51b, 52b, 53b, respectively.

[0228] Similarly, in the manufacturing process (not shown) of the Peltier element 20, the following process is also performed: the inspection terminals 51a, 52a, 53a, 21a, 22a are formed on the upper surface of the heat sink 24, and are connected to the detection pattern portions 51, 52, 53 and the electrodes 21, 22 via the through holes 51c, 52c, 53c, 21c, 22c, respectively. Fig.14 In the process shown, the Peltier element 20 thus manufactured is bonded to a substrate 50 .

[0229] Except for the above, the manufacturing process is similar to that of reference Figures 6 to 14 The manufacturing process described herein is not described, and thus its description will be omitted.

[0230] [Effects of the Third Embodiment]

[0231] Since the semiconductor device 101 according to the third embodiment of the present disclosure is configured as described above, Figures 7 to 10 The process of forming the detection pattern parts 51, 52 and 53, the insulators 51b, 52b and 53b and the inspection terminals 61a and 62a (not shown) is unnecessary. Figure 8 The process shown for applying the aluminum oxide coating is not necessary.

[0232] Furthermore, since the inspection terminals 51a, 52a, 53a, 21a, and 22a are arranged on the peripheral edge of the upper surface of the heat dissipation plate 24 arranged at the upper side of the substrate 50, an inspector probe can be easily applied and operability can be improved.

[0233] Effects of the third embodiment of the semiconductor device 101 other than the above-described effects are similar to those of the first embodiment, and thus description thereof will be omitted.

[0234] <5. Fourth Embodiment of Semiconductor Device According to the Present Disclosure>

[0235] [Basic Configuration of Fourth Embodiment]

[0236] Next, a description will be given of a fourth embodiment of the semiconductor device 101 according to the present disclosure.

[0237] Fig.23 4 is a plan view of the PGA package 30 in the plan view of the heat sink 24 of the Peltier element 20 in a state where the Peltier element 20 is bonded to the substrate 50. In addition, Fig.24 yes Fig.23 X-end view of the .

[0238] In a fourth embodiment, if Fig.23 As shown, the arrangement of the terminals 61 and 62 and the electrodes 21 and 22 is similar to Fig.19 and Fig. 20 The arrangement of the third embodiment is shown. Fig.23 As shown, the configuration and connection of the detection pattern portions 51, 52, 53 and the inspection terminals 51a, 52a, 53a, 21a, 22a are similar to Fig.19 The same is true for the third embodiment shown. In addition, the heat dissipation plate 24 is formed wider than the heat absorption plate 23 and the periphery protrudes more than the heat absorption plate 23, similar to the third embodiment.

[0239] However, in the fourth embodiment, if Figure 23 to Figure 26 As shown in , the detection pattern portions 51, 52 and 53 are not covered by the insulators 51b, 52b and 53b, respectively, as in the second embodiment. That is, in the fourth embodiment, the detection pattern portions 51, 52 and 53 are not covered by the insulators 51b, 52b and 53b, respectively, and the conductor portions are exposed, for example, the conductor portions are plated with a conductive metal 65 such as tungsten (W) or gold (Au).

[0240] In addition to the above, in the third embodiment, the structure is Figures 19 to 22 The construction in the case of is similar, so its description will be omitted.

[0241] [Wet Diffusion Inspection Method of Fourth Embodiment]

[0242] Next, a method of inspecting the wet spread of the conductive resins 71 and 72 using the inspection terminals 51 a , 52 a , 53 a connected to the detection pattern portions 51 , 52 , 53 and the inspection terminals 21 a , 22 a connected to the electrodes 21 and 22 will be described.

[0243] Fig.25 yes Fig.24The X-end view shown is a partially enlarged explanatory view showing a bonding state when wet diffusion of the conductive resins 71 and 72 does not occur between the substrate 50 and the Peltier element 20 .

[0244] In this state, the method of measuring the resistance Rx between the electrode 22 and the detection pattern portion 53 on the lower surface of the heat dissipation plate 24 and the method of measuring the resistance Ry between the electrode 22 and the detection pattern portion 51 are the same as those in the third embodiment. Fig.21 The method in the case of is similar, so its description will be omitted. In this case, both the value of the resistance Rx and the value of the resistance Ry are substantially infinite (∞).

[0245] Likewise, measurement is performed of the resistance Rx between the electrode 21 and the detection pattern portion 52 and the resistance Ry between the electrode 21 and the detection pattern portion 51. In this case, both the value of the resistance Rx and the value of the resistance Ry are substantially infinite (∞).

[0246] Fig.26 yes Fig.24 The X-end view shown is a partially enlarged view showing a bonding state when wet diffusion of the conductive resin 72 occurs between the substrate 50 and the Peltier element 20 .

[0247] In this state, the method of measuring the resistance Rx between the electrode 22 and the detection pattern portion 53 on the lower surface of the heat dissipation plate 24 is the same as that in the third embodiment. Fig. 22 The method in the case of is similar, so its description will be omitted. In this case, the electrode 22 and the detection pattern portion 53 are electrically connected to each other due to the wet diffusion of the conductive resin 72, and are in a so-called short-circuit state. For this reason, the value of the resistance Rx between the electrode 22 and the detection pattern portion 53 is substantially zero ohm (0Ω). As a result, it can be known that the conductive resin 72 wet diffuses and reaches the detection pattern portion 53.

[0248] Similarly, the method of measuring the resistance Ry between the electrode 22 and the detection pattern portion 51 is the same as that in the third embodiment. Fig. 22 The method in the case of is similar, so its description will be omitted. In this case, since the electrode 22 and the detection pattern portion 51 are short-circuited, the value of the resistance Ry is substantially zero ohm (0Ω). As a result, it can be known that the conductive resin 72 wet-diffuses and reaches the detection pattern portion 51.

[0249] Note that Fig.26 In the illustrated embodiment, since there is no wet diffusion of the conductive resin 71 between the electrode 21 and the detection pattern portion 52 and between the electrode 21 and the detection pattern portion 51, both the value of the resistance Rx between the electrode 21 and the detection pattern portion 52 and the value of the resistance Ry between the electrode 21 and the detection pattern portion 51 are essentially infinite (∞).

[0250] [Manufacturing Process of Fourth Embodiment]

[0251] In the manufacturing process of the semiconductor device 101 according to the fourth embodiment, Figures 7 to 10 The steps shown are the same as the manufacturing steps of the third embodiment, and therefore description thereof will be omitted.

[0252] In addition, in the process of forming the detection pattern portions 51, 52, 53, etc. on the lower surface of the heat sink 24 of the Peltier element 20, it is not necessary to cover the detection pattern portions 51, 52, 53 with the insulators 51b, 52b, 53b. The process is otherwise the same as the manufacturing process of the third embodiment, and therefore the description thereof is omitted.

[0253] [Effects of the Fourth Embodiment]

[0254] Since the fourth embodiment of the semiconductor device 101 according to the present disclosure is configured as described above, Figures 7 to 10 The detection pattern parts 51, 52 and 53 and the insulators 51b, 52b and 53b are formed, and the application Figure 8 The treatment of the aluminum oxide coating shown in is not necessary.

[0255] Furthermore, since the wet diffusion inspection of the conductive resins 71 and 72 can be realized by simply measuring the resistance, there is no need to use expensive inspection equipment, a simple inspector for conductivity inspection is sufficient, and the investment amount of the inspection equipment is small.

[0256] Effects of the fourth embodiment of the semiconductor device 101 other than the above-described effects are similar to those of the third embodiment, and thus description thereof will be omitted.

[0257] <6. Fifth Embodiment of Semiconductor Device According to the Present Disclosure>

[0258] [Basic Configuration of Fifth Embodiment]

[0259] Next, a description will be given of a fifth embodiment of the semiconductor device 101 according to the present disclosure.

[0260] In the fifth embodiment, in the heat sink 24 in the third embodiment, the inspection terminals 21a and 22a connected to the electrodes 21 and 22 are not provided, and similarly to the first embodiment, the inspection terminals 61a and 62a are provided on the terminals 61 and 62 on the substrate 50. That is, the fifth embodiment has a compromise structure between the third embodiment and the first embodiment.

[0261] Thus, in the fifth embodiment, if Fig. 27As shown, the inspection terminals 61a, 62a are connected to the terminals 61, 62 arranged on the substrate 50, respectively. Furthermore, the detection pattern portions 51, 52, 53 are arranged on the heat sink 24, and the detection pattern portions 51, 52, 53 are covered by insulators 51b, 52b, 53b, respectively. Moreover, the detection pattern portions 51, 52, 53 are electrically connected to the inspection terminals 51a, 52a, 53a arranged on the upper surface of the heat sink 24 via through holes 51c, 52c, 53c, respectively.

[0262] The structure other than this is the same as that described in the first embodiment.

[0263] Thus, capacitance Cx is measured between the inspection terminal 62a and the inspection terminal 53a and between the inspection terminal 61a and the inspection terminal 52a. Also, capacitance Cy is measured between the inspection terminal 62a and the inspection terminal 51a and between the inspection terminal 61a and the inspection terminal 51a.

[0264] [Wet Diffusion Inspection Method of Fifth Embodiment]

[0265] Next, an inspection method for inspecting wet diffusion of the conductive resins 71 and 72 through the inspection terminals 51 a , 52 a , and 53 a connected to the detection pattern portions 51 , 52 , and 53 and the inspection terminals 61 a and 62 a connected to the terminals 61 and 62 will be described below.

[0266] Fig. 27 : is a partially enlarged explanatory diagram showing a bonding state when wet diffusion of the conductive resins 71 and 72 does not occur between the substrate 50 and the Peltier element 20. An appropriate amount of the conductive resin 72 is applied between the electrode 22 and the terminal 62. Similarly, an appropriate amount of the conductive resin 72 is also applied between the electrode 21 and the terminal 61. For this reason, wet diffusion of the conductive resins 71 and 72 does not occur between the electrode 22 and the terminal 62 and between the electrode 21 and the terminal 61.

[0267] In this state, the capacitance Cx between the terminal 62 on the substrate 50 and the detection pattern portion 53 on the lower surface of the heat sink 24 is measured. The measurement of the capacitance Cx is performed with the inspection terminal 62a provided on the upper surface of the substrate 50 and the inspection terminal 53a provided on the upper surface of the heat sink 24. Except for the above, the method is similar to that in the first embodiment. Figure 4 In the case of the method or in the third embodiment Fig.21 In this case, the value of the capacitance Cx between the terminal 62 and the detection pattern portion 53 is substantially zero (0).

[0268] Likewise, the capacitance Cy is measured between the terminal 62 on the substrate 50 and the detection pattern portion 51 on the lower surface of the heat sink 24. In this case, the value of the capacitance Cy is substantially zero (0).

[0269] Likewise, measurement is performed of the capacitance Cx between the terminal 61 and the detection pattern portion 52 and the capacitance Cy between the terminal 61 and the detection pattern portion 51. In this case, the value of the capacitance Cx and the value of the capacitance Cy are both substantially zero (0).

[0270] Fig.28 1 is a partially enlarged explanatory diagram showing a bonding state when wet diffusion of the conductive resin 72 occurs between the substrate 50 and the Peltier element 20. An appropriate amount of the conductive resin 71 is applied between the electrode 21 and the terminal 61. However, a large amount of the conductive resin 72 is applied between the electrode 22 and the terminal 62. For this reason, wet diffusion of the conductive resin 72 occurs between the electrode 22 and the terminal 62.

[0271] In this state, the capacitance Cx between the terminal 62 on the substrate 50 and the detection pattern portion 53 on the lower surface of the heat sink 24 is measured. Figure 5 In this case, the value of the capacitance Cx is not zero (0) between the terminal 62 and the detection pattern portion 53, but is as in the first embodiment. Figure 5 As a result, it can be known that the conductive resin 72 wet-spreads and reaches the detection pattern section 53 .

[0272] Likewise, the capacitance Cy is measured between the terminal 62 and the detection pattern portion 51. Fig.28 In the example shown, since wet diffusion of the conductive resin 72 occurs between the terminal 62 and the detection pattern portion 51, the value of the capacitance Cy between the terminal 62 and the detection pattern portion 51 is not zero (0), but is equal to 0 in the first embodiment. Figure 5 As a result, it can be known that the conductive resin 72 wet-spreads and reaches the detection pattern section 51 .

[0273] Note that Fig.28 In the illustrated embodiment, since no wet diffusion of the conductive resin 71 occurs between the terminal 61 and the detection pattern portion 52 and between the terminal 61 and the detection pattern portion 51, the value of the capacitance Cx between the terminal 61 and the detection pattern portion 52 and the value of the capacitance Cy between the terminal 61 and the detection pattern portion 51 are substantially zero (0).

[0274] [Manufacturing process of the fifth embodiment]

[0275] In the manufacturing process of the fifth embodiment of the semiconductor device 101, as shown in FIG. Figures 7 to 10 As shown, there is no need to form the detection pattern portions 51, 52, 53 and the insulators 51b, 52b, 53b on the green sheet 90. For this reason, Figure 8 The method shown for applying the aluminum oxide coating is also not necessary.

[0276] In the manufacturing process (not shown) of the Peltier element 20, the detection pattern portions 51, 52, 53 are formed on the lower surface of the heat sink 24 of the Peltier element 20 and covered with insulators 51b, 52b, 53b, respectively.

[0277] Similarly, in the manufacturing process (not shown) of the Peltier element 20, a process is also performed to form inspection terminals 51a, 52a, 53a on the upper surface of the heat sink 24 and connect them to the detection pattern portions 51, 52, 53 via through holes 51c, 52c, 53c.

[0278] Except for the above, the manufacturing process is similar to that of reference Figures 6 to 14 The manufacturing process described herein is not described, and thus its description will be omitted.

[0279] [Effects of the Fifth Embodiment]

[0280] Since the third embodiment of the semiconductor device 101 according to the present disclosure is configured as described above, Figures 7 to 10 The process of forming the detection pattern portions 51, 52 and 53 and the insulators 51b, 52b and 53b on the green sheet 90 is unnecessary. Figure 8 The process shown for applying the aluminum oxide coating is not necessary.

[0281] Effects of the fifth embodiment of the semiconductor device 101 other than the above-described effects are similar to those of the first embodiment, and thus description thereof will be omitted.

[0282] <7. Sixth Embodiment of Semiconductor Device According to the Present Disclosure>

[0283] [Basic Configuration of Sixth Embodiment]

[0284] Next, a description will be given of a sixth embodiment of the semiconductor device 101 according to the present disclosure.

[0285] In the sixth embodiment, the detection pattern portions 51 , 52 , and 53 in the fifth embodiment are not covered with the insulators 51 b , 52 b , and 53 b , respectively.

[0286] Except for the above, the configuration is similar to that of the fifth embodiment. Fig. 27 and Fig.28 The configuration described in , and therefore its description is omitted.

[0287] [Wet Diffusion Inspection Method of Sixth Embodiment]

[0288] Next, an inspection method for inspecting wet diffusion of the conductive resins 71 and 72 through the inspection terminals 51 a , 52 a , and 53 a connected to the detection pattern portions 51 , 52 , and 53 and the inspection terminals 61 a and 62 a connected to the terminals 61 and 62 will be described below.

[0289] Fig.29 It is a partially enlarged explanatory diagram showing a bonding state when wet diffusion of the conductive resins 71 and 72 does not occur between the substrate 50 and the Peltier element 20 .

[0290] In this figure, instead of measuring the capacitances Cx and Cy between the terminal 62 and the detection pattern portions 53 and 51 and the capacitances Cx and Cy between the terminal 61 and the detection pattern portions 52 and 51, the respective resistances Rx and Ry are measured. Fig. 27 and Fig.17 In this case, the values ​​of the resistors Rx and Ry are substantially infinite (∞).

[0291] Fig.30 This is a partially enlarged explanatory diagram showing a bonding state when wet diffusion of the conductive resin 72 occurs between the substrate 50 and the Peltier element 20 .

[0292] exist Fig.30 The method of measuring resistance Rx and Ry is the same as Fig.28 and Fig.18 The method in the case of is similar, so its description will be omitted. In this case, the value of the resistance Rx between the two terminals 62 and the detection pattern portion 53 and the value of the resistance Ry between the terminal 62 and the detection pattern portion 51 are substantially zero ohm (0Ω). As a result, it can be known that the conductive resin 72 wet-diffuses and reaches the detection pattern portions 51 and 53.

[0293] On the other hand, since wet diffusion of the conductive resin 72 does not occur between the terminal 61 and the detection pattern portions 51, 52, the value of the resistance Rx between the terminal 61 and the detection pattern portion 52 and the value of the resistance Ry between the terminal 61 and the detection pattern portion 51 are both substantially infinite (∞). In addition to the above, in the fifth embodiment, the method is similar to Fig.28 The method in this case will therefore be omitted.

[0294] [Manufacturing Process of Sixth Embodiment]

[0295] The manufacturing process of the substrate 50 of the sixth embodiment is the same as the manufacturing process of the fifth embodiment.

[0296] The manufacturing process of the Peltier element 20 is the same as that of the fifth embodiment except that it is not necessary to cover the detection pattern portions 51 , 52 , 53 formed on the lower surface of the heat sink 24 with the insulators 51 b , 52 b , 53 b , so the description thereof is omitted.

[0297] Except for the above, the manufacturing process is similar to that of reference Figures 6 to 14 The manufacturing process described herein is not described, and thus its description will be omitted.

[0298] [Effects of the Sixth Embodiment]

[0299] Since the sixth embodiment of the semiconductor device 101 according to the present disclosure is configured as described above, Figures 7 to 10 The detection pattern parts 51, 52 and 53 and the insulators 51b, 52b and 53b are formed, and the application Figure 8 The treatment of the aluminum oxide coating shown in is not necessary.

[0300] Furthermore, since the wet diffusion inspection of the conductive resins 71 and 72 can be realized by simply measuring the resistance, there is no need to use expensive inspection equipment, a simple inspector for conductivity inspection is sufficient, and the investment amount of the inspection equipment is small.

[0301] Effects of the sixth embodiment of the semiconductor device 101 other than the above-described effects are similar to those of the fifth embodiment, and thus description thereof will be omitted.

[0302] <8. Variation of the First Embodiment of the Semiconductor Device According to the Present Disclosure>

[0303] Next, a description will be given of a modification of the first embodiment of the semiconductor device 101 according to the present disclosure (hereinafter, referred to as “present modification” in this example).

[0304] In the structure of this modification, in the first embodiment Figures 2 to 5 In the embodiment of the third embodiment, instead of the inspection terminals 61a and 62a, Figures 19 to 22 The inspection terminals 21a and 22a shown are provided to the electrodes 21 and 22. Other than this, the structure is the same as that of the first embodiment. Figures 2 to 5 In the application Figures 19 to 22 Check terminals 21a and 22a in.

[0305] In this modified example, the wet diffusion inspection of the conductive resins 71 and 72 is performed as follows. That is, the capacitance Cx is measured between the inspection terminals 21a and 52a of the electrode 21 on the lower surface of the heat sink 24 and the detection pattern portion 52 on the upper surface of the substrate 50, and between the inspection terminals 22a and 53a of the electrode 22 on the lower surface of the heat sink 24 and the detection pattern portion 53 on the upper surface of the substrate 50.

[0306] Capacitance Cy is measured between the electrode 21 and the inspection terminals 21 a and 51 a of the detection pattern portion 51 and between the electrode 22 and the inspection terminals 22 a and 51 a of the detection pattern portion 51 on the upper surface of the substrate 50 .

[0307] In addition, since the specific measurement method is similar to that of the first embodiment or the fifth embodiment, the description thereof will be omitted. Since the manufacturing process and effects are also similar to those of the above-mentioned embodiment, the description thereof will be omitted.

[0308] <9. Modification of Second Embodiment of Semiconductor Device According to the Present Disclosure>

[0309] Next, a description will be given of a modification example of the second embodiment of the semiconductor device 101 according to the present disclosure (hereinafter, referred to as “the present modification example” in this example).

[0310] In the structure of this modification, in the second embodiment Figures 15 to 18 In the embodiment of the fourth embodiment, instead of the inspection terminals 61a and 62a, Figure 23 to Figure 26 The inspection terminals 21a and 22a shown are provided to the electrodes 21 and 22. Other than this, the structure is the same as that of the second embodiment. Figures 15 to 18 In Figure 23 to Figure 26 Check terminals 21a and 22a in.

[0311] In this modified example, the wet diffusion inspection of the conductive resins 71 and 72 is performed as follows. That is, the resistance Rx is measured between the inspection terminal of the electrode 21 on the lower surface of the heat sink 24 and the inspection terminals 21a and 52a of the detection pattern portion 52 on the upper surface of the substrate 50, and between the inspection terminal of the electrode 22 on the lower surface of the heat sink 24 and the inspection terminals 22a and 53a of the detection pattern portion 53 on the upper surface of the substrate 50.

[0312] The resistance Ry is measured between the electrode 21 on the upper surface of the substrate 50 and the inspection terminals 21 a and 51 a of the detection pattern portion 51 , and between the electrode 22 and the inspection terminals 22 a and 51 a of the detection pattern portion 51 .

[0313] In addition, since the specific measurement method is similar to that of the second embodiment or the sixth embodiment, the description thereof will be omitted. Since the manufacturing process and effects are also similar to those of the above-mentioned embodiment, the description thereof will be omitted.

[0314] <10. First Modification Example of the First Embodiment or the Second Embodiment of the Semiconductor Device According to the Present Disclosure>

[0315] Next, a description will be given of a first modification example of the first embodiment or the second embodiment of the semiconductor device 101 according to the present disclosure (hereinafter, in the present embodiment, it is referred to as “first modification example”).

[0316] Fig.31 It is a plan view of the substrate 50 in the cavity 35 before the Peltier element 20 is bonded to the substrate 50 in the first modification. In the first embodiment or the second embodiment, the detection pattern portions 51, 52, 53 are arranged on the upper surface of the substrate 50 in the Y direction along the terminals 61, 62, respectively.

[0317] On the other hand, in the first modification, if Fig.31 As shown, the detection pattern portions 51, 52, 53 are respectively arranged in a plurality of detection pattern portions along the Y direction of the terminals 61, 62, rather than being respectively arranged in one detection pattern portion. The figure shows an embodiment in which two detection pattern portions are arranged on the left side of the terminal 62, three detection pattern portions are arranged between the terminals 61 and 62, and two detection pattern portions are arranged on the right side of the terminal 61.

[0318] In this case, the detection pattern portions 51, 52, 53 are covered with insulators 51b, 52b, 53b, respectively, which is the first modification of the first embodiment. Also, the detection pattern portions 51, 52, 53 are not covered with insulators 51b, 52b, 53b, respectively, which is the first modification of the second embodiment.

[0319] With the above configuration, in the manufacturing process of the semiconductor device 101 Figure 7 In the illustrated process, it is only necessary to print the paste-like conductive material on the green sheet 90 in accordance with the number of the detection pattern parts so that the numbers of the detection pattern parts 51 , 52 , and 53 are respectively predetermined numbers.

[0320] In this way, the detection pattern portions 51 , 52 , 53 are arranged in a plurality of detection pattern portions in the Y direction along the terminals 61 , 62 , thereby accurately knowing the state or degree of wet diffusion of the conductive resins 71 , 72 and appropriately determining whether the conductive resins 71 , 72 are good or bad.

[0321] Note that in the third embodiment described above, Fig.19 or the fourth embodiment Fig.23In the illustrated embodiment, the sensing pattern parts 51 , 52 , and 53 may be arranged in a plurality of sensing pattern parts in the Y direction along the electrodes 21 and 22 on the lower surface of the heat dissipation plate 24 .

[0322] <11. Second Modification Example or Second Embodiment of First Embodiment of Semiconductor Device According to the Present Disclosure>

[0323] Next, a description will be given of a second modification example of the first embodiment or the second embodiment of the semiconductor device 101 according to the present disclosure (hereinafter, in this embodiment, it is referred to as “second modification example”).

[0324] Fig.32 2 is a plan view of the substrate 50 in the cavity 35 before the Peltier element 20 is bonded to the substrate 50 in the second modification. In addition, in the second modification, each detection pattern portion 51, 52, 53 is not limited to a continuous straight line, and may be a small detection pattern portion 59 of various shapes shorter than the length of the terminals 61, 62 and the electrodes 21, 22 in the longitudinal direction.

[0325] Specifically, if Fig.32 As shown, a small detection pattern portion 59 is formed by forming the shape of the detection pattern portions 51, 52, 53 into a short line pattern 54, a rectangular pattern 55, a triangular pattern 56, a circular pattern 57, etc. In the figure, a plurality of small detection pattern portions 59 are arranged in the Y direction along the terminals 61 and 62. In addition, the shape, number, configuration, etc. of the small detection pattern portion 59 are not particularly limited.

[0326] Each small detection pattern portion 59 may also be connected to a check terminal (not shown) formed on the peripheral portion of the upper surface of the substrate 50 via, for example, a wiring layer (not shown) formed on the inner side of the bottom surface of the PGA package 30. Then, the capacitances Cx and Cy or the resistances Rx and Ry may be measured between these check terminals (not shown) and the check terminals 61a and 62a.

[0327] In this case, the case where the small detection pattern portions 59 are covered by an insulator (not shown) is a second modification of the first embodiment. Also, when the substantially circular pattern 57 or the like as the small detection pattern portion 59 is not covered by an insulator, it becomes a second modification of the second embodiment.

[0328] With the above configuration, in the semiconductor device 101 Figure 7 In the illustrated process, it is only necessary to print the paste-like conductive material on the green sheet 90 in accordance with the shape and number of the detection pattern portions so that the shape and number of the small detection pattern portions 59 are the corresponding predetermined shapes and numbers.

[0329] In this way, the small detection pattern portions 59 are arranged in a predetermined shape and number in the Y direction along the terminals 61 and 62 , thereby being able to accurately know the state or degree of wet diffusion of the conductive resins 71 and 72 and appropriately perform quality judgment.

[0330] In addition, in the third embodiment described above Fig.19 and the fourth embodiment Fig.23 In the example shown, similarly to the second modification, the detection pattern portions 51 , 52 , 53 formed in the small detection pattern portion 59 may be arranged in a plurality of detection pattern portions in the Y direction along the electrodes 21 , 22 on the lower surface of the heat sink 24 .

[0331] <12. First Modification of the Third to Sixth Embodiments of the Semiconductor Device According to the Present Disclosure>

[0332] Next, a description will be given of a first modification example of the third to sixth embodiments of the semiconductor device 101 according to the present disclosure (hereinafter, in the present embodiment, it is referred to as “first modification example”).

[0333] Fig.33 FIG. 2 is a top view of the heat sink 24 of the Peltier element 20 in the first modification example in a state where the heat sink 24 is bonded to the substrate 50. Fig.34 yes Fig.33 Y1 end view, and Fig.35 yes Fig.33 Y2 end view of the .

[0334] In each of the third to sixth embodiments, the detection pattern portions 51 , 52 , 53 are arranged linearly along the electrodes 21 , 22 on the lower surface of the heat sink 24 in the Y direction.

[0335] On the other hand, in the first modification, if Fig.33 As shown, the detection pattern portions 51, 52, 53 are arranged in a plurality of detection pattern portions on the lower surface of the heat sink 24 in the Y direction along the electrodes 21, 22. The figure shows an embodiment in which two detection pattern portions are arranged on the left side of the electrode 22, two detection pattern portions are arranged between the electrode 21 and the electrode 22, and two detection pattern portions are arranged on the right side of the electrode 21.

[0336] like Fig.33As shown, the detection pattern portions 51, 52, 53 among the plurality of detection pattern portions arranged on the lower surface of the heat sink 24 are connected to the inspection terminals 51a, 52a, 53a arranged on the upper surface of the heat sink 24 via the through holes 51c, 52c, 53c arranged on the periphery of the heat sink 24. That is, the inspection terminals 51a, 52a, 53a are connected to both ends or the approximate center of the detection pattern portions 51, 52, 53, and are arranged on the periphery of the upper surface of the heat sink 24.

[0337] In this case, the detection pattern portions 51, 52, 53 are respectively covered by the insulators 51b, 52b, 53b, which is the first modification of the third embodiment or the fifth embodiment. Also, the detection pattern portions 51, 52, 53 are not respectively covered by the insulators 51b, 52b, 53b, which is the first modification of the fourth or sixth embodiment.

[0338] The above structure is achieved by the same process as that described in the manufacturing process of the Peltier element 20 of the third embodiment. Fig.14 In the process shown, the Peltier element 20 thus manufactured is bonded to a substrate 50 .

[0339] In this way, the detection pattern portions 51 , 52 , 53 are arranged in a plurality of detection pattern portions in the Y direction along the electrodes 21 and 22 , thereby being able to accurately know the state or degree of wet diffusion of the conductive resins 71 , 72 and appropriately perform good or bad judgment.

[0340] <13. Second Modification of the Third to Sixth Embodiments of the Semiconductor Device According to the Present Disclosure>

[0341] Next, a description will be given of a second modification example of the third to sixth embodiments of the semiconductor device 101 according to the present disclosure (hereinafter, in the present embodiment, it is referred to as “second modification example”).

[0342] Fig.36 2 is a plan view of the heat sink 24 in a state where the Peltier element 20 is bonded to the substrate 50 in the second modification. Fig.37 yes Fig.36 Y3 end view of the .

[0343] In the first modified examples of the third to sixth embodiments, the detection pattern portions 51 , 52 , and 53 arranged in the plurality of detection pattern portions are formed in a single straight line.

[0344] On the other hand, in the second modification, each detection pattern portion 51, 52, 53 does not need to have a straight line shape. Fig.36 or Fig.37As shown, a plurality of substantially circular patterns are formed, and these are arranged linearly at predetermined intervals.

[0345] like Fig.37 As shown, these detection pattern portions 52, 53 are connected to the respective inspection terminals 51a, 52a, 53a arranged at the peripheral portion of the upper surface of the heat sink 24 via through holes 52c, 53c. In addition, the detection pattern portion 51 is connected to the respective inspection terminals 51a arranged at the peripheral portion of the upper surface of the heat sink 24 via through holes 51c and wiring patterns 51d.

[0346] Fig.36 or Fig.37 An embodiment is shown in which six detection pattern portions 53 formed in a substantially circular pattern 57 on the left side of the electrode 22, six detection pattern portions 51 between the electrodes 21 and 22 in the same manner, and six detection pattern portions 52 on the right side of the electrode 21 in the same manner are all arranged in a row. Note that the number of pieces to be arranged is not limited to six, and may be any number. In addition, the shapes of the detection pattern portions 51, 52, 53 may be as follows: Fig.32 Such a small detection pattern portion 59 has a shape other than the substantially circular pattern 57 .

[0347] In this case, the case where the substantially circular pattern 57 or the like as the small detection pattern portion 59 is covered by an insulator (not shown) is the third embodiment or the second variation of the fifth embodiment. Also, the case where the small detection pattern portion 59 is not covered by an insulator is the fourth embodiment or the second variation of the sixth embodiment.

[0348] The heat sink 24 is formed by the same process as the manufacturing process of the Peltier element 20 of the third embodiment. Fig.14 In the process shown, the Peltier element 20 thus manufactured is bonded to a substrate 50 .

[0349] As described above, the plurality of detection pattern portions 51, 52, and 53 are each linearly arranged at predetermined intervals in the Y direction in the plurality of detection pattern portions, whereby the position of the wet spread of the conductive resins 71 and 72 can be detected, so that data on the state or degree of wet spread can be obtained non-destructively. As a result, good or bad judgment can be appropriately made, and it can be used to investigate the cause of wet spread and its countermeasures.

[0350] <14. Electronic device including semiconductor device according to the present disclosure>

[0351] Will refer to Fig.38 A description is given of a configuration example of an electronic device including the solid-state imaging device 100 as an example of the semiconductor device 101 according to the first to sixth embodiments and their modified examples.

[0352] The semiconductor device 101 according to the present disclosure can be applied to an industrial manufacturing device, an imaging device (such as a copier) using the solid-state imaging device 100 as an image reading unit, an imaging device (such as a digital still camera or a video camera), or a mobile terminal device having an imaging function. In addition, its application is not limited to the imaging device, and can be widely applied to general electronic devices such as industrial devices including home appliances, communication devices, and vehicle-mounted devices.

[0353] Note that the solid-state imaging device 100 may be a CMOS sensor or a CCD sensor. In addition, the solid-state imaging device 100 may be formed as one chip, or may be in the form of a module having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together.

[0354] like Fig.38 As shown in FIG. 1 , an imaging device 200 as an electronic device includes an optical unit 202, a solid-state imaging device 100, a digital signal processor (DSP) circuit 203 as a camera signal processing circuit, a frame memory 204, a display unit 205, a recording unit 206, an operation unit 207, and a power supply unit 208. The DSP circuit 203, the frame memory 204, the display unit 205, the recording unit 206, the operation unit 207, and the power supply unit 208 are connected to each other via a bus 209.

[0355] The optical unit 202 includes a plurality of lenses, and captures incident light (image light) from a subject to form an image on a pixel region (not shown) of the solid-state imaging device 100. The solid-state imaging device 100 converts the incident light imaged on the pixel region by the optical unit 202 into an electrical signal in a pixel unit to output the electrical signal as a pixel signal.

[0356] The display unit 205 includes a flat panel display device such as a liquid crystal panel, an organic electroluminescence (EL) panel, or the like, and displays a moving image or a still image captured by the solid-state imaging device 100. The recording unit 206 records the moving image or the still image captured by the solid-state imaging device 100 on a recording medium such as a hard disk or a semiconductor memory.

[0357] The operation unit 207 issues operation commands for various functions of the imaging device 200 under user operation. The power supply unit 208 appropriately supplies various power sources used as operation power sources for the DSP circuit 203, the frame memory 204, the display unit 205, the recording unit 206, and the operation unit 207 to these supply targets.

[0358] In addition, the semiconductor device 101 according to the present disclosure can be widely applied not only to the solid-state imaging device 100, but also to various semiconductor devices 101 constituting circuits such as the DSP circuit 203, the frame memory 204, the recording unit 206, the display unit 205, the operation unit 207, etc.

[0359] As described above, according to the present disclosure, by using the solid-state imaging device 100 as an example of the semiconductor device 101 according to the present disclosure, a high-quality imaging device 200 having excellent cooling performance can be obtained.

[0360] Finally, the description of each of the above-mentioned embodiments is an example of the present disclosure, and the present disclosure is not limited to the above-mentioned embodiments. Therefore, it goes without saying that various modifications other than each of the above-mentioned embodiments can be made according to design, etc. without departing from the technical concept according to the present disclosure. In addition, the effects described in this specification are only examples and are not limited, and other effects can be further provided.

[0361] It should be noted that the present technology may also have the following configurations. (1)

[0363] A semiconductor device comprising:

[0364] Semiconductor components;

[0365] a cooling device on which the semiconductor element is bonded to an upper surface to transfer heat generated by the semiconductor element to a heat dissipation portion;

[0366] A semiconductor package including a cavity for housing a semiconductor element and a cooling device;

[0367] an electrode formed in a heat dissipation portion of the cooling device;

[0368] a terminal formed on a bottom surface of the cavity to face the electrode;

[0369] Conductive resin that joins the electrodes and terminals together; and

[0370] At least one or more detection pattern parts have conductivity and are used to detect wet diffusion of the conductive resin between the electrode and the terminal. (2)

[0372] The semiconductor device according to (1), wherein the detection pattern portion is insulated and arranged on a surface where the terminal is formed, and is configured to detect wet spreading of the conductive resin based on a capacitance value between the detection pattern portion and the terminal. (3)

[0374] The semiconductor device according to (1), wherein the detection pattern portion is arranged in a non-insulated manner on a surface on which the terminal is formed, and is configured to detect wet diffusion of the conductive resin based on a resistance value between the detection pattern portion and the terminal. (4)

[0376] The semiconductor device according to (1), wherein the detection pattern portion is insulated and arranged on a surface where the electrode is formed, and is configured to detect wet spreading of the conductive resin based on a capacitance value between the detection pattern portion and the electrode. (5)

[0378] The semiconductor device according to (1), wherein the detection pattern portion is arranged in a non-insulated manner on a surface where the electrode is formed, and is configured to detect wet spreading of the conductive resin based on a resistance value between the detection pattern portion and the electrode. (6)

[0380] The semiconductor device according to (1), wherein the detection pattern portion is insulated and arranged on a surface where the electrode is formed, and is configured to detect wet spreading of the conductive resin based on a capacitance value between the detection pattern portion and the terminal. (7)

[0382] The semiconductor device according to (1), wherein the detection pattern portion is arranged in a non-insulated manner on a surface where the electrode is formed, and is configured to detect wet spreading of the conductive resin based on a resistance value between the detection pattern portion and the terminal. (8)

[0384] The semiconductor device according to (1), wherein the detection pattern portion is insulated and arranged on a surface where the terminal is formed, and is configured to detect wet spreading of the conductive resin based on a capacitance value between the detection pattern portion and the electrode. (9)

[0386] The semiconductor device according to (1), wherein the detection pattern portion is arranged in a non-insulated manner on a surface on which the terminal is formed, and is configured to detect wet diffusion of the conductive resin based on a resistance value between the detection pattern portion and the electrode. (10)

[0388] The semiconductor device according to any one of (1) to (3), (8) or (9), wherein the detection pattern portion is formed linearly, and at least one detection pattern portion is arranged between the plurality of terminals and between the terminals and the inner wall of the cavity. (11)

[0390] A semiconductor device according to any one of (1) to (3), (8) or (9), wherein the detection pattern portion is formed in a plurality of small detection pattern portions, and the plurality of detection pattern portions are arranged between a plurality of terminals and between the terminals and an inner wall of the cavity. (12)

[0392] The semiconductor device according to any one of (1) or (4) to (7), wherein the detection pattern section is formed linearly, and at least one detection pattern section is arranged between the plurality of electrodes and between the electrode and the inner wall of the cavity. (13)

[0394] The semiconductor device according to any one of (1) or (4) to (7), wherein the detection pattern portion is formed as a plurality of small detection pattern portions, and the plurality of detection pattern portions are arranged between the plurality of electrodes and between the electrodes and the inner wall of the cavity. (14)

[0396] The semiconductor device according to (11) or (13), wherein the small detection pattern portion is formed in a substantially short straight line shape, a substantially rectangular shape, a substantially triangular shape, or a substantially circular shape in a plan view. (15)

[0398] The semiconductor device according to any one of (1), (2), (4), (6), (8), or (10) to (14), wherein the insulation of the detection pattern portion is aluminum oxide (Al 2 O 3 ). (16)

[0400] The semiconductor device according to any one of (1), (2), (4), (6), (8), or (10) to (14), wherein the insulation of the detection pattern portion is an insulating resin. (17)

[0402] The semiconductor device according to any one of (1) to (16), wherein the cooling device includes a Peltier element. (18)

[0404] An electronic device includes a semiconductor device, wherein the semiconductor device includes:

[0405] Semiconductor components;

[0406] a cooling device on which the semiconductor element is bonded to an upper surface to transfer heat generated by the semiconductor element to a heat dissipation portion;

[0407] A semiconductor package including a cavity for housing a semiconductor element and a cooling device;

[0408] an electrode formed in a heat dissipation portion of the cooling device;

[0409] a terminal formed on a bottom surface of the cavity to face the electrode;

[0410] Conductive resin that joins the electrodes and terminals together; and

[0411] At least one or more detection pattern parts have conductivity and are used to detect wet diffusion of the conductive resin between the electrode and the terminal.

[0412] Reference Symbols List

[0413] 10 Semiconductor components

[0414] 10a Connection terminal

[0415] 11 Die bonding materials

[0416] 20Peltier element

[0417] 21 Electrode

[0418] 21c Through hole

[0419] 22 Electrodes

[0420] 22c Through hole

[0421] 23 Ceramic substrate on the heat absorbing side (heat absorbing plate)

[0422] 24 Ceramic substrate on the heat dissipation side (heat dissipation plate)

[0423] 25N semiconductor

[0424] 26P semiconductor

[0425] 30PGA package

[0426] 31 Encapsulation frame body

[0427] 31a Connection terminal

[0428] 31b Wiring

[0429] 31c via

[0430] 31d pad

[0431] 32 Glass cover

[0432] 33 Gold wire (Au)

[0433] 34 pins

[0434] 35 Cavity

[0435] 50 substrates

[0436] 51 Detection pattern section

[0437] 51a Check terminals

[0438] 51b Insulator

[0439] 51c Through Hole

[0440] 51d wiring pattern

[0441] 52 Detection pattern section

[0442] 52a Check terminals

[0443] 52b Insulator

[0444] 52c Through hole

[0445] 53 Detection pattern section

[0446] 53a Check terminals

[0447] 53b Insulator

[0448] 53c Through hole

[0449] 54 Short Linear Pattern

[0450] 55 Rectangle Pattern

[0451] 56 triangle pattern

[0452] 57 Circular Pattern

[0453] 59 Small detection pattern section

[0454] 61 terminal

[0455] 61a Check terminals

[0456] 61d Wiring Pattern

[0457] 62 terminals

[0458] 62a Check terminals

[0459] 62d wiring pattern

[0460] 65 Conductive metal

[0461] 71 Conductive resin

[0462] 72 Conductive resin

[0463] 90 green sheets

[0464] 100 Solid-state imaging device

[0465] 101 Semiconductor Devices

[0466] 200 Imaging device

[0467] Cx, Cy capacitance

[0468] Rx, Ry resistance

Claims

1. A semiconductor device comprising: Semiconductor components; a cooling device on which the semiconductor element is bonded to the upper surface and transfers heat generated by the semiconductor element to a heat dissipation portion; A semiconductor package, comprising a cavity for accommodating the semiconductor element and the cooling device; an electrode formed in the heat dissipation portion of the cooling device; a terminal formed on a bottom surface of the cavity to face the electrode; a conductive resin that bonds the electrode and the terminal together; as well as At least one or more detection pattern parts have conductivity and are used to detect the wet diffusion of the conductive resin between the electrode and the terminal.

2. The semiconductor device according to claim 1, wherein The detection pattern portion is insulated and arranged on a surface where the terminal is formed, and is configured to detect wet spreading of the conductive resin based on a capacitance value between the detection pattern portion and the terminal.

3. The semiconductor device according to claim 1, wherein The detection pattern portion is arranged in a non-insulated manner on a surface where the terminal is formed, and is configured to detect wet spreading of the conductive resin based on a resistance value between the detection pattern portion and the terminal.

4. The semiconductor device according to claim 1, wherein The detection pattern portion is insulated and arranged on a surface where the electrode is formed, and is configured to detect wet spread of the conductive resin based on a capacitance value between the detection pattern portion and the electrode.

5. The semiconductor device according to claim 1, wherein The detection pattern portion is arranged in a non-insulated manner on a surface where the electrode is formed, and is configured to detect wet spreading of the conductive resin based on a resistance value between the detection pattern portion and the electrode.

6. The semiconductor device according to claim 1, wherein The detection pattern portion is insulated and arranged on a surface where the electrode is formed, and is configured to detect wet spread of the conductive resin based on a capacitance value between the detection pattern portion and the terminal.

7. The semiconductor device according to claim 1, wherein The detection pattern portion is arranged in a non-insulated manner on a surface where the electrode is formed, and is configured to detect wet spreading of the conductive resin based on a resistance value between the detection pattern portion and the terminal.

8. The semiconductor device according to claim 1, wherein The detection pattern portion is insulated and arranged on a surface where the terminal is formed, and is configured to detect wet spreading of the conductive resin based on a capacitance value between the detection pattern portion and the electrode.

9. The semiconductor device according to claim 1, wherein: The detection pattern portion is arranged in a non-insulated manner on a surface where the terminal is formed, and is configured to detect wet spreading of the conductive resin based on a resistance value between the detection pattern portion and the electrode.

10. The semiconductor device according to claim 1, wherein The sensing pattern portion is formed in a straight line shape, and at least one sensing pattern portion is arranged between the plurality of terminals and between the terminal and an inner wall of the cavity.

11. The semiconductor device according to claim 1, wherein The sensing pattern portion is formed into a plurality of small sensing pattern portions, and the plurality of sensing pattern portions are arranged between the plurality of terminals and between the terminals and an inner wall of the cavity.

12. The semiconductor device according to claim 1, wherein The sensing pattern portion is formed in a straight line shape, and at least one sensing pattern portion is arranged between the plurality of electrodes and between the electrode and an inner wall of the cavity.

13. The semiconductor device according to claim 1, wherein The sensing pattern portion is formed into a plurality of small sensing pattern portions, and the plurality of sensing pattern portions are arranged between the plurality of electrodes and between the electrodes and an inner wall of the cavity.

14. The semiconductor device according to claim 11, wherein The small detection pattern portion is formed in a substantially short-line shape, a substantially rectangular shape, a substantially triangular shape, or a substantially circular shape in a plan view.

15. The semiconductor device according to claim 1, wherein The insulating material of the detection pattern portion is aluminum oxide (Al2O3).

16. The semiconductor device according to claim 1, wherein The insulation of the detection pattern portion is an insulating resin.

17. The semiconductor device according to claim 1, wherein: The cooling device comprises a Peltier element.

18. An electronic device, comprising a semiconductor device, the semiconductor device comprising: Semiconductor components; a cooling device on which the semiconductor element is bonded to the upper surface and transfers heat generated by the semiconductor element to a heat dissipation portion; A semiconductor package, comprising a cavity for accommodating the semiconductor element and the cooling device; an electrode formed in the heat dissipation portion of the cooling device; a terminal formed on a bottom surface of the cavity to face the electrode; a conductive resin that bonds the electrode and the terminal together; as well as At least one or more detection pattern parts have conductivity and are used to detect the wet diffusion of the conductive resin between the electrode and the terminal.

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