Three-dimensional memory, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a three-dimensional memory, a manufacturing method thereof and a memory system, and the three-dimensional memory comprises a stacking structure which comprises gate layers and dielectric layers which are alternately stacked; the channel columns penetrate through the stacking structure in the first direction, and each channel column comprises a barrier layer, a storage layer, a tunneling layer and a channel layer which are arranged in sequence; a plurality of isolation structures located between the dielectric layer and the tunneling layer in a second direction perpendicular to the first direction; wherein the isolation structure penetrates through at least part of the storage layer in the second direction.

Description

Three-dimensional memory, manufacturing method thereof, and memory system Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to, but not limited to, a three-dimensional memory, a manufacturing method thereof, and a memory system. Background Art

[0002] A 3D memory device typically consists of stacked, insulated gate layers and a channel pillar extending through the gate layers. Along the radial direction of the channel pillar, the pillar comprises a barrier layer, a storage layer (charge-trapping layer), a tunneling layer, and a channel layer. During programming, electrons in the channel layer, under the influence of the gate layer voltage, are injected through the tunneling layer into the storage layer. Traps in the storage layer capture the electrons, allowing information to be stored.

[0003] To increase the storage density of 3D memory, the number of stacked gate layers can be increased, or the radial dimensions of the channel pillars can be reduced to increase the number of memory cells per unit wafer area, thereby increasing storage density. However, regardless of whether the number of stacked gate layers is increased or the channel pillar dimensions are reduced, the film morphology of the channel pillars is difficult to control, which reduces device performance and the stability of the 3D memory. Improving the stability of 3D memory has become a pressing issue.

[0004] Summary of the Invention

[0005] According to a first aspect of an embodiment of the present disclosure, there is provided a three-dimensional memory, comprising:

[0006] A stacked structure comprising alternately stacked gate layers and dielectric layers;

[0007] a plurality of channel pillars, each of which penetrates the stacked structure along a first direction and comprises: a barrier layer, a storage layer, a tunneling layer, and a channel layer arranged in sequence;

[0008] a plurality of isolation structures, the isolation structures being located between the dielectric layer and the tunneling layer in a second direction perpendicular to the first direction;

[0009] The isolation structure penetrates at least a portion of the storage layer along the second direction.

[0010] In some embodiments, a size of a portion of the storage layer between two adjacent isolation structures along the first direction is larger than a size of the gate layer in the first direction.

[0011] In some embodiments, an orthographic projection of a portion of the storage layer between two adjacent isolation structures along the first direction in the second direction at least partially overlaps with an orthographic projection of the gate layer in the second direction.

[0012] In some embodiments, an orthographic projection of the isolation structure in the second direction falls within an orthographic projection of the dielectric layer in the second direction.

[0013] In some embodiments, the isolation structure penetrates the storage layer along the second direction.

[0014] In some embodiments, the storage layer is divided into a plurality of first storage sub-layers by the isolation structure along the first direction.

[0015] In some embodiments, the isolation structure penetrates a portion of the thickness of the storage layer along the second direction, and the thickness of the portion of the storage layer not penetrated by the isolation structure along the second direction is less than a preset value.

[0016] In some embodiments, a portion of the storage layer between two adjacent isolation structures along the first direction constitutes a second storage sub-layer.

[0017] In some embodiments, an orthographic projection of the gate layer in the second direction falls between orthographic projections of two adjacent isolation structures in the first direction in the second direction.

[0018] In some embodiments, the isolation structure extends toward the dielectric layer, and a portion of the isolation structure extends between two adjacent gate layers.

[0019] In some embodiments, the barrier layer is located between the dielectric layer and the isolation structure, and a portion of the isolation structure extending into the dielectric layer is surrounded by the barrier layer.

[0020] In some embodiments, the blocking layer includes a first blocking sublayer and a second blocking sublayer; the second blocking sublayer is located between the first blocking sublayer and the storage layer, and the first blocking sublayer includes a high dielectric material.

[0021] In some embodiments, the first barrier layer comprises an aluminum oxide material, and the second barrier layer comprises a silicon oxide material.

[0022] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a three-dimensional memory is provided, comprising:

[0023] forming a stacked structure comprising alternately stacked dielectric layers and sacrificial layers;

[0024] forming a plurality of channel holes penetrating the stacked structure along a first direction;

[0025] Etching a portion of the dielectric layer along a second direction perpendicular to the first direction through the channel hole to form a gap between two adjacent sacrificial layers;

[0026] forming a barrier layer on the sidewalls of the channel hole;

[0027] forming an isolation structure in the gap;

[0028] forming a storage layer on the barrier layer along the second direction; wherein the isolation structure penetrates at least a portion of the storage layer; and an orthographic projection of a portion of the storage layer between two adjacent isolation structures along the first direction at least partially overlaps with an orthographic projection of the sacrificial layer in the second direction;

[0029] A tunneling layer and a channel layer covering the storage layer are sequentially formed along the second direction; wherein the isolation structure is located between the dielectric layer and the tunneling layer in the second direction.

[0030] In some embodiments, a size of a portion of the storage layer between two adjacent isolation structures along the first direction is larger than a size of the sacrificial layer in the first direction.

[0031] In some embodiments, an orthographic projection of the isolation structure in the second direction falls within an orthographic projection of the dielectric layer in the second direction.

[0032] In some embodiments, the method of forming the isolation structure includes:

[0033] forming an isolation material layer covering the barrier layer and filling the gap;

[0034] The isolation material layer covering the barrier layer is removed, and the remaining isolation material layer is oxidized to form the isolation structure.

[0035] In some embodiments, the isolation material layer is made of at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon.

[0036] In some embodiments, the method of forming the storage layer includes:

[0037] forming a storage material layer covering the barrier layer and the isolation structure;

[0038] The storage material layer is etched to expose the isolation structure to form the storage layer; wherein the storage layer is divided into a plurality of first storage sub-layers by the isolation structure.

[0039] In some embodiments, the method of forming the storage layer includes:

[0040] forming a storage material layer covering the barrier layer and the isolation structure;

[0041] The storage material layer is etched to reduce its thickness in the second direction, so that the thickness of the storage layer and the corresponding area of ​​the isolation structure in the second direction is less than a preset value; wherein, the portion of the storage layer between two adjacent isolation structures along the first direction forms a second storage sublayer.

[0042] In some embodiments, the method of making the barrier layer includes:

[0043] forming a first blocking sublayer on sidewalls of the channel hole including the void;

[0044] A second blocking sublayer is formed covering the first blocking sublayer; wherein the first blocking sublayer comprises a high dielectric material.

[0045] In some embodiments, the manufacturing method further comprises:

[0046] The sacrificial layer is replaced with a conductive material to form a gate layer.

[0047] According to a third aspect of an embodiment of the present disclosure, there is provided a memory system, including:

[0048] A memory device comprising one or more three-dimensional memories according to any one of claims 1 to 12; and

[0049] A memory controller is coupled to the memory device and controls the memory device.

[0050] A three-dimensional memory device according to an embodiment of the present disclosure comprises a stacked structure of alternating gate layers and dielectric layers, with a channel pillar extending through the stacked structure along a first direction. The channel pillar comprises a barrier layer, a memory layer, a tunneling layer, and a channel layer, arranged in sequence. Multiple isolation structures are disposed between the dielectric layer and the tunneling layer along a second direction perpendicular to the first direction, with the isolation structures extending through at least a portion of the memory layer along the second direction. The portion of the memory layer between two adjacent isolation structures in the first direction functions as a charge-trapping layer, enabling a single gate layer to control only the portion of the memory layer between the two isolation structures. The memory layer is electrically isolated by the isolation structures, preventing electron leakage between the portions of the memory layer corresponding to adjacent gate layers, thereby improving the stability of the three-dimensional memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] 1a to 1g are schematic diagrams illustrating a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present disclosure;

[0052] FIG2 is a first structural diagram of a three-dimensional memory according to an embodiment of the present disclosure;

[0053] FIG3 is a second structural diagram of a three-dimensional memory according to an embodiment of the present disclosure;

[0054] FIG4 is a third structural diagram of a three-dimensional memory according to an embodiment of the present disclosure;

[0055] FIG5 is a schematic flow chart of a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0056] 6a to 6k are schematic diagrams illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure;

[0057] FIG7 is a schematic diagram showing an exemplary system having a memory system according to an embodiment of the present disclosure;

[0058] FIG8a is a schematic diagram showing an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0059] FIG8 b is a schematic diagram showing an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0060] FIG9 is a schematic diagram showing an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0061] FIG. 10 is a schematic diagram illustrating an exemplary memory device including a memory array and peripheral circuits according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] The technical solution of the present disclosure is further elaborated in detail below with reference to the accompanying drawings and specific embodiments.

[0063] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0064] In the embodiments of the present disclosure, the term “A is in contact with B” includes a situation where A is in direct contact with B, or a situation where A is in indirect contact with B with other components interposed between A and B.

[0065] In the embodiments of the present disclosure, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent that is smaller than the extent of the lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness that is smaller than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. Furthermore, a layer may include multiple sublayers.

[0066] It will be understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means “on” something with no intervening features or layers (i.e., directly on something), but also includes “on” something with intervening features or layers.

[0067] It should be noted that although this specification is described according to implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation method can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

[0068] In a three-dimensional NAND memory, there is a stacking structure in which a gate layer and a dielectric layer are stacked alternately, and a channel column runs through the stacking structure. Generally, the storage layer in the channel column is usually a continuous film layer structure. The gate layer controls a section of the storage layer corresponding to it, and the part of the storage layer corresponding to the dielectric layer will not be controlled by the gate layer, that is, the electrons only need to be stored in a section of the storage layer corresponding to the gate layer. It can be understood that the storage layer is a continuous film layer structure, and the electrons in the storage layers corresponding to the adjacent gate layers will migrate to each other, resulting in leakage, causing the threshold voltage to shift, resulting in the verification operation of the programming (writing) stage to fail, or making it impossible to read correctly. When the number of stacking layers increases, the size of the channel column decreases, the morphology uniformity of the channel column is poor, the film thickness uniformity of the storage layer is also poor, and the storage layer's ability to bind or capture electrons decreases, which will aggravate the leakage risk between the storage layers corresponding to the gate layer and reduce the stability of the three-dimensional memory. In response to this, an exemplary embodiment of the present disclosure proposes a method for fabricating a three-dimensional memory. This method forms a non-continuous memory layer comprising multiple electrically isolated memory sublayers, each corresponding to a gate layer. This reduces mutual leakage between the memory sublayers and improves the stability of the three-dimensional memory. The method includes:

[0069] Referring to FIG. 1a , a stacked structure is formed, comprising alternating dielectric layers 111 and sacrificial layers 121. The stacked structure may be formed on a substrate (not shown). The stacked structure is etched along a first direction (z-direction) to form a plurality of channel holes 130 extending through the stacked structure. Exemplarily, the etching process may include dry etching, wet etching, or any combination thereof. The present disclosure does not limit the number or arrangement of the channel holes 130; for example, the channel holes 130 may be arranged in any array.

[0070] Exemplarily, the constituent materials of the substrate may include: elemental semiconductor materials (such as silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials or other semiconductor materials known in the art. The substrate may also be doped, such as p-type doping or n-type doping. The substrate in this embodiment is a film layer structure with a certain thickness, which may include a bare wafer or an epitaxial layer. For example, the substrate is a bare wafer (for example, a bare silicon wafer) that has not undergone processes such as coating and etching. Alternatively, the substrate is an epitaxial layer based on epitaxial growth on the surface of a bare wafer. The epitaxial layer material may be the same as or different from the bare wafer material, and the bare wafer may be removed in a certain manufacturing process.

[0071] 1b , the sacrificial layer 121 is etched along the second direction (x-direction) to reduce the size of the sacrificial layer 121 in the x-direction, thereby forming a gap 131 between two adjacent dielectric layers 111. The opening of the gap 131 faces the x-direction. It should be noted that the x-direction herein includes both the positive x-direction and the negative x-direction.

[0072] 1 c , a barrier layer 141 is formed on the sidewalls of the trench hole 130 including the gap 131 ; the barrier layer 141 extends between two adjacent dielectric layers 111 , and the barrier layer 141 does not completely fill the gap 131 .

[0073] 1 d , a storage material layer 142 is formed on the sidewalls of the channel hole 130 including the barrier layer 141 and the gap 131 . The storage material layer 142 fills the gap 131 and covers the surface of the barrier layer 141 in the x direction.

[0074] As shown in FIG1e , the storage material layer 142 is etched along the x-direction, removing a portion of the storage material layer 142 on the surface of the barrier layer 141. The storage material layer 142 remains in the gap 131 to form a storage sublayer 143. Multiple discontinuous storage sublayers 143 are electrically isolated from each other and constitute the storage layer of the three-dimensional memory. The surface of the storage sublayer 143 in the x-direction may or may not be flush with the barrier layer 141.

[0075] 1 f , a tunneling layer 144 and a channel layer 145 are sequentially formed along the x direction to cover the storage layer and the barrier layer 141 ; the channel hole 130 is filled with an insulating material to form a core 146 for supporting the channel pillar 140 .

[0076] As shown in Figure 1g, the sacrificial layer 121 in Figure 1f is removed and replaced with a conductive material to form gate layers 122. Each gate layer 122 controls a corresponding storage sublayer 143. Gate layers 122 serve as word lines for the three-dimensional memory. Exemplary materials for gate layers 122 include tungsten, gold, silver, copper, aluminum, titanium, nickel, chromium, and other conductive materials.

[0077] Exemplarily, the constituent materials of the dielectric layer 111, the barrier layer 141, the tunneling layer 144 and the core 146 include, but are not limited to, insulating materials such as silicon oxide, silicon oxynitride or aluminum oxide. The constituent materials of the sacrificial layer 121 may include, materials such as silicon nitride, polycrystalline silicon, and single crystal silicon. The constituent materials of the storage layer (or storage sublayer 143) may include silicon nitride. The constituent materials of the channel layer 145 include, but are not limited to, semiconductor materials such as single crystal silicon and polycrystalline silicon, and the channel layer 145 may have n-type or p-type doping. In the embodiment of the present disclosure, in order to make each film layer have a greater difference in etching selectivity during the etching process to achieve a better specific etching effect, the material selection along the x-direction of the barrier layer 141-storage sublayer 143-tunneling layer 144 may be: silicon oxide-silicon nitride-silicon oxide; the dielectric layer 111-sacrificial layer 121 may be: silicon oxide-silicon nitride. For example, when etching the sacrificial layer 121 in FIG. 1b , the dielectric layer 111 may be rarely etched or substantially not etched. For example, when etching the storage material layer 142 in FIG. 1e , the barrier layer 141 may be rarely etched or substantially not etched, thereby improving the manufacturing yield of the device.

[0078] For example, the process for forming the stacked structure, the barrier layer 141, the storage material layer 142, the tunneling layer 144, and the channel layer 145 may include any process known in the art, such as low-temperature chemical vapor deposition, low-pressure chemical vapor deposition, rapid thermal chemical vapor deposition, atomic layer deposition, or plasma-enhanced chemical vapor deposition. In addition to the aforementioned chemical deposition process, the process for forming the gate layer 122 also includes a physical deposition process.

[0079] In some specific embodiments, as shown in FIG1g , the storage sublayer 143 will extend into a portion of the gate layer 122, occupying a portion of the space of the gate layer 122. The size of the gate layer 122 in the x-direction will be reduced, and the carrying voltage will decrease to a certain extent, which will, to a certain extent, reduce the gate layer 122's ability to control the storage sublayer 143. In conjunction with FIG1b , on the one hand, etching the sacrificial layer 121 along the x-direction to form the void 131 will cause over-etching of the sacrificial layer 121, resulting in uneven morphology and size of the void 131 (including but not limited to the size in the x-direction or y-direction), ultimately resulting in the uneven morphology and size of the storage sublayer 143 as shown in FIG1g , which in turn causes the threshold voltage of this portion of the storage sublayer 143 to shift, reducing the stability of the memory. On the other hand, after the void 131 shown in FIG1b is formed, the dielectric layers 111 above and below the void 131 collapse and deform to varying degrees due to loss of support, resulting in uneven filling of the storage material inside. A void defect appears in FIG1g, which reduces the charge capture performance of the storage sublayer 143 and reduces the stability of the memory.

[0080] In view of this, according to some aspects of the embodiments of the present disclosure, a three-dimensional memory is provided. As shown in FIG2 , the three-dimensional memory includes:

[0081] A stacked structure comprising alternately stacked gate layers 222 and dielectric layers 211;

[0082] A plurality of channel pillars 240 , each extending through the stacked structure along a first direction (z direction), and comprising a barrier layer 241 , a storage layer 244 , a tunneling layer 245 , and a channel layer 246 , which are sequentially arranged;

[0083] A plurality of isolation structures 232 are disposed between the dielectric layer 211 and the tunneling layer 245 in a second direction (x direction) perpendicular to the first direction.

[0084] The isolation structure 232 penetrates at least a portion of the storage layer 244 along the second direction.

[0085] In some embodiments, as shown in Figure 2, the channel column 240 also includes a core 247. Along the x-direction, a barrier layer 241, a storage layer 244, a tunneling layer 245 and a channel layer 246 are sequentially arranged around the core 247. The channel layer 246 may contact the core 247, and the core 247 is used to support the channel column 240.

[0086] The first direction of the disclosed embodiment may be the z-direction in the accompanying drawings, and the second direction may be the x-direction in the accompanying drawings. The isolation structure 232 shown in FIG2 penetrates the storage layer 244 in the x-direction. The storage layer 244 includes a plurality of first storage sublayers 2441. The isolation structure 232 shown in FIG3 penetrates a portion of the thickness of the storage layer 244 in the x-direction. The storage layer 244 includes a plurality of second storage sublayers 2442. The first storage sublayers 2441 and the second storage sublayers 2442 correspond to the gate layer 222 in the x-direction. The gate layer 222 controls the storage sublayers to store or release electrons. Details are described below.

[0087] 2 , the isolation structure 232 penetrates the memory layer 244 along the second direction. In some embodiments, the memory layer 244 is divided into a plurality of first memory sub-layers 2441 along the first direction by the isolation structure 232.

[0088] In some embodiments, as shown in FIG3 , the isolation structure 232 penetrates a portion of the thickness of the storage layer 244 along the second direction. The thickness of the portion of the storage layer 244 not penetrated by the isolation structure 232 along the second direction is less than a predetermined value. In some embodiments, the portion of the storage layer 244 between two adjacent isolation structures 232 along the first direction constitutes a second storage sub-layer 2442.

[0089] In the disclosed embodiment, the isolation structure 232 may be made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. The isolation structure 232 may penetrate the storage layer 244 along the x-direction in FIG. 2 , dividing the storage layer 244 into discontinuous, electrically isolated first storage sub-layers 2441 capable of independently capturing electrons. Alternatively, as shown in FIG. 3 , the isolation structure 232 may penetrate only a portion of the thickness of the storage layer 244, with the remaining thickness of the storage layer 244 being less than the minimum thickness required for electron capture. Specifically, the portion of the storage layer 244 corresponding to the isolation structure 232 is less than a predetermined thickness, rendering it unable to capture electrons and preventing electrons from diffusing through this thin portion of the storage layer 244. The portion of the storage layer 244 between adjacent isolation structures 232 remains unchanged and maintains a thickness sufficient to capture electrons. Therefore, the isolation structure 232 electrically divides the storage layer 244 into multiple second storage sub-layers 2442 capable of independently capturing electrons.

[0090] In some embodiments, the preset value can be determined based on the composition, density, or operating conditions of the storage layer 244. Different three-dimensional memories have different design requirements. For example, the storage layer 244 shown in Figures 2 and 3 is a silicon nitride layer. In the x-direction, the minimum thickness of the silicon nitride layer that can capture electrons is 3 nm, and the preset value is 3 nm. In some specific embodiments, the thickness of the silicon nitride layer in the x-direction can range from 3 nm to 10 nm.

[0091] Specifically, the storage layer 244 shown in FIG2 is physically penetrated by the isolation structure 232. The storage layer 244 is a discontinuous film structure, and there is a relatively clear physical boundary between the first storage sublayers 2441. In this case, the thickness of the first storage sublayer 2441 can be greater than or equal to 3 nm. The storage layer 244 shown in FIG3 is only partially penetrated by the isolation structure 232. The storage layer 244 is still a continuous film layer, and there is no clear physical boundary between the second storage sublayers 2442. The different thicknesses can be used to distinguish the second storage sublayer 2442 with electron capture function from the portion of the storage layer 244 without electron capture function.

[0092] To illustrate the position of the second storage sublayer 2442, a partial enlarged view of the channel pillar 240 is shown in FIG3, and a dotted line is added in the partial enlarged view to demarcate the position of the second storage sublayer 2442. There is no such dotted line in the actual three-dimensional memory. Referring to FIG3, the storage layer 244 has at least two thicknesses in the x-direction. The second storage sublayer 2442 has a thickness greater than or equal to 3 nm, and the portion of the storage layer 244 with a thickness less than 3 nm does not have an electron capture function. In some specific examples, the thickness range of the first storage sublayer 2441 and the second storage sublayer 2442 may include: 3 nm to 10 nm. On the other hand, if the entire storage layer 244 in FIG3 is projected orthographically along the x-direction, the physical film layer corresponding to the projection between the orthographic projections of the two isolation structures 232 is the second storage sublayer 2442 of this embodiment.

[0093] It should be pointed out that the embodiments shown in Figures 2 and 3 ignore the film thickness difference between the top and bottom of the channel column 240 caused by deposition processes such as ALD. Generally, the film thickness at the top of the channel column 240 is greater than the film thickness at the bottom of the channel column 240.

[0094] Exemplarily, the constituent materials of the isolation structure 232 include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, so as to better separate the storage layer 244 .

[0095] In some embodiments, as shown in FIG. 2 and FIG. 3 , a size of a portion of the memory layer 244 between two adjacent isolation structures 232 along the first direction is larger than a size of the gate layer 222 in the first direction.

[0096] As shown in Figure 2, the isolation structure 232 penetrates the storage layer 244 in the x-direction, dividing the storage layer 244 into a plurality of first storage sub-layers 2441, and the length of the first storage sub-layer 2441 in the z-direction is greater than the thickness of the gate layer 222 in the z-direction. On the one hand, while achieving a correspondence between each gate layer 222 and a first storage sub-layer 2441 in the x-direction, the area facing each other in the x-direction between the gate layer 222 and the storage sub-layer can be increased by increasing the length of the first storage sub-layer 2441 in the z-direction, thereby improving the control performance of the gate layer 222, and also increasing the time and amount of electron capture by the storage sub-layer, thereby improving the stability of the memory. On the other hand, increasing the length of the first storage sub-layer 2441 in the z-direction will not increase the size (for example, diameter) of the channel pillar 240 in the x-direction, which is conducive to maintaining a high integration density of the channel pillar 240.

[0097] As shown in Figure 3, the isolation structure 232 penetrates a portion of the thickness of the storage layer 244 in the x-direction, and forms a second storage sublayer 2442 between the adjacent isolation structures 232 in the z-direction and the storage layer 244 that is not penetrated. The length of the second storage sublayer 2442 in the z-direction is greater than the thickness of the gate layer 222 in the z-direction, which is beneficial to improving the control performance of the gate layer 222, increasing the time and amount of electron capture by the storage sublayer, improving the stability of the memory, and maintaining a higher integration density of the channel column 240.

[0098] In some embodiments, as shown in FIG. 2 and FIG. 3 , an orthographic projection of a portion of the storage layer 244 between two adjacent isolation structures 232 along the first direction in the second direction at least partially overlaps with an orthographic projection of the gate layer 222 in the second direction.

[0099] Specifically, the orthographic projections of the first storage sublayer 2441 and the second storage sublayer 2442 in the x-direction between two adjacent isolation structures 232 shown in Figures 2 and 3 at least partially overlap with the orthographic projections of the gate layer 222 in the x-direction. This allows each gate layer 222 to correspond to a corresponding storage sublayer, controlling the corresponding storage sublayer. Adjacent storage sublayers are electrically isolated by the isolation structures 232, reducing electron migration within the storage sublayers and improving the stability of the three-dimensional memory. Compared to the method of forming storage sublayers by filling voids 131 in Figure 1c , the storage sublayers in the present embodiment achieve mutual electrical isolation to reduce leakage while not requiring them to be formed in the voids. Instead, they are formed solely on the sidewalls of the channel hole 24, resulting in better uniformity, which helps maintain good electron capture performance in the storage sublayers and improves the stability of the three-dimensional memory. The storage sublayers mentioned in the present embodiment include the first storage sublayer 2441 in Figure 2 and the second storage sublayer 2442 in Figure 3 .

[0100] In some embodiments, as shown in FIG. 2 and FIG. 3 , the orthographic projection of the isolation structure 232 in the x-direction falls within the orthographic projection of the dielectric layer 211 in the x-direction.

[0101] In some embodiments, as shown in FIG. 2 and FIG. 3 , the orthographic projection of the gate layer 222 in the x-direction falls between the orthographic projections of two adjacent isolation structures 232 in the z-direction in the x-direction.

[0102] In this structural layout, the gate layer 222 can fully participate in controlling the storage sublayer in the x-direction, which can increase the load voltage range of the gate layer 222 and maximize the facing area between the gate layer 222 and the storage sublayer in the x-direction, thereby improving the control performance of the gate layer 222, increasing the time and amount of electron capture by the storage sublayer, and improving the stability of the memory.

[0103] In some embodiments, the isolation structure 232 in Figures 2 and 3 can be offset up and down along the z-direction, reserving a portion of the storage layer 244 with charge-trapping capabilities to correspond to each gate layer 222, allowing the gate layer 222 to control the storage sublayer. It is understood that an isolation structure 232 can be offset up and down to occupy a portion of the space of the gate layer 222. Compared to Figures 2 and 3, this embodiment can reduce the difficulty of aligning the isolation structure 232 with the dielectric layer 211 while maintaining good performance of the gate layer 222 and the storage sublayer, thereby reducing manufacturing difficulty and improving the process window.

[0104] 2 and 3 may partially penetrate the barrier layer 241 along the x-direction, or completely penetrate the barrier layer 241 and extend into the dielectric layer 211. The barrier layer 241 comprises an insulating material and may be a single-layer structure or a multi-layer composite structure.

[0105] In some other embodiments, the barrier layer 241 shown in Figures 2 and 3 may include a first barrier sublayer 2411 and a second barrier sublayer 2412. The first barrier sublayer 2411 surrounds the second barrier sublayer 2412 and is located between the second barrier sublayer 2412 and the stacked structure in the x-direction, while the second barrier sublayer 2412 is located between the first barrier sublayer 2411 and the storage layer 244. The isolation structure 232 may partially or completely penetrate the second barrier sublayer 2412. After penetrating the second barrier sublayer 2412, the isolation structure 232 may also partially or completely penetrate the first barrier sublayer 2411. In some embodiments, the isolation structure 232 does not penetrate the barrier layer 241 but extends into the dielectric layer 211, and the isolation structure 232 is surrounded by the barrier layer 241. In some embodiments, the isolation structure 232 may also penetrate the barrier layer 241 and extend into the dielectric layer 211.

[0106] Exemplarily, the second blocking sublayer 2412 may include insulating materials such as silicon oxide and silicon oxynitride, and the first blocking sublayer 2411 may include high dielectric materials such as aluminum oxide to improve the insulation performance of the blocking layer 241 and reduce leakage of the gate layer 222. The first blocking sublayer 2411 can be used to protect the channel column 240 during the production process of the gate layer 222 to prevent the etchant from damaging the channel column 240 by etching.

[0107] In some embodiments, after penetrating the storage layer 244 along the x-direction, the isolation structure 232 shown in FIG. 2 may continue to extend along the x-direction, penetrating or partially penetrating the tunneling layer 245, but not extending to the channel layer 246. The tunneling layer 245 is used to facilitate electron tunneling between the storage sublayer corresponding to the gate layer 222 and the channel layer 246, and is also used to prevent leakage of the storage sublayer when not in operation. Therefore, the actual active area of ​​the tunneling layer 245 is the area corresponding to the gate layer 222 in the x-direction. The isolation structure 232 does not occupy the space of the gate layer 222, so the extension of the isolation structure 232 into the barrier layer does not reduce the stability of the memory.

[0108] The isolation structure 232 of the embodiment of the present disclosure is arranged corresponding to the dielectric layer 211. The arrangement of the isolation structure 232 does not change the thickness uniformity of the storage sublayer. On the premise that the storage sublayer corresponds to the gate layer 222, the isolation structure 232 can be extended in the x-direction. The isolation structure 232 does not extend into the channel layer 246, thereby reducing the difficulty of manufacturing the isolation structure 232.

[0109] In some embodiments, as shown in conjunction with Figures 2 and 3 , the isolation structure 232 extends toward the dielectric layer 211, with a portion of the isolation structure 232 extending between two adjacent gate layers 222. In this embodiment, the isolation structure 232 extends between the two gate layers 222 along the x-direction. This does not occupy the space within the gate layers 222 and does not disrupt the morphology of the storage sublayer. While maintaining good thickness uniformity of the storage sublayer, the isolation structure 232 can be increased in the x-direction, improving electrical isolation performance for the storage sublayer. When extending between the two adjacent gate layers 222, the isolation structure 232 can partially or completely penetrate the barrier layer 241.

[0110] In some other embodiments, the isolation structure 232 may not extend into the dielectric layer 211, that is, the isolation structure 232 does not occupy the space of the dielectric layer 211. For example, the three-dimensional memory shown in FIG4 is different from the three-dimensional memory shown in FIG2 and FIG3 , in which the orthographic projection of the isolation structure 232 along the z direction overlaps with the orthographic projection of the gate layer 222 along the z direction. In this embodiment, the orthographic projection of the isolation structure 232 along the z direction does not overlap with the orthographic projection of the gate layer 222 in the z direction. The size of the isolation structure 232 in the x direction shown in FIG4 can be smaller than the size of the isolation structure 232 in the x direction in FIG2 and FIG3 , which helps to reduce the size of the channel pillar 240 in the x direction and improve the integration density of the three-dimensional memory.

[0111] In some embodiments, the barrier layer 241 is located between the dielectric layer 211 and the isolation structure 232 , and the portion of the isolation structure 232 extending into the dielectric layer 211 is surrounded by the barrier layer 241 .

[0112] In this embodiment, the isolation structure 232 does not penetrate the barrier layer 241, which is a continuous film structure. In other embodiments, the isolation structure 232 may partially or completely penetrate the barrier layer 241 along the x-direction, and the isolation structure does not occupy the space of the gate layer 222, which helps maintain the structural uniformity of the gate layer 222 and the stability of the three-dimensional memory. The isolation structure 232 and the barrier layer 241 can have a relatively clear physical boundary. However, when the barrier layer 241 does not completely penetrate the barrier layer 241, and the material composition and film density of the isolation structure 232 and the barrier layer 241 are the same or similar, especially after high-temperature annealing to eliminate film stress and repair defects, the isolation structure 232 and the barrier layer 241 may not have a relatively clear physical boundary.

[0113] In some embodiments, the blocking layer 241 includes a first blocking sublayer 2411 and a second blocking sublayer 2412 ; the second blocking sublayer 2412 is located between the first blocking sublayer 2411 and the storage layer 244 ; the first blocking sublayer 2411 includes a high dielectric material.

[0114] In some embodiments, the first blocking sublayer 2411 includes an aluminum oxide material, and the second blocking sublayer 2412 includes a silicon oxide material.

[0115] The dielectric constant of the first blocking sublayer 2411 can be greater than that of the second blocking sublayer 2412. When achieving equivalent insulation performance, the high-dielectric material can have a smaller film thickness, thereby reducing the total thickness of the blocking layer 241 and increasing the integration density of the channel pillars 240. Specifically, the first blocking sublayer 2411 can include a high-dielectric material such as aluminum oxide, and the second insulating layer can include commonly used silicon oxide. The first blocking sublayer 2411 can also serve as an etching protection layer during the fabrication of the gate layer 222, protecting the channel pillars 240 from etching damage caused by the etchant.

[0116] According to some aspects of the embodiments of the present disclosure, a method for manufacturing a three-dimensional memory is provided. As shown in FIG5 , the method includes:

[0117] forming a stacked structure comprising alternately stacked dielectric layers and sacrificial layers; and forming a plurality of channel holes penetrating the stacked structure along a first direction.

[0118] Etching a portion of the dielectric layer along a second direction perpendicular to the first direction through the channel hole to form a gap between two adjacent sacrificial layers;

[0119] forming a barrier layer on sidewalls of the trench hole;

[0120] forming an isolation structure in the void;

[0121] A storage layer is formed on the barrier layer along the second direction; wherein the isolation structure penetrates at least a portion of the storage layer; and an orthographic projection of a portion of the storage layer between two adjacent isolation structures along the first direction in the second direction at least partially overlaps with an orthographic projection of the sacrificial layer in the second direction;

[0122] A tunneling layer and a channel layer covering the storage layer are formed in sequence along the second direction; wherein the isolation structure is located between the dielectric layer and the tunneling layer in the second direction.

[0123] Specifically, as shown in Figure 6a, dielectric layers 211 and sacrificial layers 221 can be alternately deposited on the substrate to form a stacked structure. The constituent material of the dielectric layer 211 may include silicon oxide, and the constituent material of the sacrificial layer 221 may include silicon nitride. Channel holes 24 are then formed along the z direction to penetrate the stacked structure. The embodiment of the present disclosure does not limit the number and array of the channel holes 24.

[0124] As shown in FIG6 b , the dielectric layer 211 is etched along the x-direction through the channel hole 24 to reduce the size of the dielectric layer 211 in the x-direction, so that a gap 23 is formed between two adjacent sacrificial layers 221. The opening of the gap 23 faces the x-direction, and the x-direction may include the x-positive and x-negative directions. The etching process includes, but is not limited to, dry etching, wet etching, or a combination thereof. In some specific embodiments, the dielectric layer 211 may be silicon oxide, and the sacrificial layer 221 may be silicon nitride. The silicon oxide is etched using an etching solution including hydrofluoric acid, and the etching rate of silicon nitride in hydrofluoric acid is much lower than that of silicon oxide, or silicon nitride is basically not etched in hydrofluoric acid. While forming the gap 23, the sacrificial layer 221 can also be protected from being etched, maintaining the good morphology of the sacrificial layer 221. When the sacrificial layer 221 is replaced by the gate layer 222, the gate layer 222 also has a good morphology, thereby improving the manufacturing yield of the device. The wet etching method of this embodiment has lower production cost than dry etching, and the size of the void 23 in the x-direction can be controlled by etching time. The longer the etching time, the larger the size of the void 23 in the x-direction, that is, the deeper the void 23 extends into the dielectric layer 211.

[0125] 6c , a barrier layer 241 is deposited on the sidewalls of the channel hole 24 including the void 23 in FIG. 6b . The barrier layer 241 may include a single-layer film or a multi-layer film structure. The barrier layer 241 may cover the sidewalls of the sacrificial layer 221 and the inner wall of the void 23. It will be appreciated that in some specific embodiments, as shown in conjunction with FIG. 2 and FIG. 3 , the sacrificial layer 221 will subsequently be replaced with a conductive gate layer 222 for controlling the storage layer 244. The barrier layer 241 serves as a gate dielectric layer to electrically isolate the gate layer 222 from the storage sublayer. Therefore, the barrier layer 241 in the embodiment of the present disclosure may only cover the side surfaces of the sacrificial layer 221 through a selective deposition process. The barrier layer 241 does not cover the inner wall of the void 23. In this case, the barrier layer 241 is a discontinuous film layer structure. For example, a reaction gas that is compatible with the sacrificial layer 221 but incompatible with the dielectric layer 211 can be used to selectively deposit the barrier layer 241 only on the sidewalls of the sacrificial layer 221. The sacrificial layer 221 may include silicon nitride, and the dielectric layer 211 may include silicon oxide. The barrier layer 241 may be made of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxide.

[0126] In some embodiments, as shown in FIG. 6 c , forming the barrier layer 241 includes:

[0127] forming a first blocking sublayer 2411 on the sidewalls of the channel hole 24 including the gap 23 shown in FIG6 b ;

[0128] A second blocking sublayer 2412 is formed covering the first blocking sublayer 2411. The first blocking sublayer 2411 may have a greater dielectric constant than the second blocking sublayer 2412. In this embodiment, the first blocking sublayer 2411 may comprise a high dielectric constant material such as aluminum oxide, while the second blocking sublayer 2412 may comprise silicon oxide. While maintaining or improving insulation performance, the high dielectric constant material may also reduce the overall thickness of the blocking layer 241, thereby increasing integration.

[0129] In some embodiments, a method of forming the isolation structure 232 includes:

[0130] 6 d , an isolation material layer 231 is formed to cover the barrier layer 241 and fill the gap 23 ;

[0131] 6e, a portion of the isolation material layer 231 covering the barrier layer 241 is removed;

[0132] 6 f , the remaining isolation material layer 231 is oxidized to form an isolation structure 232 .

[0133] In FIG6e , after etching away the isolation material layer 231 covering the barrier layer 241, the barrier layer 241 is exposed, leaving the sacrificial layer 221 free of the isolation material layer 231 in the x-direction. This facilitates the subsequent formation of the storage layer 244 and facilitates the subsequent control of the storage sublayer by the gate layer 222. In this embodiment, the x-direction surface of the etched isolation material layer 231 is flush with the x-direction surface of the barrier layer 241. In other embodiments, the etching process may over-etch, leaving the x-direction surface of the remaining isolation material layer 231 lower than the x-direction surface of the barrier layer 241. Oxidation of the isolation material layer 231 increases the x-direction size of the isolation material layer 231. The x-direction size of the isolation material layer 231 generated in FIG6f may be larger than that of the isolation material layer 231 shown in FIG6e , with the x-direction surface of the isolation structure 232 protruding from the x-direction surface of the barrier layer 241.

[0134] In some embodiments, the isolation material layer 231 in Figures 6d and 6e is composed of at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The silicon in the isolation material layer 231 is oxidized to form silicon oxide, causing the isolation material to grow along the x-direction to form an isolation structure 232 comprising silicon oxide. The composition of the isolation material layer 231 in this embodiment is merely illustrative; other materials may include germanium, aluminum, or the like. Oxidation of the isolation material layer 231 to form an insulating oxide forms the isolation structure 232. A longer oxidation time increases the x-direction size of the isolation structure 232. The oxidation process may include a thermal oxidation process in a tube furnace or a reaction chamber. It should be noted that in this embodiment, the entire isolation material layer 231 may participate in the oxidation reaction, i.e., the entire silicon is oxidized to silicon oxide. Alternatively, a portion of the isolation material layer 231 may participate in the oxidation reaction, i.e., a portion of the silicon exposed on the sidewalls of the channel hole 24 is oxidized to silicon oxide, while the remaining portion remains silicon.

[0135] In some embodiments, in addition to the oxidation process, the fabrication methods of Figures 6e to 6f in the embodiments of the present disclosure may also be completed using a selective deposition process. For example, the material of the isolation material layer 231 in Figure 6e is different from the material of the barrier layer 241. During the deposition process, a reactive gas that is affinity for the isolation material layer 231 is selected to react with the isolation material layer 231 to form the isolation structure 232. The barrier layer 241 is not affinity for or does not react with the reactive gas, and a film-forming reaction does not occur on the surface of the barrier layer 241. Similar to the solution of forming the isolation structure 232 by oxidizing the isolation material layer 231 in the previous embodiment, in the selective deposition process, a portion of the isolation material layer 231 participates in the film-forming reaction, or the entire isolation material layer 231 participates in the film-forming reaction.

[0136] In some embodiments, during the deposition process for forming the isolation structure 232, the isolation material layer 231 may not participate in the film-forming reaction. For example, before the deposition reaction, an activated gas is supplied to the channel hole 24. This activated gas has an affinity for the isolation material layer 231, but not for the barrier layer 241. Subsequently, the deposition reaction gas is introduced. The activated gas acts as a catalyst during the deposition reaction, accelerating the film-forming reaction on the isolation material layer 231. This results in the isolation structure 232 being formed on the side of the isolation material layer 231 exposed in the channel hole 24, while not being formed, or substantially not being formed, on the barrier layer 241. Even if a small amount of material layer is formed on the barrier layer 241, it can be removed using an etching process. At this point, the isolation structure 232 and the isolation material layer 231 are two separate structures, not shown in the figure.

[0137] In some embodiments, the size of the void 23 in the x-direction can be adjusted by adjusting the etching parameters in FIG. 6 b . When the size of the void 23 in the x-direction is large, the void 23 can extend to a greater depth into the dielectric layer 211, so that the orthographic projection of the isolation structure 232 formed in FIG. 6 e in the z-direction overlaps with the orthographic projection of the sacrificial layer 221 in the z-direction. In other embodiments, the depth of the void 23 extending into the dielectric layer 211 is small, so that the orthographic projection of the isolation structure 232 formed in the z-direction does not overlap with the orthographic projection of the sacrificial layer 221 in the z-direction. The resulting three-dimensional memory structure can be as shown in FIG. 4 .

[0138] In some embodiments, as shown in FIG. 6 f , the orthographic projection of the isolation structure 232 in the x-direction falls within the orthographic projection of the dielectric layer 211 in the second direction.

[0139] In this embodiment, the isolation structure 232 corresponds to the dielectric layer 211 and is formed between two adjacent sacrificial layers 221 in the z direction. The isolation structure 232 does not occupy the space of the sacrificial layer 221, so that the gate layer 222 formed by subsequently replacing the sacrificial layer 221 has a better morphology and a larger size, which is beneficial to increasing the load voltage of the gate layer 222 and improving the stability of the device.

[0140] In some embodiments, a method of forming the storage layer 244 includes:

[0141] 6g, a storage material layer 243 is formed covering the barrier layer 241 and the isolation structure 232;

[0142] 6 h , the storage material layer 243 is etched to expose the isolation structure 232 to form a storage layer 244 ; wherein the storage layer 244 is divided into a plurality of first storage sub-layers 2441 by the isolation structure 232 .

[0143] In Figure 6g, the isolation structure 232 protrudes from the surface of the barrier layer 241 in the x-direction. The deposited storage material layer 243 covers the surface of the barrier layer 241 and the isolation structure 232, so that a portion of the isolation structure 232 extends into the storage material layer 243. In Figure 6h, a portion of the storage material layer 243 is etched using the channel hole 24 to reduce its thickness in the x-direction until the isolation structure 232 is exposed. The originally continuous storage layer 244 is penetrated by the isolation structure 232 and divided into multiple first storage sub-layers 2441. The storage sub-layers include silicon nitride and can have a thickness in the x-direction greater than or equal to 3 nm.

[0144] In this embodiment, the isolation structure 232 can be flush with the plane of the first storage sublayer 2441 in the x-direction. As shown in FIG6i , a tunneling layer 245 and a channel layer 246 are sequentially formed in the x-direction. The isolation structure 232 is located between the dielectric layer 211 and the tunneling layer 245 in the x-direction, and the isolation structure 232 does not extend into the tunneling layer 245. Exemplarily, the tunneling layer 245 includes an insulating material such as silicon oxide or silicon oxynitride. The channel layer 246 includes a semiconductor material such as single crystal silicon or polycrystalline silicon.

[0145] In some embodiments, when etching the storage material layer 243 shown in FIG. 6g , the storage material layer 243 may be overetched to remove the isolation material layer 243 on the barrier layer 241. When the isolation structure 232 penetrates the storage layer 244 to form the first storage sub-layer 2441, it also protrudes in the x-direction beyond the surface of the first storage sub-layer 2441. The tunneling layer 245 subsequently formed is shown in FIG. 6j , with the isolation structure 232 extending into the tunneling layer 245 along the x-direction. The tunneling layer 245 facilitates electron tunneling between the storage sub-layer corresponding to the gate layer 222 and the channel layer 246, and also prevents leakage from the storage sub-layer when not in operation. Therefore, the actual active area of ​​the tunneling layer 245 is the area corresponding to the gate layer 222 in the x-direction. The isolation structure 232 does not occupy the space of the gate layer 222, so the extension of the isolation structure 232 into the barrier layer does not degrade the stability of the memory. This also increases the process window of the etching process shown in FIG. 6g , reducing manufacturing difficulty.

[0146] In some embodiments, a method of forming the storage layer 244 includes:

[0147] 6g, a storage material layer 243 is formed covering the barrier layer 241 and the isolation structure 232;

[0148] The storage material layer 243 is etched to reduce its thickness in the x-direction. The resulting storage layer 244 and the corresponding regions of the isolation structure 232 have a thickness in the second direction that is less than a predetermined value. The portion of the storage layer 244 between two adjacent isolation structures 232 in the z-direction forms the second storage sublayer 2442. In some embodiments, this predetermined value may be 3 nm. This predetermined value can be determined based on the material and density of the storage layer 244, as well as operating conditions. Different three-dimensional memories have different design requirements.

[0149] As shown in Figure 6k , by adjusting process parameters such as the etching time, the amount of etching applied to the storage material layer 243 is reduced, preventing the isolation structure 232 from being exposed. The thickness of the storage material layer 243 in the x-direction shown in Figure 6g is greater than or equal to a predetermined value. After etching, the remaining portion of the storage material layer 243 corresponding to the isolation structure 232 in the x-direction is less than the predetermined value. This portion of the storage material layer 243 is too thin to adequately capture electrons. Unlike the discontinuous storage layer 244 shown in Figures 6h to 6j , the storage layer 244 in Figure 6k is a continuous film layer. There are no clear physical boundaries between the second storage sublayers 2442. The different thicknesses allow for the distinction between the second storage sublayers 2442 with electron-trapping functionality and the portions of the storage layer 244 without it. The storage layer 244 has at least two thicknesses in the x-direction: the second storage sublayer 2442 with a thickness greater than or equal to 3 nm, and the portion of the storage layer 244 with a thickness less than 3 nm without electron-trapping functionality. On the other hand, if the entire storage layer 244 in FIG. 3 is orthographically projected along the x-direction, the projection between the two isolation structures 232 orthographic projections corresponds to the solid film layer of this embodiment, which is the second storage sub-layer 2442. It should be noted that the embodiment of the present disclosure ignores the film thickness difference between the top and bottom of the channel pillar 240 caused by deposition processes such as ALD. Generally, the film layer at the top of the channel pillar 240 is thicker than the film layer at the bottom of the channel pillar 240.

[0150] In some embodiments, as shown in FIG. 6 h and FIG. 6 k , a size of a portion of the memory layer 244 between two adjacent isolation structures 232 along the first direction is larger than a size of the gate layer 222 in the first direction.

[0151] As shown in Figure 6h, the storage layer 244 is penetrated by the isolation structure 232 in the x-direction to form a first storage sublayer 2441. The length of the first storage sublayer 2441 in the z-direction is greater than the thickness of the gate layer 222 in the z-direction. On the one hand, while achieving that each gate layer 222 corresponds to a first storage sublayer 2441 in the x-direction, the area of ​​the gate layer 222 facing the storage sublayer in the x-direction can be increased by increasing the length of the first storage sublayer 2441 in the z-direction, thereby improving the control performance of the gate layer 222, and also increasing the time and amount of electron capture by the storage sublayer, thereby improving the stability of the memory. On the other hand, increasing the length of the first storage sublayer 2441 in the z-direction will not increase the size (for example, diameter) of the channel pillar 240 in the x-direction, which is conducive to maintaining a high integration density of the channel pillar 240.

[0152] As shown in Figure 6k, the isolation structure 232 penetrates a portion of the thickness of the storage layer 244 in the x-direction, and forms a second storage sublayer 2442 between the adjacent isolation structures 232 in the z-direction and the storage layer 244 that is not penetrated. The length of the second storage sublayer 2442 in the z-direction is greater than the thickness of the gate layer 222 in the z-direction, which is beneficial to improving the control performance of the gate layer 222, increasing the time and amount of electron capture by the storage sublayer, improving the stability of the memory, and helping to maintain a higher integration density of the channel column 240.

[0153] In some embodiments, as shown in FIG. 6 i , after the channel layer 246 is fabricated, the remaining space of the channel hole 24 is filled with an insulating material to form a core portion 247 for supporting the channel pillar 240 .

[0154] In some embodiments, the fabrication method further includes replacing the sacrificial layer 221 with a conductive material to form a gate layer 222. Specifically, the sacrificial layer 221 is first etched away to form a cavity between adjacent dielectric layers 211, and the cavity is filled with a conductive material to form the gate layer 222. The gate layer 222 may be made of, but not limited to, conductive materials such as tungsten, gold, silver, copper, aluminum, titanium, nickel, and chromium. For example, the sacrificial layer 221 in FIG. 6i is replaced with the gate layer 222 to form the three-dimensional memory device shown in FIG. 2, and the sacrificial layer 221 in FIG. 6k is replaced with the gate layer 222 to form the three-dimensional memory device shown in FIG. 3.

[0155] According to some aspects of the embodiments of the present disclosure, there is provided a memory system, including:

[0156] A memory device comprising one or more three-dimensional memories as described in the above embodiments; and

[0157] A memory controller is coupled to the memory device and controls the memory device.

[0158] FIG7 shows a block diagram of an exemplary system 700 with a memory device in accordance with some aspects of the present disclosure. The system 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG7 , the system 700 may include a host 708 and a memory system 702, the memory system 702 having one or more memory devices 704 and a memory controller 706. The host 708 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 708 may be configured to send data to or receive data from the memory device 704.

[0159] Memory device 704 can be any memory disclosed in the present disclosure. As disclosed in detail below, memory device 704 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from driver transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows the size of the driver transistors to be further reduced.

[0160] According to some embodiments, the memory controller 706 is coupled to the memory device 704 and the host 708 and is configured to control the memory device 704. The memory controller 706 may manage data stored in the memory device 704 and communicate with the host 708.

[0161] In some embodiments, the memory controller 706 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 706 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The memory controller 706 can be configured to control the operations of the memory device 704, such as read, erase, and program operations. The memory controller 706 can also be configured to manage various functions related to data stored or to be stored in the memory device 704, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.

[0162] In some embodiments, the memory controller 706 is further configured to process error correction codes (ECC) on data read from or written to the memory device 704. The memory controller 706 may also perform any other suitable functions, such as formatting the memory device 704. The memory controller 706 may communicate with an external device (e.g., the host 708) according to a specific communication protocol. For example, the memory controller 706 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer miniature interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0163] The memory controller 706 and one or more memory devices 704 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of end-use electronic products. In one example, as shown in FIG8a, the memory controller 706 and a single memory device 704 can be integrated into a memory card 802. The memory card 802 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, etc. The memory card 802 can also include a memory card connector 804 that couples the memory card 802 to a host (e.g., the host 708 in FIG7 ). In another example, as shown in FIG8b, the memory controller 706 and multiple memory devices 704 can be integrated into an SSD 806. SSD 806 may also include an SSD connector 808 that couples SSD 806 to a host (e.g., host 708 in FIG. 7 ). In some embodiments, the storage capacity and / or operating speed of SSD 806 is greater than the storage capacity and / or operating speed of memory card 802. The disclosed embodiments do not limit the packaging form and execution protocol of the memory controller and memory device; these can be selected and optimized based on the host interface protocol and actual user needs.

[0164] In some embodiments, a memory device may include a memory array and a peripheral circuit. The memory array and the peripheral circuit may be arranged on the same wafer, that is, the memory array and the peripheral circuit are arranged on the same die to form a chip. The memory array and the peripheral circuit may be arranged on different wafers, that is, the memory array die and the peripheral circuit die are formed into a chip by hybrid bonding. The die mentioned in the embodiment of the present disclosure is divided based on the memory array. A die may or may not include a peripheral circuit. The memory array may include multiple dies. A die of the memory array includes at least one storage plane. Adjacent planes can be divided by cutting lines. Each plane may include multiple pages. The memory cells on each page share a word line. Each page can be used as the minimum unit for read and write operations. Each plane can be divided into multiple storage blocks. Each block can be used as the minimum unit for erase operations. A memory device may include one die or multiple dies. A memory device may include multiple memory arrays.

[0165] FIG9 shows a schematic circuit diagram of an exemplary memory device 900 including peripheral circuitry according to some aspects of the present disclosure. Memory device 900 may be an example of memory device 704 in FIG7 . Memory device 900 may include a memory array 901 and peripheral circuitry 902 coupled to memory array 901. Memory array 901 may be a NAND flash memory array in which memory cells 906 are provided in the form of an array of NAND memory strings 908, each NAND memory string 908 extending vertically above a substrate (not shown).

[0166] In some embodiments, each NAND memory string 908 includes a plurality of memory cells 906 coupled in series and stacked vertically. Each memory cell 906 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 906. Each memory cell 906 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0167] In some embodiments, each memory cell 906 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" can correspond to a first voltage range, and the second memory state "1" can correspond to a second voltage range. In some embodiments, each memory cell 906 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed by writing one of three possible nominal storage values ​​to the cell, while a fourth nominal storage value in addition to the three nominal storage values ​​can be used to represent an erased state.

[0168] As shown in Figure 9, each NAND memory string 908 can include a source select gate (SSG) 910 at its source end and a drain select gate (DSG) 912 at its drain end. The SSG 910 and DSG 912 can be configured to activate the selected NAND memory string 908 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 908 in the same block 904 are coupled by the same source line (SL) 914 (e.g., a common SL).

[0169] According to some embodiments, all NAND memory strings 908 in the same block 904 have an array common source (ACS). According to some embodiments, the DSG 912 of each NAND memory string 908 is coupled to a corresponding bit line 916, from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 908 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the DSG 912) or a deselect voltage (e.g., 0V) to the corresponding DSG 912 via one or more DSG lines 913 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor having the SSG 910) or a deselect voltage (e.g., 0V) to the corresponding SSG 910 via one or more SSG lines 915.

[0170] As shown in FIG9 , a NAND memory string 908 can be organized into a plurality of blocks 904, each of which can have a common source line 914 (e.g., coupled to ground). In some embodiments, each block 904 is a basic data unit for an erase operation, i.e., all memory cells 906 on the same block 904 are erased simultaneously. To erase the memory cells 906 in a selected block 904a, the source lines 914 coupled to the selected block 904a and the unselected blocks 904b in the same plane as the selected block 904a can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)).

[0171] It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of a block. Memory cells 906 of adjacent NAND memory strings 908 can be coupled via word lines 918, which select which row of memory cells 906 are affected by read and program operations. In some embodiments, each word line 918 is coupled to a page 920 of memory cells 906, which is the basic unit of data for programming operations. The size of a page 920 in bits can be related to the number of NAND memory strings 908 coupled by the word lines 918 in a block 904. Each word line 918 can include multiple control gates (gate electrodes) at each memory cell 906 in the corresponding page 920 and gate lines coupling the control gates. The page 920 shown in FIG. 9 can include a row of memory cells 906, or it can include multiple rows of memory cells 906 on the same layer that share a common word line voltage.

[0172] In some embodiments, the physical device structure of the NAND memory string 908 may include the structures shown in Figure 1g and Figures 2 to 4. A NAND memory string 908 may include one or more channel pillars 140, and may also include one or more channel pillars 240. A NAND string may also include multiple channel pillars stacked and coupled.

[0173] The word line 918 in FIG9 may correspond to the gate layer 122 in FIG1g or the gate layer 222 in FIG2 to FIG4. The gate layer 122 or the gate layer 222 at the top of the stack structure may extend laterally to serve as an upper select gate line, the gate layer 411 at the bottom of the stack structure 410 may extend laterally to serve as a lower select gate line, and the gate layer extending laterally between the upper select gate line and the lower select gate line may serve as a word line layer.

[0174] Referring back to FIG. 9 , the peripheral circuit 902 can be coupled to the memory array 901 via bit lines 916, word lines 918, source lines 914, SSG lines 915, and DSG lines 913. The peripheral circuit 902 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory array 901 by applying voltage and / or current signals to each target memory cell 906 and sensing voltage and / or current signals from each target memory cell 906 via the bit lines 916, word lines 918, source lines 914, SSG lines 915, and DSG lines 913. The peripheral circuit 902 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. The memory array 901 can include a plurality of arranged channel pillars 140 or a plurality of arranged channel pillars 240. The embodiments of the present disclosure are not limited to the arrangement or number of channel pillars.

[0175] In some embodiments, FIG10 shows some exemplary peripheral circuits, where the peripheral circuit 902 includes a page buffer / sense amplifier 1004, a column decoder / bit line driver 1006, a row decoder / word line driver 1008, a voltage generator 1010, a control logic unit 1012, a register 1014, an interface 1016, and a data bus 1018. It should be understood that in some examples, additional peripheral circuits not shown in FIG10 may also be included.

[0176] The page buffer / sense amplifier 1004 can be configured to read data from the memory array 901 and program (write) data to the memory array 901 based on control signals from the control logic unit 1012. In one example, the page buffer / sense amplifier 1004 can store a page of program data (write data) to be programmed into one page 920 of the memory array 901. In another example, the page buffer / sense amplifier 1004 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 906 coupled to the selected word line 918. In yet another example, the page buffer / sense amplifier 1004 can also sense a low-power signal from the bit line 916 representing a data bit stored in the memory cell 906 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 1006 can be configured to be controlled by the control logic unit 1012 and select one or more NAND memory strings 908 by applying a bit line voltage generated by the voltage generator 1010.

[0177] The row decoder / word line driver 1008 can be configured to be controlled by the control logic unit 1012 and select / deselect the block 904 of the memory array 901 and select / deselect the word line 918 of the block 904. The row decoder / word line driver 1008 can also be configured to drive the word line 918 using the word line voltage generated from the voltage generator 1010. In some embodiments, the row decoder / word line driver 1008 can also select / deselect and drive the SSG line 915 and the DSG line 913. As described in detail below, the row decoder / word line driver 1008 is configured to perform an erase operation on the memory cell 906 coupled to the selected word line(s) 918. The voltage generator 1010 can be configured to be controlled by the control logic unit 1012 and generate word line voltages (e.g., read voltage, program voltage, pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 901.

[0178] The control logic unit 1012 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. The register 1014 can be coupled to the control logic unit 1012 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 1016 can be coupled to the control logic unit 1012 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 1012, as well as buffer status information received from the control logic unit 1012 and relay it to the host. The interface 1016 can also be coupled to the column decoder / bit line driver 1006 via the data bus 1018 and act as a data I / O interface and data buffer to buffer data and relay it to the memory array 901 or relay or buffer data from the memory array 901.

[0179] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A three-dimensional memory, comprising: A stacked structure, the stacked structure comprising alternately stacked gate layers and dielectric layers; A plurality of channel pillars, wherein the channel pillars penetrate the stack structure along a first direction, and include: a barrier layer, a storage layer, a tunnel layer, and a channel layer arranged in sequence; a plurality of isolation structures, the isolation structures being located between the dielectric layer and the tunneling layer in a second direction perpendicular to the first direction; Wherein, the isolation structure penetrates at least a portion of the storage layer along the second direction.

2. The three-dimensional memory according to claim 1, wherein: A size of a portion of the storage layer between two of the isolation structures adjacent to each other along the first direction in the first direction is greater than a size of the gate layer in the first direction.

3. The three-dimensional memory according to claim 2, wherein: An orthographic projection of a portion of the storage layer between two of the isolation structures adjacent to each other along the first direction in the second direction at least partially overlaps with an orthographic projection of the gate layer in the second direction.

4. The three-dimensional memory according to claim 1, wherein: An orthographic projection of the isolation structure in the second direction falls within an orthographic projection of the dielectric layer in the second direction.

5. The three-dimensional memory according to claim 1, wherein: The isolation structure penetrates the storage layer along the second direction.

6. The three-dimensional memory according to claim 5, wherein: The storage layer is divided into a plurality of first storage sub-layers by the isolation structure along the first direction.

7. The three-dimensional memory according to claim 1, wherein: The isolation structure penetrates a portion of the storage layer along the second direction, and the thickness of the portion of the storage layer not penetrated by the isolation structure along the second direction is less than a preset value.

8. The three-dimensional memory according to claim 7, wherein: A portion of the storage layer between two of the isolation structures adjacent to each other along the first direction constitutes a second storage sub-layer.

9. The three-dimensional memory according to claim 1, wherein: The orthographic projection of the gate layer in the second direction falls between the orthographic projections of two adjacent isolation structures in the first direction in the second direction.

10. The three-dimensional memory according to claim 1, wherein: The isolation structure extends toward the dielectric layer, and a portion of the isolation structure extends into between two adjacent gate layers.

11. The three-dimensional memory according to claim 10, wherein: The barrier layer is located between the dielectric layer and the isolation structure, and a portion of the isolation structure extending into the dielectric layer is surrounded by the barrier layer.

12. The three-dimensional memory according to claim 1, wherein: The blocking layer includes a first blocking sublayer and a second blocking sublayer; the second blocking sublayer is located between the first blocking sublayer and the storage layer, and the first blocking sublayer includes a high dielectric material.

13. The three-dimensional memory according to claim 12, wherein: The first barrier layer includes an aluminum oxide material, and the second barrier layer includes a silicon oxide material.

14. A method for manufacturing a three-dimensional memory, comprising: forming a stacked structure comprising alternately stacked dielectric layers and sacrificial layers; forming a plurality of channel holes penetrating the stacked structure along a first direction; Etching a portion of the dielectric layer along a second direction perpendicular to the first direction through the channel hole to form a gap between two adjacent sacrificial layers; forming a barrier layer on the sidewalls of the channel hole; forming an isolation structure in the gap; forming a storage layer on the barrier layer; wherein the isolation structure penetrates at least a portion of the storage layer along the second direction; A tunneling layer and a channel layer covering the storage layer are formed in sequence; wherein the isolation structure is located between the dielectric layer and the tunneling layer in the second direction.

15. The method according to claim 14, wherein: A size of a portion of the storage layer between two of the isolation structures adjacent to each other along the first direction in the first direction is greater than a size of the sacrificial layer in the first direction.

16. The method according to claim 14, wherein: An orthographic projection of the isolation structure in the second direction falls within an orthographic projection of the dielectric layer in the second direction.

17. The method according to claim 14, wherein: The method of forming the isolation structure includes: forming an isolation material layer covering the barrier layer and filling the gap; The isolation material layer covering the barrier layer is removed, and the remaining isolation material layer is oxidized to form the isolation structure.

18. The method according to claim 17, wherein: The constituent material of the isolation material layer includes: at least one of single crystal silicon, polycrystalline silicon, and amorphous silicon.

19. The method according to claim 14, wherein: The method of forming the storage layer includes: forming a storage material layer covering the barrier layer and the isolation structure; The storage material layer is etched to expose the isolation structure to form the storage layer; wherein the storage layer is divided into a plurality of first storage sub-layers by the isolation structure.

20. The method according to claim 14, wherein: The method of forming the storage layer includes: forming a storage material layer covering the barrier layer and the isolation structure; The storage material layer is etched to reduce its thickness in the second direction, and the thickness of the storage layer and the corresponding area of ​​the isolation structure in the second direction is less than a preset value; wherein a portion of the storage layer between two adjacent isolation structures along the first direction forms a second storage sublayer.

21. The method according to claim 14, wherein: The method for making the barrier layer comprises: forming a first blocking sublayer on sidewalls of the channel hole including the void; forming a second barrier sublayer covering the first barrier sublayer; wherein the first barrier sublayer The layer includes a high dielectric material.

22. The method according to claim 14, wherein: The production method further comprises: The sacrificial layer is replaced with a conductive material to form a gate layer.

23. A memory system comprising: A memory device comprising one or more three-dimensional memories according to any one of claims 1 to 13; as well as A memory controller is coupled to the memory device and controls the memory device.

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