Semiconductor packaging finished product and testing method thereof

Abstract

The invention provides a semiconductor packaging finished product and a test method thereof, and belongs to the technical field of semiconductors. The semiconductor packaging finished product comprises a first crystal grain which comprises a first input circuit, a first output channel and a first coding circuit; and the second crystal grain comprises a second input circuit, a second output channel and a second coding circuit. Wherein the first input circuit and the second input circuit are used for receiving the same test signal from the same measurement output channel of a test machine, the first output channel and the second output channel are coupled to form the same shared output channel, the first coding circuit is used for coding a first crystal grain as a main crystal grain, and the second coding circuit is used for coding a second crystal grain as a main crystal grain. The second coding circuit is used for coding a second crystal grain into a slave crystal grain, and the shared output channel is used for serially outputting first test data read from the main crystal grain and second test data read from the crystal grain according to a test signal; and the first test data and the second test data which are output in series are input to the same measurement input channel of the test machine.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor packaged finished product and a testing method thereof. Background Art

[0002] In order to reduce packaging costs and increase the integration of semiconductor products, multiple dies are packaged into the same semiconductor packaged product. In related technologies, one die corresponds to one output channel, which increases the number of output channels of the same semiconductor packaged product. However, the number of measurement input channels of a test machine is usually fixed, which reduces the number of semiconductor packaged products that can be tested by the test machine at the same time, increases testing costs, and reduces testing efficiency. Summary of the invention

[0003] The embodiment of the present disclosure provides a semiconductor package product, including: a first die, including a first input circuit, a first output channel and a first encoding circuit; a second die, including a second input circuit, a second output channel and a second encoding circuit. The first input circuit and the second input circuit are used to receive the same test signal from the same measurement output channel of the test machine, the first output channel and the second output channel are coupled as the same shared output channel, the first encoding circuit is used to encode the first die as a master die, the second encoding circuit is used to encode the second die as a slave die, and the shared output channel is used to serially output the first test data read from the master die and the second test data read from the slave die according to the test signal, so as to input the first test data and the second test data outputted in series into the same measurement input channel of the test machine.

[0004] The disclosed embodiment further provides a method for testing a finished semiconductor package, wherein a first die and a second die are packaged in the finished semiconductor package, wherein the first die is a master die, and the second die is a slave die, and the first output channel of the first die and the second output channel of the second die are coupled to form a same shared output channel. The method comprises: the master die and the slave die simultaneously receive the same test signal from the same measurement output channel of the test machine, wherein the test signal comprises a delay signal; according to the test signal, first test data is read from the master die and output to the measurement input channel of the test machine through the shared output channel; according to the test signal, second test data is read from the slave die, and after a predetermined clock cycle is delayed according to the delay signal, the second test data is output to the measurement input channel through the shared output channel.

[0005] The disclosed embodiment further provides a method for testing a finished semiconductor package, wherein the finished semiconductor package includes a first die and a second die, wherein the first die is a master die, and the second die is a slave die, wherein a first output channel of the first die and a second output channel of the second die are coupled to form a shared output channel. The method includes: the same measurement output channel of a test machine simultaneously inputs the same test signal to the first die and the second die, wherein the test signal includes a delay signal; the same measurement input channel of the test machine receives first test data and second test data output in series from the shared output channel, wherein the first test data is read from the master die based on the test signal, and the second test data is read from the slave die based on the test signal and the delay signal therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic diagram of a semiconductor packaging product in the related art.

[0007] Figure 2 It is a test schematic diagram of a semiconductor packaged finished product in the related art.

[0008] Figure 3 It is a test schematic diagram of another semiconductor package product in the related art.

[0009] Figure 4 is a schematic diagram of a finished semiconductor package according to an exemplary embodiment of the present disclosure.

[0010] Figure 5 is a schematic diagram of a finished semiconductor package according to another exemplary embodiment of the present disclosure.

[0011] Figure 6 Schematic diagram of a coding circuit according to an exemplary embodiment of the present disclosure.

[0012] Figure 7 1 is a schematic diagram of testing a finished semiconductor package according to an exemplary embodiment of the present disclosure.

[0013] Figure 8 FIG. 4 is a schematic diagram of a semiconductor package product according to another exemplary embodiment of the present disclosure.

[0014] Fig. 9 is a schematic diagram of testing a finished semiconductor package according to yet another exemplary embodiment of the present disclosure.

[0015] Fig.10 FIG. 4 is a schematic diagram of a semiconductor package product according to another exemplary embodiment of the present disclosure.

[0016] Fig.11 FIG. 4 is a schematic diagram of a semiconductor package product according to another exemplary embodiment of the present disclosure.

[0017] Fig.12 FIG. 4 is a schematic diagram of a semiconductor package product according to another exemplary embodiment of the present disclosure.

[0018] Fig.13 The present invention is a flowchart of a method for testing a finished semiconductor package according to an exemplary embodiment of the present invention.

[0019] Fig.14 The flowchart of a method for testing a finished semiconductor package product according to another exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] The accompanying drawings are only schematic diagrams of the present disclosure. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. The memory provided in the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings.

[0021] like Figure 1 As shown, in the semiconductor package product in the related art, it is assumed that two dies are packaged, namely, die 1 and die 2. Die 1 and die 2 in the same semiconductor package product input the same test signal at the same time. Die 1 and die 2 have their own independent output channels, and the output channels of die 1 and die 2 output their own test data at the same time. For example, the test data read from die 1 is assumed to be 0, 1, 2, 3, and the test data read from die 2 is assumed to be a, b, c, d, that is, the output channels of die 1 and die 2 are output in parallel. Therefore, during the test process, it is necessary to use the two measurement input channels of the test machine to receive the test data output by die 1 and die 2 respectively.

[0022] like Figure 2 As shown above Figure 1 Taking the example of packaging two dies in each semiconductor packaged product, that is, testing two dies stacked in each semiconductor packaged product, assuming that the test machine has only eight fixed measurement input channels, the eight measurement input channels are respectively connected to the eight output channels of the eight dies in four semiconductor packaged products, that is, only four semiconductor packaged products can be tested, for example Figure 2 The semiconductor packaged product 1, the semiconductor packaged product 2, the semiconductor packaged product 3 and the semiconductor packaged product 4 are shown in FIG.

[0023] like Figure 3As shown, when four dies (die 1, die 2, die 3 and die 4) are packaged in each semiconductor package product, and the four output channels of the four dies are output in parallel, assuming that the test machine still has only eight fixed measurement input channels, the eight measurement input channels are respectively connected to the eight output channels of the eight dies in two semiconductor package products, that is, only two semiconductor package products can be tested, for example Figure 3 The semiconductor package product 1 and the semiconductor package product 2 shown in FIG.

[0024] According to the above Figures 1 to 3 It can be seen that since multiple dies are stacked in the same semiconductor package product, multiple output channels of the multiple dies output test data in parallel. In order to complete the test of the newly added dies, it is necessary to increase the test of the output channels of the newly added dies. When the test machine does not increase the number of measurement input channels, the related art provides a corresponding multiple (e.g. Figure 2 In the middle, it is 2 times, Figure 3 Although the test can be completed by using measurement input channels (4 times in the example) to test the same semiconductor packaged product, the number of semiconductor packaged products tested at the same time will be reduced, thereby increasing the test cost and reducing the test efficiency.

[0025] Figure 4 FIG. 1 is a schematic diagram of a semiconductor package product according to an exemplary embodiment of the present disclosure. Figure 4 As shown, the semiconductor package product 400 provided by the embodiment of the present disclosure includes a first die (eg Figure 4 The grain 410 in the embodiment and the second grain (eg Figure 4 It can be understood that the semiconductor package product in the embodiment of the present disclosure simultaneously packages two or more dies. Figure 4 The embodiment is described with two dies as an example, but the present disclosure is not limited thereto.

[0026] The die 410 includes a first input circuit ( Figure 4 ), the first output channel 412 and the first encoding circuit ( Figure 4 not shown).

[0027] Die 420 includes a second input circuit ( Figure 4 ), the second output channel 422 and the second encoding circuit ( Figure 4 not shown).

[0028] The input end 411 of the first input circuit of the die 410 and the input end 421 of the second input circuit of the die 420 are used to receive the same test signal from the same measurement output channel 510 of the test machine 500. When the die 410 and the die 420 are packaged in the same semiconductor package product 400, the input end 411 of the die 410 and the input end 421 of the die 420 receive the same test signal through the same input pin after packaging, which can reduce the number of external pins of the packaged product.

[0029] The first output channel 412 of the die 410 and the second output channel 422 of the die 420 are coupled to the same shared output channel 600. The first encoding circuit in the die 410 is used to encode the die 410 as a master, and the second encoding circuit in the die 420 is used to encode the die 420 as a slave. The shared output channel of the die 410 and the die 420 is used to serially output the first test data read from the master die and the second test data read from the slave die according to the received test signal, so as to input the serially output first test data and the second test data into the same measurement input channel of the test machine.

[0030] In the disclosed embodiment, when multiple grains are packaged in the same semiconductor package product, the output channels of two or more grains among the multiple grains are coupled into the same shared output channel. When the shared output channel is used to serially output the test data of the two or more grains, the grain that outputs its test data first is the master grain, and the grain that outputs its test data through the shared output channel after the test data of the master grain is output is the slave grain.

[0031] For example, Figure 4 As shown, assuming that according to the test signal, the first test signal read from the grain 410 is 0, 1, 2, 3, and the second test data read from the grain 420 is a, b, c, d, when the grain 410 is encoded as the master grain and the grain 420 is encoded as the slave grain, the first test signal 0, 1, 2, 3 is output first, and then the second test data a, b, c, d is output, that is, the second test data is delayed by 4 clock cycles before being output.

[0032] In an exemplary embodiment, the test signal sent by the test machine 500 to the die 410 and the die 420 may include a test mode indication signal, and the test mode indication signal is used to indicate that the semiconductor package product 400 is currently in the test mode (test mode). When the semiconductor package product 400 is in the test mode, the first output channel 412 of the die 410 and the second output channel 422 of the die 420 are coupled to the same shared output channel 600. When the semiconductor package product 400 is not in the test mode, the first output channel 412 of the die 410 and the second output channel 422 of the die 420 are independent of each other, that is, they still maintain parallel output.

[0033] During the test, the test machine 500 can judge whether the die 410 and the die 420 can perform the correct data storage function by reading the first test data and the second test data from the die 410 and the die 420. For example, it is judged whether the read first test data and the second test data are respectively consistent with the first write data and the second write data previously written into the die 410 and the die 420. If the first test data and the first write data are consistent, it is determined that the die 410 can perform the correct data storage function. If the first test data and the first write data are inconsistent, it is determined that the die 410 cannot perform the correct data storage function. If the second test data and the second write data are consistent, it is determined that the die 420 can perform the correct data storage function. If the second test data and the second write data are inconsistent, it is determined that the die 420 cannot perform the correct data storage function.

[0034] The semiconductor packaged product provided by the embodiments of the present disclosure can, on the one hand, increase the integration of semiconductor products and reduce packaging costs by simultaneously packaging multiple grains in the semiconductor packaged product; on the other hand, by coupling multiple output channels of the multiple grains into the same shared output channel, during testing, encode the multiple grains separately through the encoding circuits inside the multiple grains, for example, encode the first grain as a master grain and the second grain as a slave grain, and use the shared output channel to first output the first test data read from the master grain and then output the second test data read from the slave grain, thereby modifying the parallel output of the test data of the multiple grains into serial output. When the number of measurement input channels of the test machine is fixed, the number of semiconductor packaged products that can complete the test at the same time can be increased without purchasing additional test machines, thereby reducing the test cost and improving the test efficiency.

[0035] In an exemplary embodiment, the output end of the first encoding circuit is used to output a first switch control signal of a first level to indicate that the first die is a master die. The test signal includes a delay signal. The first die also includes: a first delay output control circuit and a first switch element. The first switch element is used to not transmit the delay signal to the first delay output control circuit according to the first switch control signal of the first level, so that the shared output channel outputs the first test data to the test machine first.

[0036] In an exemplary embodiment, the output end of the second encoding circuit is used to output a second switch control signal of a second level to indicate that the second die is a slave die. The test signal includes a delay signal. The second die also includes: a second delay output control circuit and a second switch element. The second switch element is used to transmit the delay signal to the second delay output control circuit according to the second switch control signal of the second level, so that the shared output channel delays the second test data according to the delay signal for a predetermined clock period and then outputs it to the test machine.

[0037] Combine the following Figure 5 The semiconductor package product provided by the embodiment of the present disclosure is illustrated by way of example.

[0038] like Figure 5As shown, the die 410 packaged in the semiconductor package product 400 includes a first encoding circuit 413, a first delayed output control circuit 414, a first input circuit 415, a first database 416, a first output circuit 417 and a first switch element 418. The test signal sent by the test machine includes a delay signal. In the embodiment of the present disclosure, the delay signal is used to indicate that the corresponding test data is delayed for a predetermined clock period before being output to the test machine. Among them, the predetermined clock period is greater than or equal to the number of clock periods of the test data previously output to the test machine through the shared output channel. The output end of the first encoding circuit 413 is used to output a first switch control signal Fzout1 of a first level to indicate that the die 410 is a main die. For example, the first level can be a low level, but the present disclosure is not limited thereto, as long as the first switch control signal of the first level can prevent the delay signal from being transmitted to the first delayed output control circuit 414. The first delayed output control circuit 414 includes a first input end, a second input end, a third input end and an output end. The first switch element 418 includes an input end, a control end and an output end. The first input circuit 415 also includes a first output terminal, a second output terminal and a third output terminal. The control terminal of the first switch element 418 is coupled to the output terminal of the first encoding circuit 413 to receive the first switch control signal Fzout1 of the first level, and the input terminal of the first switch element 418 is coupled to the third output terminal of the first input circuit 415 to receive the delay signal SO (abbreviation of Slave Option) in the test signal sent by the test machine from the first input circuit 415. The first input terminal of the first delay output control circuit 414 is coupled to the output terminal of the first switch element 418. The first input circuit 415 includes a plurality of input terminals, which can be used to receive differential clock signals CK_t and CK_c, and test instructions (Commands, abbreviated as Cm) respectively. The test instructions may include a plurality of test instructions, such as a read command (Read Command) or a write command (Write Command), an address signal, etc. The address signal may specifically include a bank group (storage body group) address signal, a bank (storage body) address signal, a row address signal, a column address signal, etc. Here, a read command and an address signal corresponding to the read command are used as examples for illustration, but the present disclosure is not limited thereto. The first input circuit 415 can generate a clock pulse according to the received differential clock signals CK_t and CK_c. The first output end of the first input circuit 415 is coupled to the second input end of the first delay output control circuit 414 to input the generated clock pulse to the first delay output control circuit 414. The second output end of the first input circuit 415 is coupled to the input end of the first database 416 to read the first test data from the corresponding address of the first database 416 according to the received test instruction, such as a read command and a corresponding address signal.The output end of the first database 416 is coupled to the third input end of the first delay output control circuit 414 to input the first test data to the first delay output control circuit 414. Under the control of the first switch control signal Fzout1 of the first level, the first switch element 418 is turned off (disconnected), so that the delay signal SO sent by the test machine will not be transmitted to the first delay output control circuit 414. Therefore, the first delay output control circuit 414 outputs the first test data to the input end of the first output circuit 417 through the output end of the first delay output control circuit 414 without delay according to the received clock pulse and the first test data. The output end of the first output circuit 417 is coupled to the first output channel 412 of the die 410 to output the first test data.

[0039] Continue to refer Figure 5, the packaged die 420 in the semiconductor package product 400 includes a second encoding circuit 423, a second delayed output control circuit 424, a second input circuit 425, a second database 426, a second output circuit 427 and a second switch element 428. The output end of the second encoding circuit 423 is used to output a second switch control signal Fzout2 of a second level to indicate that the die 420 is a slave die. For example, the second level can be a high level, but the present disclosure is not limited to this, as long as the second switch control signal of the second level can transmit the delay signal to the second delayed output control circuit 424. The second delayed output control circuit 424 includes a first input end, a second input end, a third input end and an output end. The second switch element 428 includes an input end, a control end and an output end. The control end of the second switch element 428 is coupled to the output end of the second encoding circuit 423 to receive the second switch control signal Fzout2 of the second level, and the input end of the second switch element 428 is coupled to the third output end of the second input circuit 425 to receive the delay signal SO sent by the test machine. The first input end of the second delay output control circuit 424 is coupled to the output end of the second switch element 428. The second input circuit 425 includes a plurality of input ends, which can be used to receive the differential clock signals CK_t and CK_c, and the test instruction (Cm) respectively. The test instruction may include a plurality of test instructions, such as a read command, an address signal, etc. The second input circuit 425 can generate a clock pulse according to the received differential clock signals CK_t and CK_c. The second input circuit 425 also includes a first output end and a second output end. The first output end of the second input circuit 425 is coupled to the second input end of the second delay output control circuit 424 to input the generated clock pulse to the second delay output control circuit 424. The second output end of the second input circuit 425 is coupled to the input end of the second database 426 to read the second test data from the corresponding address of the second database 426 according to the received test instruction, such as a read command and a corresponding address signal. The output end of the second database 426 is coupled to the third input end of the second delay output control circuit 424 to input the second test data to the second delay output control circuit 424. Under the control of the second switch control signal Fzout2 of the second level, the second switch element 428 opens (closes) the second switch element 428, so that the delay signal SO sent by the test machine is transmitted to the second delay output control circuit 424. Therefore, the second delay output control circuit 424 delays the second test data by a predetermined clock cycle according to the received clock pulse, the delay signal and the second test data, and then outputs the second test data to the input end of the second output circuit 427 through the output end of the second delay output control circuit 424.The output end of the second output circuit 427 is coupled to the second output channel 422 of the die 420. The second output channel 422 is coupled to the first output channel 412 to form a shared output channel, and the second test data after the predetermined clock cycle is delayed is output through the shared output channel. For example, if the first test data needs to occupy 4 clock cycles (4T) of the clock pulse to be output through the shared output channel, the predetermined clock cycle is greater than or equal to 4T.

[0040] In the embodiments of the present disclosure, the crystal grain may be a semiconductor memory chip, such as a DRAM (Dynamic Random Access Memory) chip. DRAM is used as an example below, but the present disclosure is not limited to this. The first input circuit and the second input circuit may be a command receiving circuit (Control logic) in a DRAM chip, and the command receiving circuit may include a Command decode, an ODT (On-Die Termination, terminal resistance on the crystal grain) control, and a Mode register, but the present disclosure is not limited to this. The first database and the second database may be a data storage module in a DRAM chip, and the data storage module may include multiple banks (for example, bank 0 to bank 15). Figure 5 Not shown in the figure, it may also include row address latches and decoders of each bank, column address counters / latches, column decoders, sense amplifiers, self-refresh counters, etc. The first delayed output control circuit and the second delayed output control circuit may be read logic in a DRAM chip. The first output circuit and the second output circuit may be drivers in a DRAM chip.

[0041] The semiconductor packaged product provided by the embodiments of the present disclosure, on the one hand, couples the output channels of at least two of the multiple dies packaged in the semiconductor packaged product (for example, the first output channel in the first die and the second output channel in the second die) into the same shared output channel, and outputs the test data of the at least two dies (for example, the first test data of the first die and the second test data of the second die) in series to the same measurement input channel of the test machine through the shared output channel, thereby increasing the number of semiconductor packaged products tested simultaneously without increasing the cost of the test machine, reducing the test cost and improving the test efficiency; on the other hand, a coding circuit is preset in the at least two dies (for example, the first coding circuit in the first die and the second coding circuit in the second die), and the at least two dies can be pre-encoded as a master die and a slave die respectively through the coding circuit preset inside the die, thereby knowing to which die's delay output control circuit the delay signal received simultaneously from the test machine is to be transmitted, so as to accurately determine which die's test data is output first and which die's test data is output later during serial transmission, thereby ensuring the accuracy of serial transmission and improving test reliability. At the same time, the encoding circuit is pre-set inside the die, and before the test, it has been encoded which die is the main die and which die is the slave die. In this way, after packaging, the at least two die can share the same external pins and receive the same test signal sent by the test machine. That is, from the external pins of the finished product after packaging, there is no difference between the at least two die, but the main die and the slave die are automatically identified inside the die, thereby reducing the complexity of the test, and there is no need to add additional external pins and additional test signals after packaging the finished product, thereby simplifying the test process.

[0042] In an exemplary embodiment, the first encoding circuit targets a one-time programming memory cell in a first die.

[0043] In an exemplary embodiment, the target one-time programming memory cell in the first die is not programmed, so that the output terminal of the first encoding circuit outputs a first switch control signal of a first level.

[0044] In an exemplary embodiment, the second encoding circuit targets a one-time programming memory cell in the second die.

[0045] In an exemplary embodiment, the target one-time programming memory cell in the second die has been programmed so that the output terminal of the second encoding circuit outputs a second switch control signal of a second level.

[0046] In other embodiments, the target one-time programming storage unit in the first die may be burned to indicate that the first die is the master die, and the target one-time programming storage unit in the second die may not be burned to indicate that the second die is the slave die. This disclosure does not limit this.

[0047] In the disclosed embodiment, the output channels of at least two of the multiple dies packaged in the same semiconductor packaged finished product are coupled as the same shared output channel. For the at least two dies, a coding circuit is pre-set inside to identify the master dies and the slave dies. The coding circuit set inside the dies can reuse the one-time programming memory (efuse) already inside the dies, thereby simplifying the internal structure of the dies and reducing the design complexity and cost. Specifically, each dies includes an efuse array, and the efuse array includes a plurality of efuse cells (one-time programming storage units) arranged in an array. Before testing, at least one efuse cell can be selected from the plurality of efuse cells in advance to be used as the coding circuit inside the dies. The efuse cell selected as the coding circuit is referred to as the target one-time programming storage unit.

[0048] Combine the following Figure 6 Examples are given for illustration, but the present disclosure is not limited thereto. Figure 6 As shown, the encoding circuit 600 in the embodiment of the present disclosure can be used as Figure 5 The first encoding circuit 413 and / or the second encoding circuit 423 in the embodiment. The encoding circuit 600 may include a control circuit 610, an efuse transistor M1 and a switch transistor M2. The control end of the efuse transistor M1 is coupled to the output end of the control circuit 610, and the first end of the efuse transistor M1 is coupled to the second end of the efuse transistor M1. The second end of the efuse transistor M1 is coupled to the first end of the switch transistor M2. The control end of the switch transistor M2 is used to receive the address selection signal Xadd. The second end of the switch transistor M2 serves as the output end of the encoding circuit 600. The switch transistor M2 can be turned on or off according to the high or low level of the received address selection signal Xadd. When the switch transistor M2 is turned on according to the received address selection signal Xadd, it is determined that the efuse transistor M1 is selected as the target one-time programming storage unit of the corresponding die. The control circuit 610 can be used to generate a first control signal Con1, and input the first control signal Con1 to the control end of the efuse transistor M1 through the output end of the control circuit 610 to control the conduction or cutoff of the efuse transistor M1. For example, when the first control signal Con1 is at a high level to turn on the efuse transistor M1, it is determined that the target one-time programming memory cell is burned, and the switch control signal Fzout output at this time is the second switch control signal Fzout2 of the second level. When the first control signal Con1 is at a low level to turn off the efuse transistor M1, it is determined that the target one-time programming memory cell is not burned, and the switch control signal Fzout output at this time is the first switch control signal Fzout1 of the first level.

[0049] Figure 6 The efuse transistor M1 and the switch transistor M2 in the embodiment can be PMOS (P-channel Metal Oxide Semiconductor, P-type channel metal oxide semiconductor) transistors, or NMOS (N-channel Metal Oxide Semiconductor, N-type channel metal oxide semiconductor) transistors. At this time, the control end of the efuse transistor M1 and the switch transistor M2 is the gate of PMOS or NMOS, the first end is the source or drain of PMOS or NMOS, and the second end is the drain or source of PMOS or NMOS. If the efuse transistor M1 and the switch transistor M2 are NMOS transistors, the high level is turned on and the low level is cut off; if they are PMOS transistors, the low level is turned on and the high level is cut off.

[0050] In the disclosed embodiment, the existing efuse inside the die is used as the encoding circuit of the corresponding die for identification of the master die and the slave die, thereby reducing the design complexity of the die and reducing the manufacturing cost of the die.

[0051] In an exemplary embodiment, the target one-time programming memory cells in the second die are burned before or after packaging the second die into a finished semiconductor package.

[0052] In the embodiment of the present disclosure, if the target one-time programming storage unit in the second die is burned to indicate that the second die is a slave die, the target one-time programming storage unit in the second die can be burned before the second die is packaged into the finished semiconductor package. Alternatively, the target one-time programming storage unit in the second die can be burned after the second die is packaged into the finished semiconductor package and before testing. Before the test, the first output channel of the first die and the second output channel of the second die are not coupled together, that is, they are independent of each other, and then the corresponding control instruction is sent to the second die to burn the target one-time programming storage unit in the second die separately.

[0053] like Figure 7 As shown, in the same case where two dies (die 1 and die 2) are packaged in each semiconductor packaged product and the test machine has 8 measurement input channels, the method provided by the embodiment of the present disclosure can simultaneously test 8 semiconductor packaged products, namely semiconductor packaged products 1 to semiconductor packaged products 8. Figure 2 The number of finished semiconductor packages tested simultaneously has doubled.

[0054] like Figure 8As shown, it is assumed that four dies are packaged in the same semiconductor package product 800, namely, die 1, die 2, die 3 and die 4. The output channels of every two dies can be coupled together to share the output channel. For example, the output channels of die 1 and die 2 are coupled to a shared output channel to serially output the first test data of die 1 and the second test data of die 2 to a measurement input channel of the test machine, and the output channels of die 3 and die 4 are coupled to another shared output channel to serially output the third test data of die 3 and the fourth test data of die 4 to another measurement input channel of the test machine.

[0055] like Fig. 9 As shown, in the same case where 4 dies (die 1 to die 4) are packaged in each semiconductor packaged product and the test machine has 8 measurement input channels, the method provided by the embodiment of the present disclosure can simultaneously test 4 semiconductor packaged products, namely semiconductor packaged products 1 to semiconductor packaged products 4. Figure 3 The number of finished semiconductor packages tested simultaneously has doubled.

[0056] like Fig.10 As shown, it is assumed that four dies are packaged in the same semiconductor package product 1000, namely, die 1, die 2, die 3 and die 4. The output channels of three of the dies can be coupled together to share the output channel, and the remaining 1 die maintains its original independent output channel. For example, the output channels of die 1 to die 3 are coupled to a shared output channel to serially output the first test data of die 1, the second test data of die 2 and the third test data of die 3 to a measurement input channel of the test machine, and the output channel of die 4 outputs the fourth test data of die 4 to another measurement input channel of the test machine.

[0057] correspond Fig.10 The semiconductor package product 1000 shown can be Fig.11 The structure shown in the figure is used to implement this. Fig.11As shown, the delay signal includes a first delay signal SO1 and a second delay signal SO2. The first delay signal SO1 is used to indicate that the second test data is delayed by a first predetermined clock cycle (for example, 4T, depending on the clock cycle occupied by the first test data) before being output to the test machine. The second delay signal SO2 is used to indicate that the third test data is delayed by a second predetermined clock cycle (for example, 8T, depending on the clock cycle occupied by the first test data and the second test data) before being output to the test machine. The first switch control signal of the first level includes a first-first switch control signal Fzout11 of the first level and a first-second switch control signal Fzout12 of the first level. The output end of the first encoding circuit 13 includes a first output end and a second output end, so as to output the first-first switch control signal Fzout11 of the first level and the first-second switch control signal Fzout12 of the first level respectively, so as to indicate that the grain 1 is the main grain. The first switch element includes a first-first switch element 181 and a first-second switch element 182. The first input end of the first delayed output control circuit 14 includes a first input end and a first second input end, which are respectively coupled to the output end of the first first switch element 181 and the output end of the first second switch element 182. The control end of the first first switch element 181 is coupled to the first output end of the first encoding circuit 13 to receive the first first switch control signal Fzout11 of the first level, and the input end of the first first switch element 181 is coupled to the third output end of the first input circuit 15 to receive the first delay signal SO1 in the test signal sent by the test machine. The control end of the first second switch element 182 is coupled to the second output end of the first encoding circuit 13 to receive the first first second switch control signal Fzout12 of the first level, and the input end of the first second switch element 182 is coupled to the fourth output end of the first input circuit 15 to receive the second delay signal SO2 in the test signal sent by the test machine. The first input end and the first second input end of the first delayed output control circuit 14 are respectively coupled to the output ends of the first first switch element 181 and the first second switch element 182. The first input circuit 15 includes a plurality of input terminals, which can be used to receive differential clock signals CK_t and CK_c and test instructions Cm, respectively. The first input circuit 15 can generate a clock pulse according to the received differential clock signals CK_t and CK_c. The first output terminal of the first input circuit 15 is coupled to the second input terminal of the first delay output control circuit 14 to input the generated clock pulse to the first delay output control circuit 14. The second output terminal of the first input circuit 15 is coupled to the input terminal of the first database 16 to read the first test data from the corresponding address of the first database 16 according to the received test instruction. The output terminal of the first database 16 is coupled to the third input terminal of the first delay output control circuit 14 to input the first test data to the first delay output control circuit 14.The first switch element 181 and the first switch element 182 are respectively controlled by the first switch control signal Fzout11 and the first switch control signal Fzout12 of the first level, and the first switch element 181 and the first switch element 182 are closed (disconnected), so that the first delay signal SO1 and the second delay signal SO2 are not transmitted to the first delay output control circuit 14. Therefore, the first delay output control circuit 14 outputs the first test data to the input end of the first output circuit 17 through the output end of the first delay output control circuit 14 without delay according to the received clock pulse and the first test data. The output end of the first output circuit 17 is coupled to the first output channel 12 of the die 1 to output the first test data.

[0058] Continue to refer Fig.11, the second switch control signal includes a second-level switch control signal Fzout21 and a second-level switch control signal Fzout22, and the output terminal of the second encoding circuit 23 includes a first output terminal and a second output terminal, so as to respectively output the second-level switch control signal Fzout21 and the second-level switch control signal Fzout22, so as to indicate that the die 2 is the first slave die. The second switch element includes a second-level switch element 281 and a second-level switch element 282. The first input terminal of the second delay output control circuit 24 includes a second-level input terminal and a second-level input terminal, so as to respectively couple the output terminal of the second-level switch element 281 and the output terminal of the second-level switch element 282. The control terminal of the second-level switch element 281 is coupled to the first output terminal of the second encoding circuit 23 to receive the second-level switch control signal Fzout21, and the input terminal of the second-level switch element 281 is coupled to the third output terminal of the second input circuit 25 to receive the first delay signal SO1. The control end of the second second switch element 282 is coupled to the second output end of the second encoding circuit 23 to receive the second second switch control signal Fzout22 of the first level, and the input end of the second second switch element 282 is coupled to the fourth output end of the second input circuit 25 to receive the second delay signal SO2. The second first input end and the second second input end of the second delay output control circuit 24 are respectively coupled to the output ends of the second first switch element 281 and the second second switch element 282. The second input circuit 25 includes a plurality of input ends, which can be used to receive the differential clock signals CK_t and CK_c and the test instruction Cm respectively. The second input circuit 25 can generate a clock pulse according to the received differential clock signals CK_t and CK_c. The first output end of the second input circuit 25 is coupled to the second input end of the second delay output control circuit 24 to input the generated clock pulse to the second delay output control circuit 24. The second output end of the second input circuit 25 is coupled to the input end of the second database 26 to read the second test data from the corresponding address of the second database 26 according to the received test instruction. The output terminal of the second database 26 is coupled to the third input terminal of the second delay output control circuit 24 to input the second test data to the second delay output control circuit 24. The second-first switch element 281 is turned on (closed) under the control of the second-first switch control signal Fzout21 of the second level, so that the first delay signal SO1 is transmitted to the second delay output control circuit 24. The second-second switch element 282 is turned off (disconnected) under the control of the second-second switch control signal Fzout22, so that the second delay signal SO2 is not transmitted to the second delay output control circuit 24.Therefore, the second delay output control circuit 24 delays the second test data by the first predetermined clock cycle according to the received clock pulse, the second test data and the first delay signal SO1, and outputs the second test data to the input end of the second output circuit 27 through the output end of the second delay output control circuit 24. The output end of the second output circuit 27 is coupled to the second output channel 22 of the die 2 to output the second test data.

[0059] Continue to refer Fig.11, the third switch control signal includes a third-first switch control signal Fzout31 of a first level and a third-second switch control signal Fzout32 of a second level, and the output end of the third encoding circuit 33 includes a first output end and a second output end, so as to respectively output the third-first switch control signal Fzout31 of a first level and the third-second switch control signal Fzout32 of a second level, so as to indicate that the die 3 is the second slave die. The third switch element includes a third-first switch element 381 and a third-second switch element 382. The first input end of the third delayed output control circuit 34 includes a third-first input end and a third-second input end, so as to respectively couple the output end of the third-first switch element 381 and the output end of the third-second switch element 382. The control end of the third-first switch element 381 is coupled to the first output end of the third encoding circuit 33 to receive the third-first switch control signal Fzout31 of a first level, and the input end of the third-first switch element 381 is coupled to the third output end of the third input circuit 35 to receive the first delayed signal SO1. The control end of the third second switch element 382 is coupled to the second output end of the third encoding circuit 33 to receive the third second switch control signal Fzout32 of the second level, and the input end of the third second switch element 382 is coupled to the fourth output end of the third input circuit 35 to receive the second delay signal SO2. The third first input end and the third second input end of the third delay output control circuit 34 are respectively coupled to the output ends of the third first switch element 381 and the third second switch element 382. The third input circuit 35 includes a plurality of input ends, which can be used to receive the differential clock signals CK_t and CK_c and the test instruction Cm respectively. The third input circuit 35 can generate a clock pulse according to the received differential clock signals CK_t and CK_c. The first output end of the third input circuit 35 is coupled to the second input end of the third delay output control circuit 34 to input the generated clock pulse to the third delay output control circuit 34. The second output end of the third input circuit 35 is coupled to the input end of the third database 36 to read the third test data from the corresponding address of the third database 36 according to the received test instruction. The output end of the third database 36 is coupled to the third input end of the third delay output control circuit 34 to input the third test data to the third delay output control circuit 34. The third-first switch element 381 is controlled by the third-first switch control signal Fzout31 of the first level, and the third-first switch element 381 is turned off (disconnected), so that the first delay signal SO1 is not transmitted to the third delay output control circuit 34. The third-second switch element 382 is controlled by the third-second switch control signal Fzout32, and the third-second switch element 382 is turned on (closed), so that the second delay signal SO2 is transmitted to the third delay output control circuit 34.Therefore, according to the received clock pulse, the third test data and the second delay signal SO2, the third delay output control circuit 34 delays the third test data by the second predetermined clock cycle and outputs the third test data to the input end of the third output circuit 37 through the output end of the third delay output control circuit 34. The output end of the third output circuit 37 is coupled to the third output channel 32 of the die 3 to output the third test data.

[0060] like Fig.12 As shown, it is assumed that four dies are packaged simultaneously in the same semiconductor package product 1200. The output channels of the four dies can be coupled together to share the output channel, so as to output the first test data of die 1, the second test data of die 2, the third test data of die 3 and the fourth test data of die 4 in series to a measurement input channel of the test machine.

[0061] Fig.13 FIG. 1 is a flow chart of a method for testing a finished semiconductor package according to an exemplary embodiment of the present disclosure. Fig.13 In an embodiment, a semiconductor package product packages a first die and a second die, the first die is a master die, the second die is a slave die, and a first output channel of the first die and a second output channel of the second die are coupled to form a shared output channel. Fig.13 As shown, the method provided by the embodiment of the present disclosure may include the following steps.

[0062] In S1310 , the master die and the slave die simultaneously receive the same test signal from the same measurement output channel of the test machine, where the test signal includes a delay signal.

[0063] In S1320 , first test data is read from the main die according to the test signal and output to a measurement input channel of the test machine through a shared output channel.

[0064] In S1330 , second test data is read from the die according to the test signal, and after the second test data is delayed by a predetermined clock cycle according to the delay signal, it is output to the measurement input channel through the shared output channel.

[0065] Fig.14 FIG. 1 is a flow chart of a method for testing a finished semiconductor package according to another exemplary embodiment of the present disclosure. Fig.14 In an embodiment, a semiconductor package product packages a first die and a second die, the first die is a master die, the second die is a slave die, and a first output channel of the first die and a second output channel of the second die are coupled to form a shared output channel. Fig.14 As shown, the method provided by the embodiment of the present disclosure may include the following steps.

[0066] In S1410 , the same measurement output channel of the test machine simultaneously inputs the same test signal to the first die and the second die, where the test signal includes a delay signal.

[0067] In S1420, the same measurement input channel of the test machine receives first test data and second test data output in series from a shared output channel, wherein the first test data is read from the master die based on a test signal, and the second test data is read from the slave die based on the test signal and a delay signal therein.

[0068] The present disclosure is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A semiconductor package product, characterized in that: include: A first die, comprising a first input circuit, a first output channel and a first encoding circuit; A second die, comprising a second input circuit, a second output channel, and a second encoding circuit; Among them, the first input circuit and the second input circuit are used to receive the same test signal from the same measurement output channel of the test machine, the first output channel and the second output channel are coupled as the same shared output channel, the first encoding circuit is used to encode the first grain as a master grain, and the second encoding circuit is used to encode the second grain as a slave grain, and the shared output channel is used to serially output the first test data read from the master grain and the second test data read from the slave grain according to the test signal, so as to input the serially output first test data and the second test data into the same measurement input channel of the test machine.

2. The semiconductor package product according to claim 1, wherein: The output terminal of the first encoding circuit is used to output a first switch control signal of a first level to indicate that the first die is a main die; the test signal includes a delay signal; The first die further includes: a first delayed output control circuit and a first switch element; The first switch element is used for not transmitting the delay signal to the first delay output control circuit according to the first switch control signal of the first level, so that the shared output channel outputs the first test data to the test machine first.

3. The semiconductor package product according to claim 2, wherein: The first encoding circuit is a target one-time programming memory cell in the first die.

4. The semiconductor package product according to claim 3, characterized in that: The target one-time programming memory cell in the first die is not programmed, so that the output end of the first encoding circuit outputs the first switch control signal of the first level.

5. The semiconductor package product according to claim 1, wherein: The output terminal of the second encoding circuit is used to output a second switch control signal of a second level to indicate that the second die is a slave die; the test signal includes a delay signal; The second die further includes: a second delayed output control circuit and a second switch element; The second switch element is used to transmit the delay signal to the second delay output control circuit according to the second switch control signal of the second level, so that the shared output channel delays the second test data by a predetermined clock cycle according to the delay signal and outputs it to the test machine.

6. The semiconductor package product according to claim 5, wherein: The second encoding circuit is a target one-time programming memory cell in the second die.

7. The semiconductor package product according to claim 6, wherein: The target one-time programming memory cell in the second die has been programmed, so that the output terminal of the second encoding circuit outputs the second switch control signal of the second level.

8. The semiconductor package product according to claim 7, wherein: Before or after packaging the second die into the finished semiconductor package, the target one-time programming memory cell in the second die is burned.

9. A method for testing a finished semiconductor package, characterized in that: The semiconductor package product encapsulates a first die and a second die, the first die is a master die, the second die is a slave die, and a first output channel of the first die and a second output channel of the second die are coupled to form a same shared output channel; wherein the method comprises: The master die and the slave die simultaneously receive the same test signal from the same measurement output channel of the test machine, wherein the test signal includes a delay signal; Reading first test data from the master die according to the test signal and outputting the first test data to the measurement input channel of the test machine through the shared output channel; The second test data is read from the slave die according to the test signal, and after the second test data is delayed for a predetermined clock cycle according to the delay signal, it is output to the measurement input channel through the shared output channel.

10. A method for testing a finished semiconductor package, characterized in that: The semiconductor package product encapsulates a first die and a second die, the first die is a master die, the second die is a slave die, and a first output channel of the first die and a second output channel of the second die are coupled to form a same shared output channel; wherein the method comprises: The same measurement output channel of the test machine simultaneously inputs the same test signal to the first die and the second die, wherein the test signal includes a delay signal; The same measurement input channel of the test machine receives first test data and second test data output serially from the shared output channel, wherein the first test data is read from the master die based on the test signal, and the second test data is read from the slave die based on the test signal and a delayed signal therein.

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