Silicon-based NMOS (N-channel metal oxide semiconductor) internal defect detection method, system and device and medium

Abstract

The invention discloses a silicon-based NMOS internal defect detection method, system and device and a medium, and the method comprises the steps: enabling a source electrode and a drain electrode to be in short circuit, respectively applying a high level and a low level to a grid electrode and a Bulk end, applying a reverse voltage to the grid electrode at a single temperature point, and recording a capacitance transient signal in a deep energy level trap filling and emission process in a space charge region; a digital system is used for recording N transient measurement values of the capacitor at different temperature points; Fourier calculation is used for converting the N transient measurement values into a relational graph of discrete Fourier coefficients and temperature, so that information such as trap level, defect concentration and capture cross section of the deep level trap can be accurately obtained. According to the method, a capacitance transient spectrogram obtained by voltage pulse excitation under a variable-temperature condition is converted into a relational graph of a discrete Fourier coefficient and temperature by Fourier calculation, so that the defect level of a deep level trap is accurately obtained. And the transient test time can be further shortened for the discrete trap level, so that the result is accurately controlled.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic device detection, and relates to a method, system, device and medium for detecting internal defects of a silicon-based NMOS. Background Art

[0002] MOS devices are one of the basic building blocks of integrated circuits, with characteristics such as low leakage and high power efficiency. Silicon is the main material for manufacturing integrated circuits, and silicon-based MOS device technology has developed to a level that can achieve high integration, which will help reduce the size of the overall circuit and improve the performance of integrated circuits. However, in the preparation process of silicon-based power devices, unintentional doping defects or inherent deep energy level impurities will be introduced, as well as point defects or dislocations caused by external conditions such as voltage after high-frequency use, which may form deep energy level traps inside the device. These impurities or defects will reduce the carrier lifetime inside the device, further leading to the degradation of the performance of silicon-based NMOS devices, such as reducing channel carrier mobility, increasing leakage current and changing threshold voltage. At present, there are few in-depth analyses of the types and states of defects generated after device irradiation in silicon-based NMOS devices, and there are problems such as inability to quickly detect and low detection efficiency. Summary of the invention

[0003] The purpose of the present invention is to solve the problem in the prior art that deep energy level traps inside silicon-based NMOS devices cannot be detected quickly and the detection efficiency is low, and to provide a method, system, device and medium for detecting internal defects of silicon-based NMOS.

[0004] In order to achieve the above object, the present invention adopts the following technical solutions: A method for detecting internal defects of a silicon-based NMOS, comprising: Get the capacitance value between the silicon-based NMOS device and the bulk; Based on the relationship between the capacitance value and the voltage borne by the silicon-based NMOS device, a capacitance-voltage curve is obtained to determine the selection range of the pulse cycle width; Based on the pulse cycle width and different test temperatures, the deep energy level transient Fourier test of the silicon-based NMOS device is carried out by voltage pulse excitation to obtain the transient curve of the capacitance at each temperature interval point; Based on the capacitance transient curve recorded by the digital system, an analog signal is obtained; and the analog signal is Fourier transformed to obtain a signal relationship diagram between a time constant and a discrete Fourier coefficient and temperature; Based on the time constant and the signal relationship diagram, the trap corresponding to the peak in the signal relationship diagram is obtained, and then the trap energy level of the deep energy level defect is determined.

[0005] A further improvement of the present invention is: Furthermore, the capacitance value between the silicon-based NMOS device and the bulk is obtained by short-circuiting the source and the drain of the NMOS device internally during the preparation of the NMOS device; and connecting the gate of the NMOS device to a positive voltage and the bulk to ground during the test.

[0006] Furthermore, the selection range of the pulse cycle width is determined, specifically: The voltage of the NMOS device under test is set to a range of -5V to 5V to obtain a CV curve; Determine the reverse voltage from the depletion region obtained from the CV curve and pulse voltage value ; Fixed reverse voltage and pulse voltage value The pulse filling time tp is determined by the relationship between the transient capacitance signal and the pulse filling time; Fixed reverse voltage , pulse voltage value The pulse filling time tp remains unchanged, and the pulse cycle width Tw is determined by the transient capacitance signal.

[0007] Furthermore, based on the pulse cycle width and different test temperatures, a deep level transient Fourier test of voltage pulse excitation is performed on the silicon-based NMOS device to obtain the transient curve of the capacitance at each temperature interval point, specifically: S31: Set the temperature test interval Tmin-Tmax, where the step length of adjacent temperature sampling points is fixed, that is, ; S32: When the temperature drops to Tmin, a voltage pulse-excited deep energy level transient spectrum test is performed on the silicon-based NMOS, and a capacitance transient curve at the current temperature point is recorded; the capacitance transient curve at the current temperature point includes N capacitance measurement value points with a sampling interval of ∆t, where the pulse period width is ; S33: At fixed step size The temperature is raised until Tmax, and step S32 is repeated at each temperature point to record the transient capacitance curves of the silicon-based NMOS corresponding to different temperature points.

[0008] Furthermore, based on the capacitance transient curve recorded by the digital system, an analog signal is obtained; and the analog signal is Fourier transformed to obtain a signal relationship diagram between the time constant and the discrete Fourier coefficient and the temperature. Specifically, since the transient state has time dependence, the capacitance transient curve is scanned by the analog-to-digital converter in the digital system to obtain the analog signal. , the analog signal Perform Fourier transform to get Fourier coefficients , specifically: ; in, is a scanned analog signal. i is an imaginary unit, n represents the nth-order Fourier coefficient, and the angular frequency ; and the coefficients contain real and imaginary parts, that is: ; In the analysis of deep level transient Fourier spectroscopy DLTFS, the time constant is obtained through the Fourier coefficient. The time constant is obtained from the optimal ratio of the two coefficients and is divided into the following three formulas: ; Among them, n and k represent different Fourier orders. , Represents cosine coefficients of different orders, , Represents sinusoidal coefficients of different orders.

[0009] Furthermore, based on the time constant and the signal relationship diagram, the trap corresponding to the peak in the signal relationship diagram is obtained, and then the trap energy level of the deep energy level defect is determined, specifically: By measuring the temperature peak position of DLTFS with time constant The change of can be used to obtain the Arrhenius curve of the defect. The expression of the Arrhenius curve is: ; in, is the time constant, is the thermal electron emission rate, is the entropy factor, k is the Boltzmann constant, T is the Kelvin temperature, To capture the cross-sectional area, is the trap energy level; is the effective density of states in the valence band or conduction band.

[0010] A silicon-based NMOS internal defect detection system, comprising: A first acquisition module, wherein the first acquisition module acquires a capacitance value between a silicon-based NMOS device and a Bulk; A construction module, wherein the construction module constructs a capacitance-voltage curve based on the relationship between the capacitance value and the voltage borne by the silicon-based NMOS device, thereby determining a selection range of the pulse cycle width; A transient curve acquisition module, wherein the transient curve acquisition module performs a deep energy level transient Fourier test of voltage pulse excitation on the silicon-based NMOS device based on the pulse cycle width and different test temperatures, and acquires a transient curve of the capacitance at each temperature interval point; A Fourier transform module, wherein the Fourier transform module obtains an analog signal based on a capacitance transient curve recorded by a digital system; and performs Fourier transform on the analog signal to obtain a signal relationship diagram between a time constant and a discrete Fourier coefficient and temperature; The second acquisition module obtains the trap corresponding to the peak in the signal relationship diagram based on the time constant and the signal relationship diagram, and further determines the trap energy level of the deep energy level defect.

[0011] A terminal device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0012] A computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0013] Compared with the prior art, the present invention has the following beneficial effects: The present invention short-circuits the source and drain, and applies high and low levels to the gate and bulk ends respectively. At a single temperature point, a reverse voltage is applied to the gate to record the capacitance transient signal during the filling and emission process of the deep energy level trap in the space charge region; a digital system is used to record N measured values ​​of the capacitance transient at different temperature points: Fourier calculation is used to convert it into a relationship diagram between discrete Fourier coefficients and temperature, so as to accurately obtain information such as the trap energy level, defect concentration and capture cross section of the deep energy level trap. The present invention uses a capacitance transient spectrum obtained by voltage pulse excitation under variable temperature conditions, and uses Fourier calculation to convert it into a relationship diagram between discrete Fourier coefficients and temperature, so as to accurately obtain the defect energy level of the deep energy level trap. And for the discrete trap level, the transient test time can be further reduced, so as to accurately control the results. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 It is a schematic flow chart of the method for detecting internal defects of silicon-based NMOS of the present invention; Figure 2 It is a schematic diagram of the pulse cycle width and the transient capacitance curve of silicon-based NMOS; Figure 3It is the deep energy level transient spectrum signal diagram of silicon-based NMOS under different temperatures and pulse cycle widths; Figure 4 It is a schematic diagram of the Arrhenius curve; Figure 5 It is a schematic diagram of the structure of the silicon-based NMOS internal defect detection system of the present invention. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0017] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0019] In the description of the embodiments of the present invention, it should be noted that if the terms "upper", "lower", "horizontal", "inner", etc. indicate an orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed when in use, it is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0020] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly tilted. For example, "horizontal" only means that its direction is more horizontal than "vertical", which does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0021] In the description of the embodiments of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] The present invention is further described in detail below in conjunction with the accompanying drawings: See also Figure 1 The present invention discloses a method for detecting internal defects of a silicon-based NMOS, comprising: S101: Obtain the capacitance value between the silicon-based NMOS device and the bulk; During the preparation process of the NMOS device, the source and drain of the NMOS device are short-circuited internally; and during the test, the gate of the NMOS device is connected to a positive voltage and the Bulk is grounded.

[0023] S102: obtaining a capacitance-voltage curve based on the relationship between the capacitance value and the voltage borne by the silicon-based NMOS device, and then determining a selection range of the pulse cycle width; The voltage of the NMOS device under test is set to a range of -5V to 5V to obtain a CV curve; The depletion region obtained from the CV curve determines the reverse voltage Ur and the pulse voltage value Up; The reverse voltage Ur and the pulse voltage value Up are fixed, and the pulse filling time tp is determined by the relationship between the transient capacitance signal and the pulse filling time; In the constant temperature mode, set the fixed reverse voltage Ur and pulse voltage Up, and set the pulse filling time tp to 10 -6 ~10 -1 The filling scan is performed in seconds, and when the transient capacitance signal reaches saturation, it is determined as the optimal pulse filling time.

[0024] The reverse voltage Ur, pulse voltage value Up and pulse filling time tp are kept constant, and the pulse cycle width Tw is determined by the transient capacitance signal.

[0025] In the constant temperature mode, a fixed reverse voltage Ur, pulse voltage Up and pulse filling time tp are set, and the cycle width Tw is changed. When the transient capacitance signal reaches complete relaxation, the optimal cycle width Tw is determined.

[0026] S103: Based on the pulse cycle width and different test temperatures, a deep energy level transient Fourier test of voltage pulse excitation is performed on the silicon-based NMOS device to obtain a transient curve of the capacitance at each temperature interval point; S103.1: Set the temperature test interval Tmin-Tmax, where the step size of adjacent temperature sampling points is fixed, that is, ; S103.2: When the temperature drops to Tmin, a voltage pulse-excited deep level transient spectrum test is performed on the silicon-based NMOS, and the capacitance transient curve at the current temperature point is recorded; Figure 2 The capacitance transient curve at the current temperature point includes N capacitance measurement value points with a sampling interval of ∆t, where the pulse period width is ; S103.3: At fixed step length The temperature is raised until Tmax, and step S103.2 is repeated at each temperature point to record the transient capacitance curves of the silicon-based NMOS corresponding to different temperature points. Figure 3 As shown. Figure 3 In the figure, the positive peak represents the multi-carrier trap and H1 represents a hole trap peak.

[0027] Each point in the DLTS signal and temperature relationship diagram corresponds to the transient capacitance curve at different temperatures. By performing Fourier transform on the capacitance transient signal at different temperatures, the signal diagram of the deep energy level transient spectrum can be obtained.

[0028] S104: acquiring an analog signal based on the capacitance transient curve recorded by the digital system; and performing Fourier transform on the analog signal to obtain a signal relationship diagram between a time constant and a discrete Fourier coefficient and temperature; Since the transient state is time-dependent, the capacitance transient curve is scanned by the analog-to-digital converter in the digital system to obtain the analog signal. , the analog signal Perform Fourier transform to get Fourier coefficients , specifically: ; in, is a scanned analog signal. i is an imaginary unit, n represents the nth-order Fourier coefficient, and the angular frequency ; and the coefficients contain real and imaginary parts, that is: ; In the analysis of deep level transient Fourier spectroscopy DLTFS, the time constant is obtained through the Fourier coefficient. The time constant is obtained from the optimal ratio of the two coefficients and is divided into the following three formulas: ; Among them, n and k represent different Fourier orders. Represents cosine coefficients of different orders, Represents sinusoidal coefficients of different orders.

[0029] The relationship between the Fourier coefficient and temperature at different temperature points is obtained from the analog signal f(t), that is, the deep energy level transient spectrum signal diagram, where each coefficient corresponds to a time constant.

[0030] S105: Based on the time constant and the signal relationship diagram, a trap corresponding to a peak in the signal relationship diagram is obtained, and then the trap energy level of the deep energy level defect is determined.

[0031] like Figure 4 As shown, by measuring the temperature peak position of DLTFS with the time constant The Arrhenius diagram of the defect is obtained by measuring the change of , the expression of the Arrhenius curve is: ; in, is the time constant, is the thermal electron emission rate, is the entropy factor, k is the Boltzmann constant, T is the Kelvin temperature, To capture the cross-sectional area, is the trap energy level; is the effective density of states in the valence band or conduction band.

[0032] Through the Arrhenius curve, the trap energy level is obtained Among them, the time constant, thermal electron emission rate, entropy factor, Boltzmann constant, Kelvin temperature, capture cross-sectional area and effective state density in the conduction band are all known through experimental measurements of NMOS tubes.

[0033] See also Figure 5 The present invention discloses a silicon-based NMOS internal defect detection system, comprising: A first acquisition module, wherein the first acquisition module acquires a capacitance value between a silicon-based NMOS device and a Bulk; A construction module, wherein the construction module constructs a capacitance-voltage curve based on the relationship between the capacitance value and the voltage borne by the silicon-based NMOS device, thereby determining a selection range of the pulse cycle width; A transient curve acquisition module, wherein the transient curve acquisition module performs a deep energy level transient Fourier test of voltage pulse excitation on the silicon-based NMOS device based on the pulse cycle width and different test temperatures, and acquires a transient curve of the capacitance at each temperature interval point; A Fourier transform module, wherein the Fourier transform module obtains an analog signal based on a capacitance transient curve recorded by a digital system; and performs Fourier transform on the analog signal to obtain a signal relationship diagram of discrete Fourier coefficients and temperature; The second acquisition module acquires the trap corresponding to the peak value in the signal relationship diagram based on the discrete Fourier coefficient, and further determines the trap energy level of the deep energy level defect.

[0034] The present invention short-circuits the source and drain, and applies high and low levels to the gate and bulk ends respectively. At a single temperature point, a reverse voltage is first applied to the gate, at which time the space charge region reaches a maximum and the total capacitance is minimum; after a pulse filling voltage is applied to the gate, the space charge region reaches the narrowest state and the total capacitance is maximum. Record the capacitance transient signal during the filling and emission process of the deep energy level trap in the space charge region; use a digital system to record N measured values ​​of the capacitance transient at different temperature points: use Fourier calculation to convert it into a relationship diagram between discrete Fourier coefficients and temperature, so as to accurately obtain information such as the trap energy level, defect concentration and capture cross section of the deep energy level trap. The present invention uses a capacitance transient spectrum obtained by voltage pulse excitation under variable temperature conditions, and uses Fourier calculation to convert it into a relationship diagram between discrete Fourier coefficients and temperature, so as to accurately obtain the defect energy level of the deep energy level trap. And for the discrete trap level, the transient test time can be further reduced, so as to accurately control the results.

[0035] A terminal device is provided in one embodiment of the present invention. The terminal device of this embodiment includes: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps in the above-mentioned method embodiments are implemented. Alternatively, when the processor executes the computer program, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0036] The computer program may be divided into one or more modules / units, and the one or more modules / units are stored in the memory and executed by the processor to accomplish the present invention.

[0037] The terminal device may be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0038] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0039] The memory may be used to store the computer programs and / or modules, and the processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and calling the data stored in the memory.

[0040] If the module / unit integrated in the terminal device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0041] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for detecting internal defects of a silicon-based NMOS, characterized in that: include: Get the capacitance value between the silicon-based NMOS device and the bulk; Based on the relationship between the capacitance value and the voltage borne by the silicon-based NMOS device, a capacitance-voltage curve is obtained to determine the selection range of the pulse cycle width; Based on the pulse cycle width and different test temperatures, the deep energy level transient Fourier test of the silicon-based NMOS device is carried out by voltage pulse excitation to obtain the transient curve of the capacitance at each temperature interval point; Based on the capacitance transient curve recorded by the digital system, an analog signal is obtained; and the analog signal is Fourier transformed to obtain a signal relationship diagram between a time constant and a discrete Fourier coefficient and temperature; Based on the time constant and the signal relationship diagram, the trap corresponding to the peak in the signal relationship diagram is obtained, and then the trap energy level of the deep energy level defect is determined.

2. The method for detecting internal defects of silicon-based NMOS according to claim 1, characterized in that: The method of obtaining the capacitance value between the silicon-based NMOS device and the bulk is specifically as follows: during the preparation process of the NMOS device, the source and the drain of the NMOS device are short-circuited internally; and during the test, the gate of the NMOS device is connected to a positive voltage and the bulk is grounded.

3. The method for detecting internal defects of silicon-based NMOS according to claim 2, characterized in that: The selection range of determining the pulse cycle width is specifically: The voltage of the NMOS device under test is set to a range of -5V to 5V to obtain a CV curve; The depletion region obtained from the CV curve determines the reverse voltage Ur and the pulse voltage value Up; The reverse voltage Ur and the pulse voltage value Up are fixed, and the pulse filling time tp is determined by the relationship between the transient capacitance signal and the pulse filling time; The reverse voltage Ur, pulse voltage value Up and pulse filling time tp are kept constant, and the pulse cycle width Tw is determined by the transient capacitance signal.

4. The method for detecting internal defects of silicon-based NMOS according to claim 3, characterized in that: Based on the pulse cycle width and different test temperatures, the deep energy level transient Fourier test of the silicon-based NMOS device is performed by voltage pulse excitation to obtain the transient curve of the capacitance at each temperature interval point, specifically: S31: Set the temperature test interval Tmin-Tmax, where the step length of adjacent temperature sampling points is fixed, that is, ; S32: When the temperature drops to Tmin, a deep energy level transient spectrum test of a voltage pulse excitation is performed on the silicon-based NMOS, and a capacitance transient curve at the current temperature point is recorded; the capacitance transient curve at the current temperature point includes N sampling intervals of Capacitance measurement point, where the pulse cycle width ; S33: At fixed step size The temperature is raised until Tmax, and step S32 is repeated at each temperature point to record the transient capacitance curves of the silicon-based NMOS corresponding to different temperature points.

5. The method for detecting internal defects of silicon-based NMOS according to claim 4, characterized in that: The method is to obtain an analog signal based on the capacitance transient curve recorded by the digital system; and to perform Fourier transform on the analog signal to obtain a signal relationship diagram between the time constant and the discrete Fourier coefficient and the temperature. Specifically, since the transient state has time dependence, the capacitance transient curve is scanned by an analog-to-digital converter in the digital system to obtain an analog signal. , the analog signal Perform Fourier transform to get Fourier coefficients , specifically: ； in, is a scanned analog signal, i is an imaginary unit, n represents the nth-order Fourier coefficient, and the angular frequency ; and the coefficients contain real and imaginary parts, that is: ； In the analysis of deep level transient Fourier spectroscopy DLTFS, the time constant is obtained through the Fourier coefficient. The time constant is obtained from the optimal ratio of the two coefficients and is divided into the following three formulas: ； Among them, n and k represent different Fourier orders. , Represents cosine coefficients of different orders, , Represents sinusoidal coefficients of different orders.

6. The method for detecting internal defects of silicon-based NMOS according to claim 5, characterized in that: Based on the time constant and the signal relationship diagram, the trap corresponding to the peak in the signal relationship diagram is obtained, and then the trap energy level of the deep energy level defect is determined, specifically: By measuring the temperature peak position of DLTFS with time constant The change of is used to obtain the Arrhenius curve of the defect. The expression of the Arrhenius curve is: ； in, is the time constant, is the thermal electron emission rate, is the entropy factor, k is the Boltzmann constant, T is the Kelvin temperature, To capture the cross-sectional area, is the trap energy level; is the effective density of states in the valence band or conduction band.

7. A silicon-based NMOS internal defect detection system, characterized in that: include: A first acquisition module, wherein the first acquisition module acquires a capacitance value between a silicon-based NMOS device and a Bulk; A construction module, wherein the construction module constructs a capacitance-voltage curve based on the relationship between the capacitance value and the voltage borne by the silicon-based NMOS device, thereby determining a selection range of the pulse cycle width; A transient curve acquisition module, wherein the transient curve acquisition module performs a deep energy level transient Fourier test of voltage pulse excitation on the silicon-based NMOS device based on the pulse cycle width and different test temperatures, and acquires a transient curve of the capacitance at each temperature interval point; A Fourier transform module, wherein the Fourier transform module obtains an analog signal based on a capacitance transient curve recorded by a digital system; and performs Fourier transform on the analog signal to obtain a signal relationship diagram between a time constant and a discrete Fourier coefficient and temperature; The second acquisition module obtains the trap corresponding to the peak in the signal relationship diagram based on the time constant and the signal relationship diagram, and further determines the trap energy level of the deep energy level defect.

8. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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