Chip test circuit structure based on group of serial input and output interfaces

Abstract

The invention relates to the technical field of chip testing, in particular to a chip testing circuit structure based on a group of serial input and output interfaces, which comprises a serial input interface, M input triggers, a decompression module, N scan chains, a compression module, M output triggers and a serial output interface, an input pin of the A1 is connected with a serial input interface; the input trigger is connected with an input pin of the decompression module; the input end of each scanning chain is connected with the output pin of the decompression module; the output end of each scanning chain is connected with the input pin of the compression module; the input pin of the BM is connected with the serial output interface, and the output triggers are connected with the output pin of the compression module. According to the invention, the test of the compression mode can be realized based on a group of serial data input interface and serial data output interface, the test coverage rate is improved, the chip test clock frequency is improved, the chip test time is shortened, and the chip test cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and in particular to a chip testing circuit structure based on a group of serial input and output interfaces. Background Art

[0002] Chip Probing Test is mainly used to perform preliminary functional and performance tests on chips at the wafer level. At this stage, the chip can usually be tested in compression mode in the automatic test equipment (ATE) based on multiple parallel input pins. The compression mode uses data compression technology to reduce test time and test costs. However, in some scenarios, there may be only one set of serial data input (Serial Data In, SDI) interface and serial data output (Serial Data Out, SDO) interface. For example, in the chip finished product test (Final Inspection Test) stage, many pins are not packaged and cannot be detected, resulting in the possibility that only one set of serial data input interface and serial data output interface remain. In the prior art, all triggers can be constructed into a test chain for testing based on a set of serial data input interface and serial data output interface. However, there are at least the following technical problems: low chip test coverage, limited chip test clock frequency, long chip test time, and high chip test cost. Summary of the invention

[0003] The purpose of the present invention is to provide a chip test circuit structure based on a group of serial input and output interfaces, which can realize compression mode testing based on a group of serial data input interfaces and serial data output interfaces, improve test coverage, increase chip test clock frequency, reduce chip test time, and reduce chip test costs.

[0004] According to a first aspect of the present invention, a chip test circuit structure based on a group of serial input and output interfaces is provided, comprising a serial input interface, M input triggers {A1, A2, ..., A m ,...,A M}, decompression module, N scan chains, compression module and M output flip-flops {B1, B2, ..., B m ,...,B M}、Serial output interface, N≥M; Among them, A m is the mth input trigger, the value range of m is 1 to M, M is the total number of input triggers, B mis the mth output flip-flop, A1, A2, ..., A m , ..., A M Connect in series, B1, B2, ..., B m ,...,B M Connect in series in sequence; The input pin of A1 is connected to the serial input interface, and the serial input interface is used to serially transmit data to A1, A2, ..., A m , ..., A M Enter data in; A1、A2、...,A m , ..., A M are connected to the input pins of the decompression module, A1, A2, ..., A m , ..., A M Used to input data to the decompression module in parallel; The input end of each scan chain is connected to the output pin of the decompression module, and the decompression module is used to convert A1, A2, ..., A m , ..., A M The input data is decompressed into N output data and output to each scan chain respectively; The output end of each scan chain is connected to the input pin of the compression module, and is used to compress the data output from all scan chains into M output data; B M The input pins of are connected to the serial output interface, B1, B2, ..., B m , ..., B M They are all connected to the output pins of the compression module, and are used to parallely obtain the M output data compressed by the compression module, and serially output the obtained M output data to the serial output interface.

[0005] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the chip test circuit structure based on a set of serial input and output interfaces provided by the present invention can achieve considerable technical advancement and practicality, and has wide industrial utilization value, and has at least the following beneficial effects: The circuit structure of the present invention first converts the data input from the serial input interface into parallel input data through M input triggers, and then implements the compression mode test through the decompression module. After passing through N scan chains, the data of the N scan chains are converted into M output data through the compression module, and then the M output data are serially output through the M input triggers, thereby implementing the compression mode test based on a group of serial data input interfaces and serial data output interfaces, improving the test coverage, increasing the chip test clock frequency, reducing the chip test time, and reducing the chip test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0007] Figure 1 A schematic diagram of a chip test circuit structure based on a set of serial input and output interfaces provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of a chip test circuit based on a group of serial input and output interfaces is provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0008] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0009] The embodiment of the present invention provides a chip test circuit structure based on a group of serial input and output interfaces, such as Figure 1 As shown, it includes a serial input interface (SDI), M input triggers {A1, A2, ..., A m ,...,A M}, decompression module, N scan chains, compression module and M output flip-flops {B1, B2, ..., B m ,...,B M}、Serial output interface (SDO), N≥M.

[0010] Among them, A m is the mth input trigger, the value range of m is 1 to M, M is the total number of input triggers, B mis the mth output flip-flop, and the total number of output flip-flops is also M. A1, A2, ..., A m , ..., A M Connect in series, B1, B2, ..., B m ,...,B M Connect in series one by one.

[0011] The input pin of A1 is connected to the serial input interface, and the serial input interface is used to serially transmit data to A1, A2, ..., A m , ..., A M Enter data in A1, A2, ..., A m , ..., A M are connected to the input pins of the decompression module, A1, A2, ..., A m , ..., A M It is used to input data to the decompression module in parallel. By setting M input triggers {A1, A2, ..., A m ,...,A M}It can convert the data input from one serial input interface into M parallel input data.

[0012] The input end of each scan chain is connected to the output pin of the decompression module, and the decompression module is used to convert A1, A2, ..., A m , ..., A M The input data is decompressed into N output data, which are output to each scan chain respectively. The output end of each scan chain is connected to the input pin of the compression module, which is used to compress the data output from all scan chains into M output data. It should be noted that each scan chain is composed of triggers in the chip connected in series. In order to improve the overall processing efficiency, it is preferred that all triggers in the chip are arranged in N scan chains as evenly as possible.

[0013] B M The input pins of are connected to the serial output interface, B1, B2, ..., B m , ..., B M are connected to the output pins of the compression module, and are used to obtain M output data compressed by the compression module in parallel, and output the obtained M output data in series to the serial output interface, by setting M output triggers {B1, B2, ..., B m ,...,B M}Then convert the M-channel output data compressed by the compression module into serial output data and output it to the serial output interface.

[0014] The chip test circuit according to the embodiment of the present invention realizes compression test based on a group of serial input and output interfaces, improves test coverage, increases chip test clock frequency, reduces chip test time, and reduces chip test cost.

[0015] like Figure 1 In the example shown, each A m and each B m are connected to the first clock, each A m and each B m All work at the first time. Each trigger in the N scan chains is connected to the second clock, and each scan chain works at the second clock. It should be noted that if the first clock is equal to the second clock, then when a target sequence needs to be obtained, it usually takes multiple cycles to obtain it, and the target sequence will be mixed with a lot of inefficient and invalid redundant codes, and these redundant codes are difficult to compress through test vector compression technology, resulting in longer test time and higher test cost. In order to solve such problems, the present invention sets the first clock frequency = M × second clock frequency. By setting the first clock frequency to M times the second clock frequency, the construction cycle of the target sequence can be shortened, the invalid redundant codes in the target sequence can be reduced, the chip test time can be shortened, and the chip test cost can be reduced. M = first clock frequency / second clock frequency, the first clock frequency is set to be less than or equal to the maximum clock frequency that the serial input interface can support, and the second clock frequency can be set according to specific test requirements. Therefore, it is necessary to comprehensively consider the maximum clock frequency that the serial input interface can support and the expected value of the second clock frequency to specifically set the value of M, and M can be specifically set to an integer power of 2.

[0016] As an embodiment, the decompression module is composed of logic gates arranged in multiple levels, including M input pins and N output pins, and each input pin of the decompression module is connected to an A m Each output pin of the decompression module is connected to an input end of a scan chain. Specifically, the logic gate may be an XOR gate, and the specific combination of the logic gates is set according to the specific decompression requirements. The decompression module can further convert M-way parallel data into N-way parallel data.

[0017] As an embodiment, the compression module is composed of logic gates arranged in multiple levels, including N input pins and M output pins, each input pin of the compression module is connected to the output end of a scan chain, and each output pin of the compression module is connected to a B m The logic gate may specifically use an XOR gate, and the specific combination of the logic gates is set according to specific compression requirements.

[0018] In order to enable the circuit structure to be used for testing at different stages, such as Figure 2 As shown, the circuit structure also includes M input selectors {C1, C2, ..., C m ,...,C M} and select control circuit, C m is the mth input selector, the value range of m is 1 to M, C m Including the first selection pin, the second selection pin, the enable pin and the output pin, C m The first selection pin is connected to a m The second selection pin is used to connect the mth parallel input interface P m , C m The enable pin is connected to the selection control circuit.

[0019] As an example, during the chip wafer level testing phase, there are usually multiple P m When there are R parallel interfaces that can be detected in the chip to be tested, the selection control circuit controls all C m The second selection pin is selected by M parallel input interfaces P m Input data to the decompression module, and obtain output data from the decompression module through RM parallel output interfaces, R≥M+2, and the RM parallel output interfaces are specifically Q1, Q2, ..., Q i ,...,Q R-M , Q i is the i-th parallel output interface, the value range of i is 1 to Q i .

[0020] As an embodiment, during the finished product testing stage of the chip, many pins are not packaged and cannot be detected, which may result in only one set of serial data input interface and serial data output interface remaining and unable to implement compression testing. Or there are relatively few remaining input interfaces and output interfaces, and the coverage rate of directly performing compression testing is not high. In such cases, the chip test circuit structure based on the present invention can greatly improve the test coverage rate. When there are no R parallel interfaces that can be detected in the chip to be tested, the selection control circuit controls all C m The first selection pin is selected by A1, A2, ..., A m ,...,A M Input data to the decompression module. By setting M input selectors {C1, C2, ..., C m ,...,C M} and selection control circuit, so that the circuit structure can be suitable for chip testing at different stages.

[0021] As an embodiment, the selection control circuit includes an OR gate and an inverter, wherein the first input pin of the OR gate is connected to the output pin of the inverter, the second input pin of the OR gate is connected to the parallel input enable signal, the first input pin of the inverter is connected to the first clock enable signal, and the output of the OR gate is connected to each A m When the output of the OR gate is 1, all C m The second selection pin is selected, and the OR gate output is 0 when all C m The first select pin is selected.

[0022] Each A m and each B m Each of the N scan chains is connected to the first clock, and each trigger in the N scan chains is connected to the second clock. When there are R detectable parallel interfaces in the chip under test, the parallel input enable signal is set to 1, and the first clock enable signal is set to 0. When the first clock enable signal is set to 0, the first clock is set equal to the second clock.

[0023] When there are no R detectable parallel interfaces in the chip under test, the parallel input enable signal is set to 0, the first clock enable signal is set to 1, and when the first clock enable signal is set to 1, the first clock frequency is set to M×the second clock frequency.

[0024] As an embodiment, the circuit structure further includes a clock setting circuit, which includes a clock input interface, a 1 / M frequency divider and a clock selector. The input of the clock setting circuit is a first clock, and the output is a second clock. The clock input interface is respectively connected to the input pin of the 1 / M frequency divider and the first input pin of the clock selector, the output pin of the 1 / M frequency divider is connected to the second input pin of the clock selector, and the output of the clock selector is connected to each A m and each B m The clock selector is connected to the clock selection enable signal. When the clock selection enable signal is 1, the second input pin is enabled. When the clock selection enable signal is 0, the first input pin is enabled. When there are R parallel interfaces that can be detected in the chip to be tested, the clock selection enable signal is set to 0, the first input pin is enabled, and the clock frequencies of the second clock output by the clock setting circuit are equal to the first clock. When there are no R parallel interfaces that can be detected in the chip to be tested, the clock selection enable signal is set to 1, the second input pin is enabled, and the sum of the clock frequencies of the second clock output by the clock setting circuit is 1 / M of the clock frequency of the first clock.

[0025] The chip test circuit structure described in the embodiment of the present invention first converts the data input by the serial input interface into parallel input data through M input triggers, and then implements the compression mode test through the decompression module. After passing through N scan chains, the data of the N scan chains are converted into M output data through the compression module, and then the M output data are serially output through M input triggers, thereby implementing the compression mode test based on a group of serial data input interfaces and serial data output interfaces, improving the test coverage, increasing the chip test clock frequency, reducing the chip test time, and reducing the chip test cost.

[0026] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A chip test circuit structure based on a set of serial input and output interfaces, characterized in that: It includes a serial input interface, M input triggers {A1, A2, ..., A m ,...,A M }, decompression module, N scan chains, compression module and M output flip-flops {B1, B2, ..., B m ,...,B M }、Serial output interface, N≥M; Among them, A m is the mth input trigger, the value range of m is 1 to M, M is the total number of input triggers, B m is the mth output flip-flop, A1, A2, ..., A m , ..., A M Connect in series, B1, B2, ..., B m ,...,B M Connect in series in sequence; The input pin of A1 is connected to the serial input interface, and the serial input interface is used to serially transmit data to A1, A2, ..., A m , ..., A M Enter data in; A1、A2、...,A m , ..., A M are connected to the input pins of the decompression module, A1, A2, ..., A m , ..., A M Used to input data to the decompression module in parallel; The input end of each scan chain is connected to the output pin of the decompression module, and the decompression module is used to convert A1, A2, ..., A m , ..., A M The input data is decompressed into N output data and output to each scan chain respectively; The output end of each scan chain is connected to the input pin of the compression module, and is used to compress the data output from all scan chains into M output data; B M The input pins of are connected to the serial output interface, B1, B2, ..., B m , ..., B M They are all connected to the output pins of the compression module, and are used to parallely obtain the M output data compressed by the compression module, and serially output the obtained M output data to the serial output interface.

2. The chip test circuit structure according to claim 1, characterized in that: Each A m and each B m They are all connected to the first clock, each trigger in the N scan chains is connected to the second clock, and the first clock frequency = M × the second clock frequency.

3. The chip test circuit structure according to claim 1, characterized in that: The decompression module is composed of multiple levels of logic gates, including M input pins and N output pins. Each input pin of the decompression module is connected to an A m Each output pin of the decompression module is connected to an input end of a scan chain.

4. The chip test circuit structure according to claim 1, characterized in that: The compression module is composed of multiple levels of logic gates, including N input pins and M output pins. Each input pin of the compression module is connected to the output end of a scan chain, and each output pin of the compression module is connected to a B m connected.

5. The chip test circuit structure according to claim 1, characterized in that: The circuit structure also includes M input selectors {C1, C2, ..., C m ,...,C M } and select control circuit, C m is the mth input selector, the value range of m is 1 to M, C m Including the first selection pin, the second selection pin, the enable pin and the output pin, C m The first selection pin is connected to a m The second selection pin is used to connect the mth parallel input interface P m , C m The enable pin is connected to the selection control circuit.

6. The chip test circuit structure according to claim 5, characterized in that: When there are R parallel interfaces that can be detected in the chip to be tested, the selection control circuit controls all C m The second selection pin is selected by M parallel input interfaces P m Input data to the decompression module, and obtain output data from the decompression module through RM parallel output interfaces, R≥M+2; When there are no R parallel interfaces that can be detected in the chip to be tested, the selection control circuit controls all C m The first selection pin is selected by A1, A2, ..., A m ,...,A M Data is input to the decompression module.

7. The chip test circuit structure according to claim 6, characterized in that: The selection control circuit includes an OR gate and an inverter, wherein the first input pin of the OR gate is connected to the output pin of the inverter, the second input pin of the OR gate is connected to the parallel input enable signal, the input pin of the inverter is connected to the first clock enable signal, and the output of the OR gate is connected to each A m When the output of the OR gate is 1, all C m The second selection pin is selected, and the OR gate output is 0 when all C m The first selection pin is selected; Each A m and each B m are connected to the first clock, and each trigger in the N scan chains is connected to the second clock; When there are R detectable parallel interfaces in the chip to be tested, the parallel input enable signal is set to 1, the first clock enable signal is set to 0, and when the first clock enable signal is set to 0, the first clock is set to be equal to the second clock; When there are no R detectable parallel interfaces in the chip under test, the parallel input enable signal is set to 0, the first clock enable signal is set to 1, and when the first clock enable signal is set to 1, the first clock frequency is set to M×the second clock frequency.

8. The chip test circuit structure according to claim 7, characterized in that: The circuit structure also includes a clock setting circuit, which includes a clock input interface, a 1 / M frequency divider and a clock selector. The input of the clock setting circuit is a first clock, and the output is a second clock. The clock input interface is respectively connected to the input pin of the 1 / M frequency divider and the first input pin of the clock selector, the output pin of the 1 / M frequency divider is connected to the second input pin of the clock selector, and the output of the clock selector is connected to each A m and each B m The enable pin of the clock selector is connected to the clock selection enable signal. When the clock selection enable signal is 1, the second input pin is enabled. When the clock selection enable signal is 0, the first input pin is enabled. When there are R detectable parallel interfaces in the chip to be tested, the clock selection enable signal is set to 0. When there are not R detectable parallel interfaces in the chip to be tested, the clock selection enable signal is set to 1.

Images