Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device, and the array substrate comprises a substrate; the plurality of shift register units are arranged on one side of the substrate; the multiple clock signal lines and the shifting register units are arranged on the same side of the substrate, the multiple clock signal lines and the multiple shifting register units are arranged in a one-to-one correspondence mode, and each clock signal line is used for inputting a clock signal of a clock signal source into the corresponding shifting register unit; the overlapping conductive wires are arranged on the sides, away from the substrate, of the clock signal wires, the orthographic projection of the overlapping conductive wires on the substrate and the orthographic projection of each clock signal wire on the substrate have overlapping areas, and overlapping capacitance is formed between the overlapping conductive wires and the clock signal wires. According to the technical scheme provided by the embodiment of the invention, the waveforms of the clock signals output to the shift register unit by the plurality of clock signal lines can be consistent, so that charging difference can be avoided, horizontal stripes are avoided, and the display effect is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] At present, the gate drive circuit is usually formed on the array substrate of the liquid crystal display through an array process, that is, the array substrate row drive (Gate driver on Array, GOA) process. The gate drive circuit usually includes a plurality of shift register units, and each shift register unit inputs a clock signal through a corresponding clock signal line. There is a coupling effect between the clock signal lines, and the coupling effect of the two clock signal lines that are close to each other is strong, and the coupling effect of the two clock signal lines that are far away is weak. Therefore, the clock signal lines at the edge and the clock signal lines in the middle are coupled to different degrees, resulting in differences in the output clock signal waveforms, which causes charging differences and produces horizontal stripes. Summary of the invention

[0003] Embodiments of the present application provide an array substrate, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As one aspect of an embodiment of the present application, the embodiment of the present application provides an array substrate, including: a substrate; a plurality of shift register units, arranged on one side of the substrate; a plurality of clock signal lines, arranged on the same side of the substrate as the shift register units, the plurality of clock signal lines being arranged in one-to-one correspondence with the plurality of shift register units, each clock signal line being used to input a clock signal of a clock signal source into a corresponding shift register unit; an overlapping conductive line, arranged on a side of the clock signal line away from the substrate, the orthographic projection of the overlapping conductive line on the substrate and the orthographic projection of each clock signal line on the substrate both having an overlapping area to form an overlapping capacitor with each clock signal line.

[0005] In one embodiment, the overlapping conductive line is located at an end of the clock signal line away from a clock signal source.

[0006] In one embodiment, the ratio of the width of the overlapping conductive line to the width of each clock signal line is 0.5-2.

[0007] In one embodiment, the array substrate further includes: a gate metal layer, which is arranged on one side of the substrate, and the gate metal layer includes a plurality of clock signal lines; a source-drain metal layer, which is arranged on the side of the gate metal layer away from the substrate; and a transparent electrode layer, which is arranged on the side of the gate metal layer away from the substrate; wherein the source-drain metal layer includes overlapping conductive lines; or, the transparent electrode layer includes overlapping conductive lines.

[0008] In one embodiment, when the source-drain metal layer includes overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of multiple clock signal lines on the substrate is S1; when the transparent electrode layer includes overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of multiple clock signal lines on the substrate is S2; wherein, S1<S2.

[0009] In one embodiment, the array substrate further includes: a DC signal line, which is arranged on the same layer as multiple clock signal lines and is used to input a DC signal from a DC signal source into a shift register unit, wherein an orthographic projection of the DC signal line on the substrate and an orthographic projection of the overlapping conductive line on the substrate have an overlapping area.

[0010] In one embodiment, the array substrate also includes: a DC signal line, which is arranged on the same layer as multiple clock signal lines, at least one insulating layer is arranged between the DC signal line and the overlapping conductive lines, and vias are formed on each insulating layer, and the DC signal line is electrically connected to the overlapping conductive lines through the vias.

[0011] In one embodiment, a plurality of clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; and the overlapping conductive lines extend along the first direction.

[0012] In one embodiment, a plurality of clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; and the extending directions of the overlapping conductive lines are inclined relative to both the first direction and the second direction.

[0013] In one embodiment, a plurality of clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the overlapping conductive line includes a first connecting segment, a second connecting segment, and a third connecting segment, and the extension direction of the first connecting segment and the third connecting segment is parallel to the first direction, the second connecting segment is connected between the first connecting segment and the third connecting segment, and the extension direction of the second connecting segment is parallel to the second direction.

[0014] In one embodiment, a plurality of clock signal lines are arranged at intervals along a first direction, and each clock signal line extends along a second direction perpendicular to the first direction; the overlapping conductive lines include a fourth connecting segment, a fifth connecting segment, a sixth connecting segment, a seventh connecting segment and an eighth connecting segment, the fifth connecting segment is connected between one end of the sixth connecting segment and the fourth connecting segment, and the seventh connecting segment is connected between the other end of the sixth connecting segment and the eighth connecting segment; wherein the fourth connecting segment, the sixth connecting segment and the eighth connecting segment all extend along the first direction, and the fifth connecting segment and the seventh connecting segment both extend along the second direction.

[0015] As another aspect of an embodiment of the present application, an embodiment of the present application provides a display panel, comprising an array substrate of any of the above-mentioned embodiments.

[0016] As another aspect of the embodiments of the present application, the embodiments of the present application provide a display device, comprising a display panel of any of the above-mentioned embodiments.

[0017] The embodiment of the present application adopts the above technical solution to make the clock signal waveforms output by multiple clock signal lines to the shift register unit consistent, thereby avoiding charging differences and horizontal stripes, and effectively improving the display effect.

[0018] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present application will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0020] Figure 1 A schematic diagram showing a clock signal line and a DC signal line in the related art;

[0021] Figure 2 A clock signal waveform diagram of an input clock signal line in the related art is shown;

[0022] Figure 3 A schematic diagram showing a clock signal line, a shift register unit and overlapping conductive lines according to an embodiment of the present application;

[0023] Figure 4 A schematic diagram of a partial cross-sectional structure of an array substrate according to an embodiment of the present application is shown;

[0024] Figure 5 A schematic diagram showing a clock signal line, a DC signal line, and an overlapping conductive line according to a first embodiment of the present application;

[0025] Figure 6 A schematic diagram showing a clock signal line, a DC signal line, and an overlapping conductive line according to a second embodiment of the present application;

[0026] Figure 7 A schematic diagram showing a clock signal line, a DC signal line, and an overlapping conductive line according to a third embodiment of the present application;

[0027] Figure 8 A schematic diagram showing a clock signal line, a DC signal line and an overlapping conductive line according to a fourth embodiment of the present application;

[0028] Fig. 9 A schematic diagram showing a clock signal line, a DC signal line and an overlapping conductive line according to a fifth embodiment of the present application is shown.

[0029] Description of reference numerals:

[0030] 100: substrate; 300: clock signal line; 400: overlapping conductive line; 410: first connecting section; 420: second connecting section; 430: third connecting section; 440: fourth connecting section; 450: fifth connecting section; 460: sixth connecting section; 470: seventh connecting section; 480: eighth connecting section; 500: gate metal layer; 600: source-drain metal layer; 700: transparent electrode layer; 800: gate insulating layer; 900: source-drain insulating layer; 1000: DC signal line. DETAILED DESCRIPTION

[0031] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0032] Figure 1 A schematic diagram showing a clock signal line, a DC signal line and a shift register unit in the related art; Figure 2 FIG. 1 shows a clock signal waveform diagram of an input clock signal line in the related art. Figure 1 and Figure 2 As shown, the TV device GOA product usually adopts a multiple clock signal line design, the multiple clock signal lines are arranged side by side, and a DC signal line such as a low-level signal line is set on one side of the multiple clock signal lines. Figure 1 and Figure 2 Eight clock signal lines CLK1~CLK8 and one DC signal line LVGL are shown in the figure. The clock signal of each clock signal line has a coupling effect on the clock signal of the nearby clock signal line when it jumps (such as high level jumps to low level or low level jumps to high level). The higher the refresh rate, the stronger the coupling effect between the clock signal lines. Among them, the coupling effect of the two clock signal lines that are close to each other is strong, and the coupling effect of the two clock signal lines that are far away is weak. Therefore, the clock signal line at the edge and the clock signal line in the middle are coupled to different degrees, resulting in differences in the clock signal waveforms output by the clock signal line at the edge and the clock signal line in the middle, which causes charging differences and causes horizontal stripes on the display panel.

[0033] In order to solve the above problems, the first aspect of the present application provides an array substrate. Figure 3-Figure 9An array substrate according to an embodiment of the first aspect of the present application is described.

[0034] Figure 3 A schematic diagram showing a clock signal line 300, a shift register unit and an overlapping conductive line 400 according to an embodiment of the present application; Figure 4 FIG. 2 is a schematic diagram showing a partial cross-sectional structure of an array substrate according to an embodiment of the present application. Figure 3 and Figure 4 As shown, the array substrate includes: a substrate 100, a plurality of shift register units, a plurality of clock signal lines 300 and overlapping conductive lines 400. The substrate 100 may be a glass substrate or a flexible substrate. In the description of this application, "plurality" means two or more.

[0035] Specifically, a plurality of shift register units are arranged on one side of the substrate 100. A plurality of clock signal lines 300 and the shift register units are arranged on the same side of the substrate 100, and the plurality of clock signal lines 300 are arranged one-to-one with the plurality of shift register units, and each clock signal line 300 is used to input the clock signal of the clock signal source into the corresponding shift register unit. The overlapping conductive line 400 is arranged on the side of the clock signal line 300 away from the substrate 100, and the orthographic projection of the overlapping conductive line 400 on the substrate 100 and the orthographic projection of each clock signal line 300 on the substrate 100 both have an overlapping area, so as to form an overlapping capacitor with each clock signal line 300.

[0036] For example, the substrate 100 may have a display area and a non-display area outside the display area, for example, the non-display area may be arranged around the display area. The plurality of shift register units, the plurality of clock signal lines 300 and the overlapping conductive lines 400 may all be located in the non-display area. Figure 3 , eight clock signal lines 300 and eight shift register units GOA(n) to GOA(n+7) are shown. The eight clock signal lines 300 may be arranged at intervals along a first direction, and each clock signal line 300 may extend along a second direction perpendicular to the first direction. Figure 3The first direction is the left-right direction, and the second direction is the up-down direction. One end of each clock signal line 300 can be connected to a clock signal source to input the clock signal of the clock signal source into the corresponding shift register unit. The overlapping area of ​​the orthographic projection of the overlapping conductive line 400 on the substrate 100 and the orthographic projection of each clock signal line 300 on the substrate 100 can be equal or unequal. Since the orthographic projection of the overlapping conductive line 400 on the substrate 100 and the orthographic projection of each clock signal line 300 on the substrate 100 both have overlapping areas, overlapping capacitance can be formed between the overlapping conductive line 400 and each clock signal line 300. According to the principle of capacitive coupling, when any of the eight clock signal lines 300 causes the clock signal to change due to coupling, the overlapping capacitance will pull the clock signals of the remaining clock signal lines 300 to change together, thereby suppressing the difference in the clock signal waveforms output by the multiple clock signal lines 300, so that the clock signal waveforms output by the multiple clock signal lines 300 remain consistent.

[0037] Optionally, the material of the overlapping conductive lines 400 may be metal or other conductive materials, for example, metal oxide semiconductor, such as tin-doped indium oxide (ITO).

[0038] Figure 3 Eight clock signal lines 300 and eight shift register units are shown for illustrative purposes, but after reading the technical solution of the present application, an ordinary technician can obviously understand that the solution can be applied to the technical solution of other numbers of clock signal lines 300 and shift register units, which also falls within the scope of protection of the present application.

[0039] According to the array substrate of the embodiment of the present application, an overlapping conductive line 400 is arranged on the side of the clock signal line 300 facing away from the substrate 100, and the orthographic projection of the overlapping conductive line 400 on the substrate 100 and the orthographic projection of each clock signal line 300 on the substrate 100 have an overlapping area, so as to form an overlapping capacitor between each clock signal line 300, so that the clock signal waveforms output by multiple clock signal lines 300 to the shift register unit are consistent, thereby avoiding charging differences and horizontal stripes, thereby effectively improving the display effect.

[0040] In one embodiment, the overlapping conductive line 400 is located at an end of the clock signal line 300 that is far away from the clock signal source. For example, the clock signal line 300 may have a first end and a second end, the first end is connected to the clock signal source, and the second end is arranged away from the clock signal source. The overlapping conductive line 400 is arranged close to the second end of the clock signal line 300, that is, the minimum distance between the overlapping conductive line 400 and the first end of the clock signal line 300 is greater than the minimum distance between the overlapping conductive line 400 and the second end of the clock signal line 300. Since the clock signal source can provide a stable clock signal, the coupling effect between the two clock signal lines 300 can be suppressed to a certain extent, so that horizontal stripes are not easy to appear near the first end of the clock signal line 300, and horizontal stripes usually appear near the second end of the clock signal line 300.

[0041] In this embodiment, by locating the overlapping conductive line 400 at the end of the clock signal line 300 away from the clock signal source, it is further ensured that the clock signal waveforms output by multiple clock signal lines 300 to the shift register unit are consistent, thereby avoiding charging differences and avoiding the generation of horizontal stripes at the end of the clock signal line 300 away from the clock signal source.

[0042] In one embodiment, the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is 0.5 to 2 (including the end value). That is, the width of the overlapping conductive line 400 is 0.5 to 2 times the width of each clock signal line 300. Among them, the width direction can be parallel to the surface of the substrate 100. Specifically, for example, when the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is less than 0.5, the width of the overlapping conductive line 400 may be too small, thereby reducing the structural strength of the overlapping conductive line 400 and affecting the reliability of the overlapping conductive line 400 in suppressing the coupling difference between the clock signal lines 300; when the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is greater than 2, the width of the overlapping conductive line 400 may be too large, resulting in the overlapping conductive line 400 occupying too much space, which is not conducive to the arrangement of other connecting lines in the array substrate.

[0043] In this embodiment, by making the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 be 0.5-2, the ratio of the width of the overlapping conductive line 400 to the width of each clock signal line 300 is reasonable, while ensuring that the overlapping conductive line 400 can effectively suppress the coupling difference between the clock signal lines 300, while avoiding the overlapping conductive line 400 from occupying too large an area, thereby facilitating the layout of other connecting lines.

[0044] In one embodiment, reference Figure 3 and Figure 4, the array substrate further includes a gate metal layer 500, a source-drain metal layer 600 and a transparent electrode layer 700. The gate metal layer 500 is disposed on one side of the substrate 100, and the gate metal layer 500 includes the above-mentioned multiple clock signal lines 300. The source-drain metal layer 600 is disposed on the side of the gate metal layer 500 away from the substrate 100. The transparent electrode layer 700 is disposed on the side of the gate metal layer 500 away from the substrate 100. Among them, the source-drain metal layer 600 includes the above-mentioned overlapping conductive lines 400; or, the transparent electrode layer 700 includes the above-mentioned overlapping conductive lines 400.

[0045] Exemplarily, the gate metal layer 500 may include a gate. The source-drain metal layer 600 may include a first electrode and a second electrode, one of the first electrode and the second electrode is a source electrode, and the other of the first electrode and the second electrode is a drain electrode. The substrate 100 may also include an active layer (not shown in the figure), the active layer may include a channel region and a non-channel region located on both sides of the channel region, and the first electrode and the second electrode are in contact with the corresponding non-channel region, respectively. A gate insulating layer 800 is provided between the source-drain metal layer 600 and the gate metal layer 500, and a source-drain insulating layer 900 is provided between the source-drain metal layer 600 and the transparent electrode layer 700. Among them, the gate, the first electrode, the second electrode and the active layer constitute a thin film transistor. The transparent electrode layer 700 may be a pixel electrode layer or a common electrode layer. When the source-drain metal layer 600 includes overlapping conductive lines 400, the vertical distance between the overlapping conductive lines 400 and the clock signal line 300 is the thickness of the gate insulating layer 800; when the transparent electrode layer 700 includes overlapping conductive lines 400, the vertical distance between the overlapping conductive lines 400 and the clock signal line 300 is the sum of the thicknesses of the gate insulating layer 800 and the source-drain insulating layer 900.

[0046] Optionally, the material of the transparent electrode layer 700 may be ITO.

[0047] It should be noted that the array substrate in the embodiment of the present application can be an array substrate with a bottom gate structure, an array substrate with a top gate structure, an array substrate with a double gate structure (i.e., including a bottom gate and a top gate), or any mixture of the above three structures.

[0048] In this embodiment, the overlapping conductive lines 400 can be prepared by utilizing the original film structure of the array substrate (ie, the source-drain metal layer 600 or the transparent electrode layer 700 ), thereby simplifying the preparation process of the array substrate.

[0049] In one embodiment, when the source-drain metal layer 600 includes overlapping conductive lines 400, the overlapping area of ​​the orthographic projection of the overlapping conductive lines 400 on the substrate 100 and the orthographic projection of the plurality of clock signal lines 300 on the substrate 100 is S1; when the transparent electrode layer 700 includes overlapping conductive lines 400, the overlapping area of ​​the orthographic projection of the overlapping conductive lines 400 on the substrate 100 and the orthographic projection of the plurality of clock signal lines 300 on the substrate 100 is S2; wherein, S1<S2.

[0050] Exemplarily, when the source-drain metal layer 600 includes the overlapping conductive line 400, the vertical distance D1 between the overlapping conductive line 400 and the clock signal line 300 is the thickness of the gate insulating layer 800; when the transparent electrode layer 700 includes the overlapping conductive line 400, the vertical distance D2 between the overlapping conductive line 400 and the clock signal line 300 is the sum of the thicknesses of the gate insulating layer 800 and the source-drain insulating layer 900, so D2 is greater than D1. The greater the vertical distance between the overlapping conductive line 400 and the clock signal line 300, the smaller the overlapping capacitance formed between the overlapping conductive line 400 and the clock signal line 300. When the source-drain metal layer 600 includes the overlapping conductive line 400, the overlapping capacitance formed between the overlapping conductive line 400 and the clock signal line 300 is C1; when the transparent electrode layer 700 includes the overlapping conductive line 400, the overlapping capacitance formed between the overlapping conductive line 400 and the clock signal line 300 is C2. If S1=S2, then C1>C2.

[0051] Therefore, by making S1 < S2, when the vertical distance between the overlapping conductive line 400 and the clock signal line 300 is large, the overlapping capacitance between the overlapping conductive line 400 and the clock signal line 300 can be increased, thereby improving the suppression effect of the overlapping capacitance on the coupling difference between the clock signal lines 300.

[0052] Figure 5 FIG. 1 is a schematic diagram showing a clock signal line 300, a DC signal line 1000 and an overlapping conductive line 400 according to a first embodiment of the present application. Figure 4 and Figure 5 As shown, the array substrate further includes a DC signal line 1000, which is arranged on the same layer as the plurality of clock signal lines 300, and is used to input the DC signal of the DC signal source into the shift register unit, and the orthographic projection of the DC signal line 1000 on the substrate 100 and the orthographic projection of the overlapping conductive line 400 on the substrate 100 have an overlapping area. Exemplarily, the DC signal line 1000 can be a low-level signal line. The DC signal line 1000 can be arranged on one side of the plurality of clock signal lines 300, and the extension direction of the DC signal line 1000 can be the same as the extension direction of each clock signal line 300.

[0053] In the present embodiment, since the DC signal line 1000 can stably input a DC signal through a DC signal source, by making the orthographic projection of the DC signal line 1000 on the substrate 100 and the orthographic projection of the overlapping conductive line 400 on the substrate 100 have an overlapping area, overlapping capacitance can also be generated between the DC signal line 1000 and the overlapping conductive line 400, so that the DC signal can be used to more effectively suppress the coupling difference between the clock signal lines 300, thereby improving the display effect.

[0054] Figure 6 FIG. 1 is a schematic diagram showing a clock signal line 300, a DC signal line 1000 and an overlapping conductive line 400 according to a second embodiment of the present application. Figure 4 and Figure 6 The array substrate also includes a DC signal line 1000, which is arranged on the same layer as the multiple clock signal lines 300. At least one insulating layer is arranged between the DC signal line 1000 and the overlapping conductive line 400. Vias are formed on each insulating layer, and the DC signal line 1000 is electrically connected to the overlapping conductive line 400 through the vias.

[0055] Exemplarily, the DC signal line 1000 can be used to input the DC signal of the DC signal source into the shift register unit; or, the DC signal line 1000 can be used to output the DC signal of the shift register unit. In the case where the source-drain metal layer 600 includes the overlapping conductive line 400, the insulating layer between the DC signal line 1000 and the overlapping conductive line 400 is the gate insulating layer 800, and the DC signal line 1000 is electrically connected to the overlapping conductive line 400 through the via hole on the gate insulating layer 800. In the case where the transparent electrode layer 700 includes the overlapping conductive line 400, the insulating layer between the DC signal line 1000 and the overlapping conductive line 400 is the gate insulating layer 800 and the source-drain insulating layer 900, and the DC signal line 1000 is electrically connected to the overlapping conductive line 400 through the via hole on the gate insulating layer 800 and the via hole on the source-drain insulating layer 900.

[0056] In this embodiment, the overlapping conductive line 400 can be electrically connected to the DC signal line 1000, so that the overlapping conductive line 400 can stably input a DC signal through a DC signal source, thereby utilizing a stable DC signal to more effectively suppress the coupling difference between the clock signal lines 300 and improve the display effect.

[0057] In one embodiment, Figure 5 As shown, a plurality of clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; and the overlapping conductive line 400 extends along the first direction. Figure 5In the embodiment, the first direction is the left-right direction, and the second direction is the up-down direction. The array substrate further includes a DC signal line 1000 extending along the second direction, and the overlapping conductive line 400 is perpendicular to the DC signal line 1000 and each clock signal line 300. The orthographic projection of the overlapping conductive line 400 on the substrate 100 may overlap or may not overlap with the orthographic projection of the DC signal line 1000 on the substrate 100.

[0058] In this embodiment, the overlapping conductive line 400 is perpendicular to each clock signal line 300. While ensuring that the orthographic projection of the overlapping conductive line 400 on the substrate 100 overlaps with the orthographic projection of each clock signal line 300 on the substrate 100, the overlapping conductive line 400 is short in length and has a simple structure, which is beneficial to reducing the cost of the array substrate.

[0059] Figure 7 FIG. 1 is a schematic diagram showing a clock signal line 300, a DC signal line 1000 and an overlapping conductive line 400 according to a third embodiment of the present application. Figure 7 As shown, a plurality of clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; the extending direction of the overlapping conductive line 400 is inclined relative to both the first direction and the second direction, that is, the extending direction of the overlapping conductive line 400 is not parallel to the first direction and is not parallel to the second direction. Figure 7 In the example of , the first direction is the left-right direction, and the second direction is the up-down direction. In the direction from left to right, the overlapping conductive line 400 gradually tilts downward. The array substrate also includes a DC signal line 1000 extending along the second direction. The orthographic projection of the overlapping conductive line 400 on the substrate 100 may overlap or may not overlap with the orthographic projection of the DC signal line 1000 on the substrate 100.

[0060] In this embodiment, the overlapping conductive lines 400 are arranged obliquely relative to the clock signal lines 300. The structure of the overlapping conductive lines 400 is also simple, and the arrangement of the overlapping conductive lines 400 arranged in this way is relatively easy, thereby improving the overall preparation efficiency of the array substrate.

[0061] Figure 8 FIG. 1 is a schematic diagram showing a clock signal line 300, a DC signal line 1000 and an overlapping conductive line 400 according to a fourth embodiment of the present application. Figure 8, multiple clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; the overlapping conductive line 400 includes a first connecting segment 410, a second connecting segment 420 and a third connecting segment 430, and the extension direction of the first connecting segment 410 and the third connecting segment 430 is parallel to the first direction, the second connecting segment 420 is connected between the first connecting segment 410 and the third connecting segment 430, and the extension direction of the second connecting segment 420 is parallel to the second direction.

[0062] For example, Figure 8 In the embodiment, the first direction is the left-right direction, and the second direction is the up-down direction. Figure 8 Eight clock signal lines 300 are shown in the figure, and the array substrate also includes a DC signal line 1000 extending along the second direction. For the convenience of description, the eight clock signal lines 300 are referred to as "first clock signal line 300", "second clock signal line 300" ... "eighth clock signal line 300" from left to right. The overlapping conductive line 400 is formed into a "Z" shape. The orthographic projection of the first connecting section 410 on the substrate 100 has an overlapping area with the orthographic projections of the first clock signal line 300 to the fourth clock signal line 300 on the substrate 100. The orthographic projection of the second connecting section 420 on the substrate 100 has an overlapping area with the orthographic projections of the fourth clock signal line 300 and the fifth clock signal line 300 on the substrate 100. The orthographic projection of the third connection segment 430 on the substrate 100 overlaps with the orthographic projections of the fifth to eighth clock signal lines 300 to 300 on the substrate 100 , and the orthographic projection of the third connection segment 430 on the substrate 100 overlaps with the orthographic projection of the DC signal line 1000 on the substrate 100 .

[0063] In this embodiment, the overlapping conductive lines 400 form overlapping capacitors with the clock signal lines 300 to avoid horizontal stripes, and can effectively avoid the connection lines between the clock signal lines 300 and the shift register units, facilitating routing.

[0064] Fig. 9 FIG. 4 is a schematic diagram showing a clock signal line 300, a DC signal line 1000 and an overlapping conductive line 400 according to a fifth embodiment of the present application. Fig. 9As shown, multiple clock signal lines 300 are arranged at intervals along a first direction, and each clock signal line 300 extends along a second direction perpendicular to the first direction; the overlapping conductive line 400 includes a fourth connecting segment 440, a fifth connecting segment 450, a sixth connecting segment 460, a seventh connecting segment 470 and an eighth connecting segment 480, the fifth connecting segment 450 is connected between one end of the sixth connecting segment 460 and the fourth connecting segment 440, and the seventh connecting segment 470 is connected between the other end of the sixth connecting segment 460 and the eighth connecting segment 480; wherein the fourth connecting segment 440, the sixth connecting segment 460 and the eighth connecting segment 480 all extend along the first direction, and the fifth connecting segment 450 and the seventh connecting segment 470 all extend along the second direction.

[0065] For example, Fig. 9 , the first direction is the left-right direction, and the second direction is the up-down direction. The overlapping conductive line 400 is formed in a "U" shape. The orthographic projection of the fourth connecting segment 440 on the substrate 100 has an overlapping area with the orthographic projections of the first clock signal line 300 and the second clock signal line 300 on the substrate 100. The orthographic projection of the fifth connecting segment 450 on the substrate 100 has an overlapping area with the orthographic projections of the second clock signal line 300 and the third clock signal line 300 on the substrate 100. The orthographic projection of the sixth connecting segment 460 on the substrate 100 has an overlapping area with the orthographic projections of the third clock signal line 300 to the sixth clock signal line 300 on the substrate 100. The orthographic projection of the seventh connecting segment 470 on the substrate 100 has an overlapping area with the orthographic projections of the sixth clock signal line 300 and the seventh clock signal line 300 on the substrate 100. The orthographic projection of the eighth connection segment 480 on the substrate 100 has an overlapping area with the orthographic projections of the seventh clock signal line 300 , the eighth clock signal line 300 and the DC signal line 1000 on the substrate 100 .

[0066] In this embodiment, the overlapping conductive lines 400 can also form overlapping capacitors with each clock signal line 300, thereby avoiding the generation of horizontal stripes. At the same time, the overlapping conductive lines 400 arranged in this way can also avoid the connection lines between the clock signal lines 300 and the shift register units, thereby facilitating routing.

[0067] A display panel according to an embodiment of the second aspect of the present application includes an array substrate according to any implementation of the first aspect of the present application.

[0068] According to the display panel of the embodiment of the present application, by adopting the above-mentioned array substrate, the clock signal waveforms output by multiple clock signal lines 300 to the shift register unit are consistent, thereby avoiding charging differences and horizontal stripes, thereby effectively improving the display effect.

[0069] The display device according to the third aspect of the present application includes the above-mentioned display panel, wherein the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0070] According to the display device of the embodiment of the present application, by adopting the above-mentioned display panel, the generation of horizontal stripes can be avoided, thereby improving the display quality and yield.

[0071] The array substrate, display panel and other components of the display device in the above-mentioned embodiments may adopt various technical solutions known to ordinary technicians in the field now and in the future, and will not be described in detail here.

[0072] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0073] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0074] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0075] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0076] The disclosure above provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numerals and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A plurality of shift register units are arranged on one side of the substrate; A plurality of clock signal lines are arranged on the same side of the substrate as the shift register units, the plurality of clock signal lines are arranged in one-to-one correspondence with the plurality of shift register units, and each of the clock signal lines is used to input a clock signal of a clock signal source into a corresponding shift register unit; The overlapping conductive line is arranged on a side of the clock signal line away from the substrate, and the orthographic projection of the overlapping conductive line on the substrate and the orthographic projection of each of the clock signal lines on the substrate have overlapping areas to form overlapping capacitances with each of the clock signal lines.

2. The array substrate according to claim 1, characterized in that: The overlapping conductive line is located at an end of the clock signal line away from the clock signal source.

3. The array substrate according to claim 1, characterized in that: The ratio of the width of the overlapping conductive line to the width of each of the clock signal lines is 0.5-2.

4. The array substrate according to claim 1, characterized in that: Also includes: A gate metal layer, disposed on one side of the substrate, the gate metal layer comprising the plurality of clock signal lines; A source-drain metal layer, disposed on a side of the gate metal layer away from the substrate; A transparent electrode layer, disposed on a side of the gate metal layer away from the substrate; Wherein, the source-drain metal layer includes the overlapping conductive lines; or, the transparent electrode layer includes the overlapping conductive lines.

5. The array substrate according to claim 4, characterized in that: When the source-drain metal layer includes the overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of the multiple clock signal lines on the substrate is S1; when the transparent electrode layer includes the overlapping conductive lines, the overlapping area of ​​the orthographic projection of the overlapping conductive lines on the substrate and the orthographic projection of the multiple clock signal lines on the substrate is S2; wherein, S1<S2.

6. The array substrate according to claim 1, characterized in that: Also includes: A DC signal line is arranged in the same layer as the multiple clock signal lines, and is used to input a DC signal from a DC signal source into the shift register unit. The orthographic projection of the DC signal line on the substrate and the orthographic projection of the overlapping conductive line on the substrate have an overlapping area.

7. The array substrate according to claim 1, characterized in that: Also includes: A DC signal line is arranged on the same layer as the multiple clock signal lines. At least one insulating layer is arranged between the DC signal line and the overlapping conductive lines. Vias are formed on each of the insulating layers. The DC signal line is electrically connected to the overlapping conductive lines through the vias.

8. The array substrate according to any one of claims 1 to 7, characterized in that: The plurality of clock signal lines are arranged at intervals along a first direction, and each of the clock signal lines extends along a second direction perpendicular to the first direction; and the overlapping conductive lines extend along the first direction.

9. The array substrate according to any one of claims 1 to 7, characterized in that: The plurality of clock signal lines are arranged at intervals along a first direction, and each of the clock signal lines extends along a second direction perpendicular to the first direction; and the extending direction of the overlapping conductive lines is inclined relative to both the first direction and the second direction.

10. The array substrate according to any one of claims 1 to 7, characterized in that: The multiple clock signal lines are arranged at intervals along a first direction, and each of the clock signal lines extends along a second direction perpendicular to the first direction; the overlapping conductive lines include a first connecting segment, a second connecting segment and a third connecting segment, the extension directions of the first connecting segment and the third connecting segment are parallel to the first direction, the second connecting segment is connected between the first connecting segment and the third connecting segment, and the extension direction of the second connecting segment is parallel to the second direction.

11. The array substrate according to any one of claims 1 to 7, characterized in that: The multiple clock signal lines are arranged at intervals along a first direction, and each of the clock signal lines extends along a second direction perpendicular to the first direction; the overlapping conductive lines include a fourth connecting segment, a fifth connecting segment, a sixth connecting segment, a seventh connecting segment and an eighth connecting segment, the fifth connecting segment is connected between one end of the sixth connecting segment and the fourth connecting segment, and the seventh connecting segment is connected between the other end of the sixth connecting segment and the eighth connecting segment; wherein the fourth connecting segment, the sixth connecting segment and the eighth connecting segment all extend along the first direction, and the fifth connecting segment and the seventh connecting segment all extend along the second direction.

12. A display panel, characterized in that: It comprises an array substrate according to any one of claims 1 to 11.

13. A display device, characterized in that: Includes the display panel as claimed in claim 12.

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