Waveform synchronization method and device and synchronous waveform generation equipment

Abstract

The invention discloses a waveform synchronization method and device, and the method comprises the steps: firstly generating a dot frequency signal which has the same frequency with a low-frequency reference clock and is synchronous with the low-frequency reference clock after a system is started, feeding back the dot frequency signal in the form of a clock after passing through a signal link, carrying out the digital phase discrimination with the low-speed reference clock, and adjusting the delay of the signal link. And the feedback clock and the reference clock are aligned in phase, so that the certainty of signal link delay is realized. By adopting the thought similar to a phase-locked loop, the problems of uncertain time delay and non-synchronization between channels between the DAC and the FPGA interface can be solved under the condition that an ADC is not used for collecting a feedback waveform and carrying out complex correction calculation, the hardware complexity and cost of the system are remarkably reduced, and the digital phase discrimination speed and the calibration speed are high. In addition, the precision of delay calibration mainly depends on the establishment and retention time of the D trigger, and very high precision can be achieved. The invention also discloses synchronous waveform generation equipment.

Description

Technical Field

[0001] The present invention relates to the field of electronic information technology, and in particular to a waveform synchronization method, device and synchronization waveform generating equipment. Background Art

[0002] In the data transmission between the digital-to-analog converter (DAC) and the programmable logic device (FPGA) interface, the uncertainty of delay and the asynchrony between multiple channels are key issues affecting system performance. Especially in high-precision signal processing and multi-channel applications, such as multi-channel RF signal generation in radar, high-speed communication and other systems, the synchronization and accuracy of data transmission are crucial. The more common interfaces between DAC and FPGA are parallel or serial data interfaces based on LVDS or CMOS levels and deterministic delay interfaces based on the JESD204 protocol. For DACs using LVDS or CMOS level data interfaces, data needs to be switched between the FPGA processing clock and the DAC conversion clock, which can easily cause a clock cycle of delay uncertainty. Especially when the DAC conversion clock frequency is high, the synchronization signal is prone to metastable due to various factors such as temperature, cable transmission, clock jitter and phase drift, and channel inconsistency, resulting in data delay changes. For interfaces using the JESD204 protocol, although the protocol is designed to provide a more accurate source synchronization solution, when the DAC conversion clock frequency is very high, the SYSREF synchronization signal is still difficult to meet the setup and hold time requirements, resulting in data delay uncertainty and system inability to synchronize.

[0003] A common solution is to generate a standard calibration reference signal from the DAC output every time the system is powered on, then use the ADC to collect the waveform output by the DAC and send it to the FPGA or processor for calibration calculation, and finally compensate the calculated delay compensation value to the signal link. This method requires the additional use of ADC devices and related peripheral circuits, correction networks, interfaces and computing equipment, and requires complex calculation and calibration processes, which increases the complexity of the system, takes a long time to calibrate, and has a large overhead of software and hardware resources. In addition, in some situations where the system needs to be powered on quickly to enter the working state or there is strong external interference, it may not be allowed to perform calibration calculations for a long time after power-on, or perform closed-loop transceiver calibration at the full system level.

[0004] In view of this situation, it is necessary to study a new waveform synchronization method. Without using ADC to collect feedback waveforms and perform complex correction calculations, it is necessary to solve the problems of uncertain delay and channel asynchrony between DAC and FPGA interface with less resource overhead, while reducing the complexity and cost of the system. Summary of the invention

[0005] In order to solve the technical problems existing in the background technology, the present invention provides a waveform synchronization method and device.

[0006] A waveform synchronization method proposed by the present invention comprises the following steps:

[0007] S1, sending the reference clock signal a to the first frequency synthesizer, outputting the reference clock signal b, the system clock signal c and the DAC conversion clock signal d;

[0008] S2, switching the input signal selector and the output signal analog switch to the calibration signal path;

[0009] S3, generating a synchronization signal e synchronized with the reference clock signal b, and generating a single-point frequency digital calibration signal f having the same frequency as the reference clock signal b in the system clock domain according to the synchronization signal e;

[0010] S4, after the single-point frequency digital calibration signal f completes the clock domain switching through the buffer, it is sent to the DAC for digital-to-analog conversion, and finally the image signal is filtered out through a low-pass filter to obtain the single-point frequency analog calibration signal g;

[0011] S5, sending the single-point frequency analog calibration signal g to the second frequency synthesizer, and outputting a feedback clock signal h with the same frequency as the reference clock b;

[0012] S6. Adjust the initial phase of the single-point frequency digital calibration signal f to align the phases of the reference clock signal b and the feedback clock signal h, and record the initial phase value of the single-point frequency digital calibration signal f.

[0013] S7. Each time the system is powered on, S1-S5 are repeated; wherein the initial phase of the single-point frequency digital calibration signal f in S3 is set to:

[0014]

[0015] in, is the initial phase of the single-point frequency digital calibration signal f after each system power-on, N is a positive odd number and N>3, f base is the frequency of the reference clock signal b, f dac is the frequency of the DAC conversion clock signal d;

[0016] S8, sending the reference clock signal b and the feedback clock signal h generated in S7 to a digital phase detector for phase detection, and outputting a phase error mark signal i;

[0017] S9: Check whether the phase error marker signal i has been pulled high; if so, the calibration is completed; if not, increase the delay compensation value signal j in the signal link by one DAC conversion clock cycle, and then recheck the phase error marker signal i until it is detected that the phase error marker signal i has been pulled high.

[0018] Preferably, in S7,

[0019] Preferably, the reference clock signal b in S1, the system clock signal c and the feedback clock signal h in S5 are all square waves;

[0020] The frequency of the reference clock signal b is an integer multiple of the frequency of the reference clock signal a, the frequency of the system clock signal c is an integer multiple of the frequency of the reference clock signal b, and the frequency of the DAC conversion clock signal d is an integer multiple of the frequency of the system clock signal c.

[0021] Preferably, in S1, the initial phase differences between the reference clock signal b, the system clock signal c, the DAC conversion clock signal d and the reference clock signal a are fixed values;

[0022] In S5, the phase difference between the feedback clock signal h and the single-point frequency analog calibration signal g is a fixed value.

[0023] Preferably, in S6, the phase alignment is specifically that the phase difference between the reference clock signal b and the feedback clock signal h is less than

[0024] Preferably, in S9, each time after the delay compensation value signal j in the signal link is changed, the clock lock mark signal k output by the second frequency synthesizer is waited to be pulled high, and then the phase detection enable mark signal o is issued to allow the digital phase detector to perform phase detection.

[0025] The present invention also provides a waveform synchronization device for implementing the above-mentioned waveform synchronization method, comprising: a reference clock source, a first frequency synthesizer, a synchronization signal generating module, a calibration signal generating module, an input signal selector, a delay compensation module, a buffer, a DAC, an analog switch, a low-pass filter, a second frequency synthesizer, a digital phase detector and a delay controller;

[0026] The reference clock source is used to output a reference clock signal a to the first frequency synthesizer;

[0027] The first frequency synthesizer is used to output a reference clock signal b to the synchronization signal generation module and the digital phase detector, output a system clock signal c to the calibration signal generation module, and output a DAC conversion clock signal d to the DAC;

[0028] The synchronization signal generating module is used to output a synchronization signal e synchronized with the reference clock b to the calibration signal generating module;

[0029] The calibration signal generating module is used to generate a single-point frequency digital calibration signal f with the same frequency as the reference clock signal b in the system clock domain according to the synchronization signal e, and send it to the input signal selector;

[0030] The input signal selector is used to send the single-point frequency digital calibration signal f to the delay compensation module;

[0031] The delay compensation module is used to delay the single-point frequency digital calibration signal f or the digital working waveform signal m under the control of the delay compensation value signal j, and output the delayed digital signal p to the buffer;

[0032] The buffer is used to switch the delayed digital signal p between the system clock domain and the DAC clock domain, obtain the data q, and output it to the DAC;

[0033] DAC is used to perform digital-to-analog conversion on data q and output analog signal r to the analog switch;

[0034] The analog switch is used to output the analog signal r to the low-pass filter;

[0035] The low-pass filter is used to filter out the high-frequency image signal in the analog signal r sent by the analog switch, and output the single-point frequency analog calibration signal g to the second frequency synthesizer;

[0036] The second frequency synthesizer is used for outputting a feedback clock signal h having the same frequency as the reference clock signal b and a fixed phase relationship with the single-point frequency analog calibration signal g to the digital phase detector based on the single-point frequency analog calibration signal g, and outputting a clock lock mark signal k to the delay controller;

[0037] The digital phase detector is used to detect whether the phases of the feedback clock signal h and the reference clock signal b are aligned, and output a phase error mark signal i to the delay controller;

[0038] The delay controller is used to output a phase detection enable mark o to the digital phase detector, and output a delay compensation value signal j to the delay compensation module.

[0039] Preferably, the digital phase detector comprises: a first D flip-flop, a second D flip-flop and an XOR gate;

[0040] The first D flip-flop is used to sample the feedback clock signal h according to the beat of the reference clock signal b, and output the signal s to the second D flip-flop and the XOR gate when the phase detection enable flag o is pulled high;

[0041] The second D flip-flop is used to sample the signal s according to the beat of the reference clock signal b, and output the signal t to the XOR gate;

[0042] The XOR gate is used to perform an XOR operation on the signal s and the signal t, and output a phase error mark signal i.

[0043] Preferably, the delay controller is also used to wait for the lock mark signal k output by the second frequency synthesizer to be pulled high each time after the delay compensation value signal j in the signal link is changed, and then pull high the phase detection enable mark signal o.

[0044] In the present invention, the waveform synchronization method and device proposed first generate a dot frequency signal with the same and synchronous frequency as the low-frequency reference clock after the system is turned on, and then feed it back in the form of a clock after passing through the signal link to perform digital phase identification with the low-speed reference clock, and adjust the signal link delay to align the feedback clock with the reference clock phase, thereby achieving the certainty of the signal link delay. At the same time, since the low-speed reference clock is obtained by multiplying the external reference clock, the generated waveform is synchronized with the external reference clock shared by each channel. By adopting this idea similar to a phase-locked loop, the problem of uncertain delay and asynchronism between channels between the DAC and the FPGA interface can be solved without using an ADC to collect feedback waveforms and perform complex correction calculations, significantly reducing the hardware complexity and cost of the system, and the digital phase identification speed is fast and the calibration speed is fast. In addition, the accuracy of the delay calibration mainly depends on the setup and hold time of the D flip-flop, and a very high accuracy can be achieved.

[0045] The present invention also provides a synchronous waveform generating device, comprising the above-mentioned waveform synchronization device;

[0046] The input signal selector is used to send the digital working waveform signal m to the delay compensation module after the waveform synchronization is completed;

[0047] The analog switch is used to output the analog signal r as the analog working waveform signal n after the waveform synchronization is completed.

[0048] In the present invention, the proposed synchronous waveform generating device, based on the above-mentioned waveform synchronization method and device, can generate a synchronous waveform. In addition to the reference clock source, DAC, analog switch, low-pass filter and other modules, other functional units in the system are easy to implement in FPGA or dedicated integrated circuits and have strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 The figure is a schematic diagram of a synchronization waveform generation process according to an implementation of a waveform synchronization method proposed in the present invention.

[0050] Figure 2 A schematic structural diagram of an implementation of a waveform synchronization device proposed by the present invention.

[0051] Figure 3 A schematic structural diagram of an implementation of a digital phase detector of a waveform synchronization device proposed by the present invention. DETAILED DESCRIPTION

[0052] like Figures 1 to 3 As shown, Figure 1 The figure is a schematic diagram of a synchronization waveform generation process according to an implementation of a waveform synchronization method proposed in the present invention. Figure 2 A schematic diagram of the structure of an implementation of a waveform synchronization device proposed by the present invention. Figure 3 A schematic structural diagram of an implementation of a digital phase detector of a waveform synchronization device proposed by the present invention.

[0053] A waveform synchronization method proposed by the present invention comprises the following steps:

[0054] S1, sending the reference clock signal a to the first frequency synthesizer 202, outputting the reference clock signal b, the system clock signal c and the DAC conversion clock signal d;

[0055] Specifically, the reference clock signal b and the system clock signal c are square waves, the frequency of the reference clock signal b is an integer multiple of the frequency of the reference clock signal a, the frequency of the system clock signal c is an integer multiple of the frequency of the reference clock signal b, and the frequency of the DAC conversion clock signal d is an integer multiple of the frequency of the system clock signal c; the initial phase difference between the clock signals b, c and d and the reference clock signal a is a fixed value.

[0056] During the specific signal transmission process, the reference clock source 201 outputs a reference clock signal a to the first frequency synthesizer 202; the first frequency synthesizer 202 outputs a reference clock signal b to the synchronization signal generating module 203 and the digital phase detector 212, outputs a system clock signal c to the calibration signal generating module 204, and outputs a DAC 208 conversion clock signal d to the DAC 208.

[0057] S2, switching the input signal selector 205 and the output signal analog switch 209 to the calibration signal path;

[0058] S3, generating a synchronization signal e synchronized with the reference clock signal b, and generating a single-point frequency digital calibration signal f having the same frequency as the reference clock signal b in the system clock domain according to the synchronization signal e;

[0059] During the specific signal transmission process, the synchronization signal generating module 203 outputs a synchronization signal e synchronized with the reference clock b to the calibration signal generating module 204; the calibration signal generating module 204 generates a single-point frequency digital calibration signal f having the same frequency as the reference clock signal b in the system clock domain according to the synchronization signal e, and sends it to the input signal selector 205.

[0060] S4, after the single-point frequency digital calibration signal f completes the clock domain switching through the buffer 207, it is sent to the DAC 208 for digital-to-analog conversion, and finally the image signal is filtered out through the low-pass filter 210 to obtain the single-point frequency analog calibration signal g;

[0061] In the specific signal transmission process, the buffer 207 switches the delayed digital signal p between the system clock domain and the DAC 208 clock domain to obtain data q, and outputs it to the DAC 208; the DAC 208 performs digital-to-analog conversion on the data q, and outputs an analog signal r to the analog switch 209; the analog switch 209 outputs the analog signal r to the low-pass filter 210; the low-pass filter 210 filters out the high-frequency image signal in the analog signal r sent by the analog switch 209, and outputs a single-point frequency analog calibration signal g to the second frequency synthesizer 211;

[0062] S5, sending the single-point frequency analog calibration signal g to the second frequency synthesizer 211, and outputting a feedback clock signal h with the same frequency as the reference clock b;

[0063] Specifically, the phase difference between the feedback clock signal h and the single-point frequency analog calibration signal g is a fixed value.

[0064] S6. Adjust the initial phase of the single-point frequency digital calibration signal f to align the phases of the reference clock signal b and the feedback clock signal h, and record the initial phase value of the single-point frequency digital calibration signal f.

[0065] Specifically, the phase alignment judgment standard is that the phase difference between the reference clock signal b and the feedback clock signal h is less than An oscilloscope may be used to observe whether the phases are aligned, or the phase error marker signal i may be observed to be pulled high to determine whether the phases are aligned.

[0066] S7. Each time the system is powered on, S1-S5 are repeated; wherein the initial phase of the single-point frequency digital calibration signal f in S3 is set to:

[0067]

[0068] in, is the initial phase of the single-point frequency digital calibration signal f after each system power-on, N is a positive odd number and N>3, f base is the frequency of the reference clock signal b, f dac The frequency of the clock signal d is converted by the DAC 208;

[0069] Specifically, N>3, ensuring that the rising edge of the feedback clock signal h is adjusted to a fixed side of the rising edge of the reference clock signal b.

[0070] S8, sending the reference clock signal b and the feedback clock signal h generated in S7 to the digital phase detector 212 for phase detection, and outputting a phase error mark signal i;

[0071] S9: Check whether the phase error mark signal i has been pulled high; if so, the calibration is completed; if not, increase the delay compensation value signal j in the signal chain by one DAC 208 conversion clock cycle, and then recheck the phase error mark signal i until it is detected that the phase error mark signal i has been pulled high.

[0072] Specifically, each time the delay compensation value signal j in the signal chain is changed, the clock lock mark signal k output by the second frequency synthesizer 211 is waited to be pulled high, and then the phase detection enable mark signal o is issued to allow the digital phase detector 212 to perform phase detection.

[0073] In actual work, S1-S6 can be completed before leaving the factory, and S7-S9 can be completed each time the system is powered on.

[0074] Accordingly, refer to Figure 2 This embodiment also proposes a waveform synchronization device for implementing the above-mentioned waveform synchronization method, including: a reference clock source 201, a first frequency synthesizer 202, a synchronization signal generating module 203, a calibration signal generating module 204, an input signal selector 205, a delay compensation module 206, a buffer 207, a DAC 208, an analog switch 209, a low-pass filter 210, a second frequency synthesizer 211, a digital phase detector 212 and a delay controller 213.

[0075] The reference clock source 201 is used to output a reference clock signal a to the first frequency synthesizer 202 .

[0076] The first frequency synthesizer 202 is used to output a reference clock signal b to the synchronization signal generating module 203 and the digital phase detector 212 , output a system clock signal c to the calibration signal generating module 204 , and output a DAC 208 conversion clock signal d to the DAC 208 .

[0077] The synchronization signal generating module 203 is used to output a synchronization signal e synchronized with the reference clock b to the calibration signal generating module 204 .

[0078] The calibration signal generating module 204 is used to generate a single-point frequency digital calibration signal f having the same frequency as the reference clock signal b in the system clock domain according to the synchronization signal e, and send the signal to the input signal selector 205 .

[0079] The input signal selector 205 is used to send the single-point frequency digital calibration signal f to the delay compensation module 206;

[0080] The delay compensation module 206 is used to delay the single-point frequency digital calibration signal f or the digital working waveform signal m under the control of the delay compensation value signal j, and output the delayed digital signal p to the buffer 207 .

[0081] The buffer 207 is used to switch the delayed digital signal p between the system clock domain and the DAC 208 clock domain to obtain data q and output it to the DAC 208 .

[0082] The DAC 208 is used to perform digital-to-analog conversion on the data q and output an analog signal r to the analog switch 209 .

[0083] The analog switch 209 is used to output the analog signal r to the low-pass filter 210 .

[0084] The low-pass filter 210 is used to filter out the high-frequency image signal in the analog signal r sent from the analog switch 209 , and output the single-point frequency analog calibration signal g to the second frequency synthesizer 211 .

[0085] The second frequency synthesizer 211 is used to output a feedback clock signal h with the same frequency as the reference clock signal b and a fixed phase relationship with the single-point frequency analog calibration signal g to the digital phase detector 212 based on the single-point frequency analog calibration signal g, and output a clock lock mark signal k to the delay controller 213.

[0086] The digital phase detector 212 is used to detect whether the phases of the feedback clock signal h and the reference clock signal b are aligned, and output a phase error mark signal i to the delay controller 213 .

[0087] Specifically, refer to Figure 3 , the digital phase detector 212 includes: a first D flip-flop 212a, a second D flip-flop 212b and an XOR gate 212c;

[0088] The first D flip-flop 212a is used to sample the feedback clock signal h according to the beat of the reference clock signal b, and output the signal s to the second D flip-flop 212b and the XOR gate 212c when the phase-detection enable flag o is pulled high;

[0089] The second D flip-flop 212b is used to sample the signal s according to the beat of the reference clock signal b, and output the signal t to the XOR gate 212c;

[0090] The XOR gate 212c is used to perform an XOR operation on the signal s and the signal t, and output a phase error mark signal i.

[0091] The delay controller 213 is used to output a phase detection enable mark o to the digital phase detector 212 , and output a delay compensation value signal j to the delay compensation module 206 .

[0092] In addition, the delay controller 213 is also used to wait for the lock mark signal k output by the second frequency synthesizer 211 to be pulled high each time after changing the delay compensation value signal j in the signal link, and then pull high the phase detection enable mark signal o.

[0093] In this embodiment, the proposed waveform synchronization method and device first generate a dot frequency signal with the same and synchronous frequency as the low-frequency reference clock after the system is turned on, and then feedback is returned in the form of a clock after passing through the signal link to perform digital phase identification with the low-speed reference clock. By adjusting the signal link delay, the feedback clock is aligned with the reference clock phase, thereby achieving the certainty of the signal link delay. At the same time, since the low-speed reference clock is obtained by multiplying the external reference clock, the generated waveform is synchronized with the external reference clock shared by each channel. By adopting this idea similar to a phase-locked loop, the problem of uncertain delay and asynchronism between channels between DAC and FPGA interface can be solved without using ADC to collect feedback waveforms and perform complex correction calculations, which significantly reduces the hardware complexity and cost of the system, and the system software resource overhead is small, the digital phase identification speed is fast, and the calibration speed is fast. In addition to modules such as the reference clock source, DAC, analog switch, and low-pass filter in the system, other functional units are easy to implement in FPGA or a dedicated integrated circuit, and have strong versatility. At the same time, by applying the embodiment of the present invention, the accuracy of delay calibration mainly depends on the setup and hold time of the D flip-flop, and a very high accuracy can be achieved.

[0094] This embodiment also provides a synchronous waveform generating device, including the above-mentioned waveform synchronization device. After the calibration is completed, the input signal selector and the output signal analog switch are switched to the normal working path, the digital working waveform signal m enters the signal link, and after delay compensation, clock domain switching, digital-to-analog conversion and other processing, the analog working waveform signal n is finally output, and the system enters the normal working state.

[0095] During specific operation, the input signal selector 205 is used to send the digital working waveform signal m to the delay compensation module 206 after the waveform synchronization is completed; the analog switch 209 is used to output the analog signal r as the analog working waveform signal n after the waveform synchronization is completed.

[0096] The following describes in detail the waveform synchronization and the synchronous waveform generation process of this embodiment through an example of a synchronous waveform generation method.

[0097] Reference Figure 1 , a synchronization waveform generation method proposed in this embodiment includes:

[0098] S101: Send a reference clock signal a to a first frequency synthesizer, and the first frequency synthesizer outputs a reference clock signal b, a system clock signal c, and a DAC conversion clock signal d.

[0099] Specifically, the reference clock signal b and the system clock signal c are square waves, the frequency of the reference clock signal b is an integer multiple of the frequency of the reference clock signal a, the frequency of the system clock signal c is an integer multiple of the frequency of the reference clock signal b, and the frequency of the DAC conversion clock signal d is an integer multiple of the frequency of the system clock signal c; the initial phase difference between the clock signals b, c and d and the reference clock signal a is a fixed value.

[0100] In the embodiment of the present invention, the frequencies of the reference clock signal a, the base clock signal b, the system clock signal c and the DAC conversion clock signal d are 20 MHz, 20 MHz, 120 MHz and 480 MHz respectively.

[0101] S102: Switch the input signal selector and the output signal analog switch to the calibration signal path.

[0102] Specifically, the input signal selector selects to send the single-point frequency digital calibration signal f generated by the calibration signal generation module to the delay compensation module, and the analog switch selects to output the analog signal r output by the DAC to the low-pass filter.

[0103] S103: Generate a synchronization signal e that is synchronized with the reference clock signal b, and under the control of the synchronization signal e, generate a single-point frequency digital calibration signal f with the same frequency as the reference clock signal b in the system clock domain;

[0104] Exemplarily, the synchronization signal e may be a single-cycle pulse signal generated using the reference clock signal b, and is used to reset the calibration signal generating module. The working clock signal of the calibration signal generating module is the system clock signal c, and a single-point frequency digital calibration signal f having the same frequency as the reference clock signal b and a fixed phase relationship is generated in the system clock domain.

[0105] The single-point frequency digital calibration signal f can be a real-point frequency signal:

[0106]

[0107] Among them, S f (n) is the single digital calibration signal f; f0 is the analog frequency, f dac is the DAC conversion frequency, n is an integer between [0, +∞), is the initial phase.

[0108] In this embodiment, the analog frequency f0 of the single-point frequency digital calibration signal f is 20 MHz, and the DAC conversion frequency f dac =480Msps, initial phase

[0109] S104: the single-point frequency digital calibration signal f is sent to the DAC for digital-to-analog conversion after clock domain switching is completed in the buffer, and finally the image signal is filtered out by a low-pass filter to obtain the single-point frequency analog calibration signal g;

[0110] Exemplarily, the buffer write-side clock is the system clock signal c, and the read-side clock can be the associated clock of the DAC.

[0111] S105: the single-point frequency analog calibration signal g is sent to the second frequency synthesizer, and then the second frequency synthesizer outputs a feedback clock signal h with the same frequency as the reference clock signal b;

[0112] Specifically, the feedback clock signal h is a square wave, and the phase difference between the feedback clock signal h and the single-point frequency analog calibration signal g is a fixed value.

[0113] S106: Adjust the initial phase of the single-point frequency digital calibration signal f to align the phases of the reference clock signal b and the feedback clock signal h, and record the initial phase value of the single-point frequency digital calibration signal f at this time. System power failure;

[0114] Specifically, the phase alignment standard of the reference clock b and the feedback clock h is that the phase difference between the two is less than Among them, f base is the frequency of the reference clock signal b, f dac It is the frequency of the DAC conversion clock signal d. Use an oscilloscope to observe whether the phase is aligned, or observe whether the phase error marker signal i is pulled high to determine whether the phase is aligned.

[0115] In the embodiment of the present invention, the phase difference between the reference clock signal b and the feedback clock signal h is less than In fact, the smaller the phase difference, the better. For example, adjust the initial phase of the single-point frequency digital calibration signal f so that the phase difference between the reference clock signal b and the feedback clock signal h is less than Record the initial phase value of the single-point frequency digital calibration signal f at this time

[0116] S107: Each time the system is powered on, steps 1 to 5 are repeated, wherein in step 3, the initial phase of the single-point frequency digital calibration signal f is set to:

[0117]

[0118] in, is the initial phase of the single-point frequency digital calibration signal f after each system power-on, N is greater than or equal to 5 and less than Odd number, f base is the frequency of the reference clock signal b, f dac is the frequency of the DAC conversion clock signal d;

[0119] In the embodiment of the present invention, in S103, N is set to 5, and the initial phase of the single-point frequency digital calibration signal f is set to

[0120] S108: Send the reference clock signal b generated by S101 and the feedback clock signal h generated by S104 to a digital phase detector for phase detection, and output a phase error mark signal i. When pulled high, it indicates that the two clock signals are phase-aligned;

[0121] Specifically, the digital phase detector is allowed to perform phase detection only after the phase detection enable flag signal o is pulled high.

[0122] S109: Check whether the phase error mark signal i has been pulled high. If not, increase the delay compensation value signal j in the signal link by 1 (the initial value is 0, and the unit is one DAC conversion clock cycle), and then recheck the phase error mark signal i. Repeat this step until it is detected that the phase error mark signal i has been pulled high, and the calibration is completed.

[0123] Specifically, each time the delay compensation value signal j in the signal link is changed, it is necessary to wait for the clock lock mark signal k output by the second frequency synthesizer to be pulled high, and then send out the phase detection enable mark signal o to allow the digital phase detector to perform phase detection.

[0124] S110: Switch the input signal selector and the output signal analog switch to the normal working path, the digital working waveform signal m enters the signal chain, and after delay compensation, clock domain switching, digital-to-analog conversion and other processing, the analog working waveform signal n is finally output, and the system enters the normal working state.

[0125] Specifically, the input signal selector selects to send the digital working waveform signal m to the delay compensation module, and the analog switch selects to output the analog signal r output by the DAC as the analog working waveform signal n.

[0126] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A waveform synchronization method, characterized in that: The following steps are involved: S1, sending a reference clock signal a to a first frequency synthesizer (202), outputting a reference clock signal b, a system clock signal c and a DAC conversion clock signal d; S2, switching the input signal selector (205) and the output signal analog switch (209) to the calibration signal path; S3, generating a synchronization signal e synchronized with the reference clock signal b, and generating a single-point frequency digital calibration signal f having the same frequency as the reference clock signal b in the system clock domain according to the synchronization signal e; S4, after the single-point frequency digital calibration signal f is switched in the clock domain by the buffer (207), it is sent to the DAC (208) for digital-to-analog conversion, and finally the image signal is filtered out by the low-pass filter (210) to obtain the single-point frequency analog calibration signal g; S5, sending the single-point frequency analog calibration signal g to the second frequency synthesizer (211), and outputting a feedback clock signal h having the same frequency as the reference clock b; S6. Adjust the initial phase of the single-point frequency digital calibration signal f to align the phases of the reference clock signal b and the feedback clock signal h, and record the initial phase value of the single-point frequency digital calibration signal f. S7. Each time the system is powered on, S1-S5 are repeated; wherein the initial phase of the single-point frequency digital calibration signal f in S3 is set to: in, is the initial phase of the single-point frequency digital calibration signal f after each system power-on, N is a positive odd number and N>3, f base is the frequency of the reference clock signal b, f dac is the frequency of the DAC conversion clock signal d; S8, sending the reference clock signal b and the feedback clock signal h generated in S7 to the digital phase detector (212) for phase detection, and outputting a phase error mark signal i; S9: Check whether the phase error marker signal i has been pulled high; if so, the calibration is completed; if not, increase the delay compensation value signal j in the signal link by one DAC conversion clock cycle, and then recheck the phase error marker signal i until it is detected that the phase error marker signal i has been pulled high.

2. The waveform synchronization method according to claim 1, characterized in that: In S7, 3. The waveform synchronization method according to claim 1, characterized in that: The reference clock signal b in S1, the system clock signal c, and the feedback clock signal h in S5 are all square waves; The frequency of the reference clock signal b is an integer multiple of the frequency of the reference clock signal a, the frequency of the system clock signal c is an integer multiple of the frequency of the reference clock signal b, and the frequency of the DAC conversion clock signal d is an integer multiple of the frequency of the system clock signal c.

4. The waveform synchronization method according to claim 1, characterized in that: In S1, the initial phase differences between the reference clock signal b, the system clock signal c, and the DAC conversion clock signal d and the reference clock signal a are fixed values; In S5, the phase difference between the feedback clock signal h and the single-point frequency analog calibration signal g is a fixed value.

5. The waveform synchronization method according to claim 1, characterized in that: In S6, the phase alignment is specifically that the phase difference between the reference clock signal b and the feedback clock signal h is less than 6. The waveform synchronization method according to claim 1, characterized in that: In S9, each time the delay compensation value signal j in the signal link is changed, the clock lock mark signal k output by the second frequency synthesizer (211) is waited to be pulled high, and then a phase detection enable mark signal o is issued to allow the digital phase detector (212) to perform phase detection.

7. A waveform synchronization device, used to implement the waveform synchronization method according to any one of claims 1 to 6, characterized in that: include: A reference clock source (201), a first frequency synthesizer (202), a synchronization signal generating module (203), a calibration signal generating module (204), an input signal selector (205), a delay compensation module (206), a buffer (207), a DAC (208), an analog switch (209), a low-pass filter (210), a second frequency synthesizer (211), a digital phase detector (212), and a delay controller (213); The reference clock source (201) is used to output a reference clock signal a to a first frequency synthesizer (202); The first frequency synthesizer (202) is used to output a reference clock signal b to a synchronization signal generating module (203) and a digital phase detector (212), output a system clock signal c to a calibration signal generating module (204), and output a DAC conversion clock signal d to a DAC (208); The synchronization signal generating module (203) is used to output a synchronization signal e synchronized with the reference clock b to the calibration signal generating module (204); The calibration signal generating module (204) is used to generate a single-point frequency digital calibration signal f having the same frequency as the reference clock signal b in the system clock domain according to the synchronization signal e, and send the signal to the input signal selector (205); The input signal selector (205) is used to send the single-point frequency digital calibration signal f to the delay compensation module (206); The delay compensation module (206) is used to delay the single-point frequency digital calibration signal f or the digital working waveform signal m under the control of the delay compensation value signal j, and output the delayed digital signal p to the buffer (207); The buffer (207) is used to switch the delayed digital signal p between the system clock domain and the DAC (208) clock domain to obtain data q and output it to the DAC (208); The DAC (208) is used to perform digital-to-analog conversion on the data q and output an analog signal r to the analog switch (209); The analog switch (209) is used to output the analog signal r to the low-pass filter (210); The low-pass filter (210) is used to filter out the high-frequency image signal in the analog signal r sent by the analog switch (209), and output a single-point frequency analog calibration signal g to the second frequency synthesizer (211); The second frequency synthesizer (211) is used for outputting a feedback clock signal h having the same frequency as the reference clock signal b and a fixed phase relationship with the single-point frequency analog calibration signal g to the digital phase detector (212) based on the single-point frequency analog calibration signal g, and outputting a clock lock mark signal k to the delay controller (213); The digital phase detector (212) is used to detect whether the phases of the feedback clock signal h and the reference clock signal b are aligned, and output a phase error mark signal i to the delay controller (213); The delay controller (213) is used to output a phase detection enable mark o to the digital phase detector (212), and output a delay compensation value signal j to the delay compensation module (206).

8. The waveform synchronization device according to claim 7, characterized in that: The digital phase detector (212) comprises: a first D flip-flop (212a), a second D flip-flop (212b) and an XOR gate (212c); The first D flip-flop (212a) is used to sample the feedback clock signal h according to the beat of the reference clock signal b, and output the signal s to the second D flip-flop (212b) and the XOR gate (212c) when the phase detection enable flag o is pulled high; The second D flip-flop (212b) is used to sample the signal s according to the beat of the reference clock signal b, and output the signal t to the XOR gate (212c); The XOR gate (212c) is used to perform an XOR operation on the signal s and the signal t, and output a phase error mark signal i.

9. The waveform synchronization device according to claim 7, characterized in that: The delay controller (213) is also used to wait for the lock mark signal k output by the second frequency synthesizer (211) to be pulled high each time after the delay compensation value signal j in the signal link is changed, and then pull high the phase detection enable mark signal o.

10. A synchronous waveform generating device, characterized in that: Comprising a waveform synchronization device according to any one of claims 7 to 9; The input signal selector (205) is used to send the digital working waveform signal m to the delay compensation module (206) after the waveform synchronization is completed; The analog switch (209) is used to output the analog signal r as the analog working waveform signal n after the waveform synchronization is completed.

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