motherboard, motherboard system, server, node interconnect fabric, and server system

Abstract

The application discloses a mainboard, a mainboard system, a server, a node interconnection structure and a server system, and relates to the technical field of data transmission. The first connector is located at one end of the mainboard, so that the processor arranged on the mainboard is transmitted by a bus protocol inside the mainboard to the first connector to realize data transmission between the processor and the first connector. The data transmission is directly realized from the inside of the mainboard, without cable wiring, and if the mainboard is used as a second node in the node interconnection structure, the interface space of the processor is also reduced. The first connector is connected with the connector assembly through the plug-in part arranged at one end of the connector assembly, so as to realize plug-in connection between the processor and the connector of the connector assembly, and facilitate subsequent data transmission to other devices. The plug-in part is arranged at one end of the connector assembly, and the plug-in part is connected with the first connector in a plug-in mode, so that the connector assembly can be replaced through the plug-in mode without disassembling the whole mainboard, and the operation steps are simplified.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a motherboard, motherboard system, server, node interconnection structure, and server system. Background Technology

[0002] In the node interconnection structure, the first node uses male and female connectors to output cables to the second node, which has a server network card equipped with the Open Compute Project (OCP) interface specification, enabling communication between the two nodes. The central processing unit (CPU) within the first node reserves an interface for cable connection with the female connector to achieve data transmission within the node. This results in messy cable routing and a correspondingly higher risk of signal damage. The second node, having the same structure as the first node, does not connect its reserved interface to other interfaces, thus occupying CPU interface space. Furthermore, the male and female connectors of the first node are fixed to the node; if the communication cable between the first and second nodes is damaged or bent, replacing the male and female connectors requires disassembling and replacing the entire first node, making the operation quite complex.

[0003] Therefore, how to save internal space in nodes and simplify the assembly and disassembly of node connector components is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a motherboard, motherboard system, server, node interconnection structure, and server system to solve the problems of large interface space occupied by the reserved interface of the node processor and the complex disassembly and assembly of the connector components.

[0005] To solve the above-mentioned technical problems, the present invention provides a motherboard, including a processor and a first connector;

[0006] The processor is mounted on the motherboard, and the first connector is located at one end of the motherboard for receiving data from the processor transmitted by the bus protocol inside the motherboard.

[0007] The first connector is connected to the connector assembly via a plug-in component disposed at one end of the connector assembly to realize data transmission between the processor and the connector of the connector assembly.

[0008] On one hand, the connector assembly includes a second connector and an adapter plate;

[0009] The second connector is directly connected to one end of the adapter plate;

[0010] The other end of the adapter plate is provided with the plug-in component;

[0011] The adapter board is connected to the first connector via the plug-in component.

[0012] On the other hand, the connector assembly includes a third connector;

[0013] The insertion component is provided at one end of the third connector;

[0014] The third connector is connected to the first connector via the plug-in component.

[0015] On the other hand, the first connector is provided with a limiting boss;

[0016] The limiting boss cooperates with the slot of the first connector, and adjacent slots are connected by the limiting boss, for inserting the pin of the plug-in component along a preset path when the pin is inserted into the slot.

[0017] On the other hand, the adapter board is equipped with a reminder device and a first controller;

[0018] The reminder device is connected to the first controller;

[0019] The first controller is used to receive the link bandwidth rate transmitted between the processor and the first connector; when the link bandwidth rate is lower than the preset link bandwidth rate, it generates a reminder instruction and sends it to the reminder device so that the reminder device can provide a work reminder according to the reminder instruction.

[0020] On the other hand, when the number of processors does not exceed the preset number, the processors are transmitted to the first connector through the bus protocol inside the motherboard;

[0021] When the number of processors exceeds a preset number, the slots corresponding to the external pins of the processors are connected to the plug-in components of the connector assembly; wherein the length of the plug-in components is the same as the sum of the lengths of the slots corresponding to the external pins of each processor;

[0022] Correspondingly, the multiple processors are in a master-slave relationship, with the master processor and the slave processor interconnected. The enable signal corresponding to the connection between the slot of the external pin of the master processor and the plug-in part of the connector assembly is valid; the enable signal corresponding to the connection between the slot of the external pin of the slave processor and the plug-in part of the connector assembly is invalid.

[0023] The processor is used to receive information about its own processor's usage of computing resources corresponding to its server.

[0024] If the main processor's computing resource usage exceeds the preset resource usage, the main processor sends a first enable change instruction to the backup processor; so that the backup processor can change the enable signal corresponding to the corresponding slot to be plugged into the plug-in component to be enabled according to the first enable change instruction.

[0025] The main processor generates a second enable change instruction to change the enable signal corresponding to the slot being plugged into the plug-in component to an invalid enable signal, according to the second enable change instruction.

[0026] To address the aforementioned technical problems, the present invention also provides a motherboard system, comprising a plurality of the aforementioned motherboards;

[0027] Multiple motherboards are connected through corresponding connector assemblies to enable data transmission between them.

[0028] To address the aforementioned technical problems, the present invention also provides a server, including the aforementioned motherboard system.

[0029] To address the aforementioned technical problems, the present invention also provides a node interconnection structure, comprising a plurality of the aforementioned servers; wherein the servers include a first server and a second server;

[0030] The first server is equipped with a network card, and an interface for a fourth connector is reserved at the network card;

[0031] The second server connects to the fourth connector of the network card of the first server through its own connector component to achieve interconnection between the first server and the second server.

[0032] On one hand, the server's connector assembly includes a first switch and a second controller;

[0033] The first switch is connected to the second controller;

[0034] The second controller is used to receive the data transmission amount from each second server to the first server; if the data transmission amount is less than a preset transmission amount, it controls the first switch to turn off the data output of the connector component of the corresponding second server.

[0035] To address the aforementioned technical problems, the present invention also provides a server system comprising the aforementioned node interconnection structure.

[0036] The present invention provides a motherboard including a processor and a first connector; the processor is disposed on the motherboard, and the first connector is located at one end of the motherboard for receiving data of the processor transmitted by the bus protocol inside the motherboard; the first connector is connected to the connector assembly through a plug-in component disposed at one end of the connector assembly to realize data transmission between the processor and the connector assembly.

[0037] The beneficial effects of this invention are as follows: Firstly, by utilizing the existing first connector on the motherboard, located at one end of the motherboard, the processor mounted on the motherboard transmits data to the first connector via the motherboard's internal bus protocol, thus realizing data transmission between the processor and the first connector. When used as the first node in a node interconnect structure, it avoids the risk of signal damage caused by messy cable routing when conventional server processors connect to connector components via reserved interfaces. Data transmission is achieved directly from within the motherboard, eliminating the need for cable routing. When used as the second node in a node interconnect structure, it also reduces the interface space required by the processor. Secondly, the first connector connects to the connector assembly via a plug-in component at one end of the connector assembly, enabling a plug-in connection between the processor and the connector assembly's connector, facilitating subsequent data transmission to other devices. Furthermore, compared to the conventional fixed-structure installation method of the first node's connector assembly, the connector assembly of this invention has a plug-in component at one end, enabling a pluggable connection with the first connector. Even if the cable connecting the connector assembly to external devices is damaged and the connector assembly needs replacement, it is not necessary to disassemble the entire motherboard; the connector assembly can be replaced simply by plugging and unplugging, simplifying the operation.

[0038] Secondly, the second connector connects directly to one end of the adapter board, eliminating the need for additional cables or intermediate components, thus reducing signal loss and improving electrical performance. The adapter board connects to the first connector via a plug-in component, supporting the second connector while improving the ease of hot-swapping. The third connector connects to the first connector via a plug-in component, enabling the replacement of the connector assembly's plug-in method. Limiting bosses ensure correct alignment of pins or holes, preventing misalignment that could lead to poor contact or damage. They also prevent the connector assembly from being inserted too deeply, which could damage internal terminals or circuitry. After the connector assembly is fully inserted, they provide additional mechanical support, ensuring connection stability and reliability. Simultaneously, the unique shape or position of the bosses and slots enables polarity identification, preventing reverse insertion. The first controller connects to an alert device, which, by monitoring the link bandwidth rate in real time and comparing the current link bandwidth rate with a preset link bandwidth rate, generates alert commands and promptly notifies users of any abnormal situations, allowing for timely handling of anomalies. During signal switching, the connector assembly is directly connected to each processor. By monitoring the main and backup processors, the enable signal of the corresponding connector changes when the processor switches, thereby improving the accuracy of data switching and the reliability of signal processing.

[0039] In addition, the present invention also provides a motherboard system, a server, a node interconnection structure, and a server system, which have the same beneficial effects as the motherboard described above. Attached Figure Description

[0040] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic diagram of a conventional interconnection structure between upper and lower nodes;

[0042] Figure 2 This is a schematic diagram of a motherboard structure provided in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of another motherboard structure provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of a node interconnection structure provided in an embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0046] The core of this invention is to provide a motherboard, a motherboard system, a server, a node interconnection structure, and a server system to solve the problems of large interface space occupied by the reserved interface of the node's processor and the complex disassembly and assembly of the connector components.

[0047] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] Multi-host OCP network interface cards (NICs), as an innovative network interface card architecture, support network traffic connecting multiple CPU slots without traversing the inter-process bus. They enable direct access via Peripheral Component Interconnect Express (PCIe) connections, optimizing overall network performance and maximum throughput, maximizing network data processing performance, and better meeting the demands of demanding applications and markets. With Multi-host OCP NICs, multiple CPUs in a multi-processor server can directly connect to the network through their respective designated PCIe interfaces. Multi-host OCP NICs provide a highly scalable heterogeneous computing and storage platform, interconnecting multiple computing and storage nodes with a single NIC, reducing the number of switches, NICs, and network cables, while balancing high performance with low power consumption.

[0049] Figure 1 This is a schematic diagram of a conventional interconnection structure between upper and lower nodes, such as... Figure 1 As shown, the processor 1 in the upper node is located on the server motherboard 2 of the upper node, with a reserved interface (Mini Cool Edge IO (MCIO) interface 3) that connects to the interface of the female connector 4 of the connector assembly. This allows the processor 1 to connect to the female connector 4, facilitating connection to the network card 6 of the lower node via the subsequent male connector 5, thus enabling interconnection with the outside world. The reserved interface of the processor 1 in the upper node connects to the interface of the female connector 4 via cable, which poses a risk of signal interference and damage during cable routing. Furthermore, the female connector 4 is fixed to the upper node using a fixed structural component, meaning that if the cable is damaged during interconnection and the female connector 4 needs to be replaced, the entire upper node needs to be disassembled, resulting in cumbersome operations. The server provided by this invention can solve the above problems.

[0050] Figure 2 This is a schematic diagram of a motherboard structure provided in an embodiment of the present invention, such as... Figure 2 As shown, it includes a processor 1 and a first connector 7;

[0051] A processor 1 is mounted on the motherboard 2, and a first connector 7 is located at one end of the motherboard 2 for receiving data from the processor 1 transmitted by the bus protocol inside the motherboard 2.

[0052] The first connector 7 is connected to the connector assembly 10 via a plug-in component 9 located at one end of the connector assembly 10, thereby enabling data transmission between the processor 1 and the connector of the connector assembly 10. Specifically, the motherboard in this embodiment can be a server motherboard or the motherboard of other hardware devices; there is no limitation here, and it can be set according to the actual situation.

[0053] The first connector, located on the motherboard, is an existing connector on the motherboard in this embodiment. It is not used in conventional node interconnection structures and is a connector that has always been present on the motherboard. This embodiment does not limit the type of the first connector; it can be an OCP connector or other connectors.

[0054] The OCP connector on the motherboard is primarily used for efficient interconnection between data centers and servers. The first connector is located at one end of the motherboard. It should be noted that the first connector is fixed to the motherboard; this fixing method can be soldering or other methods, used to achieve electrical and mechanical connections. The first connector is used to receive processor data transmitted via the motherboard's internal bus protocol. This replaces the original method of connecting processor data via interface cables with a method of transmission via the motherboard's internal bus protocol. The bus protocol can be a PCIe bus connection or another bus protocol; there are no restrictions as long as it is an internal motherboard connection. Internal motherboard transmission achieves higher data transfer rates. Due to the shorter distance, internal data transmission has lower signal latency, reducing the complexity of external cables and improving the interference resistance of complex data cable routing.

[0055] The connector assembly in this embodiment can be a part of the motherboard or a device attached to the motherboard but isolated from it; there is no limitation here.

[0056] The term "connector assembly" can refer specifically to a connector or is a general term encompassing both connectors and adapters. It should be noted that the adapter, in addition to ensuring compatibility between different protocols, also provides support for the corresponding connector, facilitating the insertion and removal of the connector assembly. The type of connector used in this embodiment is not limited; it can be the same as or different from the first connector.

[0057] One end of the connector assembly has a mating component, and the other end connects to other servers or devices to achieve interconnection. This mating component can be a gold finger array, designed for good electrical contact, essentially providing a pluggable electrical connection, and located at the edge of the connector assembly. Alternatively, it can use a plug and socket type such as an RJ45 interface, or other methods such as direct-insertion connectors, crimping, or threaded connections. There are no limitations here, as long as the mating method between the connector assembly and the first connector is achieved.

[0058] The connector assembly connects to the first connector via a plug-in component, thereby transmitting data from the first connector to other servers or transmitting data from other servers to the processor for further processing. Compared to conventional cable transmission, the data transmission path formed between the processor, the first connector, and the connector assembly in this embodiment improves the anti-interference capability of data transmission. Furthermore, the plug-in connection of the connector assembly avoids the complex operation of replacing the connector assembly due to damage to cables from other servers, and the plug-and-play method enhances ease of operation.

[0059] This invention provides a motherboard including a processor and a first connector. The processor is mounted on the motherboard, and the first connector is located at one end of the motherboard for receiving data transmitted by the processor via an internal bus protocol. The first connector connects to a connector assembly via a plug-in component at one end of the connector assembly, enabling data transmission between the processor and the connector assembly. On one hand, utilizing the existing first connector on the motherboard, located at one end, allows the processor mounted on the motherboard to transmit data to the first connector via the internal bus protocol, thus achieving data transmission between the processor and the first connector. If used as the first node in a node interconnect structure, this avoids the risk of signal damage caused by messy cable routing when conventional server processors connect to the connector assembly via reserved interfaces, as data transmission is achieved directly from within the motherboard, eliminating the need for cable routing. If used as the second node in a node interconnect structure, it also reduces the interface space required by the processor. On the other hand, the first connector connects to the connector assembly via a plug-in component at one end of the connector assembly, enabling a plug-in connection between the processor and the connector assembly, facilitating subsequent data transmission to other devices. In addition, compared with the conventional connector assembly of the first node which adopts a fixed structural component installation method, the connector assembly of the present invention is provided with a plug-in component at one end, which realizes a pluggable connection with the first connector. Even if the cable connecting the connector assembly to the external device is damaged and the connector assembly is replaced, it is not necessary to disassemble the entire motherboard. The connector assembly can be replaced simply by plugging and unplugging, simplifying the operation steps.

[0060] In some embodiments, the connector assembly includes a second connector and an adapter plate;

[0061] The second connector is directly connected to one end of the adapter board;

[0062] The other end of the adapter board is equipped with a plug-in component;

[0063] The adapter board is connected to the first connector via a plug-in component.

[0064] Specifically, the second connector in this embodiment can be the same type as or different from the first connector; no limitation is made here. The adapter plate supports the second connector, enabling it to connect to the first connector via a plug-in method, making plugging and unplugging more convenient. Since the interface size of the second connector is small, this embodiment uses an adapter plate as a supporting component. Furthermore, the second connector is directly connected to one end of the adapter plate. This direct connection can be achieved through soldering, where the pins or terminals of the second connector are directly soldered to pads on the adapter plate. It can also be a surface mount method, where the pins of the second connector are mounted onto pads on the adapter plate. Alternatively, it can be a through-hole method, where the pins of the second connector pass through holes in the adapter plate and are soldered from the back of the adapter plate. Mechanical fixing is also an option. No limitation is made here.

[0065] The second connector provided in this embodiment is directly connected to one end of the adapter board, eliminating the need for additional cables or intermediate components, thereby reducing signal loss and improving electrical performance. The adapter board is connected to the first connector via a plug-in component, supporting the second connector while improving the convenience of hot-swapping.

[0066] In other embodiments, Figure 3 This is a schematic diagram of another motherboard structure provided in an embodiment of the present invention, such as... Figure 3 As shown, connector assembly 10 includes a third connector 11;

[0067] One end of the third connector 11 is provided with a plug-in component 9;

[0068] The third connector 11 is connected to the first connector 7 via the plug-in component 9.

[0069] Specifically, the connector assembly in this embodiment includes only a third connector, which can be a male connector and a female connector. The first end of the female connector connects to the male connector, and the second end of the female connector is provided with a plug-in component for direct plug-in connection with the first connector. The third connector can also be other connectors, which are not limited here.

[0070] The male connector's contact conductors are needle-shaped and protrude, while the female connector's contact conductors are hole-shaped and recessed. In connectors for electronic devices, the circuit's output end typically has a plug, i.e., a male connector, while the circuit's input end has a socket, i.e., a female connector. The second end of the female connector has a mating component that connects the auxiliary first connector to the female connector.

[0071] In this embodiment, the third connector is connected to the first connector via a plug-in component, thereby enabling the replacement of the plug-in / plug-out method of the connector assembly.

[0072] In some embodiments, the first connector is provided with a slot; wherein, the sidewall of the slot is provided with multiple rows of terminal modules; each row of terminal modules includes multiple terminals;

[0073] The connector assembly is connected to multiple terminals of the first connector via a mating component.

[0074] Specifically, when the plug-in component is an array of gold fingers, the gold fingers are golden conductive contacts, and their surfaces can be gold-plated to improve conductivity and wear resistance. During the connection process, the connector assembly needs to be inserted into the slot of the first connector, so that the gold fingers of the connector assembly contact the terminals of the first connector to achieve electrical connection. The first connector includes bumps or notches for polarity. To ensure correct polarity connection, anti-reverse features are provided on the bumps or notches to ensure correct gold finger insertion and avoid incorrect connection direction. The sidewall of the slot of the first connector is provided with multiple rows of terminal modules. The terminal modules include multiple terminals, which are usually elastic metal strips, fixed together by injection molding to form multiple rows of terminal modules. The contact surfaces of the elastic contact parts on the terminals that contact the gold fingers can be gold-plated to improve contact reliability. The edges of the plug-in component can be beveled to ensure correct connection. The beveling always occurs at the edges of the gold fingers to ensure successful connection with the device.

[0075] In addition, the width and length of the gold fingers are determined according to the specific standard settings of the first connector and are not limited here.

[0076] The terminal arrangement in the slot of the first connector provided in this embodiment allows the connector assembly to contact and connect with multiple terminals through a plug-in component, thereby realizing the electrical connection between the connector assembly and the first connector, and also enabling the connector assembly to be plugged in and removed.

[0077] In some embodiments, the first connector is provided with a limiting boss;

[0078] The limiting boss cooperates with the slot of the first connector, and adjacent slots are connected by the limiting boss, which is used to insert the pin of the plug-in component along a preset path when the pin is inserted into the slot.

[0079] Specifically, the limiting boss is a mechanical structure used to ensure that the connector assembly to which the plug-in component belongs is correctly inserted and positioned in the first connector. The limiting boss works in conjunction with the slot, and there is a limiting boss between every two slots. That is, the two slots are connected by the limiting boss, so that the pins of the plug-in component are inserted into the slot according to a preset path.

[0080] The limiting boss provided in this embodiment ensures correct alignment of pins or holes, preventing errors that could lead to poor contact or damage. It also prevents the connector assembly from being inserted too deeply, which could damage internal terminals or circuitry. After the connector assembly is fully inserted, it provides additional mechanical support, ensuring a stable and reliable connection. Furthermore, the unique shape or position of the boss and slot enables polarity identification, preventing reverse insertion.

[0081] In some embodiments, the limiting boss includes a first limiting boss and a second limiting boss;

[0082] The first limiting boss is engaged with the slot of the first connector, located at one end of the slot of the first connector, and adjacent slots are separated by the first limiting boss;

[0083] The second limiting boss is provided along the length of the slot of the first connector and is used to lock after the pins of the plug-in component are fully inserted into the slot.

[0084] Specifically, it includes a first limiting boss and a second limiting boss. The first limiting boss is located at one end of the first connector and is connected to a slot. Adjacent slots are separated by the first limiting boss, which provides a barrier in the initial stage of the connector assembly insertion process to prevent the connector assembly from being inserted too early or at the wrong angle.

[0085] The second limiting boss can be located at the other end of the first connector or distributed along the length of the first connector. Its function is to provide additional positioning and locking after the plugging part of the connector assembly is fully inserted, which can prevent the connector assembly from accidentally falling off due to vibration or external force during use.

[0086] In this embodiment, the first and second limiting bosses are precisely matched with the internal structure of the slot of the first connector to ensure that the connector assembly can be smoothly inserted and correctly positioned, thereby improving reliability and stability.

[0087] In some embodiments, a reminder device and a first controller are provided on the adapter board;

[0088] The reminder device is connected to the first controller;

[0089] The first controller is used to receive the link bandwidth rate transmitted to the processor by the first connector; when the link bandwidth rate is lower than the preset link bandwidth rate, it generates an alert instruction and sends it to the alert device so that the alert device can provide a work reminder according to the alert instruction.

[0090] Specifically, the adapter board is equipped with an alert device and a first controller. The first controller is used to receive the link bandwidth rate monitoring between the corresponding processor on the motherboard and the first connector. When the link bandwidth rate is lower than the preset link bandwidth rate, since data transmission is carried out inside the motherboard, the corresponding internal transmission status cannot be directly viewed. Therefore, it is necessary to generate an alert instruction for the abnormal situation where the current link bandwidth rate is lower than the preset link bandwidth rate, and the alert device will issue an alert.

[0091] It should be noted that the specific type and shape of the reminder device in this embodiment are not limited. It can be a light-emitting diode to display in response to reminder commands, such as turning red to remind. Other reminder devices can also be used, or it can be connected to the control platform of the interactive interface to display in real time on the screen. There are no limitations here.

[0092] The first controller provided in this embodiment is connected to the reminder device. By monitoring the link bandwidth rate in real time, it generates a reminder command based on the comparison between the current link bandwidth rate and the preset link bandwidth rate, and promptly reminds users of the current abnormal situation so that users can handle the abnormality in a timely manner.

[0093] In some embodiments, when the number of processors does not exceed a preset number, the processors are transmitted to the first connector via the bus protocol inside the motherboard;

[0094] When the number of processors exceeds the preset number, the slots corresponding to the external pins of the processors are connected to the plug-in parts of the connector assembly; wherein, the length of the plug-in parts is the same as the sum of the lengths of the slots corresponding to the external pins of each processor;

[0095] Correspondingly, multiple processors are in a master-slave relationship, with the master processor and the slave processor interconnected. The enable signal corresponding to the connection between the slot of the external pin of the master processor and the plug-in part of the connector assembly is valid; the enable signal corresponding to the connection between the slot of the external pin of the slave processor and the plug-in part of the connector assembly is invalid.

[0096] The processor is used to receive information about its own processor's usage of computing resources on the server.

[0097] If the main processor's computing resource usage exceeds the preset resource usage, the main processor sends a first enable change instruction to the backup processor; so that the backup processor can change the enable signal of the corresponding slot to the corresponding plug-in component to be enabled according to the first enable change instruction.

[0098] The main processor generates a second enable change instruction to change the enable signal of the corresponding slot to be plugged into the plug-in component to be invalid.

[0099] Specifically, considering that a server may contain not only one processor but also multiple processors, when the number of processors is limited, i.e., the number of processors does not exceed the preset number, the processors transmit to the first connector through the bus protocol inside the motherboard, and transmit directly through the internal communication of the motherboard.

[0100] If the number of processors exceeds a preset number, to avoid confusion in the bus protocol transmission within the motherboard, this embodiment directly connects the slots corresponding to the external pins of the processors to the connector, preventing signal interruptions during data transmission. The length of the connector is the same as the sum of the lengths of the slots corresponding to the external pins of each processor, ensuring that all processor slots can be fully inserted into the connector.

[0101] Within the motherboard, the processors have a primary / backup relationship. By default, the primary processor handles the server's computational resources, while the backup processor remains idle. The primary and backup processors are connected. When the primary processor's computational resources are heavily utilized, the backup processor will handle subsequent signal processing. At this point, signal switching between the primary and backup processors is required. Although the primary and backup processors are connected via connectors, to emphasize that the backup processor does not switch signals when idle, the primary and backup processors are interconnected. For the primary processor, the enable signal corresponding to the slot of its external pin and the connector assembly's plug-in component is active; for the backup processor, the enable signal corresponding to the slot of its external pin and the connector assembly's plug-in component is inactive.

[0102] Signal switching only occurs when the main processor's computing resource usage exceeds the preset limit. The standby processor then performs subsequent computation and signal transmission. The switching process involves the main processor sending a first enable change instruction to the standby processor. The standby processor, upon receiving this instruction, changes its corresponding enable signal to a valid one. At this point, the main processor should be idle and needs to generate a second enable change instruction to invalidate its own enable signal.

[0103] In the signal switching process provided in this embodiment, the connector assembly is directly connected to each processor through a plug-in component. By monitoring the main and backup processors, the enable signal of the corresponding connector changes when the processor switches, thereby improving the accuracy of data switching and the reliability of signal processing.

[0104] Furthermore, the present invention also provides a motherboard system comprising multiple motherboards;

[0105] Multiple motherboards are connected through corresponding connector assemblies to enable data transmission between them.

[0106] It should be noted that multiple motherboards can refer to multiple motherboards within a single server node, enabling connections between motherboards; or they can refer to a single motherboard within a single server node, enabling connections between motherboards across multiple servers.

[0107] The connection relationships differ depending on the application scenario. In a single server with multiple motherboards, each motherboard corresponds to a single connector assembly, enabling data transmission between the motherboards within the same node. To connect to motherboards within other nodes, an additional connector assembly needs to be configured within the same server. This additional connector assembly connects the existing connector assemblies for the multiple motherboards, facilitating data transmission between the motherboards of other nodes.

[0108] A server contains multiple motherboards, each with its own connector assembly. To enable data transfer between these motherboards within a single node, the connector assemblies of each motherboard are connected. To enable data transfer between motherboards in other nodes, an additional connector assembly is required within the server. The connector assemblies of each motherboard are then connected to this additional connector assembly, thus enabling data transfer between motherboards in other nodes.

[0109] One motherboard corresponds to one server. To achieve data transmission between motherboards of multiple servers, each motherboard is connected to the corresponding connector assembly.

[0110] For a description of the motherboard system provided by this invention, please refer to the above method embodiments. This invention will not be repeated here, but it has the same beneficial effects as the aforementioned motherboard. Furthermore, this invention also provides a node interconnection structure. Figure 4 This is a schematic diagram of a node interconnection structure provided in an embodiment of the present invention, as shown below. Figure 4 As shown, server 8 includes a first server 14 and a second server 13;

[0111] The first server 14 is equipped with network card 6, and an interface for the fourth connector 12 is reserved at the network card;

[0112] The second server 13 connects to the fourth connector 12 of the network card 6 of the first server 14 via its own connector assembly 10 to achieve interconnection between the first server 14 and the second server 13.

[0113] Specifically, the server of this invention can be used as an upper node or a lower node in an interconnected structure, without limitation. Furthermore, besides applications in interconnected structures, it can also be used as a standalone server, without limitation, and can be handled according to actual circumstances, as long as the aforementioned problems are solved.

[0114] Furthermore, the node interconnection structure of this invention can be a top-bottom node interconnection structure, a left-right node interconnection structure, or a vertical node interconnection structure. The servers corresponding to the top-bottom and left-right node interconnection structures are arranged in the same plane. The vertical node interconnection structure exists in a three-dimensional space, with servers stacked, or in a matrix arrangement based on the corresponding stacking method. Regardless of the node interconnection structure, the number of servers is not limited. For each node interconnection structure, there is one first server and at least one second server.

[0115] For current scenarios involving the management and scheduling of multiple hosts and multiple processors, multiple hosts are connected to a centralized control system. One server acts as a central control node, responsible for managing and controlling all hosts. The specific steps are achieved by setting up network cards internally to enable sharing among multiple servers. One of the servers has a reserved interface for a fourth connector on its network card. This fourth connector can be the same as or different from the first, second, and third connectors mentioned in the above embodiments, and is not limited here.

[0116] The remaining servers connect to the fourth connector of one of the servers' network cards via their respective connector components, thereby enabling interconnection between multiple servers and sharing the network card.

[0117] The settings for the fourth connector correspond to the interface of the fourth connector added under different bandwidth conditions.

[0118] The shared resource establishment process in this embodiment facilitates the dynamic allocation of network interface card (NIC) resources based on the remaining resource utilization of multiple servers. It also includes centralized processing via data loopback and fault-tolerant switching.

[0119] The node interconnection structure provided in this embodiment enables the connection between multiple servers to share a single network card, based on solving the interface space of the processors inside each server and the plugging and unplugging of connector components.

[0120] In some embodiments, the connector assembly of the server includes a first switch and a second controller;

[0121] The first switch is connected to the second controller;

[0122] The second controller is used to receive the data transmission amount from each second server to the first server; if the data transmission amount is less than the preset transmission amount, it controls the first switch to shut down the data output of the connector component of the corresponding second server.

[0123] Specifically, if the data transmission volume between servers is less than the preset transmission volume, then the data transmission may not be required in the interconnection scenario between servers. In this case, the data output of the connected machine components can be turned off by the first switch, and the operation of the corresponding second server will not be affected.

[0124] The second controller in this embodiment can be of the same type as or different from the first controller in the above embodiment, and can be set according to the actual situation.

[0125] The connector assembly in this embodiment includes a first switch and a second controller. The connection between the first switch and the second controller can be such that when there is no need for interconnection and data sharing between servers, the function can be turned off by the first switch without affecting the internal operation of each second server, thus improving the flexibility and versatility of the system.

[0126] Furthermore, the present invention also provides a server system comprising the above-described node interconnection structure.

[0127] Specifically, the server system connects to a centralized control system through multiple hosts and uses centralized management tools for unified management and scheduling. This control system can be a central control node or a distributed control system, responsible for managing and controlling all hosts and providing a unified interface for administrators to operate and monitor. Each host registers its information with the control plane before joining the multi-host system, including its Internet Protocol Address (IP) address, hardware configuration, and available resources. The control system records this information and assigns a unique identifier to each host. Based on the host's registration information and the administrator's needs, the control system performs resource scheduling and allocation. It can rationally distribute tasks across different hosts based on their performance and load to achieve load balancing and optimal performance. The control system manages communication between hosts to enable them to collaborate and share resources. It can set up virtual networks, provide virtual IP addresses to hosts, and protect host information through network isolation and security measures.

[0128] When a host fails or becomes unavailable, the control plane can detect this and execute appropriate actions. It can reallocate tasks to other healthy hosts to ensure system stability and reliability. In essence, it centrally manages and schedules multiple hosts, allocating resources and scheduling tasks through the control system to improve overall system performance and availability. It is widely used in distributed systems and cloud computing, effectively enhancing resource utilization and system scalability.

[0129] For an introduction to the server system provided by the present invention, please refer to the above method embodiments. The present invention will not be described in detail here, but it has the same beneficial effects as the above node interconnection structure.

[0130] The foregoing has provided a detailed description of a motherboard, motherboard system, server, node interconnection structure, and server system provided by the present invention. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the invention, and these improvements and modifications also fall within the protection scope of the present invention.

[0131] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A motherboard, characterized in that, Includes the processor and the first connector; The processor is mounted on the motherboard, and the first connector is located at one end of the motherboard for receiving data from the processor transmitted by the bus protocol inside the motherboard. When the first connector serves as the first node in the node interconnect structure, data transmission is achieved from inside the motherboard without the need for cable routing. When it serves as the second node in the node interconnect structure, it reduces the interface space of the processor. The first connector is connected to the connector assembly via a plug-in component disposed at one end of the connector assembly to realize data transmission between the processor and the connector of the connector assembly; wherein, the plug-in component at one end of the connector assembly is located at the edge of the connector assembly and is pluggable and detachable connected to the first connector in a plug-in manner; Correspondingly, the connector assembly includes a second connector and an adapter plate; wherein the adapter plate is used to support the second connector; The second connector is directly connected to one end of the adapter plate; The other end of the adapter plate is provided with the plug-in component; The adapter plate is connected to the first connector via the plug-in component; Correspondingly, the first connector is provided with a slot; wherein, the side wall of the slot is provided with multiple rows of terminal modules; each row of terminal modules includes multiple terminals; The connector assembly is connected to multiple terminals of the first connector via a mating component; wherein the first connector includes a protrusion or recess for polarity to ensure proper insertion of the mating component; Correspondingly, the first connector is provided with a limiting boss; The limiting boss cooperates with the slot of the first connector, and adjacent slots are connected by the limiting boss, for inserting the pin of the plug-in component along a preset path when it is inserted into the slot; the limiting boss and the slot cooperate with each other, and there is a limiting boss between every two slots, so that the pin of the plug-in component is inserted into the slot along a preset path. Correspondingly, the limiting boss includes a first limiting boss and a second limiting boss; The first limiting boss is engaged with the slot of the first connector, located at one end of the slot of the first connector, and adjacent slots are separated by the first limiting boss; The second limiting boss is provided along the length of the slot of the first connector and is used to lock after the pins of the plug-in component are fully inserted into the slot; Correspondingly, when the number of processors does not exceed the preset number, the processors are transmitted to the first connector through the bus protocol inside the motherboard; When the number of processors exceeds a preset number, the slots corresponding to the external pins of the processors are connected to the plug-in components of the connector assembly; wherein the length of the plug-in components is the same as the sum of the lengths of the slots corresponding to the external pins of each processor; Correspondingly, the multiple processors are in a master-slave relationship, with the master processor and the slave processor interconnected. The enable signal corresponding to the connection between the slot of the external pin of the master processor and the plug-in part of the connector assembly is valid; the enable signal corresponding to the connection between the slot of the external pin of the slave processor and the plug-in part of the connector assembly is invalid. The processor is used to receive information about its own processor's usage of computing resources corresponding to its server. If the main processor's computing resource usage exceeds the preset resource usage, the main processor sends a first enable change instruction to the backup processor; so that the backup processor can change the enable signal corresponding to the corresponding slot to be plugged into the plug-in component to be enabled according to the first enable change instruction. The main processor generates a second enable change instruction to change the enable signal corresponding to the slot being plugged into the plug-in component to an invalid enable signal, according to the second enable change instruction.

2. The motherboard according to claim 1, characterized in that, The connector assembly includes a third connector; The insertion component is provided at one end of the third connector; The third connector is connected to the first connector via the plug-in component.

3. The motherboard according to claim 1, characterized in that, The adapter board is equipped with a reminder device and a first controller; The reminder device is connected to the first controller; The first controller is used to receive the link bandwidth rate transmitted between the processor and the first connector; when the link bandwidth rate is lower than the preset link bandwidth rate, it generates a reminder instruction and sends it to the reminder device so that the reminder device can provide a work reminder according to the reminder instruction.

4. A motherboard system, characterized in that, Includes the motherboard as described in any one of claims 1 to 3; Multiple motherboards are connected through corresponding connector assemblies to enable data transmission between them.

5. A server, characterized in that, Includes the motherboard system as described in claim 4.

6. A node interconnection structure, characterized in that, The server includes multiple servers as described in claim 5; wherein the server includes a first server and a second server; The first server is equipped with a network card, and an interface for a fourth connector is reserved at the network card; The second server connects to the fourth connector of the network card of the first server through its own connector component to achieve interconnection between the first server and the second server.

7. The node interconnection structure according to claim 6, characterized in that, The server's connector assembly includes a first switch and a second controller; The first switch is connected to the second controller; The second controller is used to receive the data transmission amount from each second server to the first server; if the data transmission amount is less than a preset transmission amount, it controls the first switch to turn off the data output of the connector component of the corresponding second server.

8. A server system, characterized in that, It is composed of the node interconnection structure described in claim 6 or 7.

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