Processing method capable of correcting error CE and computing equipment

Abstract

The invention provides a processing method capable of correcting error CE and computing equipment, and relates to the technical field of computers.The method is applied to a BMC in the computing equipment, and the computing equipment further comprises a processor; the processor comprises a target pin and a plurality of state registers, and when the state registers are in a first state, the state registers are used for indicating that corresponding parts have CE faults; when the state of the at least one state register is a first state, the target pin of the processor is set; the method comprises the following steps: resetting a target pin in response to the situation that the target pin of the processor is set; obtaining the states of a plurality of state registers in the processor, and marking the state register in the first state; setting the marked state register in a second state, and processing the CE fault of the corresponding part according to the obtained state; wherein the second state is used for indicating that the corresponding part has no CE fault. According to the scheme, the missing processing of the CE can be reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a processing method and computing device capable of correcting CE errors. Background Art

[0002] In modern computer systems, such as the Intel Birch Stream platform, the central processing unit (CPU) may generate correctable errors (CE) when performing computing tasks. To ensure stable and reliable operation of the system, these CEs need to be processed. And to reduce the burden on the CPU, the Birch Stream platform transfers part of the CE processing work from the CPU to the baseboard management controller (BMC). However, the current CE processing mechanism is prone to CE leakage during execution. Summary of the invention

[0003] The embodiments of the present application provide a processing method and a computing device for correcting erroneous CE, which can reduce the missed processing of CE.

[0004] In a first aspect, an embodiment of the present application provides a CE processing method, which is applied to a BMC in a computing device, and the computing device also includes a processor; the processor includes a target pin and a plurality of status registers; the method includes: in response to the target pin of the processor being set, resetting the target pin, wherein the set state of the target pin is used to indicate the presence of a CE fault, and the reset state of the target pin is used to indicate the absence of a CE fault; obtaining the states of the plurality of status registers in the processor, and marking the status register when the state of the status register is the first state, wherein the first state indicates that a CE fault has occurred in a component corresponding to the status register; setting the marked status register to a second state, and processing the CE fault of the corresponding component according to the acquired state in the marked status register; wherein the second state is used to indicate that the component corresponding to the status register has no CE fault.

[0005] In the embodiment of the present application, when the status register is in the first state, it is used to indicate that a CE fault has occurred in the corresponding component; when the state of at least one status register is in the first state, the target pin of the processor is set.

[0006] The embodiment of the present application proposes that when the target pin of the processor is set, the target pin can be reset first, and then the state of each status register can be obtained, and after the acquisition is completed, the status register in the first state is set to the second state, and the CE failure of the corresponding component is processed according to the acquired state. On the one hand, the embodiment of the present application enables the target pin to be set in time when a new CE is generated, thereby reducing the missed processing of CE. For example, after the target pin is reset, if a component in the system generates a new CE during the state acquisition process and the new CE causes the state of a status register that has been acquired to change to the first state, the status register can trigger the target pin to be set again, so that the above-mentioned CE processing flow can be entered again, so that the new CE can be detected and processed in time.

[0007] In addition, the present application also proposes that when acquiring the register status, the status registers in the first state can be marked first, so that when the status registers in the first state need to be placed in the second state later, these status registers can be quickly found based on the marks.

[0008] In combination with the above-mentioned first aspect, in certain implementations of the first aspect, the BMC includes a memory, and marking the status register includes: storing address information of the status register whose state is the first state in the memory; and placing the marked status register in the second state includes: acquiring the address information from the memory; and placing the status register whose state is the first state in the second state based on the address information.

[0009] The present application proposes that the status registers can be marked by storing the address information of the status registers in the first state in the memory, so that these status registers can be quickly found based on the address information when the status registers in the first state need to be placed in the second state later.

[0010] In combination with the above first aspect, in some implementations of the first aspect, the BMC includes a listener, and in response to the target pin of the processor being set, before resetting the target pin, the method further includes: monitoring through the listener that the target pin of the processor is set.

[0011] In combination with the above-mentioned first aspect, in certain implementations of the first aspect, after placing the marked status register in the second state, the method further includes: checking whether the target pin of the processor is set; when it is checked that the target pin of the processor is set, performing the CE processing operation again, the CE processing operation includes: in response to the target pin of the processor being set, resetting the target pin; obtaining the status of multiple status registers in the processor, and marking the status register when the status of the status register is the first state; placing the marked status register in the second state, and processing the CE fault of the corresponding component according to the obtained status in the marked status register.

[0012] It should be noted that BMC generally obtains the state of the target pin by polling the listener, which results in a certain delay between the occurrence of CE and CE processing. To this end, the present application proposes that after the marked status register is placed in the second state, it can actively check whether the target pin of the processor is set. If the target pin of the processor is set, it means that a new CE has appeared, and the CE processing operation can be executed again to process the new CE. Compared with the method of triggering the execution of the CE processing operation based on the monitoring result of the listener, the delay of the new CE processing can be reduced.

[0013] In combination with the above-mentioned first aspect, in certain implementations of the first aspect, the BMC includes a timer, and the timer includes a first mode and a second mode. In the first mode, the timer triggers a status acquisition operation on the multiple status registers once every first time period, and in the second mode, the timer triggers a status acquisition operation on the multiple status registers once every second time period, and the first time period is greater than the second time period. The method also includes: in response to the target pin of the processor being set, adjusting the timer to the second mode; based on the second mode, when no status register in the first state is found in n consecutive status acquisition operations, adjusting the timer to the first mode, where n is a positive integer.

[0014] It should be noted that in actual operation, there may be a situation where the state of the status register changes to the first state due to a system failure but does not trigger the target pin to be set, which in turn causes the BMC to be unable to process the existing CE in a timely manner. To avoid the above problem, the present application proposes that a state acquisition operation can be triggered at regular intervals by setting a timer, so as to ensure that the newly generated CE is discovered and processed in a timely manner when the CE processing mechanism is abnormal.

[0015] In addition, the timer proposed in the present application may include a first mode and a second mode. Based on this, under normal circumstances, the timer can be adjusted to the first mode to trigger a status acquisition operation at a long interval; after a fault occurs, the timer is adjusted to the second mode to trigger a status acquisition operation at a short interval, thereby ensuring that the newly generated CE can be discovered and processed in time when the CE processing mechanism is abnormal while reducing resource consumption.

[0016] In combination with the above-mentioned first aspect, in certain implementations of the first aspect, in response to the target pin of the processor being set, adjusting the timer to the second mode includes: in response to the target pin of the processor being set, adjusting the timer to the second mode, and pausing the status acquisition operation of the multiple status registers triggered by the timer; after completing the CE processing, starting the status acquisition operation of the multiple status registers triggered by the timer.

[0017] The present application proposes that when the target pin is set, the timer can be adjusted to the second mode, and the status acquisition operation of multiple status registers based on the timer trigger can be suspended, and after the CE processing is completed, the status acquisition operation of multiple status registers based on the timer trigger can be started again, thereby avoiding the conflict between the status acquisition operation in the CE processing and the status acquisition operation in the timing trigger, and ensuring the stable operation of the system.

[0018] In combination with the first aspect, in some implementations of the first aspect, placing the marked state register in the second state includes: sending a write command to the processor, the write command being used to instruct the processor to write the second state in the marked state register. The second state can be understood as a specific value to be written into the state register.

[0019] In combination with the above-mentioned first aspect, in certain implementations of the first aspect, the computing device also includes a complex programmable logic device CPLD, and relevant registers in the CPLD are used to record the status of the target pin, and the BMC obtains the status of the target pin by polling the relevant registers of the CPLD.

[0020] BMC obtains the state of the target pin by polling the relevant registers of CPLD, which means that BMC sends a query request to CPLD at a predetermined time interval, and at each query, CPLD responds to BMC's request and returns the current state information of the target pin. This application uses polling to enable BMC to continuously obtain the latest state of the target pin within a predetermined time interval.

[0021] In combination with the above-mentioned first aspect, in some implementations of the first aspect, obtaining the status of multiple status registers in the processor includes: obtaining the status of multiple status registers in the processor in sequence.

[0022] In a second aspect, an embodiment of the present application provides a computing device, which includes a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, which are loaded and executed by the processor to enable the computing device to implement any possible method as described in the first aspect above.

[0023] In a third aspect, an embodiment of the present application provides a CE processing device, which is applied to a BMC in a computing device, and the computing device also includes a processor; the processor includes a target pin and multiple status registers, and when the status register is in a first state, it is used to indicate that a CE fault has occurred in the corresponding component; when the state of at least one status register is in the first state, the target pin of the processor is set; the device includes: a reset module, in response to the target pin of the processor being set, for resetting the target pin, wherein the set state of the target pin is used to indicate the presence of a CE fault, and the reset state of the target pin is used to indicate that there is no CE fault; an acquisition and marking module, for acquiring the states of multiple status registers in the processor, and marking the status register when the state of the status register is in the first state; a processing module, for setting the marked status register to a second state, and processing the CE fault of the corresponding component according to the acquired state in the marked status register; wherein the second state is used to indicate that the corresponding component has no CE fault.

[0024] In a fourth aspect, an embodiment of the present application provides a computing device, which includes a processor and a BMC, wherein the processor includes a target pin and multiple status registers, and when the status register is in a first state, it is used to indicate that a CE failure has occurred in the corresponding component; when the state of at least one status register is the first state, the target pin of the processor is set; and the BMC is used to execute any possible method of the above-mentioned first aspect when the target pin of the processor is set.

[0025] In combination with the fourth aspect above, in some implementations of the fourth aspect, the processor includes a CPU.

[0026] In combination with the fourth aspect, in certain implementations of the fourth aspect, the plurality of status registers include status registers in a storage area bank and / or an integrated error handler (IEH).

[0027] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores instructions. When the computer-readable storage medium is run on a computer, it enables the computer to execute any possible method of the first aspect above.

[0028] In a sixth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any possible method of the first aspect described above.

[0029] The technical effects obtained in the above-mentioned second to sixth aspects are similar to the technical effects obtained by the corresponding technical means in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic diagram of a computing device provided in an embodiment of the present application;

[0031] Figure 2 It is a flow chart of a CE processing method provided in an embodiment of the present application;

[0032] Figure 3 It is a flow chart of a CE processing situation provided in an embodiment of the present application;

[0033] Figure 4 It is a flow chart of another CE processing situation provided in an embodiment of the present application;

[0034] Figure 5 It is a schematic diagram of a timing mechanism provided in an embodiment of the present application;

[0035] Figure 6 It is a structural schematic diagram of a CE processing device provided in an embodiment of the present application;

[0036] Figure 7 It is a schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first chip and the second chip are only used to distinguish different chips, and their order is not limited. Those skilled in the art can understand that the words "first" and "second" do not limit the quantity and execution order, and the words "first" and "second" do not necessarily limit them to be different.

[0038] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0039] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0040] The present application scheme is described in detail below with reference to the accompanying drawings.

[0041] Figure 1 is a schematic diagram of a computing device provided in an embodiment of the present application. Figure 1 As shown, the computing device includes a processor 11 and a BMC 12 .

[0042] The processor 11 includes a target pin and a plurality of status registers. Each status register can be used to record whether a CE occurs in a corresponding component. For example, when a certain status register is in the first state, it can indicate that a CE fault occurs in the component corresponding to the status register. When a certain status register is in the second state, it can indicate that there is no CE fault in the component corresponding to the status register. The set state of the target pin can be used to indicate that there is a CE fault, and the reset state of the target pin can be used to indicate that there is no CE fault. When the state of at least one of the plurality of status registers is in the first state, the target pin of the processor 11 is triggered to be set. Exemplarily, the above-mentioned target pin can be specifically the ERR0 pin.

[0043] Optionally, the components corresponding to the status register may be memory, storage device, hard disk, network interface, peripheral interface, subsystem of the processor itself, etc., which is not limited in the present application.

[0044] Optionally, the status register may be a register in a bank array, wherein the bank array may be a linear topology structure, each bank may be viewed as a container containing a group of registers, and the processor 11 may access the registers in a specific bank through an integrated memory controller (IMC) to detect whether a CE exists.

[0045] Optionally, the status register may also be a register in an integrated error handler (IEH). In the IEH, registers are usually organized into a tree structure, and each register is regarded as a node of the tree.

[0046] The BMC 12 is used to perform CE processing according to the method 200 provided in the present application when the target pin of the processor 11 is set.

[0047] Optionally, the BMC 12 can be used to monitor whether a target pin of the processor 11 is set.

[0048] In a possible implementation, the computing device may further include a complex programmable logic device (CPLD), and relevant registers in the CPLD may be used to record the state of the target pin of the processor 11. The BMC 12 may be connected to the CPLD via a local bus, and the CPLD is connected to the target pin of the processor 11. Based on this, the BMC 12 may poll the relevant registers in the CPLD to obtain the state of the target pin of the processor 11. Specifically, the BMC 12 may poll the relevant registers in the CPLD via a listener to obtain the state of the target pin of the processor 11.

[0049] In another possible implementation, the pin of BMC 12 itself may be connected to the target pin of processor 11. In this case, BMC 12 may directly poll the state of the target pin of processor 11; for example, BMC may directly poll the state of the target pin of processor through a listener.

[0050] Optionally, the computing device may further include an interface protocol (platform environment control interface, PECI), and when the BMC 12 monitors that the target pin of the processor 11 is set, the CE process may be performed through the PECI.

[0051] Optionally, the processor may be a CPU, or a graphics processing unit (GPU), a memory controller, or a redundant arrays of independent disks (RAID) controller, or other devices that may include the status register and target pin, and this application does not limit this.

[0052] Optionally, in practical applications, the BMC 12 may be replaced by other modules or devices that can independently perform CE processing, which is not limited in the present application. However, for ease of description, the BMC will be taken as an example for description below.

[0053] Based on the introduction of the above computing devices, the following will be combined Figure 2 Details how the BMC 12 performs CE processing when the processor's target pin is asserted.

[0054] Figure 2 is a flow chart of a CE processing method provided in an embodiment of the present application. Figure 2 As shown, the method 200 may include steps S210 to S230, which are described in detail below.

[0055] S210 , in response to a target pin of the processor being set, resetting the target pin.

[0056] That is to say, when the target pin of the processor is set, the target pin can be reset first, so as to ensure that the target pin can be triggered to be set again when a new CE is generated subsequently.

[0057] Optionally, when the BMC includes a monitor, before executing step S210, the monitor may be used to monitor whether the target pin of the processor is set. When it is detected that the target pin of the processor is set, step S210 is executed.

[0058] Optionally, when the computing device also includes a CPLD, the BMC can obtain the state of the target pin by polling the relevant registers of the CPLD. The BMC can obtain the state of the target pin by polling the relevant registers of the CPLD, which means that the BMC can send a query request to the CPLD at a predetermined time interval, and at each query, the CPLD will respond to the BMC's request and return the current state information of the target pin. The present application uses a polling method to enable the BMC to continuously obtain the latest state of the target pin within a predetermined time interval. For example, the BMC 12 can obtain the state of the target pin of the processor 11 by polling the relevant registers in the CPLD through a listener.

[0059] Alternatively, when the BMC's own pin is directly connected to the target pin of the processor, the BMC may directly poll the state of the target pin of the processor. For example, the BMC may directly poll the state of the target pin of the processor through a listener.

[0060] Optionally, the BMC may instruct the processor to reset the target pin by sending a reset instruction to the processor, or may directly reset the target pin. This application does not limit this. The specific implementation method depends on whether the BMC has the ability to directly access and operate the target pin.

[0061] S220, obtaining states of multiple state registers in the processor, and marking the state register when the state of the state register is a first state.

[0062] Optionally, the BMC may sequentially obtain status of multiple status registers in the processor.

[0063] Optionally, the BMC may send a status acquisition request to the processor, and the processor may return the status of the status register in response to the status acquisition request.

[0064] Optionally, in the case where the computing device includes a memory, the BMC may mark the status register by storing address information of the status register in the first state in the memory; so that when the status register in the first state needs to be placed in the second state later, these status registers can be quickly found based on the address information. For example, the BMC may first obtain the address information from the memory, and then place the status register in the first state in the second state based on the address information.

[0065] Optionally, the address information of the status register may be stored in a target queue in the memory, so that the address information may be subsequently obtained based on the queue when needed.

[0066] Optionally, the memory may be located in the BMC or outside the BMC, which is not limited in the present application.

[0067] S230, placing the marked status register in a second state, and processing the CE fault of the corresponding component according to the acquired state in the marked status register.

[0068] Specifically, the BMC may send a write command to the processor, the write command being used to instruct the processor to write the second state into the marked state register, wherein the second state may be understood as a specific value to be written into the state register.

[0069] In summary, the present application proposes that when the target pin of the processor is set, the target pin can be reset first, and then the state of each status register can be obtained, and after all the acquisitions are completed, the status register with the first state can be placed in the second state, and the CE fault of the corresponding component can be processed according to the acquired state. On the one hand, the present application scheme enables the target pin to be triggered to be set in time when a new CE is generated, thereby reducing the missed processing of CE. For example, after the target pin is reset, if a component in the system generates a new CE during the state acquisition process and the new CE causes the state of a status register that has been acquired to change to the first state, the status register can trigger the target pin to be set again, so that the above-mentioned CE processing flow can be entered again, so that the new CE can be detected and processed in time; on the other hand, compared with the method of placing the status register with the first state in the second state at the same time as the acquisition, and uniformly processing the CE faults of the corresponding components after all the acquisitions are completed, the present application scheme can avoid the phenomenon that the target pin is triggered to be set again in the current CE processing flow due to the same CE (that is, the CE that previously triggered the register state to change to the first state)

[0070] In addition, the present application also proposes that when acquiring the register status, the status registers in the first state can be marked first, so that when the status registers in the first state need to be placed in the second state later, these status registers can be quickly found based on the marks.

[0071] It should be noted that BMC generally obtains the state of the target pin by polling the listener, which results in a certain delay between the occurrence of CE and CE processing. To this end, the present application proposes that after the marked status register is placed in the second state, it can actively check whether the target pin of the processor is set (see step S240). If the target pin of the processor is set, it means that a new CE has appeared, and the CE processing operation can be performed again (i.e., steps S210 to S230 are performed again) to process the new CE. Compared with the method of triggering the execution of the CE processing operation based on the monitoring result of the listener, the delay of the new CE processing can be reduced.

[0072] To facilitate understanding of the above content, the following Figure 3 and Figure 4 Two situations involved in this application scheme are explained.

[0073] Figure 3 It is a flow chart of a CE processing situation provided by an embodiment of the present application. It should be understood that this situation mainly introduces that after obtaining the state of a certain register (ie the above-mentioned state register, hereinafter referred to as register) as the first state, the component corresponding to the register generates a new CE.

[0074] like Figure 3 As shown, the process 300 mainly includes steps S310 to S350, which are introduced below.

[0075] S310, when the state of at least one register of the processor is a first state, triggering a target pin of the processor to be set.

[0076] like Figure 3 As shown in (a), when the state of register 3 is the first state, the target pin is triggered to be set and the CE processing flow is entered.

[0077] S320 , in response to the target pin of the processor being set, the BMC resets the target pin of the processor.

[0078] like Figure 3 As shown in (b) in the figure, the target pin of the processor is reset before obtaining the status of the register.

[0079] S330, the BMC obtains the status of registers in sequence, and marks the registers whose status is the first status.

[0080] like Figure 3 As shown in (c), when the state of register 3 is the first state, register 3 is marked, for example, address information of register 3 can be stored in a memory.

[0081] S340: During the state acquisition process, the component corresponding to the register in the first state generates a new CE.

[0082] For example, Figure 3 As shown in (d), when the state of register 10 is obtained, assuming that the component corresponding to the marked register 3 generates a new CE, the new CE does not trigger a change in the state of register 10.

[0083] S350: After the status acquisition is completed, the BMC sets the marked status register to the second state and processes the CE fault of the corresponding component.

[0084] For example, Figure 3 As shown in (e), after the state acquisition is completed, the state of register 3 is set to the second state. It should be understood that, usually when a new CE appears in the component corresponding to the register, if the new CE has not been processed, then after the state of the register is set to the second state, the new CE will trigger the state of the register to change from the second state to the first state again, thereby triggering the target pin to be set, so that the CE processing flow can be started again to process the new CE.

[0085] In addition, in order to reduce the delay of processing the new CE, after step S350, the BMC can also actively check whether the target pin is set, and if it is set, it can enter the CE processing flow to process the new CE.

[0086] Figure 4 It is a flow chart of another CE processing situation provided by an embodiment of the present application. It should be understood that this situation mainly introduces that in the process of state acquisition, a component corresponding to a register that has acquired a state and is not marked generates a new CE.

[0087] like Figure 4 As shown, the process 400 mainly includes steps S410 to S450, which are introduced below.

[0088] Among them, S410 to S430 can refer to the above steps S310 to S330 and will not be repeated here.

[0089] S440, during the state acquisition process, the component corresponding to the register whose state has been acquired and not marked generates a new CE.

[0090] For example, Figure 4 As shown in (d), when the state of register 10 is obtained, the component corresponding to register 2 generates a new CE, which changes the state of register 2 to the first state, thereby triggering the target pin to be set again.

[0091] S450, after the status acquisition is completed, the BMC sets the marked status register to the second state and processes the CE fault of the corresponding component.

[0092] For example, Figure 4 As shown in (e) in FIG. 1 , after the state acquisition is completed, the state of register 3 is set to the second state.

[0093] It can be understood that since register 2 is not marked, the state of register 2 will not be placed in the second state after the state acquisition is completed. However, since the component corresponding to register 2 generates a new CE, the new CE causes the state of register 2 to be changed to the first state, thereby triggering the target pin to be set again, so that the CE processing flow can be started again to process the new CE.

[0094] Similarly, in order to reduce the delay of processing the new CE, after step S450, the BMC may also actively check whether the target pin is set, and if it is set, the CE processing flow may be entered to process the new CE.

[0095] In addition, it should be noted that in actual operation, there may be a situation where the state of the status register changes to the first state due to a system failure but does not trigger the target pin to be set, which in turn causes the BMC to be unable to process the existing CE in a timely manner. To avoid the above problem, the present application proposes that a state acquisition operation can be triggered at regular intervals by setting a timer, so as to ensure that the newly generated CE is discovered and processed in a timely manner when the CE processing mechanism is abnormal.

[0096] Specifically, the timer can be set to include a first mode and a second mode, in which the first mode triggers a state acquisition operation on the multiple state registers every first time period, and in the second mode, the timer triggers a state acquisition operation on the multiple state registers every second time period, and the first time period is greater than the second time period. The first time period can be, for example, half an hour, 1 hour, or 2 hours, and the second time period can be, for example, 1 minute, 2 minutes, or 3 minutes.

[0097] Based on this setting, Figure 5 As shown, when the target pin is set, in response to the target pin being set, the timer can be adjusted to the second mode, and based on the second mode, when no state register in the first state is found in n consecutive state acquisition operations, the timer is adjusted to the first mode, where n is a positive integer. For example, n can be a value such as 5, 10 or 15.

[0098] That is to say, based on this setting, under normal circumstances, the timer can be adjusted to the first mode, triggering a status acquisition operation at a long interval; after CE occurs, the timer is adjusted to the second mode, triggering a status acquisition operation at a short interval, thereby ensuring that the newly generated CE can be discovered and processed in time when the CE processing mechanism is abnormal while reducing resource consumption.

[0099] Based on the timer setting, the present application also proposes that when the target pin is set, the timer can be adjusted to the second mode, and the status acquisition operation of multiple status registers based on the timer trigger can be suspended. After the CE processing is completed (that is, after executing the above steps S210 to S240), the status acquisition operation of multiple status registers based on the timer trigger is started again, thereby avoiding the conflict between the status acquisition operation in the CE processing and the status acquisition operation in the timing trigger, thereby ensuring the stable operation of the system.

[0100] The following, combined Figure 6The CE processing device 600 provided in the embodiment of the present application is described. The device 600 can be applied to the BMC in the computing device (for example, the device 600 can be the BMC, or a module or unit placed in the BMC). The computing device also includes a processor, and the processor includes a target pin and a plurality of status registers. When the status register is in a first state, it is used to indicate that a CE failure has occurred in the corresponding component; when the state of at least one status register is in the first state, the target pin of the processor is set. Figure 6 As shown, the device 600 may include a resetting module 610 , an acquiring and marking module 620 , and a processing module 630 .

[0101] Among them, the reset module 610, the acquisition and marking module 620 and the processing module 630 are used for the device 600 to perform the corresponding processing steps in the above method embodiment. For example, in response to the target pin of the processor being set, the reset module 610 is used to reset the target pin, wherein the set state of the target pin is used to indicate the presence of a CE fault, and the reset state of the target pin is used to indicate that there is no CE fault; the acquisition and marking module 620 is used to obtain the status of multiple status registers in the processor, and when the status of the status register is the first state, mark the status register; the processing module 630 is used to put the marked status register in the second state, and according to the acquired state in the marked status register, process the CE fault of the corresponding component, wherein the second state is used to indicate that the corresponding component has no CE fault.

[0102] It should be understood that other related steps performed by the resetting module 610, the acquiring and marking module 620 and the processing module 630 can be found in the introduction of the above method embodiment and will not be described in detail.

[0103] In a possible implementation, the device 600 may further include a storage module. The storage module is connected to the reset module 610, the acquisition and marking module 620, and the processing module 630 via a line. The storage module may include one or more memories, and the memory may be a device used to store programs or data in one or more devices or circuits. The storage module may exist independently and be connected to the reset module 610, the acquisition and marking module 620, and the processing module 630 via a communication bus. The storage module may also be integrated with the reset module 610, the acquisition and marking module 620, and the processing module 630.

[0104] The storage module can store computer-executable instructions of the method in the apparatus 600 so that the apparatus 600 executes the method in the above embodiment. The storage module can be a register, a cache memory, or a random access memory (RAM), etc. The storage module can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions.

[0105] Figure 7 is a schematic diagram of the structure of a chip 700 provided in an embodiment of the present application. Figure 7 As shown, the chip 700 includes one or more (including two) processors 701 , a communication line 702 and a communication interface 703 . Optionally, the chip 700 also includes a memory 704 .

[0106] In some implementations, the memory 704 stores the following elements: executable modules or data structures, or a subset thereof, or an extended set thereof.

[0107] The method described in the above embodiment of the present application can be applied to the processor 701, or implemented by the processor 701. The processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method can be completed by hardware integrated logic circuits in the processor 701 or instructions in software form. The above processor 701 can be a general-purpose processor (for example, a microprocessor or a conventional processor), a digital signal processor, an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates, transistor logic devices or discrete hardware components.

[0108] The steps of the method disclosed in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. Among them, the software module can be located in a mature storage medium in the field such as a random access memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable read only memory (EEPROM). The storage medium is located in the memory 704, and the processor 701 reads the information in the memory 704 and completes the steps of the above method in combination with its hardware.

[0109] The processor 701 , the memory 704 , and the communication interface 703 may communicate with each other via the communication line 702 .

[0110] In the above embodiments, the instructions stored in the memory for execution by the processor may be implemented in the form of a computer program product, wherein the computer program product may be pre-written in the memory, or may be downloaded and installed in the memory in the form of software.

[0111] The present application embodiment also provides a computer program product, which includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a server, a data center, etc. that includes one or more available media integrated. For example, the available medium can include a magnetic medium (e.g., a floppy disk, a hard disk or a tape), an optical medium (e.g., a digital versatile disc (digital versatiledisc, DVD)), or a semiconductor medium (e.g., a solid state drive (solid state disk, SSD)), etc.

[0112] The embodiment of the present application provides a chip. The chip includes a processor, and the processor is used to call a computer program in a memory to execute the technical solution in the above embodiment. Its implementation principle and technical effect are similar to those of the above related embodiments, and will not be repeated here.

[0113] The embodiments of the present application also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program or instruction. The above method is implemented when the computer program or instruction is executed by the processor. The method described in the above embodiment can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. If implemented in software, the function can be stored as one or more instructions or codes on a computer-readable medium or transmitted on a computer-readable medium. Computer-readable media can include computer storage media and communication media, and can also include any medium that can transfer a computer program from one place to another. The storage medium can be any target medium that can be accessed by a computer.

[0114] As a possible design, the computer-readable medium may include a compact disc read-only memory (CD-ROM), RAM, ROM, EEPROM or other optical disc storage; the computer-readable medium may include a magnetic disk storage or other magnetic disk storage device. Moreover, any connecting line may also be appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave), the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology such as infrared, radio and microwave are included in the definition of the medium. Disks and optical discs as used herein include compact discs (CDs), laser discs, optical discs, DVDs, floppy disks and Blu-ray discs, where disks generally reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included in the scope of computer-readable media.

[0115] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0116] The above specific implementation methods further illustrate the purpose, technical solutions and beneficial effects of the present application in detail. It should be understood that the above are only specific implementation methods of the present application and are not used to limit the protection scope of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present application should be included in the protection scope of the present application.

Claims

1. A method for processing a correctable error CE, characterized in that: The method is applied to a baseboard management controller BMC in a computing device, wherein the computing device further comprises a processor; the processor comprises a target pin and a plurality of status registers, and the method comprises: In response to a target pin of the processor being set, resetting the target pin, wherein the set state of the target pin is used to indicate the presence of a CE fault, and the reset state of the target pin is used to indicate the absence of a CE fault; Acquire the status of multiple status registers in the processor, and mark the status register when the status of the status register is a first status; wherein the first status indicates that a CE fault occurs in a component corresponding to the status register; The marked status register is placed in a second state, and the CE fault of the corresponding component is processed according to the acquired state in the marked status register; wherein the second state is used to indicate that the component corresponding to the status register has no CE fault.

2. The method according to claim 1, characterized in that The BMC includes a memory, and the marking of the status register includes: storing address information of a state register whose state is the first state in the memory; Placing the marked status register into the second state comprises: Acquiring the address information from the memory; The state of the state register in the first state is placed in the second state based on the address information.

3. The method according to claim 1 or 2, characterized in that: The BMC includes a listener, and before resetting the target pin in response to the target pin of the processor being set, the method further includes: The target pin of the processor is detected to be set through the monitor.

4. The method according to claim 1 or 2, characterized in that: After placing the marked status register in the second state, the method further comprises: checking whether a target pin of the processor is set; When it is detected that the target pin of the processor is set, the CE processing operation is performed again, and the CE processing operation includes: in response to the target pin of the processor being set, resetting the target pin; obtaining the status of multiple status registers in the processor, and marking the status register when the status of the status register is the first state; setting the marked status register to the second state, and processing the CE fault of the corresponding component according to the acquired state in the marked status register.

5. The method according to claim 1 or 2, characterized in that: The BMC includes a timer, and the timer includes a first mode and a second mode. In the first mode, the timer triggers a state acquisition operation on the multiple state registers once every first time period, and in the second mode, the timer triggers a state acquisition operation on the multiple state registers once every second time period, and the first time period is greater than the second time period. The method further includes: In response to a target pin of the processor being set, adjusting the timer to the second mode; Based on the second mode, when no state register in the first state is found in n consecutive state acquisition operations, the timer is adjusted to the first mode, where n is a positive integer.

6. The method according to claim 5, characterized in that In response to the target pin of the processor being set, adjusting the timer to the second mode comprises: In response to the target pin of the processor being set, adjusting the timer to the second mode, and suspending the state acquisition operation of the multiple state registers triggered by the timer; After the CE process is completed, the status acquisition operation of the plurality of status registers is started based on the timer trigger.

7. The method according to claim 1 or 2, characterized in that: Placing the marked status register into the second state comprises: A write command is sent to the processor, where the write command is used to instruct the processor to write the second state into the marked state register.

8. The method according to claim 1 or 2, characterized in that: The computing device further comprises a complex programmable logic device (CPLD), wherein a relevant register in the CPLD is used to record the state of the target pin, and the BMC obtains the state of the target pin by polling the relevant register of the CPLD.

9. The method according to claim 1 or 2, characterized in that: The obtaining of the status of the plurality of status registers in the processor comprises: The states of a plurality of state registers in the processor are obtained in sequence.

10. A computing device, characterized in that The computing device includes a processor and a memory; the processor is coupled to the memory; the memory is used to store computer instructions, and the computer instructions are loaded and executed by the processor to enable the computing device to implement the method for processing correctable error CE as described in any one of claims 1 to 9.

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