Parallel CRC circuit and CRC implementation method thereof, hardware description code automatic generator and generation method thereof

Abstract

The present invention discloses a parallel CRC circuit and a CRC implementation method thereof, a hardware description code automatic generator and a generation method thereof, including: obtaining configuration parameters including a generation polynomial definition and a processing parallelism w; the generation polynomial definition includes the degree m of the generation polynomial and the coefficient P, P = { P 0 , P 1 , P 2 ,…, P m−1}; the configuration parameters are input into a code generation function; the code generation function generates hardware description code according to a CRC expression and the configuration parameters; the CRC expression is an exclusive OR and multiplication operation related to the configuration parameters. This solution first determines a recursive formula and derives a parallel implementation from the recursive formula. Compared with the previous parallel implementation methods, it has the characteristics of faster speed and more compactness, and the provided expression only needs to perform exclusive OR and multiplication operations after obtaining F w . Compared with the traditional expression that first performs multiplication and exclusive OR and then performs the sum of polynomials, the implemented hardware circuit is more concise and efficient.

Description

Technical Field

[0001] The invention belongs to the field of cyclic redundancy check implementation, and in particular relates to a parallel CRC circuit and a CRC implementation method thereof, a hardware description code automatic generator and a generation method thereof. Background Art

[0002] CRC (Cyclic Redundancy Check) is widely used in data communication and storage devices as a powerful method for handling data errors. It is also used in many other fields such as testing of integrated circuits and detection of logic failures. Currently, one of the more mature hardware solutions is a linear feedback shift register (LFSR) with serial data input. The serial LFSR implementation of CRC is suboptimal for a given design. Due to the serial data input, only one data bit of CRC calculation is allowed per clock. If a design has an N-bit data path, this means that each clock CRC module must calculate the CRC on N bits of data, and the serial CRC will not work.

[0003] In summary, the existing CRC implementation method, serial linear feedback shift register, has limitations when processing high data rates. Therefore, a parallel CRC implementation method is needed to improve the verification speed and reduce hardware resource consumption.

[0004] In order to realize the parallel CRC circuit, people have conducted a lot of research. For example, a Chinese patent discloses a parallel CRC algorithm Verilog HDL code automatic generator and method [Publication No.: CN101826011A]. However, like many parallel implementation schemes, this scheme has problems such as large amount of calculation and complex implementation. Although this scheme achieves the purpose of parallelization, it is essentially to temporarily store the serial intermediate results and then parallelize the results. Once the data is too long and too large, the size of the hardware will be very large. In view of the problems existing in the current parallel implementation scheme, this scheme proposes a targeted solution. Summary of the invention

[0005] The object of the present invention is to provide a hardware description code automatic generator of a parallel CRC circuit and a generation method thereof in view of the above problems;

[0006] Another object of the present invention is to provide a parallel CRC circuit and a CRC implementation method thereof designed and implemented based on the hardware description code generated by the above-mentioned automatic generation method.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] A method for automatically generating hardware description code of a parallel CRC circuit, comprising:

[0009] Obtain configuration parameters including the definition of the generator polynomial and the processing parallelism w;

[0010] The generator polynomial definition includes the degree m and coefficient P of the generator polynomial. ;

[0011] The configuration parameters are input to the code generation function;

[0012] The code generation function generates a hardware description code according to the CRC expression and the configuration parameters;

[0013] The CRC expression is an XOR and multiplication operation related to the configuration parameters.

[0014] In the above-mentioned method for automatically generating hardware description code for a parallel CRC circuit, the CRC expression is related to the state transition matrix of the polynomial generator, which is a process of calculating the next state of the polynomial generator based on the current state of the polynomial generator, the processing parallelism w and the input data k.

[0015] In the above-mentioned method for automatically generating hardware description code of parallel CRC circuit, the CRC expression is:

[0016] (1)

[0017] represents the next state of the polynomial generator;

[0018] is the w-th power of the state transfer matrix, which is recursively calculated by matrix multiplication and XOR operation, where F is the matrix representation of the polynomial generator and w is the processing parallelism;

[0019] Represents a multiplication operation;

[0020] Represents the current state of the polynomial generator;

[0021] It indicates the bitwise XOR operation;

[0022] Represents the input data of the current clock cycle, with a bit width of w.

[0023] In the above-mentioned method for automatically generating hardware description code for parallel CRC circuit, the The specific method is recursive as follows:

[0024] (2)

[0025] Represents the state transition matrix of the polynomial generator in the i-th state F ;

[0026] Represents the state transition matrix at the i-1th state F ;

[0027] is the coefficient matrix of the generating polynomial coefficients P, m is the degree of the generating polynomial;

[0028] Formula (2) represents the matrix through the i-1th state Modulo 2 multiplication with the vector consisting of the coefficients of the generator polynomial, and then with the matrix The first m-1 columns of the XOR operation are used to calculate the matrix of the i-th state F ;

[0029] Construct F according to the processing parallelism w w Matrix, from F 1 Start building to F w The polynomial generator of the CRC expression is F w Perform state transfer for the unit.

[0030] In the above-mentioned method for automatically generating hardware description codes of parallel CRC circuits, the configuration parameters also include a specified file format of the hardware description codes;

[0031] The generated hardware description code includes any one or more combinations of package definition, library declaration, entity declaration, architecture declaration, input data processing, clock and reset logic, output logic, and CRC calculation logic;

[0032] The package definition, library declaration, and entity declaration are fixed line contents, while the architecture declaration, input data processing, clock and reset logic, output logic, and CRC calculation logic are dynamic codes.

[0033] In the above-mentioned method for automatically generating hardware description codes of parallel CRC circuits, the physical structure of the generated hardware description codes includes a reset signal, a clock signal, input data and an output check code.

[0034] In the above-mentioned method for automatically generating hardware description code for a parallel CRC circuit, the code generation function is based on F w Arranging the shift registers and XOR gates in a matrix so as to conform to the algorithm operation defined by the CRC expression to generate the hardware description code;

[0035] The enable signal of the hardware circuit implemented based on the hardware description code is taken from F w matrix.

[0036] A hardware description code automatic generator for a parallel CRC circuit, comprising:

[0037] A storage file is used to store configuration parameters and CRC expression (1) required for generating hardware description code; the configuration parameters include a generator polynomial definition and a processing parallelism w, and the generator polynomial definition includes a degree m and a coefficient P of the generator polynomial. ; The CRC expression is an XOR and multiplication operation related to the configuration parameters;

[0038] A code generation function, taking the configuration parameters and the CRC expression as input, is used to generate a hardware description code;

[0039] The CRC script file based on the simulation platform is used to call the storage file and the code generation function to generate the hardware description code.

[0040] In the hardware description code automatic generator of the parallel CRC circuit, the CRC expression and the w-th power of the state transition matrix of the polynomial generator are Related, and the storage file is also used to store the state transfer matrix The recursive formula (2)

[0041] The code generation function obtains the state transfer matrix according to the configuration parameters through the recursive formula (2): , and determined based on The expression generates the hardware description code;

[0042] The fixed line content of the hardware description code is stored in a storage file, and the dynamic code of the hardware description code is generated by a code generation function. After the code generation function generates the dynamic code according to the CRC expression and configuration parameters, the dynamic code is combined with the fixed line content to generate the complete hardware description code.

[0043] A parallel CRC circuit is designed and implemented according to the hardware description code automatically generated by the hardware description code automatic generator.

[0044] In the CRC implementation method of the above parallel CRC circuit, it includes:

[0045] Data sender:

[0046] Add n zeros at the end of data k to obtain sequence S, so that sequence S can be divided by the parallelism w, n ≥ m; when k and m are both multiples of w, m zeros can be directly added after k.

[0047] go through After the clock cycle, the CRC circuit outputs the check value;

[0048] The check value is appended to the end of the data k, and when n>m, nm zeros are added between the check value and the data k to obtain the sequence S', which is sent to the data receiver;

[0049] Data Recipients:

[0050] Receive the sequence S' and divide the sequence S' by the generating polynomial coefficient P. If there is no remainder, the verification is correct, otherwise the verification is wrong.

[0051] The advantages of the present invention are:

[0052] (1) This scheme first determines a recursive formula and derives a parallel implementation from the recursive formula. Compared with previous parallel implementation methods, it is faster and more compact.

[0053] (2) The expression provided by this scheme only needs to be obtained when F w Then perform XOR and multiplication operations. Compared with the traditional expression of first performing multiplication and XOR and then summing the polynomials, the implemented hardware circuit is more concise and efficient.

[0054] (3) Construct an expression based on the idea of ​​state transfer, and use F in the expression w The state is transferred as a unit, and F is obtained by the recursive formula w Therefore, there is no process of temporarily storing serial intermediate results, and the hardware size is not affected by the data length;

[0055] (4) The hardware description code generated by the hardware description code generation method provided by this solution can generate a parallel CRC circuit, and the generated CRC circuit achieves the effect of saving the amount of hardware and achieving a higher frequency;

[0056] (5) The solution provided by this scheme can automatically adapt to the requirements of different polynomials to generate the hardware code description of the CRC hardware circuit, and the hardware circuit implemented by the hardware code description can quickly check data of different lengths. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 The overall architecture block diagram of the parallel CRC circuit hardware description code automatic generator;

[0058] Figure 2 A physical structure diagram of the generated hardware description code;

[0059] Figure 3 The architecture block diagram of the parallel CRC circuit hardware description code automatic generator described for the example;

[0060] Figure 4 This is a schematic diagram of the implemented CRC hardware circuit structure. DETAILED DESCRIPTION

[0061] The present invention provides a parallel CRC circuit hardware description code automatic generator, such as Figure 1 As shown, including,

[0062] Storage file used to store configuration parameters and CRC expressions (1) required to generate hardware description code.

[0063] Configuration parameters include the degree m and coefficients P of the generator polynomial, as well as the processing parallelism w, and the specified file format of the hardware description code. , each coefficient P i It is 0 or 1 according to the actual situation.

[0064] The CRC expression (1) is an XOR and multiplication operation related to the configuration parameters and the w-th power F of the state transition matrix of the polynomial generator. w It is a process of calculating the next state of the polynomial generator according to the current state of the polynomial generator, the processing parallelism w and the input data k. The specific formula is as follows:

[0065] (1)

[0066] Indicates the next state of the polynomial generator, that is, the new CRC state after processing the current clock cycle;

[0067] is the w-th power of the state transfer matrix, which is recursively calculated by matrix multiplication and XOR operation, where F is the matrix representation of the polynomial generator and w is the processing parallelism;

[0068] Represents a multiplication operation;

[0069] Indicates the current state of the polynomial generator, that is, the CRC state of the current clock cycle before processing the corresponding data;

[0070] It indicates the bitwise XOR operation;

[0071] Represents the input data of the current clock cycle, with a bit width of w. In each clock cycle, new w-bit data is loaded into D and used to update the CRC status.

[0072] State transition matrix It is obtained by the following recursive formula (2), which is stored in the storage file:

[0073] (2)

[0074] Represents the state transition matrix of the polynomial generator in the i-th state F ;

[0075] Represents the state transition matrix at the i-1th state F ;

[0076] is the coefficient matrix of the generating polynomial coefficients P, m is the degree of the generating polynomial;

[0077] Formula (2) represents the matrix through the i-1th state Modulo 2 multiplication with the vector consisting of the coefficients of the generator polynomial, and then with the matrix The first m-1 columns of the XOR operation are used to calculate the matrix of the i-th state F ;

[0078] Construct F according to the processing parallelism w w Matrix, from F 1 Start building to F w The polynomial generator of the CRC expression is F w Perform state transfer for the unit.

[0079] The code generation function takes the configuration parameters and CRC expression (1) as input and is used to generate the hardware description code. Specifically, the state transfer matrix is ​​obtained through the recursive formula (2) according to the configuration parameters. , and determined based on The CRC expression (1) generates the hardware description code.

[0080] The CRC script file based on the simulation platform is used to call the configuration parameters and code generation functions of the storage file to generate the required hardware description code.

[0081] The simulation platform can use the MATLAB simulation platform or other simulation platforms, there is no restriction here.

[0082] Specifically, the automatic generation method of the hardware description code of the parallel CRC circuit generated by the CRC circuit hardware description code automatic generator is as follows:

[0083] The CRC script file obtains configuration parameters including the degree m of the generating polynomial, the coefficient P and the processing parallelism w from the storage file. These configuration parameters can be configured by the developer according to the requirements.

[0084] Then call the code generation function and input the configuration parameters into the code generation function;

[0085] The code generation function generates hardware description code based on the CRC expression and configuration parameters.

[0086] Preferably, the fixed line content of the hardware description code is stored in a storage file, and the dynamic code of the hardware description code is generated by a code generation function, and after the code generation function generates the dynamic code according to the CRC expression and the configuration parameters, the dynamic code is combined with the fixed line content to generate the complete hardware description code. In this way, the repeated code lines in the script file can be prevented from stacking, and the generation of the hardware description code file can be facilitated.

[0087] Specifically, the generated hardware description code includes package definition, library declaration, entity declaration, architecture declaration, input data processing, clock and reset logic, output logic, CRC calculation logic and other parts.

[0088] Among them, package definition, library declaration, and entity declaration can be used as fixed line content, and architecture declaration, processing input data, clock and reset logic, output logic, and CRC calculation logic can be used as dynamic code.

[0089] Furthermore, if Figure 2 As shown, the physical structure of the generated hardware description code includes a reset signal res, a clock signal clk, input data Din and an output check code Xout.

[0090] This embodiment uses the generation of VHDL format hardware description code as an example to illustrate this solution:

[0091] like Figure 3 As shown, the hardware description code automatic generator architecture includes a front-end character file crcgen.txt, and the user defines the code generator's generator polynomial degree m, processing parallelism w and file format opt, which are stored in a storage file. In this embodiment, the user-defined generator polynomial is CRC-16=[1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1] as an example, the generator polynomial degree m is 16, the coefficient P=[1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1], and the parallelism w is set to DATAWINTH=16.

[0092] Based on the CRC script file crcgen.m of the matlab simulation platform, run the crcgen.m script file to call the front-end character file crcgen.txt and the code generation function crcgen to generate the VHDL code file crcgen.vhd.

[0093] The input parameters of the code generation function crcgen include the defined generating polynomial CRC-16 = [1 1 0 0 0 0 00 0 0 0 0 0 0 1 0 1], the processing parallelism w-16, and the file format opt-vhd.

[0094] The outputs are: S (the bold part of the following code): bitwise XOR operation string; F k (The matrix representation corresponding to the bold code): Calculate the kth power of matrix F (k=w), and take the result modulo 2; Dimxor: Count the number of XOR inputs (that is, the number of 1s) in each row of the matrix; FH: F k The hexadecimal representation of the matrix, calling the crcgen function to calculate F w The CRC XOR gate structure is arranged in parallel. These outputs do not affect the generation of the final crcgen.vhd, but are just a reflection of the required matrix for the convenience of statistical observation.

[0095] Finally, the hardware CRC-16 code crcgen.vhd is as follows:

[0096] package crcpack is

[0097] constant CRCDIM: integer:=16;

[0098] constant DATA_WIDTH: integer:=16;

[0099] end crcpack; --------------------------------------------------Package definition

[0100] library ieee;

[0101] use ieee.std_logic_1164.all;

[0102] use work.crcpack.all; -----------------------------------------Library Declaration

[0103] entity crcgen is

[0104] port(

[0105] res,clk : std_logic;

[0106] Din : in std_logic_vector(DATA_WIDTH-1 downto 0);

[0107] Xout : out std_logic_vector(CRCDIM-1 downto 0));

[0108] end crcgen; -----------------------------------------------------Entity declaration

[0109] architecture rtl of crcgen is

[0110] signal X,Xl,X2,Dins: std_logic_vector(CRCDIM-l downto 0);

[0111] begin -----------------------------------------------------Architecture Declaration

[0112] process(Din)

[0113] variable Dinv: std_logic_vector(CRCDIM-l downto 0);

[0114] begin

[0115] Dinv := (others =>'0');

[0116] Dinv(DATA_WIDTH-1 downto 0) := Din;

[0117] Dins<= Dinv;

[0118] end process; -----------------------------------------------------Process input data

[0119] X2<= X;

[0120] process(res,clk)

[0121] begin

[0122] if res = '0' then X <= (others => '0');

[0123] elsif rising_edge(clk) then X <= Xl xor Dins;

[0124] end if;

[0125] end process; -------------------------------------------------- Clock and reset logic

[0126] Xout <= X; -------------------------------------------------- Output logic

[0127] --CRC = x^16+x^15+x^2+x

[0128] X1(15) <= X2(15) xor X2(14) xor X2(12) xor X2(11) xor X2(10) xor X2(9) xor X2(8) xor X2(7) xor X2(6) xor X2(5) xor X2(4) xor X2(3) xor X2(2) xor X2(1) xor X2(0);

[0129] X1(14) <= X2(13) xor X2(12);

[0130] X1(13) <= X2(12) xor X2(11);

[0131] X1(12) <= X2(11) xor X2(10);

[0132] X1(11) <= X2(10) xor X2(9);

[0133] X1(10) <= X2(9) xor X2(8);

[0134] X1(9) <= X2(8) xor X2(7);

[0135] X1(8) <= X2(7) xor X2(6);

[0136] X1(7) <= X2(6) xor X2(5);

[0137] X1(6) <= X2(5) xor X2(4);

[0138] X1(5)<=X2(4)xor X2(3);

[0139] X1(4)<=X2(3)xor X2(2);

[0140] X1(3)<=X2(15)xor X2(2)xor X2(1);

[0141] X1(2)<=X2(14)xorX2(1)xor X2(0);

[0142] X1(1)<= X2(14)xor X2(13)xor X2(12)xor X2(11)xor X2(10)xor X2(9)xor

[0143] X1(0)<= X2(15)xor X2(13)xor X2(12)xor X2(11)xor X2(10)xor X2(9)xor

[0144] end rtl; --------------------------------------------------CRC calculation logic

[0145] Verify the functionality of crcgen.vhd: set the reset signal res from low potential '0' to '1' after 20ns, the clock clk flips every 5ns, the clock cycle is 10ns, the initial value of the input signal Din is x"8001", and x"0001" is accumulated every clock. The output result Xout meets the expected verification result, and the generator is successful.

[0146] Further, Figure 4 The figure shows an example of a CRC hardware circuit implemented by a parallel CRC circuit hardware description code automatic generator and a parallel CRC circuit hardware description code generation method. The enable signal e of the AND gate logic r,c Taken from F w , enable signal e r,c Equal to F w The value of row r and column c in . Figure 4In the case of , if the divisor P is fixed, then the AND gate can be replaced by XOR.

[0147] The principle of CRC cyclic redundancy check error is:

[0148] 1) Assume that the transmitter T sends a k-bit sequence S 1 :{b 0 ,b 1 ,...,b k-1} to the receiver R, while T generates another m-bit sequence S 2 :{ , ,..., }, allowing the receiver to detect possible errors. Sequence S 2 It is usually called the frame check sequence (FCS). It is generated by taking into account the fact that the S 1 and S 2 The complete sequence obtained by concatenation With P that can be represented by a predetermined sequence of m+1 bits: {p 0 ,p 1 ,...,p k-1}The property of divisibility (following a specific arithmetic). After T sends S to R, R, upon receiving the message, divides S (i.e. the message and FCS) by P using the same specific algorithm. If there is no remainder, R is considered to have no errors.

[0149] 2) Modulo 2 arithmetic is used in the digital implementation of CRC: the product operator is performed by bitwise AND operation, while the sum and subtraction operators are both performed by bitwise XOR operation. In this case, a CRC circuit (modulo 2 divisor) can be easily implemented as a special shift register, called LFSR. It can be used by both the transmitter and the receiver. In the case of the transmitter, the dividend is the sequence S1 concatenated with a sequence of m zeros on the right. The divisor is P. In the simple case of the receiver, the dividend is the received sequence and the divisor is the same P.

[0150] 3) Parallel implementation of CRC: Assume that the degree m of the polynomial generator and the length k of the message to be processed are both multiples of the number of bits (w) to be processed in parallel. In the final circuit obtained, the sequence S 1 Add m zeros and send them to the circuit in blocks of w bits each. After one clock cycle, the FFs output will give the desired FCS.

[0151] The following is the reasoning source of the CRC expression (1) and recursive formula (2) used in this solution:

[0152] From the linear system theory, we know that a discrete time-invariant linear system can be expressed as:

[0153] (3)

[0154] Where X is the state of the system, U is the input, and Y is the output. We use F, G, H, J to represent matrices, and X, Y, and U to represent column vectors.

[0155] The solution of equation (3) is:

[0156] (4)

[0157] Replace multiplication and addition with AND and XOR operators respectively, using represents the XOR operation, and the product is represented by It is a discrete linear time-invariant system. The input U(i) is the i-th bit of the input sequence. The state X represents the output of FFs. The vector Y coincides with X, that is, H and J are the unit matrix and the zero matrix respectively. Therefore, we have:

[0158]

[0159] H = I m The identity matrix of size m×m

[0160]

[0161] U=d

[0162]

[0163]

[0164] Where pi is the digit of the divisor P (i.e., the coefficient of the generating polynomial). When i and w coincide, substituting the operator, the solution obtained from equation (4) is:

[0165] (5)

[0166] Considering the system is time-invariant, we get the recursive formula:

[0167] (6)

[0168] Represents the initial state of the polynomial generator.

[0169] It turns out that the m-bit FCS can be calculated by sending the k-bit message S1 followed by m-bit 0s in blocks of w bits each. After one clock cycle, X is the desired FCS.

[0170] Then, the matrix F is evaluated and can be constructed recursively:

[0171] (2)

[0172] It can be seen that when F m If it already exists, you can get F w .

[0173] Let p' represent the vector have:

[0174] (7)

[0175] Among them I m-w is the same matrix of order mw. Further, we have:

[0176] (8)

[0177] Therefore, by F m You can get F w : F w The first w columns are F m The last w columns, F w The upper right part is I m-w , fill the lower right part with zeros, and finally get the following CRC expression:

[0178] (1).

[0179] The CRC expression defines the core operations of the CRC algorithm, which are implemented in hardware through logic gates and registers. The above method can automatically generate hardware description code through the CRC expression. In the hardware description language, these operations are converted into specific codes that can be used to build actual hardware circuits.

[0180] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

[0181] Although this article uses more terms such as generator polynomial, polynomial generator, CRC expression, storage file, code generation function, CRC script file, etc., it does not exclude the possibility of using other terms. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional restriction is contrary to the spirit of the present invention.

Claims

1. A method for automatically generating hardware description code for a parallel CRC circuit, characterized in that: include: Obtain configuration parameters including generator polynomial definition and processing parallelism w; The generator polynomial definition includes the degree m and coefficient P of the generator polynomial, P={ P 0 , P 1 , P 2 ,…, P m−1 }; The configuration parameters are input to the code generation function; The code generation function generates a hardware description code according to the CRC expression and the configuration parameters; The CRC expression is: （1） represents the next state of the polynomial generator; is the w-th power of the state transfer matrix, which is recursively calculated by matrix multiplication and XOR operation, where F is the matrix representation of the polynomial generator and w is the processing parallelism; Represents a multiplication operation; Represents the current state of the polynomial generator; It indicates the bitwise XOR operation; Represents the input data of the current clock cycle, with a bit width of w.

2. The method for automatically generating hardware description codes for parallel CRC circuits according to claim 1, wherein: The The specific method is recursive as follows: （2） Represents the state transition matrix of the polynomial generator in the i-th state F ; Represents the state transition matrix at the i-1th state F ; is the coefficient matrix of the generating polynomial coefficients P, m is the degree of the generating polynomial; Formula (2) represents the matrix through the i-1th state Modulo 2 multiplication with the vector consisting of the coefficients of the generator polynomial, and then with the matrix Perform an XOR operation to calculate the matrix of the i-th state F ; Construct F according to the processing parallelism w w Matrix, through formula (2) from F 1 Start building to F w The polynomial generator of the CRC expression is F w Perform state transfer for the unit.

3. The method for automatically generating hardware description codes for parallel CRC circuits according to claim 1, wherein: The configuration parameters also include a specified file format of the hardware description code; The generated hardware description code includes any one or more combinations of package definition, library declaration, entity declaration, architecture declaration, input data processing, clock and reset logic, output logic, and CRC calculation logic; Among them, package definition, library declaration, and entity declaration are fixed line contents, while architecture declaration, input data processing, clock and reset logic, output logic, and CRC calculation logic are dynamic codes; The physical structure of the generated hardware description code includes a reset signal, a clock signal, input data and an output check code.

4. The method for automatically generating hardware description codes for parallel CRC circuits according to claim 1 or 2, characterized in that: The code generation function is based on F w Arranging shift registers and XOR gates in a matrix so as to conform to the algorithm operation defined by the CRC expression to generate the hardware description code; The enable signal of the hardware circuit implemented based on the hardware description code is taken from F w matrix.

5. A hardware description code automatic generator for a parallel CRC circuit, characterized in that: include, Storage file used to store the configuration parameters and CRC expressions required to generate hardware description code (1): （1） represents the next state of the polynomial generator; is the w-th power of the state transfer matrix, which is recursively calculated by matrix multiplication and XOR operation, where F is the matrix representation of the polynomial generator and w is the processing parallelism; Represents a multiplication operation; Represents the current state of the polynomial generator; It indicates the bitwise XOR operation; Represents the input data of the current clock cycle, with a bit width of w; The configuration parameters include the definition of the generating polynomial and the processing parallelism w, and the definition of the generating polynomial includes the degree m and coefficient P of the generating polynomial, P={ P 0 , P 1 , P 2 ,…, P m−1 }; The CRC expression is an XOR and multiplication operation related to the configuration parameters; A code generation function, taking the configuration parameters and the CRC expression as input, is used to generate a hardware description code; The CRC script file based on the simulation platform is used to call the storage file and the code generation function to generate the hardware description code.

6. The hardware description code automatic generator of the parallel CRC circuit according to claim 5, characterized in that: The CRC expression and the state transition matrix of the polynomial generator are w powers Related, and the storage file is also used to store the state transfer matrix The recursive formula (2) The code generation function obtains the state transfer matrix according to the configuration parameters through the recursive formula (2): , and determined based on The expression generates the hardware description code; The fixed line content of the hardware description code is stored in a storage file, and the dynamic code of the hardware description code is generated by a code generation function. After the code generation function generates the dynamic code according to the CRC expression and configuration parameters, the dynamic code is combined with the fixed line content to generate the complete hardware description code.

7. A parallel CRC circuit, characterized in that: The hardware description code design automatically generated by the hardware description code automatic generator according to claim 5 or 6 is implemented.

8. The CRC implementation method of the parallel CRC circuit according to claim 7, characterized in that: include: Data sender: Add n zeros to the end of data k to obtain sequence S, so that sequence S can be divided by the parallelism w, n ≥ m; go through After the clock cycle, the CRC circuit outputs the check value; The check value is appended to the end of the data k, and when n>m, nm zeros are added between the check value and the data k to obtain the sequence S', which is sent to the data receiver; Data Recipients: Receive the sequence S' and divide the sequence S' by the generating polynomial coefficient P. If there is no remainder, the verification is correct, otherwise the verification is wrong.

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